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Linux/arch/x86/kernel/i8259.c

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  1 #include <linux/linkage.h>
  2 #include <linux/errno.h>
  3 #include <linux/signal.h>
  4 #include <linux/sched.h>
  5 #include <linux/ioport.h>
  6 #include <linux/interrupt.h>
  7 #include <linux/timex.h>
  8 #include <linux/random.h>
  9 #include <linux/init.h>
 10 #include <linux/kernel_stat.h>
 11 #include <linux/syscore_ops.h>
 12 #include <linux/bitops.h>
 13 #include <linux/acpi.h>
 14 #include <linux/io.h>
 15 #include <linux/delay.h>
 16 
 17 #include <linux/atomic.h>
 18 #include <asm/timer.h>
 19 #include <asm/hw_irq.h>
 20 #include <asm/pgtable.h>
 21 #include <asm/desc.h>
 22 #include <asm/apic.h>
 23 #include <asm/i8259.h>
 24 
 25 /*
 26  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 27  * present in the majority of PC/AT boxes.
 28  * plus some generic x86 specific things if generic specifics makes
 29  * any sense at all.
 30  */
 31 static void init_8259A(int auto_eoi);
 32 
 33 static int i8259A_auto_eoi;
 34 DEFINE_RAW_SPINLOCK(i8259A_lock);
 35 
 36 /*
 37  * 8259A PIC functions to handle ISA devices:
 38  */
 39 
 40 /*
 41  * This contains the irq mask for both 8259A irq controllers,
 42  */
 43 unsigned int cached_irq_mask = 0xffff;
 44 
 45 /*
 46  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 47  * boards the timer interrupt is not really connected to any IO-APIC pin,
 48  * it's fed to the master 8259A's IR0 line only.
 49  *
 50  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 51  * this 'mixed mode' IRQ handling costs nothing because it's only used
 52  * at IRQ setup time.
 53  */
 54 unsigned long io_apic_irqs;
 55 
 56 static void mask_8259A_irq(unsigned int irq)
 57 {
 58         unsigned int mask = 1 << irq;
 59         unsigned long flags;
 60 
 61         raw_spin_lock_irqsave(&i8259A_lock, flags);
 62         cached_irq_mask |= mask;
 63         if (irq & 8)
 64                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 65         else
 66                 outb(cached_master_mask, PIC_MASTER_IMR);
 67         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 68 }
 69 
 70 static void disable_8259A_irq(struct irq_data *data)
 71 {
 72         mask_8259A_irq(data->irq);
 73 }
 74 
 75 static void unmask_8259A_irq(unsigned int irq)
 76 {
 77         unsigned int mask = ~(1 << irq);
 78         unsigned long flags;
 79 
 80         raw_spin_lock_irqsave(&i8259A_lock, flags);
 81         cached_irq_mask &= mask;
 82         if (irq & 8)
 83                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 84         else
 85                 outb(cached_master_mask, PIC_MASTER_IMR);
 86         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 87 }
 88 
 89 static void enable_8259A_irq(struct irq_data *data)
 90 {
 91         unmask_8259A_irq(data->irq);
 92 }
 93 
 94 static int i8259A_irq_pending(unsigned int irq)
 95 {
 96         unsigned int mask = 1<<irq;
 97         unsigned long flags;
 98         int ret;
 99 
100         raw_spin_lock_irqsave(&i8259A_lock, flags);
101         if (irq < 8)
102                 ret = inb(PIC_MASTER_CMD) & mask;
103         else
104                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
105         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
106 
107         return ret;
108 }
109 
110 static void make_8259A_irq(unsigned int irq)
111 {
112         disable_irq_nosync(irq);
113         io_apic_irqs &= ~(1<<irq);
114         irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
115         enable_irq(irq);
116 }
117 
118 /*
119  * This function assumes to be called rarely. Switching between
120  * 8259A registers is slow.
121  * This has to be protected by the irq controller spinlock
122  * before being called.
123  */
124 static inline int i8259A_irq_real(unsigned int irq)
125 {
126         int value;
127         int irqmask = 1<<irq;
128 
129         if (irq < 8) {
130                 outb(0x0B, PIC_MASTER_CMD);     /* ISR register */
131                 value = inb(PIC_MASTER_CMD) & irqmask;
132                 outb(0x0A, PIC_MASTER_CMD);     /* back to the IRR register */
133                 return value;
134         }
135         outb(0x0B, PIC_SLAVE_CMD);      /* ISR register */
136         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
137         outb(0x0A, PIC_SLAVE_CMD);      /* back to the IRR register */
138         return value;
139 }
140 
141 /*
142  * Careful! The 8259A is a fragile beast, it pretty
143  * much _has_ to be done exactly like this (mask it
144  * first, _then_ send the EOI, and the order of EOI
145  * to the two 8259s is important!
146  */
147 static void mask_and_ack_8259A(struct irq_data *data)
148 {
149         unsigned int irq = data->irq;
150         unsigned int irqmask = 1 << irq;
151         unsigned long flags;
152 
153         raw_spin_lock_irqsave(&i8259A_lock, flags);
154         /*
155          * Lightweight spurious IRQ detection. We do not want
156          * to overdo spurious IRQ handling - it's usually a sign
157          * of hardware problems, so we only do the checks we can
158          * do without slowing down good hardware unnecessarily.
159          *
160          * Note that IRQ7 and IRQ15 (the two spurious IRQs
161          * usually resulting from the 8259A-1|2 PICs) occur
162          * even if the IRQ is masked in the 8259A. Thus we
163          * can check spurious 8259A IRQs without doing the
164          * quite slow i8259A_irq_real() call for every IRQ.
165          * This does not cover 100% of spurious interrupts,
166          * but should be enough to warn the user that there
167          * is something bad going on ...
168          */
169         if (cached_irq_mask & irqmask)
170                 goto spurious_8259A_irq;
171         cached_irq_mask |= irqmask;
172 
173 handle_real_irq:
174         if (irq & 8) {
175                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
176                 outb(cached_slave_mask, PIC_SLAVE_IMR);
177                 /* 'Specific EOI' to slave */
178                 outb(0x60+(irq&7), PIC_SLAVE_CMD);
179                  /* 'Specific EOI' to master-IRQ2 */
180                 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
181         } else {
182                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
183                 outb(cached_master_mask, PIC_MASTER_IMR);
184                 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
185         }
186         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
187         return;
188 
189 spurious_8259A_irq:
190         /*
191          * this is the slow path - should happen rarely.
192          */
193         if (i8259A_irq_real(irq))
194                 /*
195                  * oops, the IRQ _is_ in service according to the
196                  * 8259A - not spurious, go handle it.
197                  */
198                 goto handle_real_irq;
199 
200         {
201                 static int spurious_irq_mask;
202                 /*
203                  * At this point we can be sure the IRQ is spurious,
204                  * lets ACK and report it. [once per IRQ]
205                  */
206                 if (!(spurious_irq_mask & irqmask)) {
207                         printk(KERN_DEBUG
208                                "spurious 8259A interrupt: IRQ%d.\n", irq);
209                         spurious_irq_mask |= irqmask;
210                 }
211                 atomic_inc(&irq_err_count);
212                 /*
213                  * Theoretically we do not have to handle this IRQ,
214                  * but in Linux this does not cause problems and is
215                  * simpler for us.
216                  */
217                 goto handle_real_irq;
218         }
219 }
220 
221 struct irq_chip i8259A_chip = {
222         .name           = "XT-PIC",
223         .irq_mask       = disable_8259A_irq,
224         .irq_disable    = disable_8259A_irq,
225         .irq_unmask     = enable_8259A_irq,
226         .irq_mask_ack   = mask_and_ack_8259A,
227 };
228 
229 static char irq_trigger[2];
230 /**
231  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
232  */
233 static void restore_ELCR(char *trigger)
234 {
235         outb(trigger[0], 0x4d0);
236         outb(trigger[1], 0x4d1);
237 }
238 
239 static void save_ELCR(char *trigger)
240 {
241         /* IRQ 0,1,2,8,13 are marked as reserved */
242         trigger[0] = inb(0x4d0) & 0xF8;
243         trigger[1] = inb(0x4d1) & 0xDE;
244 }
245 
246 static void i8259A_resume(void)
247 {
248         init_8259A(i8259A_auto_eoi);
249         restore_ELCR(irq_trigger);
250 }
251 
252 static int i8259A_suspend(void)
253 {
254         save_ELCR(irq_trigger);
255         return 0;
256 }
257 
258 static void i8259A_shutdown(void)
259 {
260         /* Put the i8259A into a quiescent state that
261          * the kernel initialization code can get it
262          * out of.
263          */
264         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
265         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
266 }
267 
268 static struct syscore_ops i8259_syscore_ops = {
269         .suspend = i8259A_suspend,
270         .resume = i8259A_resume,
271         .shutdown = i8259A_shutdown,
272 };
273 
274 static void mask_8259A(void)
275 {
276         unsigned long flags;
277 
278         raw_spin_lock_irqsave(&i8259A_lock, flags);
279 
280         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
281         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
282 
283         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
284 }
285 
286 static void unmask_8259A(void)
287 {
288         unsigned long flags;
289 
290         raw_spin_lock_irqsave(&i8259A_lock, flags);
291 
292         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
293         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
294 
295         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
296 }
297 
298 static void init_8259A(int auto_eoi)
299 {
300         unsigned long flags;
301         unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
302         unsigned char new_val;
303 
304         i8259A_auto_eoi = auto_eoi;
305 
306         raw_spin_lock_irqsave(&i8259A_lock, flags);
307 
308         /*
309          * Check to see if we have a PIC.
310          * Mask all except the cascade and read
311          * back the value we just wrote. If we don't
312          * have a PIC, we will read 0xff as opposed to the
313          * value we wrote.
314          */
315         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
316         outb(probe_val, PIC_MASTER_IMR);
317         new_val = inb(PIC_MASTER_IMR);
318         if (new_val != probe_val) {
319                 printk(KERN_INFO "Using NULL legacy PIC\n");
320                 legacy_pic = &null_legacy_pic;
321                 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
322                 return;
323         }
324 
325         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
326 
327         /*
328          * outb_pic - this has to work on a wide range of PC hardware.
329          */
330         outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
331 
332         /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
333         outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
334 
335         /* 8259A-1 (the master) has a slave on IR2 */
336         outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
337 
338         if (auto_eoi)   /* master does Auto EOI */
339                 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
340         else            /* master expects normal EOI */
341                 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
342 
343         outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
344 
345         /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
346         outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
347         /* 8259A-2 is a slave on master's IR2 */
348         outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
349         /* (slave's support for AEOI in flat mode is to be investigated) */
350         outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
351 
352         if (auto_eoi)
353                 /*
354                  * In AEOI mode we just have to mask the interrupt
355                  * when acking.
356                  */
357                 i8259A_chip.irq_mask_ack = disable_8259A_irq;
358         else
359                 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
360 
361         udelay(100);            /* wait for 8259A to initialize */
362 
363         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
364         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
365 
366         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
367 }
368 
369 /*
370  * make i8259 a driver so that we can select pic functions at run time. the goal
371  * is to make x86 binary compatible among pc compatible and non-pc compatible
372  * platforms, such as x86 MID.
373  */
374 
375 static void legacy_pic_noop(void) { };
376 static void legacy_pic_uint_noop(unsigned int unused) { };
377 static void legacy_pic_int_noop(int unused) { };
378 static int legacy_pic_irq_pending_noop(unsigned int irq)
379 {
380         return 0;
381 }
382 
383 struct legacy_pic null_legacy_pic = {
384         .nr_legacy_irqs = 0,
385         .chip = &dummy_irq_chip,
386         .mask = legacy_pic_uint_noop,
387         .unmask = legacy_pic_uint_noop,
388         .mask_all = legacy_pic_noop,
389         .restore_mask = legacy_pic_noop,
390         .init = legacy_pic_int_noop,
391         .irq_pending = legacy_pic_irq_pending_noop,
392         .make_irq = legacy_pic_uint_noop,
393 };
394 
395 struct legacy_pic default_legacy_pic = {
396         .nr_legacy_irqs = NR_IRQS_LEGACY,
397         .chip  = &i8259A_chip,
398         .mask = mask_8259A_irq,
399         .unmask = unmask_8259A_irq,
400         .mask_all = mask_8259A,
401         .restore_mask = unmask_8259A,
402         .init = init_8259A,
403         .irq_pending = i8259A_irq_pending,
404         .make_irq = make_8259A_irq,
405 };
406 
407 struct legacy_pic *legacy_pic = &default_legacy_pic;
408 
409 static int __init i8259A_init_ops(void)
410 {
411         if (legacy_pic == &default_legacy_pic)
412                 register_syscore_ops(&i8259_syscore_ops);
413 
414         return 0;
415 }
416 
417 device_initcall(i8259A_init_ops);
418 

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