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Linux/arch/x86/kernel/irq.c

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  1 /*
  2  * Common interrupt code for 32 and 64 bit
  3  */
  4 #include <linux/cpu.h>
  5 #include <linux/interrupt.h>
  6 #include <linux/kernel_stat.h>
  7 #include <linux/of.h>
  8 #include <linux/seq_file.h>
  9 #include <linux/smp.h>
 10 #include <linux/ftrace.h>
 11 #include <linux/delay.h>
 12 #include <linux/export.h>
 13 
 14 #include <asm/apic.h>
 15 #include <asm/io_apic.h>
 16 #include <asm/irq.h>
 17 #include <asm/mce.h>
 18 #include <asm/hw_irq.h>
 19 #include <asm/desc.h>
 20 
 21 #define CREATE_TRACE_POINTS
 22 #include <asm/trace/irq_vectors.h>
 23 
 24 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
 25 EXPORT_PER_CPU_SYMBOL(irq_stat);
 26 
 27 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
 28 EXPORT_PER_CPU_SYMBOL(irq_regs);
 29 
 30 atomic_t irq_err_count;
 31 
 32 /* Function pointer for generic interrupt vector handling */
 33 void (*x86_platform_ipi_callback)(void) = NULL;
 34 
 35 /*
 36  * 'what should we do if we get a hw irq event on an illegal vector'.
 37  * each architecture has to answer this themselves.
 38  */
 39 void ack_bad_irq(unsigned int irq)
 40 {
 41         if (printk_ratelimit())
 42                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
 43 
 44         /*
 45          * Currently unexpected vectors happen only on SMP and APIC.
 46          * We _must_ ack these because every local APIC has only N
 47          * irq slots per priority level, and a 'hanging, unacked' IRQ
 48          * holds up an irq slot - in excessive cases (when multiple
 49          * unexpected vectors occur) that might lock up the APIC
 50          * completely.
 51          * But only ack when the APIC is enabled -AK
 52          */
 53         ack_APIC_irq();
 54 }
 55 
 56 #define irq_stats(x)            (&per_cpu(irq_stat, x))
 57 /*
 58  * /proc/interrupts printing for arch specific interrupts
 59  */
 60 int arch_show_interrupts(struct seq_file *p, int prec)
 61 {
 62         int j;
 63 
 64         seq_printf(p, "%*s: ", prec, "NMI");
 65         for_each_online_cpu(j)
 66                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
 67         seq_puts(p, "  Non-maskable interrupts\n");
 68 #ifdef CONFIG_X86_LOCAL_APIC
 69         seq_printf(p, "%*s: ", prec, "LOC");
 70         for_each_online_cpu(j)
 71                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
 72         seq_puts(p, "  Local timer interrupts\n");
 73 
 74         seq_printf(p, "%*s: ", prec, "SPU");
 75         for_each_online_cpu(j)
 76                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
 77         seq_puts(p, "  Spurious interrupts\n");
 78         seq_printf(p, "%*s: ", prec, "PMI");
 79         for_each_online_cpu(j)
 80                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
 81         seq_puts(p, "  Performance monitoring interrupts\n");
 82         seq_printf(p, "%*s: ", prec, "IWI");
 83         for_each_online_cpu(j)
 84                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
 85         seq_puts(p, "  IRQ work interrupts\n");
 86         seq_printf(p, "%*s: ", prec, "RTR");
 87         for_each_online_cpu(j)
 88                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
 89         seq_puts(p, "  APIC ICR read retries\n");
 90 #endif
 91         if (x86_platform_ipi_callback) {
 92                 seq_printf(p, "%*s: ", prec, "PLT");
 93                 for_each_online_cpu(j)
 94                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
 95                 seq_puts(p, "  Platform interrupts\n");
 96         }
 97 #ifdef CONFIG_SMP
 98         seq_printf(p, "%*s: ", prec, "RES");
 99         for_each_online_cpu(j)
100                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
101         seq_puts(p, "  Rescheduling interrupts\n");
102         seq_printf(p, "%*s: ", prec, "CAL");
103         for_each_online_cpu(j)
104                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
105         seq_puts(p, "  Function call interrupts\n");
106         seq_printf(p, "%*s: ", prec, "TLB");
107         for_each_online_cpu(j)
108                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
109         seq_puts(p, "  TLB shootdowns\n");
110 #endif
111 #ifdef CONFIG_X86_THERMAL_VECTOR
112         seq_printf(p, "%*s: ", prec, "TRM");
113         for_each_online_cpu(j)
114                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
115         seq_puts(p, "  Thermal event interrupts\n");
116 #endif
117 #ifdef CONFIG_X86_MCE_THRESHOLD
118         seq_printf(p, "%*s: ", prec, "THR");
119         for_each_online_cpu(j)
120                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
121         seq_puts(p, "  Threshold APIC interrupts\n");
122 #endif
123 #ifdef CONFIG_X86_MCE_AMD
124         seq_printf(p, "%*s: ", prec, "DFR");
125         for_each_online_cpu(j)
126                 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
127         seq_puts(p, "  Deferred Error APIC interrupts\n");
128 #endif
129 #ifdef CONFIG_X86_MCE
130         seq_printf(p, "%*s: ", prec, "MCE");
131         for_each_online_cpu(j)
132                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
133         seq_puts(p, "  Machine check exceptions\n");
134         seq_printf(p, "%*s: ", prec, "MCP");
135         for_each_online_cpu(j)
136                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
137         seq_puts(p, "  Machine check polls\n");
138 #endif
139 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
140         if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
141                 seq_printf(p, "%*s: ", prec, "HYP");
142                 for_each_online_cpu(j)
143                         seq_printf(p, "%10u ",
144                                    irq_stats(j)->irq_hv_callback_count);
145                 seq_puts(p, "  Hypervisor callback interrupts\n");
146         }
147 #endif
148         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
149 #if defined(CONFIG_X86_IO_APIC)
150         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
151 #endif
152 #ifdef CONFIG_HAVE_KVM
153         seq_printf(p, "%*s: ", prec, "PIN");
154         for_each_online_cpu(j)
155                 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
156         seq_puts(p, "  Posted-interrupt notification event\n");
157 
158         seq_printf(p, "%*s: ", prec, "NPI");
159         for_each_online_cpu(j)
160                 seq_printf(p, "%10u ",
161                            irq_stats(j)->kvm_posted_intr_nested_ipis);
162         seq_puts(p, "  Nested posted-interrupt event\n");
163 
164         seq_printf(p, "%*s: ", prec, "PIW");
165         for_each_online_cpu(j)
166                 seq_printf(p, "%10u ",
167                            irq_stats(j)->kvm_posted_intr_wakeup_ipis);
168         seq_puts(p, "  Posted-interrupt wakeup event\n");
169 #endif
170         return 0;
171 }
172 
173 /*
174  * /proc/stat helpers
175  */
176 u64 arch_irq_stat_cpu(unsigned int cpu)
177 {
178         u64 sum = irq_stats(cpu)->__nmi_count;
179 
180 #ifdef CONFIG_X86_LOCAL_APIC
181         sum += irq_stats(cpu)->apic_timer_irqs;
182         sum += irq_stats(cpu)->irq_spurious_count;
183         sum += irq_stats(cpu)->apic_perf_irqs;
184         sum += irq_stats(cpu)->apic_irq_work_irqs;
185         sum += irq_stats(cpu)->icr_read_retry_count;
186 #endif
187         if (x86_platform_ipi_callback)
188                 sum += irq_stats(cpu)->x86_platform_ipis;
189 #ifdef CONFIG_SMP
190         sum += irq_stats(cpu)->irq_resched_count;
191         sum += irq_stats(cpu)->irq_call_count;
192 #endif
193 #ifdef CONFIG_X86_THERMAL_VECTOR
194         sum += irq_stats(cpu)->irq_thermal_count;
195 #endif
196 #ifdef CONFIG_X86_MCE_THRESHOLD
197         sum += irq_stats(cpu)->irq_threshold_count;
198 #endif
199 #ifdef CONFIG_X86_MCE
200         sum += per_cpu(mce_exception_count, cpu);
201         sum += per_cpu(mce_poll_count, cpu);
202 #endif
203         return sum;
204 }
205 
206 u64 arch_irq_stat(void)
207 {
208         u64 sum = atomic_read(&irq_err_count);
209         return sum;
210 }
211 
212 
213 /*
214  * do_IRQ handles all normal device IRQ's (the special
215  * SMP cross-CPU interrupts have their own specific
216  * handlers).
217  */
218 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
219 {
220         struct pt_regs *old_regs = set_irq_regs(regs);
221         struct irq_desc * desc;
222         /* high bit used in ret_from_ code  */
223         unsigned vector = ~regs->orig_ax;
224 
225         /*
226          * NB: Unlike exception entries, IRQ entries do not reliably
227          * handle context tracking in the low-level entry code.  This is
228          * because syscall entries execute briefly with IRQs on before
229          * updating context tracking state, so we can take an IRQ from
230          * kernel mode with CONTEXT_USER.  The low-level entry code only
231          * updates the context if we came from user mode, so we won't
232          * switch to CONTEXT_KERNEL.  We'll fix that once the syscall
233          * code is cleaned up enough that we can cleanly defer enabling
234          * IRQs.
235          */
236 
237         entering_irq();
238 
239         /* entering_irq() tells RCU that we're not quiescent.  Check it. */
240         RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
241 
242         desc = __this_cpu_read(vector_irq[vector]);
243 
244         if (!handle_irq(desc, regs)) {
245                 ack_APIC_irq();
246 
247                 if (desc != VECTOR_RETRIGGERED) {
248                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
249                                              __func__, smp_processor_id(),
250                                              vector);
251                 } else {
252                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
253                 }
254         }
255 
256         exiting_irq();
257 
258         set_irq_regs(old_regs);
259         return 1;
260 }
261 
262 /*
263  * Handler for X86_PLATFORM_IPI_VECTOR.
264  */
265 void __smp_x86_platform_ipi(void)
266 {
267         inc_irq_stat(x86_platform_ipis);
268 
269         if (x86_platform_ipi_callback)
270                 x86_platform_ipi_callback();
271 }
272 
273 __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
274 {
275         struct pt_regs *old_regs = set_irq_regs(regs);
276 
277         entering_ack_irq();
278         __smp_x86_platform_ipi();
279         exiting_irq();
280         set_irq_regs(old_regs);
281 }
282 
283 #ifdef CONFIG_HAVE_KVM
284 static void dummy_handler(void) {}
285 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
286 
287 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
288 {
289         if (handler)
290                 kvm_posted_intr_wakeup_handler = handler;
291         else
292                 kvm_posted_intr_wakeup_handler = dummy_handler;
293 }
294 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
295 
296 /*
297  * Handler for POSTED_INTERRUPT_VECTOR.
298  */
299 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
300 {
301         struct pt_regs *old_regs = set_irq_regs(regs);
302 
303         entering_ack_irq();
304         inc_irq_stat(kvm_posted_intr_ipis);
305         exiting_irq();
306         set_irq_regs(old_regs);
307 }
308 
309 /*
310  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
311  */
312 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
313 {
314         struct pt_regs *old_regs = set_irq_regs(regs);
315 
316         entering_ack_irq();
317         inc_irq_stat(kvm_posted_intr_wakeup_ipis);
318         kvm_posted_intr_wakeup_handler();
319         exiting_irq();
320         set_irq_regs(old_regs);
321 }
322 
323 /*
324  * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
325  */
326 __visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
327 {
328         struct pt_regs *old_regs = set_irq_regs(regs);
329 
330         entering_ack_irq();
331         inc_irq_stat(kvm_posted_intr_nested_ipis);
332         exiting_irq();
333         set_irq_regs(old_regs);
334 }
335 #endif
336 
337 __visible void __irq_entry smp_trace_x86_platform_ipi(struct pt_regs *regs)
338 {
339         struct pt_regs *old_regs = set_irq_regs(regs);
340 
341         entering_ack_irq();
342         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
343         __smp_x86_platform_ipi();
344         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
345         exiting_irq();
346         set_irq_regs(old_regs);
347 }
348 
349 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
350 
351 #ifdef CONFIG_HOTPLUG_CPU
352 
353 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
354  * below, which is protected by stop_machine().  Putting them on the stack
355  * results in a stack frame overflow.  Dynamically allocating could result in a
356  * failure so declare these two cpumasks as global.
357  */
358 static struct cpumask affinity_new, online_new;
359 
360 /*
361  * This cpu is going to be removed and its vectors migrated to the remaining
362  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
363  * This function is protected by stop_machine().
364  */
365 int check_irq_vectors_for_cpu_disable(void)
366 {
367         unsigned int this_cpu, vector, this_count, count;
368         struct irq_desc *desc;
369         struct irq_data *data;
370         int cpu;
371 
372         this_cpu = smp_processor_id();
373         cpumask_copy(&online_new, cpu_online_mask);
374         cpumask_clear_cpu(this_cpu, &online_new);
375 
376         this_count = 0;
377         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
378                 desc = __this_cpu_read(vector_irq[vector]);
379                 if (IS_ERR_OR_NULL(desc))
380                         continue;
381                 /*
382                  * Protect against concurrent action removal, affinity
383                  * changes etc.
384                  */
385                 raw_spin_lock(&desc->lock);
386                 data = irq_desc_get_irq_data(desc);
387                 cpumask_copy(&affinity_new,
388                              irq_data_get_affinity_mask(data));
389                 cpumask_clear_cpu(this_cpu, &affinity_new);
390 
391                 /* Do not count inactive or per-cpu irqs. */
392                 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
393                         raw_spin_unlock(&desc->lock);
394                         continue;
395                 }
396 
397                 raw_spin_unlock(&desc->lock);
398                 /*
399                  * A single irq may be mapped to multiple cpu's
400                  * vector_irq[] (for example IOAPIC cluster mode).  In
401                  * this case we have two possibilities:
402                  *
403                  * 1) the resulting affinity mask is empty; that is
404                  * this the down'd cpu is the last cpu in the irq's
405                  * affinity mask, or
406                  *
407                  * 2) the resulting affinity mask is no longer a
408                  * subset of the online cpus but the affinity mask is
409                  * not zero; that is the down'd cpu is the last online
410                  * cpu in a user set affinity mask.
411                  */
412                 if (cpumask_empty(&affinity_new) ||
413                     !cpumask_subset(&affinity_new, &online_new))
414                         this_count++;
415         }
416         /* No need to check any further. */
417         if (!this_count)
418                 return 0;
419 
420         count = 0;
421         for_each_online_cpu(cpu) {
422                 if (cpu == this_cpu)
423                         continue;
424                 /*
425                  * We scan from FIRST_EXTERNAL_VECTOR to first system
426                  * vector. If the vector is marked in the used vectors
427                  * bitmap or an irq is assigned to it, we don't count
428                  * it as available.
429                  *
430                  * As this is an inaccurate snapshot anyway, we can do
431                  * this w/o holding vector_lock.
432                  */
433                 for (vector = FIRST_EXTERNAL_VECTOR;
434                      vector < first_system_vector; vector++) {
435                         if (!test_bit(vector, used_vectors) &&
436                             IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector])) {
437                                 if (++count == this_count)
438                                         return 0;
439                         }
440                 }
441         }
442 
443         if (count < this_count) {
444                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
445                         this_cpu, this_count, count);
446                 return -ERANGE;
447         }
448         return 0;
449 }
450 
451 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
452 void fixup_irqs(void)
453 {
454         unsigned int irr, vector;
455         struct irq_desc *desc;
456         struct irq_data *data;
457         struct irq_chip *chip;
458 
459         irq_migrate_all_off_this_cpu();
460 
461         /*
462          * We can remove mdelay() and then send spuriuous interrupts to
463          * new cpu targets for all the irqs that were handled previously by
464          * this cpu. While it works, I have seen spurious interrupt messages
465          * (nothing wrong but still...).
466          *
467          * So for now, retain mdelay(1) and check the IRR and then send those
468          * interrupts to new targets as this cpu is already offlined...
469          */
470         mdelay(1);
471 
472         /*
473          * We can walk the vector array of this cpu without holding
474          * vector_lock because the cpu is already marked !online, so
475          * nothing else will touch it.
476          */
477         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
478                 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
479                         continue;
480 
481                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
482                 if (irr  & (1 << (vector % 32))) {
483                         desc = __this_cpu_read(vector_irq[vector]);
484 
485                         raw_spin_lock(&desc->lock);
486                         data = irq_desc_get_irq_data(desc);
487                         chip = irq_data_get_irq_chip(data);
488                         if (chip->irq_retrigger) {
489                                 chip->irq_retrigger(data);
490                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
491                         }
492                         raw_spin_unlock(&desc->lock);
493                 }
494                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
495                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
496         }
497 }
498 #endif
499 

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