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Linux/arch/x86/kernel/irq.c

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  1 /*
  2  * Common interrupt code for 32 and 64 bit
  3  */
  4 #include <linux/cpu.h>
  5 #include <linux/interrupt.h>
  6 #include <linux/kernel_stat.h>
  7 #include <linux/of.h>
  8 #include <linux/seq_file.h>
  9 #include <linux/smp.h>
 10 #include <linux/ftrace.h>
 11 #include <linux/delay.h>
 12 #include <linux/export.h>
 13 
 14 #include <asm/apic.h>
 15 #include <asm/io_apic.h>
 16 #include <asm/irq.h>
 17 #include <asm/idle.h>
 18 #include <asm/mce.h>
 19 #include <asm/hw_irq.h>
 20 #include <asm/desc.h>
 21 
 22 #define CREATE_TRACE_POINTS
 23 #include <asm/trace/irq_vectors.h>
 24 
 25 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
 26 EXPORT_PER_CPU_SYMBOL(irq_stat);
 27 
 28 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
 29 EXPORT_PER_CPU_SYMBOL(irq_regs);
 30 
 31 atomic_t irq_err_count;
 32 
 33 /* Function pointer for generic interrupt vector handling */
 34 void (*x86_platform_ipi_callback)(void) = NULL;
 35 
 36 /*
 37  * 'what should we do if we get a hw irq event on an illegal vector'.
 38  * each architecture has to answer this themselves.
 39  */
 40 void ack_bad_irq(unsigned int irq)
 41 {
 42         if (printk_ratelimit())
 43                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
 44 
 45         /*
 46          * Currently unexpected vectors happen only on SMP and APIC.
 47          * We _must_ ack these because every local APIC has only N
 48          * irq slots per priority level, and a 'hanging, unacked' IRQ
 49          * holds up an irq slot - in excessive cases (when multiple
 50          * unexpected vectors occur) that might lock up the APIC
 51          * completely.
 52          * But only ack when the APIC is enabled -AK
 53          */
 54         ack_APIC_irq();
 55 }
 56 
 57 #define irq_stats(x)            (&per_cpu(irq_stat, x))
 58 /*
 59  * /proc/interrupts printing for arch specific interrupts
 60  */
 61 int arch_show_interrupts(struct seq_file *p, int prec)
 62 {
 63         int j;
 64 
 65         seq_printf(p, "%*s: ", prec, "NMI");
 66         for_each_online_cpu(j)
 67                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
 68         seq_puts(p, "  Non-maskable interrupts\n");
 69 #ifdef CONFIG_X86_LOCAL_APIC
 70         seq_printf(p, "%*s: ", prec, "LOC");
 71         for_each_online_cpu(j)
 72                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
 73         seq_puts(p, "  Local timer interrupts\n");
 74 
 75         seq_printf(p, "%*s: ", prec, "SPU");
 76         for_each_online_cpu(j)
 77                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
 78         seq_puts(p, "  Spurious interrupts\n");
 79         seq_printf(p, "%*s: ", prec, "PMI");
 80         for_each_online_cpu(j)
 81                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
 82         seq_puts(p, "  Performance monitoring interrupts\n");
 83         seq_printf(p, "%*s: ", prec, "IWI");
 84         for_each_online_cpu(j)
 85                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
 86         seq_puts(p, "  IRQ work interrupts\n");
 87         seq_printf(p, "%*s: ", prec, "RTR");
 88         for_each_online_cpu(j)
 89                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
 90         seq_puts(p, "  APIC ICR read retries\n");
 91 #endif
 92         if (x86_platform_ipi_callback) {
 93                 seq_printf(p, "%*s: ", prec, "PLT");
 94                 for_each_online_cpu(j)
 95                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
 96                 seq_puts(p, "  Platform interrupts\n");
 97         }
 98 #ifdef CONFIG_SMP
 99         seq_printf(p, "%*s: ", prec, "RES");
100         for_each_online_cpu(j)
101                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
102         seq_puts(p, "  Rescheduling interrupts\n");
103         seq_printf(p, "%*s: ", prec, "CAL");
104         for_each_online_cpu(j)
105                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
106                                         irq_stats(j)->irq_tlb_count);
107         seq_puts(p, "  Function call interrupts\n");
108         seq_printf(p, "%*s: ", prec, "TLB");
109         for_each_online_cpu(j)
110                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
111         seq_puts(p, "  TLB shootdowns\n");
112 #endif
113 #ifdef CONFIG_X86_THERMAL_VECTOR
114         seq_printf(p, "%*s: ", prec, "TRM");
115         for_each_online_cpu(j)
116                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
117         seq_puts(p, "  Thermal event interrupts\n");
118 #endif
119 #ifdef CONFIG_X86_MCE_THRESHOLD
120         seq_printf(p, "%*s: ", prec, "THR");
121         for_each_online_cpu(j)
122                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
123         seq_puts(p, "  Threshold APIC interrupts\n");
124 #endif
125 #ifdef CONFIG_X86_MCE_AMD
126         seq_printf(p, "%*s: ", prec, "DFR");
127         for_each_online_cpu(j)
128                 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
129         seq_puts(p, "  Deferred Error APIC interrupts\n");
130 #endif
131 #ifdef CONFIG_X86_MCE
132         seq_printf(p, "%*s: ", prec, "MCE");
133         for_each_online_cpu(j)
134                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
135         seq_puts(p, "  Machine check exceptions\n");
136         seq_printf(p, "%*s: ", prec, "MCP");
137         for_each_online_cpu(j)
138                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
139         seq_puts(p, "  Machine check polls\n");
140 #endif
141 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
142         if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
143                 seq_printf(p, "%*s: ", prec, "HYP");
144                 for_each_online_cpu(j)
145                         seq_printf(p, "%10u ",
146                                    irq_stats(j)->irq_hv_callback_count);
147                 seq_puts(p, "  Hypervisor callback interrupts\n");
148         }
149 #endif
150         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
151 #if defined(CONFIG_X86_IO_APIC)
152         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
153 #endif
154 #ifdef CONFIG_HAVE_KVM
155         seq_printf(p, "%*s: ", prec, "PIN");
156         for_each_online_cpu(j)
157                 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
158         seq_puts(p, "  Posted-interrupt notification event\n");
159 
160         seq_printf(p, "%*s: ", prec, "PIW");
161         for_each_online_cpu(j)
162                 seq_printf(p, "%10u ",
163                            irq_stats(j)->kvm_posted_intr_wakeup_ipis);
164         seq_puts(p, "  Posted-interrupt wakeup event\n");
165 #endif
166         return 0;
167 }
168 
169 /*
170  * /proc/stat helpers
171  */
172 u64 arch_irq_stat_cpu(unsigned int cpu)
173 {
174         u64 sum = irq_stats(cpu)->__nmi_count;
175 
176 #ifdef CONFIG_X86_LOCAL_APIC
177         sum += irq_stats(cpu)->apic_timer_irqs;
178         sum += irq_stats(cpu)->irq_spurious_count;
179         sum += irq_stats(cpu)->apic_perf_irqs;
180         sum += irq_stats(cpu)->apic_irq_work_irqs;
181         sum += irq_stats(cpu)->icr_read_retry_count;
182 #endif
183         if (x86_platform_ipi_callback)
184                 sum += irq_stats(cpu)->x86_platform_ipis;
185 #ifdef CONFIG_SMP
186         sum += irq_stats(cpu)->irq_resched_count;
187         sum += irq_stats(cpu)->irq_call_count;
188 #endif
189 #ifdef CONFIG_X86_THERMAL_VECTOR
190         sum += irq_stats(cpu)->irq_thermal_count;
191 #endif
192 #ifdef CONFIG_X86_MCE_THRESHOLD
193         sum += irq_stats(cpu)->irq_threshold_count;
194 #endif
195 #ifdef CONFIG_X86_MCE
196         sum += per_cpu(mce_exception_count, cpu);
197         sum += per_cpu(mce_poll_count, cpu);
198 #endif
199         return sum;
200 }
201 
202 u64 arch_irq_stat(void)
203 {
204         u64 sum = atomic_read(&irq_err_count);
205         return sum;
206 }
207 
208 
209 /*
210  * do_IRQ handles all normal device IRQ's (the special
211  * SMP cross-CPU interrupts have their own specific
212  * handlers).
213  */
214 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
215 {
216         struct pt_regs *old_regs = set_irq_regs(regs);
217         struct irq_desc * desc;
218         /* high bit used in ret_from_ code  */
219         unsigned vector = ~regs->orig_ax;
220 
221         /*
222          * NB: Unlike exception entries, IRQ entries do not reliably
223          * handle context tracking in the low-level entry code.  This is
224          * because syscall entries execute briefly with IRQs on before
225          * updating context tracking state, so we can take an IRQ from
226          * kernel mode with CONTEXT_USER.  The low-level entry code only
227          * updates the context if we came from user mode, so we won't
228          * switch to CONTEXT_KERNEL.  We'll fix that once the syscall
229          * code is cleaned up enough that we can cleanly defer enabling
230          * IRQs.
231          */
232 
233         entering_irq();
234 
235         /* entering_irq() tells RCU that we're not quiescent.  Check it. */
236         RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
237 
238         desc = __this_cpu_read(vector_irq[vector]);
239 
240         if (!handle_irq(desc, regs)) {
241                 ack_APIC_irq();
242 
243                 if (desc != VECTOR_RETRIGGERED) {
244                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
245                                              __func__, smp_processor_id(),
246                                              vector);
247                 } else {
248                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
249                 }
250         }
251 
252         exiting_irq();
253 
254         set_irq_regs(old_regs);
255         return 1;
256 }
257 
258 /*
259  * Handler for X86_PLATFORM_IPI_VECTOR.
260  */
261 void __smp_x86_platform_ipi(void)
262 {
263         inc_irq_stat(x86_platform_ipis);
264 
265         if (x86_platform_ipi_callback)
266                 x86_platform_ipi_callback();
267 }
268 
269 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
270 {
271         struct pt_regs *old_regs = set_irq_regs(regs);
272 
273         entering_ack_irq();
274         __smp_x86_platform_ipi();
275         exiting_irq();
276         set_irq_regs(old_regs);
277 }
278 
279 #ifdef CONFIG_HAVE_KVM
280 static void dummy_handler(void) {}
281 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
282 
283 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
284 {
285         if (handler)
286                 kvm_posted_intr_wakeup_handler = handler;
287         else
288                 kvm_posted_intr_wakeup_handler = dummy_handler;
289 }
290 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
291 
292 /*
293  * Handler for POSTED_INTERRUPT_VECTOR.
294  */
295 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
296 {
297         struct pt_regs *old_regs = set_irq_regs(regs);
298 
299         entering_ack_irq();
300         inc_irq_stat(kvm_posted_intr_ipis);
301         exiting_irq();
302         set_irq_regs(old_regs);
303 }
304 
305 /*
306  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
307  */
308 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
309 {
310         struct pt_regs *old_regs = set_irq_regs(regs);
311 
312         entering_ack_irq();
313         inc_irq_stat(kvm_posted_intr_wakeup_ipis);
314         kvm_posted_intr_wakeup_handler();
315         exiting_irq();
316         set_irq_regs(old_regs);
317 }
318 #endif
319 
320 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
321 {
322         struct pt_regs *old_regs = set_irq_regs(regs);
323 
324         entering_ack_irq();
325         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
326         __smp_x86_platform_ipi();
327         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
328         exiting_irq();
329         set_irq_regs(old_regs);
330 }
331 
332 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
333 
334 #ifdef CONFIG_HOTPLUG_CPU
335 
336 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
337  * below, which is protected by stop_machine().  Putting them on the stack
338  * results in a stack frame overflow.  Dynamically allocating could result in a
339  * failure so declare these two cpumasks as global.
340  */
341 static struct cpumask affinity_new, online_new;
342 
343 /*
344  * This cpu is going to be removed and its vectors migrated to the remaining
345  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
346  * This function is protected by stop_machine().
347  */
348 int check_irq_vectors_for_cpu_disable(void)
349 {
350         unsigned int this_cpu, vector, this_count, count;
351         struct irq_desc *desc;
352         struct irq_data *data;
353         int cpu;
354 
355         this_cpu = smp_processor_id();
356         cpumask_copy(&online_new, cpu_online_mask);
357         cpumask_clear_cpu(this_cpu, &online_new);
358 
359         this_count = 0;
360         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
361                 desc = __this_cpu_read(vector_irq[vector]);
362                 if (IS_ERR_OR_NULL(desc))
363                         continue;
364                 /*
365                  * Protect against concurrent action removal, affinity
366                  * changes etc.
367                  */
368                 raw_spin_lock(&desc->lock);
369                 data = irq_desc_get_irq_data(desc);
370                 cpumask_copy(&affinity_new,
371                              irq_data_get_affinity_mask(data));
372                 cpumask_clear_cpu(this_cpu, &affinity_new);
373 
374                 /* Do not count inactive or per-cpu irqs. */
375                 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
376                         raw_spin_unlock(&desc->lock);
377                         continue;
378                 }
379 
380                 raw_spin_unlock(&desc->lock);
381                 /*
382                  * A single irq may be mapped to multiple cpu's
383                  * vector_irq[] (for example IOAPIC cluster mode).  In
384                  * this case we have two possibilities:
385                  *
386                  * 1) the resulting affinity mask is empty; that is
387                  * this the down'd cpu is the last cpu in the irq's
388                  * affinity mask, or
389                  *
390                  * 2) the resulting affinity mask is no longer a
391                  * subset of the online cpus but the affinity mask is
392                  * not zero; that is the down'd cpu is the last online
393                  * cpu in a user set affinity mask.
394                  */
395                 if (cpumask_empty(&affinity_new) ||
396                     !cpumask_subset(&affinity_new, &online_new))
397                         this_count++;
398         }
399 
400         count = 0;
401         for_each_online_cpu(cpu) {
402                 if (cpu == this_cpu)
403                         continue;
404                 /*
405                  * We scan from FIRST_EXTERNAL_VECTOR to first system
406                  * vector. If the vector is marked in the used vectors
407                  * bitmap or an irq is assigned to it, we don't count
408                  * it as available.
409                  *
410                  * As this is an inaccurate snapshot anyway, we can do
411                  * this w/o holding vector_lock.
412                  */
413                 for (vector = FIRST_EXTERNAL_VECTOR;
414                      vector < first_system_vector; vector++) {
415                         if (!test_bit(vector, used_vectors) &&
416                             IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector]))
417                             count++;
418                 }
419         }
420 
421         if (count < this_count) {
422                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
423                         this_cpu, this_count, count);
424                 return -ERANGE;
425         }
426         return 0;
427 }
428 
429 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
430 void fixup_irqs(void)
431 {
432         unsigned int irq, vector;
433         static int warned;
434         struct irq_desc *desc;
435         struct irq_data *data;
436         struct irq_chip *chip;
437         int ret;
438 
439         for_each_irq_desc(irq, desc) {
440                 int break_affinity = 0;
441                 int set_affinity = 1;
442                 const struct cpumask *affinity;
443 
444                 if (!desc)
445                         continue;
446                 if (irq == 2)
447                         continue;
448 
449                 /* interrupt's are disabled at this point */
450                 raw_spin_lock(&desc->lock);
451 
452                 data = irq_desc_get_irq_data(desc);
453                 affinity = irq_data_get_affinity_mask(data);
454                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
455                     cpumask_subset(affinity, cpu_online_mask)) {
456                         raw_spin_unlock(&desc->lock);
457                         continue;
458                 }
459 
460                 /*
461                  * Complete the irq move. This cpu is going down and for
462                  * non intr-remapping case, we can't wait till this interrupt
463                  * arrives at this cpu before completing the irq move.
464                  */
465                 irq_force_complete_move(irq);
466 
467                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
468                         break_affinity = 1;
469                         affinity = cpu_online_mask;
470                 }
471 
472                 chip = irq_data_get_irq_chip(data);
473                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
474                         chip->irq_mask(data);
475 
476                 if (chip->irq_set_affinity) {
477                         ret = chip->irq_set_affinity(data, affinity, true);
478                         if (ret == -ENOSPC)
479                                 pr_crit("IRQ %d set affinity failed because there are no available vectors.  The device assigned to this IRQ is unstable.\n", irq);
480                 } else {
481                         if (!(warned++))
482                                 set_affinity = 0;
483                 }
484 
485                 /*
486                  * We unmask if the irq was not marked masked by the
487                  * core code. That respects the lazy irq disable
488                  * behaviour.
489                  */
490                 if (!irqd_can_move_in_process_context(data) &&
491                     !irqd_irq_masked(data) && chip->irq_unmask)
492                         chip->irq_unmask(data);
493 
494                 raw_spin_unlock(&desc->lock);
495 
496                 if (break_affinity && set_affinity)
497                         pr_notice("Broke affinity for irq %i\n", irq);
498                 else if (!set_affinity)
499                         pr_notice("Cannot set affinity for irq %i\n", irq);
500         }
501 
502         /*
503          * We can remove mdelay() and then send spuriuous interrupts to
504          * new cpu targets for all the irqs that were handled previously by
505          * this cpu. While it works, I have seen spurious interrupt messages
506          * (nothing wrong but still...).
507          *
508          * So for now, retain mdelay(1) and check the IRR and then send those
509          * interrupts to new targets as this cpu is already offlined...
510          */
511         mdelay(1);
512 
513         /*
514          * We can walk the vector array of this cpu without holding
515          * vector_lock because the cpu is already marked !online, so
516          * nothing else will touch it.
517          */
518         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
519                 unsigned int irr;
520 
521                 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
522                         continue;
523 
524                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
525                 if (irr  & (1 << (vector % 32))) {
526                         desc = __this_cpu_read(vector_irq[vector]);
527 
528                         raw_spin_lock(&desc->lock);
529                         data = irq_desc_get_irq_data(desc);
530                         chip = irq_data_get_irq_chip(data);
531                         if (chip->irq_retrigger) {
532                                 chip->irq_retrigger(data);
533                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
534                         }
535                         raw_spin_unlock(&desc->lock);
536                 }
537                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
538                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
539         }
540 }
541 #endif
542 

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