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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/pci-calgary_64.c

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  1 /*
  2  * Derived from arch/powerpc/kernel/iommu.c
  3  *
  4  * Copyright IBM Corporation, 2006-2007
  5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
  6  *
  7  * Author: Jon Mason <jdmason@kudzu.us>
  8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
  9 
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  *
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 23  */
 24 
 25 #include <linux/kernel.h>
 26 #include <linux/init.h>
 27 #include <linux/types.h>
 28 #include <linux/slab.h>
 29 #include <linux/mm.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/string.h>
 32 #include <linux/crash_dump.h>
 33 #include <linux/dma-mapping.h>
 34 #include <linux/bitops.h>
 35 #include <linux/pci_ids.h>
 36 #include <linux/pci.h>
 37 #include <linux/delay.h>
 38 #include <linux/scatterlist.h>
 39 #include <linux/iommu-helper.h>
 40 
 41 #include <asm/iommu.h>
 42 #include <asm/calgary.h>
 43 #include <asm/tce.h>
 44 #include <asm/pci-direct.h>
 45 #include <asm/system.h>
 46 #include <asm/dma.h>
 47 #include <asm/rio.h>
 48 #include <asm/bios_ebda.h>
 49 
 50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
 51 int use_calgary __read_mostly = 1;
 52 #else
 53 int use_calgary __read_mostly = 0;
 54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
 55 
 56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
 57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
 58 
 59 /* register offsets inside the host bridge space */
 60 #define CALGARY_CONFIG_REG      0x0108
 61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
 62 #define PHB_PLSSR_OFFSET        0x0120
 63 #define PHB_CONFIG_RW_OFFSET    0x0160
 64 #define PHB_IOBASE_BAR_LOW      0x0170
 65 #define PHB_IOBASE_BAR_HIGH     0x0180
 66 #define PHB_MEM_1_LOW           0x0190
 67 #define PHB_MEM_1_HIGH          0x01A0
 68 #define PHB_IO_ADDR_SIZE        0x01B0
 69 #define PHB_MEM_1_SIZE          0x01C0
 70 #define PHB_MEM_ST_OFFSET       0x01D0
 71 #define PHB_AER_OFFSET          0x0200
 72 #define PHB_CONFIG_0_HIGH       0x0220
 73 #define PHB_CONFIG_0_LOW        0x0230
 74 #define PHB_CONFIG_0_END        0x0240
 75 #define PHB_MEM_2_LOW           0x02B0
 76 #define PHB_MEM_2_HIGH          0x02C0
 77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
 78 #define PHB_MEM_2_SIZE_LOW      0x02E0
 79 #define PHB_DOSHOLE_OFFSET      0x08E0
 80 
 81 /* CalIOC2 specific */
 82 #define PHB_SAVIOR_L2           0x0DB0
 83 #define PHB_PAGE_MIG_CTRL       0x0DA8
 84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
 85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
 86 
 87 /* PHB_CONFIG_RW */
 88 #define PHB_TCE_ENABLE          0x20000000
 89 #define PHB_SLOT_DISABLE        0x1C000000
 90 #define PHB_DAC_DISABLE         0x01000000
 91 #define PHB_MEM2_ENABLE         0x00400000
 92 #define PHB_MCSR_ENABLE         0x00100000
 93 /* TAR (Table Address Register) */
 94 #define TAR_SW_BITS             0x0000ffffffff800fUL
 95 #define TAR_VALID               0x0000000000000008UL
 96 /* CSR (Channel/DMA Status Register) */
 97 #define CSR_AGENT_MASK          0xffe0ffff
 98 /* CCR (Calgary Configuration Register) */
 99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
101 #define PMR_SOFTSTOP            0x80000000
102 #define PMR_SOFTSTOPFAULT       0x40000000
103 #define PMR_HARDSTOP            0x20000000
104 
105 /*
106  * The maximum PHB bus number.
107  * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
108  * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
109  * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
110  * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
111  */
112 #define MAX_PHB_BUS_NUM         256
113 
114 #define PHBS_PER_CALGARY          4
115 
116 /* register offsets in Calgary's internal register space */
117 static const unsigned long tar_offsets[] = {
118         0x0580 /* TAR0 */,
119         0x0588 /* TAR1 */,
120         0x0590 /* TAR2 */,
121         0x0598 /* TAR3 */
122 };
123 
124 static const unsigned long split_queue_offsets[] = {
125         0x4870 /* SPLIT QUEUE 0 */,
126         0x5870 /* SPLIT QUEUE 1 */,
127         0x6870 /* SPLIT QUEUE 2 */,
128         0x7870 /* SPLIT QUEUE 3 */
129 };
130 
131 static const unsigned long phb_offsets[] = {
132         0x8000 /* PHB0 */,
133         0x9000 /* PHB1 */,
134         0xA000 /* PHB2 */,
135         0xB000 /* PHB3 */
136 };
137 
138 /* PHB debug registers */
139 
140 static const unsigned long phb_debug_offsets[] = {
141         0x4000  /* PHB 0 DEBUG */,
142         0x5000  /* PHB 1 DEBUG */,
143         0x6000  /* PHB 2 DEBUG */,
144         0x7000  /* PHB 3 DEBUG */
145 };
146 
147 /*
148  * STUFF register for each debug PHB,
149  * byte 1 = start bus number, byte 2 = end bus number
150  */
151 
152 #define PHB_DEBUG_STUFF_OFFSET  0x0020
153 
154 #define EMERGENCY_PAGES 32 /* = 128KB */
155 
156 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
157 static int translate_empty_slots __read_mostly = 0;
158 static int calgary_detected __read_mostly = 0;
159 
160 static struct rio_table_hdr     *rio_table_hdr __initdata;
161 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
162 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
163 
164 struct calgary_bus_info {
165         void *tce_space;
166         unsigned char translation_disabled;
167         signed char phbid;
168         void __iomem *bbar;
169 };
170 
171 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
172 static void calgary_tce_cache_blast(struct iommu_table *tbl);
173 static void calgary_dump_error_regs(struct iommu_table *tbl);
174 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
175 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
176 static void calioc2_dump_error_regs(struct iommu_table *tbl);
177 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
178 static void get_tce_space_from_tar(void);
179 
180 static struct cal_chipset_ops calgary_chip_ops = {
181         .handle_quirks = calgary_handle_quirks,
182         .tce_cache_blast = calgary_tce_cache_blast,
183         .dump_error_regs = calgary_dump_error_regs
184 };
185 
186 static struct cal_chipset_ops calioc2_chip_ops = {
187         .handle_quirks = calioc2_handle_quirks,
188         .tce_cache_blast = calioc2_tce_cache_blast,
189         .dump_error_regs = calioc2_dump_error_regs
190 };
191 
192 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
193 
194 static inline int translation_enabled(struct iommu_table *tbl)
195 {
196         /* only PHBs with translation enabled have an IOMMU table */
197         return (tbl != NULL);
198 }
199 
200 static void iommu_range_reserve(struct iommu_table *tbl,
201         unsigned long start_addr, unsigned int npages)
202 {
203         unsigned long index;
204         unsigned long end;
205         unsigned long flags;
206 
207         index = start_addr >> PAGE_SHIFT;
208 
209         /* bail out if we're asked to reserve a region we don't cover */
210         if (index >= tbl->it_size)
211                 return;
212 
213         end = index + npages;
214         if (end > tbl->it_size) /* don't go off the table */
215                 end = tbl->it_size;
216 
217         spin_lock_irqsave(&tbl->it_lock, flags);
218 
219         iommu_area_reserve(tbl->it_map, index, npages);
220 
221         spin_unlock_irqrestore(&tbl->it_lock, flags);
222 }
223 
224 static unsigned long iommu_range_alloc(struct device *dev,
225                                        struct iommu_table *tbl,
226                                        unsigned int npages)
227 {
228         unsigned long flags;
229         unsigned long offset;
230         unsigned long boundary_size;
231 
232         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
233                               PAGE_SIZE) >> PAGE_SHIFT;
234 
235         BUG_ON(npages == 0);
236 
237         spin_lock_irqsave(&tbl->it_lock, flags);
238 
239         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
240                                   npages, 0, boundary_size, 0);
241         if (offset == ~0UL) {
242                 tbl->chip_ops->tce_cache_blast(tbl);
243 
244                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
245                                           npages, 0, boundary_size, 0);
246                 if (offset == ~0UL) {
247                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
248                         spin_unlock_irqrestore(&tbl->it_lock, flags);
249                         if (panic_on_overflow)
250                                 panic("Calgary: fix the allocator.\n");
251                         else
252                                 return bad_dma_address;
253                 }
254         }
255 
256         tbl->it_hint = offset + npages;
257         BUG_ON(tbl->it_hint > tbl->it_size);
258 
259         spin_unlock_irqrestore(&tbl->it_lock, flags);
260 
261         return offset;
262 }
263 
264 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
265                               void *vaddr, unsigned int npages, int direction)
266 {
267         unsigned long entry;
268         dma_addr_t ret = bad_dma_address;
269 
270         entry = iommu_range_alloc(dev, tbl, npages);
271 
272         if (unlikely(entry == bad_dma_address))
273                 goto error;
274 
275         /* set the return dma address */
276         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
277 
278         /* put the TCEs in the HW table */
279         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
280                   direction);
281 
282         return ret;
283 
284 error:
285         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
286                "iommu %p\n", npages, tbl);
287         return bad_dma_address;
288 }
289 
290 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
291         unsigned int npages)
292 {
293         unsigned long entry;
294         unsigned long badend;
295         unsigned long flags;
296 
297         /* were we called with bad_dma_address? */
298         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
299         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
300                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
301                        "address 0x%Lx\n", dma_addr);
302                 return;
303         }
304 
305         entry = dma_addr >> PAGE_SHIFT;
306 
307         BUG_ON(entry + npages > tbl->it_size);
308 
309         tce_free(tbl, entry, npages);
310 
311         spin_lock_irqsave(&tbl->it_lock, flags);
312 
313         iommu_area_free(tbl->it_map, entry, npages);
314 
315         spin_unlock_irqrestore(&tbl->it_lock, flags);
316 }
317 
318 static inline struct iommu_table *find_iommu_table(struct device *dev)
319 {
320         struct pci_dev *pdev;
321         struct pci_bus *pbus;
322         struct iommu_table *tbl;
323 
324         pdev = to_pci_dev(dev);
325 
326         /* search up the device tree for an iommu */
327         pbus = pdev->bus;
328         do {
329                 tbl = pci_iommu(pbus);
330                 if (tbl && tbl->it_busno == pbus->number)
331                         break;
332                 tbl = NULL;
333                 pbus = pbus->parent;
334         } while (pbus);
335 
336         BUG_ON(tbl && (tbl->it_busno != pbus->number));
337 
338         return tbl;
339 }
340 
341 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
342                              int nelems,enum dma_data_direction dir,
343                              struct dma_attrs *attrs)
344 {
345         struct iommu_table *tbl = find_iommu_table(dev);
346         struct scatterlist *s;
347         int i;
348 
349         if (!translation_enabled(tbl))
350                 return;
351 
352         for_each_sg(sglist, s, nelems, i) {
353                 unsigned int npages;
354                 dma_addr_t dma = s->dma_address;
355                 unsigned int dmalen = s->dma_length;
356 
357                 if (dmalen == 0)
358                         break;
359 
360                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
361                 iommu_free(tbl, dma, npages);
362         }
363 }
364 
365 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
366                           int nelems, enum dma_data_direction dir,
367                           struct dma_attrs *attrs)
368 {
369         struct iommu_table *tbl = find_iommu_table(dev);
370         struct scatterlist *s;
371         unsigned long vaddr;
372         unsigned int npages;
373         unsigned long entry;
374         int i;
375 
376         for_each_sg(sg, s, nelems, i) {
377                 BUG_ON(!sg_page(s));
378 
379                 vaddr = (unsigned long) sg_virt(s);
380                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
381 
382                 entry = iommu_range_alloc(dev, tbl, npages);
383                 if (entry == bad_dma_address) {
384                         /* makes sure unmap knows to stop */
385                         s->dma_length = 0;
386                         goto error;
387                 }
388 
389                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
390 
391                 /* insert into HW table */
392                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
393 
394                 s->dma_length = s->length;
395         }
396 
397         return nelems;
398 error:
399         calgary_unmap_sg(dev, sg, nelems, dir, NULL);
400         for_each_sg(sg, s, nelems, i) {
401                 sg->dma_address = bad_dma_address;
402                 sg->dma_length = 0;
403         }
404         return 0;
405 }
406 
407 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
408                                    unsigned long offset, size_t size,
409                                    enum dma_data_direction dir,
410                                    struct dma_attrs *attrs)
411 {
412         void *vaddr = page_address(page) + offset;
413         unsigned long uaddr;
414         unsigned int npages;
415         struct iommu_table *tbl = find_iommu_table(dev);
416 
417         uaddr = (unsigned long)vaddr;
418         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
419 
420         return iommu_alloc(dev, tbl, vaddr, npages, dir);
421 }
422 
423 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
424                                size_t size, enum dma_data_direction dir,
425                                struct dma_attrs *attrs)
426 {
427         struct iommu_table *tbl = find_iommu_table(dev);
428         unsigned int npages;
429 
430         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
431         iommu_free(tbl, dma_addr, npages);
432 }
433 
434 static void* calgary_alloc_coherent(struct device *dev, size_t size,
435         dma_addr_t *dma_handle, gfp_t flag)
436 {
437         void *ret = NULL;
438         dma_addr_t mapping;
439         unsigned int npages, order;
440         struct iommu_table *tbl = find_iommu_table(dev);
441 
442         size = PAGE_ALIGN(size); /* size rounded up to full pages */
443         npages = size >> PAGE_SHIFT;
444         order = get_order(size);
445 
446         flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
447 
448         /* alloc enough pages (and possibly more) */
449         ret = (void *)__get_free_pages(flag, order);
450         if (!ret)
451                 goto error;
452         memset(ret, 0, size);
453 
454         /* set up tces to cover the allocated range */
455         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
456         if (mapping == bad_dma_address)
457                 goto free;
458         *dma_handle = mapping;
459         return ret;
460 free:
461         free_pages((unsigned long)ret, get_order(size));
462         ret = NULL;
463 error:
464         return ret;
465 }
466 
467 static void calgary_free_coherent(struct device *dev, size_t size,
468                                   void *vaddr, dma_addr_t dma_handle)
469 {
470         unsigned int npages;
471         struct iommu_table *tbl = find_iommu_table(dev);
472 
473         size = PAGE_ALIGN(size);
474         npages = size >> PAGE_SHIFT;
475 
476         iommu_free(tbl, dma_handle, npages);
477         free_pages((unsigned long)vaddr, get_order(size));
478 }
479 
480 static struct dma_map_ops calgary_dma_ops = {
481         .alloc_coherent = calgary_alloc_coherent,
482         .free_coherent = calgary_free_coherent,
483         .map_sg = calgary_map_sg,
484         .unmap_sg = calgary_unmap_sg,
485         .map_page = calgary_map_page,
486         .unmap_page = calgary_unmap_page,
487 };
488 
489 static inline void __iomem * busno_to_bbar(unsigned char num)
490 {
491         return bus_info[num].bbar;
492 }
493 
494 static inline int busno_to_phbid(unsigned char num)
495 {
496         return bus_info[num].phbid;
497 }
498 
499 static inline unsigned long split_queue_offset(unsigned char num)
500 {
501         size_t idx = busno_to_phbid(num);
502 
503         return split_queue_offsets[idx];
504 }
505 
506 static inline unsigned long tar_offset(unsigned char num)
507 {
508         size_t idx = busno_to_phbid(num);
509 
510         return tar_offsets[idx];
511 }
512 
513 static inline unsigned long phb_offset(unsigned char num)
514 {
515         size_t idx = busno_to_phbid(num);
516 
517         return phb_offsets[idx];
518 }
519 
520 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
521 {
522         unsigned long target = ((unsigned long)bar) | offset;
523         return (void __iomem*)target;
524 }
525 
526 static inline int is_calioc2(unsigned short device)
527 {
528         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
529 }
530 
531 static inline int is_calgary(unsigned short device)
532 {
533         return (device == PCI_DEVICE_ID_IBM_CALGARY);
534 }
535 
536 static inline int is_cal_pci_dev(unsigned short device)
537 {
538         return (is_calgary(device) || is_calioc2(device));
539 }
540 
541 static void calgary_tce_cache_blast(struct iommu_table *tbl)
542 {
543         u64 val;
544         u32 aer;
545         int i = 0;
546         void __iomem *bbar = tbl->bbar;
547         void __iomem *target;
548 
549         /* disable arbitration on the bus */
550         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
551         aer = readl(target);
552         writel(0, target);
553 
554         /* read plssr to ensure it got there */
555         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
556         val = readl(target);
557 
558         /* poll split queues until all DMA activity is done */
559         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
560         do {
561                 val = readq(target);
562                 i++;
563         } while ((val & 0xff) != 0xff && i < 100);
564         if (i == 100)
565                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
566                        "continuing anyway\n");
567 
568         /* invalidate TCE cache */
569         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
570         writeq(tbl->tar_val, target);
571 
572         /* enable arbitration */
573         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
574         writel(aer, target);
575         (void)readl(target); /* flush */
576 }
577 
578 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
579 {
580         void __iomem *bbar = tbl->bbar;
581         void __iomem *target;
582         u64 val64;
583         u32 val;
584         int i = 0;
585         int count = 1;
586         unsigned char bus = tbl->it_busno;
587 
588 begin:
589         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
590                "sequence - count %d\n", bus, count);
591 
592         /* 1. using the Page Migration Control reg set SoftStop */
593         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
594         val = be32_to_cpu(readl(target));
595         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
596         val |= PMR_SOFTSTOP;
597         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
598         writel(cpu_to_be32(val), target);
599 
600         /* 2. poll split queues until all DMA activity is done */
601         printk(KERN_DEBUG "2a. starting to poll split queues\n");
602         target = calgary_reg(bbar, split_queue_offset(bus));
603         do {
604                 val64 = readq(target);
605                 i++;
606         } while ((val64 & 0xff) != 0xff && i < 100);
607         if (i == 100)
608                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
609                        "continuing anyway\n");
610 
611         /* 3. poll Page Migration DEBUG for SoftStopFault */
612         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
613         val = be32_to_cpu(readl(target));
614         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
615 
616         /* 4. if SoftStopFault - goto (1) */
617         if (val & PMR_SOFTSTOPFAULT) {
618                 if (++count < 100)
619                         goto begin;
620                 else {
621                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
622                                "aborting TCE cache flush sequence!\n");
623                         return; /* pray for the best */
624                 }
625         }
626 
627         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
628         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
629         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
630         val = be32_to_cpu(readl(target));
631         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
632         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
633         val = be32_to_cpu(readl(target));
634         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
635 
636         /* 6. invalidate TCE cache */
637         printk(KERN_DEBUG "6. invalidating TCE cache\n");
638         target = calgary_reg(bbar, tar_offset(bus));
639         writeq(tbl->tar_val, target);
640 
641         /* 7. Re-read PMCR */
642         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
643         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
644         val = be32_to_cpu(readl(target));
645         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
646 
647         /* 8. Remove HardStop */
648         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
649         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
650         val = 0;
651         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
652         writel(cpu_to_be32(val), target);
653         val = be32_to_cpu(readl(target));
654         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
655 }
656 
657 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
658         u64 limit)
659 {
660         unsigned int numpages;
661 
662         limit = limit | 0xfffff;
663         limit++;
664 
665         numpages = ((limit - start) >> PAGE_SHIFT);
666         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
667 }
668 
669 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
670 {
671         void __iomem *target;
672         u64 low, high, sizelow;
673         u64 start, limit;
674         struct iommu_table *tbl = pci_iommu(dev->bus);
675         unsigned char busnum = dev->bus->number;
676         void __iomem *bbar = tbl->bbar;
677 
678         /* peripheral MEM_1 region */
679         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
680         low = be32_to_cpu(readl(target));
681         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
682         high = be32_to_cpu(readl(target));
683         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
684         sizelow = be32_to_cpu(readl(target));
685 
686         start = (high << 32) | low;
687         limit = sizelow;
688 
689         calgary_reserve_mem_region(dev, start, limit);
690 }
691 
692 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
693 {
694         void __iomem *target;
695         u32 val32;
696         u64 low, high, sizelow, sizehigh;
697         u64 start, limit;
698         struct iommu_table *tbl = pci_iommu(dev->bus);
699         unsigned char busnum = dev->bus->number;
700         void __iomem *bbar = tbl->bbar;
701 
702         /* is it enabled? */
703         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
704         val32 = be32_to_cpu(readl(target));
705         if (!(val32 & PHB_MEM2_ENABLE))
706                 return;
707 
708         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
709         low = be32_to_cpu(readl(target));
710         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
711         high = be32_to_cpu(readl(target));
712         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
713         sizelow = be32_to_cpu(readl(target));
714         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
715         sizehigh = be32_to_cpu(readl(target));
716 
717         start = (high << 32) | low;
718         limit = (sizehigh << 32) | sizelow;
719 
720         calgary_reserve_mem_region(dev, start, limit);
721 }
722 
723 /*
724  * some regions of the IO address space do not get translated, so we
725  * must not give devices IO addresses in those regions. The regions
726  * are the 640KB-1MB region and the two PCI peripheral memory holes.
727  * Reserve all of them in the IOMMU bitmap to avoid giving them out
728  * later.
729  */
730 static void __init calgary_reserve_regions(struct pci_dev *dev)
731 {
732         unsigned int npages;
733         u64 start;
734         struct iommu_table *tbl = pci_iommu(dev->bus);
735 
736         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
737         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
738 
739         /* avoid the BIOS/VGA first 640KB-1MB region */
740         /* for CalIOC2 - avoid the entire first MB */
741         if (is_calgary(dev->device)) {
742                 start = (640 * 1024);
743                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
744         } else { /* calioc2 */
745                 start = 0;
746                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
747         }
748         iommu_range_reserve(tbl, start, npages);
749 
750         /* reserve the two PCI peripheral memory regions in IO space */
751         calgary_reserve_peripheral_mem_1(dev);
752         calgary_reserve_peripheral_mem_2(dev);
753 }
754 
755 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
756 {
757         u64 val64;
758         u64 table_phys;
759         void __iomem *target;
760         int ret;
761         struct iommu_table *tbl;
762 
763         /* build TCE tables for each PHB */
764         ret = build_tce_table(dev, bbar);
765         if (ret)
766                 return ret;
767 
768         tbl = pci_iommu(dev->bus);
769         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
770 
771         if (is_kdump_kernel())
772                 calgary_init_bitmap_from_tce_table(tbl);
773         else
774                 tce_free(tbl, 0, tbl->it_size);
775 
776         if (is_calgary(dev->device))
777                 tbl->chip_ops = &calgary_chip_ops;
778         else if (is_calioc2(dev->device))
779                 tbl->chip_ops = &calioc2_chip_ops;
780         else
781                 BUG();
782 
783         calgary_reserve_regions(dev);
784 
785         /* set TARs for each PHB */
786         target = calgary_reg(bbar, tar_offset(dev->bus->number));
787         val64 = be64_to_cpu(readq(target));
788 
789         /* zero out all TAR bits under sw control */
790         val64 &= ~TAR_SW_BITS;
791         table_phys = (u64)__pa(tbl->it_base);
792 
793         val64 |= table_phys;
794 
795         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
796         val64 |= (u64) specified_table_size;
797 
798         tbl->tar_val = cpu_to_be64(val64);
799 
800         writeq(tbl->tar_val, target);
801         readq(target); /* flush */
802 
803         return 0;
804 }
805 
806 static void __init calgary_free_bus(struct pci_dev *dev)
807 {
808         u64 val64;
809         struct iommu_table *tbl = pci_iommu(dev->bus);
810         void __iomem *target;
811         unsigned int bitmapsz;
812 
813         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
814         val64 = be64_to_cpu(readq(target));
815         val64 &= ~TAR_SW_BITS;
816         writeq(cpu_to_be64(val64), target);
817         readq(target); /* flush */
818 
819         bitmapsz = tbl->it_size / BITS_PER_BYTE;
820         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
821         tbl->it_map = NULL;
822 
823         kfree(tbl);
824         
825         set_pci_iommu(dev->bus, NULL);
826 
827         /* Can't free bootmem allocated memory after system is up :-( */
828         bus_info[dev->bus->number].tce_space = NULL;
829 }
830 
831 static void calgary_dump_error_regs(struct iommu_table *tbl)
832 {
833         void __iomem *bbar = tbl->bbar;
834         void __iomem *target;
835         u32 csr, plssr;
836 
837         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
838         csr = be32_to_cpu(readl(target));
839 
840         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
841         plssr = be32_to_cpu(readl(target));
842 
843         /* If no error, the agent ID in the CSR is not valid */
844         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
845                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
846 }
847 
848 static void calioc2_dump_error_regs(struct iommu_table *tbl)
849 {
850         void __iomem *bbar = tbl->bbar;
851         u32 csr, csmr, plssr, mck, rcstat;
852         void __iomem *target;
853         unsigned long phboff = phb_offset(tbl->it_busno);
854         unsigned long erroff;
855         u32 errregs[7];
856         int i;
857 
858         /* dump CSR */
859         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
860         csr = be32_to_cpu(readl(target));
861         /* dump PLSSR */
862         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
863         plssr = be32_to_cpu(readl(target));
864         /* dump CSMR */
865         target = calgary_reg(bbar, phboff | 0x290);
866         csmr = be32_to_cpu(readl(target));
867         /* dump mck */
868         target = calgary_reg(bbar, phboff | 0x800);
869         mck = be32_to_cpu(readl(target));
870 
871         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
872                tbl->it_busno);
873 
874         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
875                csr, plssr, csmr, mck);
876 
877         /* dump rest of error regs */
878         printk(KERN_EMERG "Calgary: ");
879         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
880                 /* err regs are at 0x810 - 0x870 */
881                 erroff = (0x810 + (i * 0x10));
882                 target = calgary_reg(bbar, phboff | erroff);
883                 errregs[i] = be32_to_cpu(readl(target));
884                 printk("0x%08x@0x%lx ", errregs[i], erroff);
885         }
886         printk("\n");
887 
888         /* root complex status */
889         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
890         rcstat = be32_to_cpu(readl(target));
891         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
892                PHB_ROOT_COMPLEX_STATUS);
893 }
894 
895 static void calgary_watchdog(unsigned long data)
896 {
897         struct pci_dev *dev = (struct pci_dev *)data;
898         struct iommu_table *tbl = pci_iommu(dev->bus);
899         void __iomem *bbar = tbl->bbar;
900         u32 val32;
901         void __iomem *target;
902 
903         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
904         val32 = be32_to_cpu(readl(target));
905 
906         /* If no error, the agent ID in the CSR is not valid */
907         if (val32 & CSR_AGENT_MASK) {
908                 tbl->chip_ops->dump_error_regs(tbl);
909 
910                 /* reset error */
911                 writel(0, target);
912 
913                 /* Disable bus that caused the error */
914                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
915                                      PHB_CONFIG_RW_OFFSET);
916                 val32 = be32_to_cpu(readl(target));
917                 val32 |= PHB_SLOT_DISABLE;
918                 writel(cpu_to_be32(val32), target);
919                 readl(target); /* flush */
920         } else {
921                 /* Reset the timer */
922                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
923         }
924 }
925 
926 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
927         unsigned char busnum, unsigned long timeout)
928 {
929         u64 val64;
930         void __iomem *target;
931         unsigned int phb_shift = ~0; /* silence gcc */
932         u64 mask;
933 
934         switch (busno_to_phbid(busnum)) {
935         case 0: phb_shift = (63 - 19);
936                 break;
937         case 1: phb_shift = (63 - 23);
938                 break;
939         case 2: phb_shift = (63 - 27);
940                 break;
941         case 3: phb_shift = (63 - 35);
942                 break;
943         default:
944                 BUG_ON(busno_to_phbid(busnum));
945         }
946 
947         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
948         val64 = be64_to_cpu(readq(target));
949 
950         /* zero out this PHB's timer bits */
951         mask = ~(0xFUL << phb_shift);
952         val64 &= mask;
953         val64 |= (timeout << phb_shift);
954         writeq(cpu_to_be64(val64), target);
955         readq(target); /* flush */
956 }
957 
958 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
959 {
960         unsigned char busnum = dev->bus->number;
961         void __iomem *bbar = tbl->bbar;
962         void __iomem *target;
963         u32 val;
964 
965         /*
966          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
967          */
968         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
969         val = cpu_to_be32(readl(target));
970         val |= 0x00800000;
971         writel(cpu_to_be32(val), target);
972 }
973 
974 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
975 {
976         unsigned char busnum = dev->bus->number;
977 
978         /*
979          * Give split completion a longer timeout on bus 1 for aic94xx
980          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
981          */
982         if (is_calgary(dev->device) && (busnum == 1))
983                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
984                                                      CCR_2SEC_TIMEOUT);
985 }
986 
987 static void __init calgary_enable_translation(struct pci_dev *dev)
988 {
989         u32 val32;
990         unsigned char busnum;
991         void __iomem *target;
992         void __iomem *bbar;
993         struct iommu_table *tbl;
994 
995         busnum = dev->bus->number;
996         tbl = pci_iommu(dev->bus);
997         bbar = tbl->bbar;
998 
999         /* enable TCE in PHB Config Register */
1000         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1001         val32 = be32_to_cpu(readl(target));
1002         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1003 
1004         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1005                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1006                "Calgary" : "CalIOC2", busnum);
1007         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1008                "bus.\n");
1009 
1010         writel(cpu_to_be32(val32), target);
1011         readl(target); /* flush */
1012 
1013         init_timer(&tbl->watchdog_timer);
1014         tbl->watchdog_timer.function = &calgary_watchdog;
1015         tbl->watchdog_timer.data = (unsigned long)dev;
1016         mod_timer(&tbl->watchdog_timer, jiffies);
1017 }
1018 
1019 static void __init calgary_disable_translation(struct pci_dev *dev)
1020 {
1021         u32 val32;
1022         unsigned char busnum;
1023         void __iomem *target;
1024         void __iomem *bbar;
1025         struct iommu_table *tbl;
1026 
1027         busnum = dev->bus->number;
1028         tbl = pci_iommu(dev->bus);
1029         bbar = tbl->bbar;
1030 
1031         /* disable TCE in PHB Config Register */
1032         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1033         val32 = be32_to_cpu(readl(target));
1034         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1035 
1036         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1037         writel(cpu_to_be32(val32), target);
1038         readl(target); /* flush */
1039 
1040         del_timer_sync(&tbl->watchdog_timer);
1041 }
1042 
1043 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1044 {
1045         pci_dev_get(dev);
1046         set_pci_iommu(dev->bus, NULL);
1047 
1048         /* is the device behind a bridge? */
1049         if (dev->bus->parent)
1050                 dev->bus->parent->self = dev;
1051         else
1052                 dev->bus->self = dev;
1053 }
1054 
1055 static int __init calgary_init_one(struct pci_dev *dev)
1056 {
1057         void __iomem *bbar;
1058         struct iommu_table *tbl;
1059         int ret;
1060 
1061         bbar = busno_to_bbar(dev->bus->number);
1062         ret = calgary_setup_tar(dev, bbar);
1063         if (ret)
1064                 goto done;
1065 
1066         pci_dev_get(dev);
1067 
1068         if (dev->bus->parent) {
1069                 if (dev->bus->parent->self)
1070                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1071                                "bus->parent->self!\n", dev);
1072                 dev->bus->parent->self = dev;
1073         } else
1074                 dev->bus->self = dev;
1075 
1076         tbl = pci_iommu(dev->bus);
1077         tbl->chip_ops->handle_quirks(tbl, dev);
1078 
1079         calgary_enable_translation(dev);
1080 
1081         return 0;
1082 
1083 done:
1084         return ret;
1085 }
1086 
1087 static int __init calgary_locate_bbars(void)
1088 {
1089         int ret;
1090         int rioidx, phb, bus;
1091         void __iomem *bbar;
1092         void __iomem *target;
1093         unsigned long offset;
1094         u8 start_bus, end_bus;
1095         u32 val;
1096 
1097         ret = -ENODATA;
1098         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1099                 struct rio_detail *rio = rio_devs[rioidx];
1100 
1101                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1102                         continue;
1103 
1104                 /* map entire 1MB of Calgary config space */
1105                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1106                 if (!bbar)
1107                         goto error;
1108 
1109                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1110                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1111                         target = calgary_reg(bbar, offset);
1112 
1113                         val = be32_to_cpu(readl(target));
1114 
1115                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1116                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1117 
1118                         if (end_bus) {
1119                                 for (bus = start_bus; bus <= end_bus; bus++) {
1120                                         bus_info[bus].bbar = bbar;
1121                                         bus_info[bus].phbid = phb;
1122                                 }
1123                         } else {
1124                                 bus_info[start_bus].bbar = bbar;
1125                                 bus_info[start_bus].phbid = phb;
1126                         }
1127                 }
1128         }
1129 
1130         return 0;
1131 
1132 error:
1133         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1134         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1135                 if (bus_info[bus].bbar)
1136                         iounmap(bus_info[bus].bbar);
1137 
1138         return ret;
1139 }
1140 
1141 static int __init calgary_init(void)
1142 {
1143         int ret;
1144         struct pci_dev *dev = NULL;
1145         struct calgary_bus_info *info;
1146 
1147         ret = calgary_locate_bbars();
1148         if (ret)
1149                 return ret;
1150 
1151         /* Purely for kdump kernel case */
1152         if (is_kdump_kernel())
1153                 get_tce_space_from_tar();
1154 
1155         do {
1156                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1157                 if (!dev)
1158                         break;
1159                 if (!is_cal_pci_dev(dev->device))
1160                         continue;
1161 
1162                 info = &bus_info[dev->bus->number];
1163                 if (info->translation_disabled) {
1164                         calgary_init_one_nontraslated(dev);
1165                         continue;
1166                 }
1167 
1168                 if (!info->tce_space && !translate_empty_slots)
1169                         continue;
1170 
1171                 ret = calgary_init_one(dev);
1172                 if (ret)
1173                         goto error;
1174         } while (1);
1175 
1176         dev = NULL;
1177         for_each_pci_dev(dev) {
1178                 struct iommu_table *tbl;
1179 
1180                 tbl = find_iommu_table(&dev->dev);
1181 
1182                 if (translation_enabled(tbl))
1183                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1184         }
1185 
1186         return ret;
1187 
1188 error:
1189         do {
1190                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1191                 if (!dev)
1192                         break;
1193                 if (!is_cal_pci_dev(dev->device))
1194                         continue;
1195 
1196                 info = &bus_info[dev->bus->number];
1197                 if (info->translation_disabled) {
1198                         pci_dev_put(dev);
1199                         continue;
1200                 }
1201                 if (!info->tce_space && !translate_empty_slots)
1202                         continue;
1203 
1204                 calgary_disable_translation(dev);
1205                 calgary_free_bus(dev);
1206                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1207                 dev->dev.archdata.dma_ops = NULL;
1208         } while (1);
1209 
1210         return ret;
1211 }
1212 
1213 static inline int __init determine_tce_table_size(u64 ram)
1214 {
1215         int ret;
1216 
1217         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1218                 return specified_table_size;
1219 
1220         /*
1221          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1222          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1223          * larger table size has twice as many entries, so shift the
1224          * max ram address by 13 to divide by 8K and then look at the
1225          * order of the result to choose between 0-7.
1226          */
1227         ret = get_order(ram >> 13);
1228         if (ret > TCE_TABLE_SIZE_8M)
1229                 ret = TCE_TABLE_SIZE_8M;
1230 
1231         return ret;
1232 }
1233 
1234 static int __init build_detail_arrays(void)
1235 {
1236         unsigned long ptr;
1237         unsigned numnodes, i;
1238         int scal_detail_size, rio_detail_size;
1239 
1240         numnodes = rio_table_hdr->num_scal_dev;
1241         if (numnodes > MAX_NUMNODES){
1242                 printk(KERN_WARNING
1243                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1244                         "but system has %d nodes.\n",
1245                         MAX_NUMNODES, numnodes);
1246                 return -ENODEV;
1247         }
1248 
1249         switch (rio_table_hdr->version){
1250         case 2:
1251                 scal_detail_size = 11;
1252                 rio_detail_size = 13;
1253                 break;
1254         case 3:
1255                 scal_detail_size = 12;
1256                 rio_detail_size = 15;
1257                 break;
1258         default:
1259                 printk(KERN_WARNING
1260                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1261                        rio_table_hdr->version);
1262                 return -EPROTO;
1263         }
1264 
1265         ptr = ((unsigned long)rio_table_hdr) + 3;
1266         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1267                 scal_devs[i] = (struct scal_detail *)ptr;
1268 
1269         for (i = 0; i < rio_table_hdr->num_rio_dev;
1270                     i++, ptr += rio_detail_size)
1271                 rio_devs[i] = (struct rio_detail *)ptr;
1272 
1273         return 0;
1274 }
1275 
1276 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1277 {
1278         int dev;
1279         u32 val;
1280 
1281         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1282                 /*
1283                  * FIXME: properly scan for devices accross the
1284                  * PCI-to-PCI bridge on every CalIOC2 port.
1285                  */
1286                 return 1;
1287         }
1288 
1289         for (dev = 1; dev < 8; dev++) {
1290                 val = read_pci_config(bus, dev, 0, 0);
1291                 if (val != 0xffffffff)
1292                         break;
1293         }
1294         return (val != 0xffffffff);
1295 }
1296 
1297 /*
1298  * calgary_init_bitmap_from_tce_table():
1299  * Funtion for kdump case. In the second/kdump kernel initialize
1300  * the bitmap based on the tce table entries obtained from first kernel
1301  */
1302 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1303 {
1304         u64 *tp;
1305         unsigned int index;
1306         tp = ((u64 *)tbl->it_base);
1307         for (index = 0 ; index < tbl->it_size; index++) {
1308                 if (*tp != 0x0)
1309                         set_bit(index, tbl->it_map);
1310                 tp++;
1311         }
1312 }
1313 
1314 /*
1315  * get_tce_space_from_tar():
1316  * Function for kdump case. Get the tce tables from first kernel
1317  * by reading the contents of the base adress register of calgary iommu
1318  */
1319 static void __init get_tce_space_from_tar(void)
1320 {
1321         int bus;
1322         void __iomem *target;
1323         unsigned long tce_space;
1324 
1325         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1326                 struct calgary_bus_info *info = &bus_info[bus];
1327                 unsigned short pci_device;
1328                 u32 val;
1329 
1330                 val = read_pci_config(bus, 0, 0, 0);
1331                 pci_device = (val & 0xFFFF0000) >> 16;
1332 
1333                 if (!is_cal_pci_dev(pci_device))
1334                         continue;
1335                 if (info->translation_disabled)
1336                         continue;
1337 
1338                 if (calgary_bus_has_devices(bus, pci_device) ||
1339                                                 translate_empty_slots) {
1340                         target = calgary_reg(bus_info[bus].bbar,
1341                                                 tar_offset(bus));
1342                         tce_space = be64_to_cpu(readq(target));
1343                         tce_space = tce_space & TAR_SW_BITS;
1344 
1345                         tce_space = tce_space & (~specified_table_size);
1346                         info->tce_space = (u64 *)__va(tce_space);
1347                 }
1348         }
1349         return;
1350 }
1351 
1352 void __init detect_calgary(void)
1353 {
1354         int bus;
1355         void *tbl;
1356         int calgary_found = 0;
1357         unsigned long ptr;
1358         unsigned int offset, prev_offset;
1359         int ret;
1360 
1361         /*
1362          * if the user specified iommu=off or iommu=soft or we found
1363          * another HW IOMMU already, bail out.
1364          */
1365         if (swiotlb || no_iommu || iommu_detected)
1366                 return;
1367 
1368         if (!use_calgary)
1369                 return;
1370 
1371         if (!early_pci_allowed())
1372                 return;
1373 
1374         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1375 
1376         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1377 
1378         rio_table_hdr = NULL;
1379         prev_offset = 0;
1380         offset = 0x180;
1381         /*
1382          * The next offset is stored in the 1st word.
1383          * Only parse up until the offset increases:
1384          */
1385         while (offset > prev_offset) {
1386                 /* The block id is stored in the 2nd word */
1387                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1388                         /* set the pointer past the offset & block id */
1389                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1390                         break;
1391                 }
1392                 prev_offset = offset;
1393                 offset = *((unsigned short *)(ptr + offset));
1394         }
1395         if (!rio_table_hdr) {
1396                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1397                        "in EBDA - bailing!\n");
1398                 return;
1399         }
1400 
1401         ret = build_detail_arrays();
1402         if (ret) {
1403                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1404                 return;
1405         }
1406 
1407         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1408                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1409 
1410         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1411                 struct calgary_bus_info *info = &bus_info[bus];
1412                 unsigned short pci_device;
1413                 u32 val;
1414 
1415                 val = read_pci_config(bus, 0, 0, 0);
1416                 pci_device = (val & 0xFFFF0000) >> 16;
1417 
1418                 if (!is_cal_pci_dev(pci_device))
1419                         continue;
1420 
1421                 if (info->translation_disabled)
1422                         continue;
1423 
1424                 if (calgary_bus_has_devices(bus, pci_device) ||
1425                     translate_empty_slots) {
1426                         /*
1427                          * If it is kdump kernel, find and use tce tables
1428                          * from first kernel, else allocate tce tables here
1429                          */
1430                         if (!is_kdump_kernel()) {
1431                                 tbl = alloc_tce_table();
1432                                 if (!tbl)
1433                                         goto cleanup;
1434                                 info->tce_space = tbl;
1435                         }
1436                         calgary_found = 1;
1437                 }
1438         }
1439 
1440         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1441                calgary_found ? "found" : "not found");
1442 
1443         if (calgary_found) {
1444                 iommu_detected = 1;
1445                 calgary_detected = 1;
1446                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1447                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1448                        specified_table_size);
1449 
1450                 /* swiotlb for devices that aren't behind the Calgary. */
1451                 if (max_pfn > MAX_DMA32_PFN)
1452                         swiotlb = 1;
1453         }
1454         return;
1455 
1456 cleanup:
1457         for (--bus; bus >= 0; --bus) {
1458                 struct calgary_bus_info *info = &bus_info[bus];
1459 
1460                 if (info->tce_space)
1461                         free_tce_table(info->tce_space);
1462         }
1463 }
1464 
1465 int __init calgary_iommu_init(void)
1466 {
1467         int ret;
1468 
1469         if (no_iommu || (swiotlb && !calgary_detected))
1470                 return -ENODEV;
1471 
1472         if (!calgary_detected)
1473                 return -ENODEV;
1474 
1475         /* ok, we're trying to use Calgary - let's roll */
1476         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1477 
1478         ret = calgary_init();
1479         if (ret) {
1480                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1481                        "falling back to no_iommu\n", ret);
1482                 return ret;
1483         }
1484 
1485         force_iommu = 1;
1486         bad_dma_address = 0x0;
1487         /* dma_ops is set to swiotlb or nommu */
1488         if (!dma_ops)
1489                 dma_ops = &nommu_dma_ops;
1490 
1491         return 0;
1492 }
1493 
1494 static int __init calgary_parse_options(char *p)
1495 {
1496         unsigned int bridge;
1497         size_t len;
1498         char* endp;
1499 
1500         while (*p) {
1501                 if (!strncmp(p, "64k", 3))
1502                         specified_table_size = TCE_TABLE_SIZE_64K;
1503                 else if (!strncmp(p, "128k", 4))
1504                         specified_table_size = TCE_TABLE_SIZE_128K;
1505                 else if (!strncmp(p, "256k", 4))
1506                         specified_table_size = TCE_TABLE_SIZE_256K;
1507                 else if (!strncmp(p, "512k", 4))
1508                         specified_table_size = TCE_TABLE_SIZE_512K;
1509                 else if (!strncmp(p, "1M", 2))
1510                         specified_table_size = TCE_TABLE_SIZE_1M;
1511                 else if (!strncmp(p, "2M", 2))
1512                         specified_table_size = TCE_TABLE_SIZE_2M;
1513                 else if (!strncmp(p, "4M", 2))
1514                         specified_table_size = TCE_TABLE_SIZE_4M;
1515                 else if (!strncmp(p, "8M", 2))
1516                         specified_table_size = TCE_TABLE_SIZE_8M;
1517 
1518                 len = strlen("translate_empty_slots");
1519                 if (!strncmp(p, "translate_empty_slots", len))
1520                         translate_empty_slots = 1;
1521 
1522                 len = strlen("disable");
1523                 if (!strncmp(p, "disable", len)) {
1524                         p += len;
1525                         if (*p == '=')
1526                                 ++p;
1527                         if (*p == '\0')
1528                                 break;
1529                         bridge = simple_strtoul(p, &endp, 0);
1530                         if (p == endp)
1531                                 break;
1532 
1533                         if (bridge < MAX_PHB_BUS_NUM) {
1534                                 printk(KERN_INFO "Calgary: disabling "
1535                                        "translation for PHB %#x\n", bridge);
1536                                 bus_info[bridge].translation_disabled = 1;
1537                         }
1538                 }
1539 
1540                 p = strpbrk(p, ",");
1541                 if (!p)
1542                         break;
1543 
1544                 p++; /* skip ',' */
1545         }
1546         return 1;
1547 }
1548 __setup("calgary=", calgary_parse_options);
1549 
1550 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1551 {
1552         struct iommu_table *tbl;
1553         unsigned int npages;
1554         int i;
1555 
1556         tbl = pci_iommu(dev->bus);
1557 
1558         for (i = 0; i < 4; i++) {
1559                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1560 
1561                 /* Don't give out TCEs that map MEM resources */
1562                 if (!(r->flags & IORESOURCE_MEM))
1563                         continue;
1564 
1565                 /* 0-based? we reserve the whole 1st MB anyway */
1566                 if (!r->start)
1567                         continue;
1568 
1569                 /* cover the whole region */
1570                 npages = (r->end - r->start) >> PAGE_SHIFT;
1571                 npages++;
1572 
1573                 iommu_range_reserve(tbl, r->start, npages);
1574         }
1575 }
1576 
1577 static int __init calgary_fixup_tce_spaces(void)
1578 {
1579         struct pci_dev *dev = NULL;
1580         struct calgary_bus_info *info;
1581 
1582         if (no_iommu || swiotlb || !calgary_detected)
1583                 return -ENODEV;
1584 
1585         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1586 
1587         do {
1588                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1589                 if (!dev)
1590                         break;
1591                 if (!is_cal_pci_dev(dev->device))
1592                         continue;
1593 
1594                 info = &bus_info[dev->bus->number];
1595                 if (info->translation_disabled)
1596                         continue;
1597 
1598                 if (!info->tce_space)
1599                         continue;
1600 
1601                 calgary_fixup_one_tce_space(dev);
1602 
1603         } while (1);
1604 
1605         return 0;
1606 }
1607 
1608 /*
1609  * We need to be call after pcibios_assign_resources (fs_initcall level)
1610  * and before device_initcall.
1611  */
1612 rootfs_initcall(calgary_fixup_tce_spaces);
1613 

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