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Linux/arch/x86/kernel/process.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  3 
  4 #include <linux/errno.h>
  5 #include <linux/kernel.h>
  6 #include <linux/mm.h>
  7 #include <linux/smp.h>
  8 #include <linux/prctl.h>
  9 #include <linux/slab.h>
 10 #include <linux/sched.h>
 11 #include <linux/sched/idle.h>
 12 #include <linux/sched/debug.h>
 13 #include <linux/sched/task.h>
 14 #include <linux/sched/task_stack.h>
 15 #include <linux/init.h>
 16 #include <linux/export.h>
 17 #include <linux/pm.h>
 18 #include <linux/tick.h>
 19 #include <linux/random.h>
 20 #include <linux/user-return-notifier.h>
 21 #include <linux/dmi.h>
 22 #include <linux/utsname.h>
 23 #include <linux/stackprotector.h>
 24 #include <linux/cpuidle.h>
 25 #include <linux/acpi.h>
 26 #include <linux/elf-randomize.h>
 27 #include <trace/events/power.h>
 28 #include <linux/hw_breakpoint.h>
 29 #include <asm/cpu.h>
 30 #include <asm/apic.h>
 31 #include <asm/syscalls.h>
 32 #include <linux/uaccess.h>
 33 #include <asm/mwait.h>
 34 #include <asm/fpu/internal.h>
 35 #include <asm/debugreg.h>
 36 #include <asm/nmi.h>
 37 #include <asm/tlbflush.h>
 38 #include <asm/mce.h>
 39 #include <asm/vm86.h>
 40 #include <asm/switch_to.h>
 41 #include <asm/desc.h>
 42 #include <asm/prctl.h>
 43 #include <asm/spec-ctrl.h>
 44 #include <asm/io_bitmap.h>
 45 #include <asm/proto.h>
 46 
 47 #include "process.h"
 48 
 49 /*
 50  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 51  * no more per-task TSS's. The TSS size is kept cacheline-aligned
 52  * so they are allowed to end up in the .data..cacheline_aligned
 53  * section. Since TSS's are completely CPU-local, we want them
 54  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 55  */
 56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
 57         .x86_tss = {
 58                 /*
 59                  * .sp0 is only used when entering ring 0 from a lower
 60                  * privilege level.  Since the init task never runs anything
 61                  * but ring 0 code, there is no need for a valid value here.
 62                  * Poison it.
 63                  */
 64                 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
 65 
 66                 /*
 67                  * .sp1 is cpu_current_top_of_stack.  The init task never
 68                  * runs user code, but cpu_current_top_of_stack should still
 69                  * be well defined before the first context switch.
 70                  */
 71                 .sp1 = TOP_OF_INIT_STACK,
 72 
 73 #ifdef CONFIG_X86_32
 74                 .ss0 = __KERNEL_DS,
 75                 .ss1 = __KERNEL_CS,
 76 #endif
 77                 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
 78          },
 79 };
 80 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
 81 
 82 DEFINE_PER_CPU(bool, __tss_limit_invalid);
 83 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
 84 
 85 /*
 86  * this gets called so that we can store lazy state into memory and copy the
 87  * current task into the new thread.
 88  */
 89 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 90 {
 91         memcpy(dst, src, arch_task_struct_size);
 92 #ifdef CONFIG_VM86
 93         dst->thread.vm86 = NULL;
 94 #endif
 95 
 96         return fpu__copy(dst, src);
 97 }
 98 
 99 /*
100  * Free thread data structures etc..
101  */
102 void exit_thread(struct task_struct *tsk)
103 {
104         struct thread_struct *t = &tsk->thread;
105         struct fpu *fpu = &t->fpu;
106 
107         if (test_thread_flag(TIF_IO_BITMAP))
108                 io_bitmap_exit(tsk);
109 
110         free_vm86(t);
111 
112         fpu__drop(fpu);
113 }
114 
115 static int set_new_tls(struct task_struct *p, unsigned long tls)
116 {
117         struct user_desc __user *utls = (struct user_desc __user *)tls;
118 
119         if (in_ia32_syscall())
120                 return do_set_thread_area(p, -1, utls, 0);
121         else
122                 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
123 }
124 
125 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
126                     unsigned long arg, struct task_struct *p, unsigned long tls)
127 {
128         struct inactive_task_frame *frame;
129         struct fork_frame *fork_frame;
130         struct pt_regs *childregs;
131         int ret = 0;
132 
133         childregs = task_pt_regs(p);
134         fork_frame = container_of(childregs, struct fork_frame, regs);
135         frame = &fork_frame->frame;
136 
137         frame->bp = 0;
138         frame->ret_addr = (unsigned long) ret_from_fork;
139         p->thread.sp = (unsigned long) fork_frame;
140         p->thread.io_bitmap = NULL;
141         memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
142 
143 #ifdef CONFIG_X86_64
144         savesegment(gs, p->thread.gsindex);
145         p->thread.gsbase = p->thread.gsindex ? 0 : current->thread.gsbase;
146         savesegment(fs, p->thread.fsindex);
147         p->thread.fsbase = p->thread.fsindex ? 0 : current->thread.fsbase;
148         savesegment(es, p->thread.es);
149         savesegment(ds, p->thread.ds);
150 #else
151         p->thread.sp0 = (unsigned long) (childregs + 1);
152         /*
153          * Clear all status flags including IF and set fixed bit. 64bit
154          * does not have this initialization as the frame does not contain
155          * flags. The flags consistency (especially vs. AC) is there
156          * ensured via objtool, which lacks 32bit support.
157          */
158         frame->flags = X86_EFLAGS_FIXED;
159 #endif
160 
161         /* Kernel thread ? */
162         if (unlikely(p->flags & PF_KTHREAD)) {
163                 memset(childregs, 0, sizeof(struct pt_regs));
164                 kthread_frame_init(frame, sp, arg);
165                 return 0;
166         }
167 
168         frame->bx = 0;
169         *childregs = *current_pt_regs();
170         childregs->ax = 0;
171         if (sp)
172                 childregs->sp = sp;
173 
174 #ifdef CONFIG_X86_32
175         task_user_gs(p) = get_user_gs(current_pt_regs());
176 #endif
177 
178         /* Set a new TLS for the child thread? */
179         if (clone_flags & CLONE_SETTLS)
180                 ret = set_new_tls(p, tls);
181 
182         if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
183                 io_bitmap_share(p);
184 
185         return ret;
186 }
187 
188 void flush_thread(void)
189 {
190         struct task_struct *tsk = current;
191 
192         flush_ptrace_hw_breakpoint(tsk);
193         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
194 
195         fpu__clear(&tsk->thread.fpu);
196 }
197 
198 void disable_TSC(void)
199 {
200         preempt_disable();
201         if (!test_and_set_thread_flag(TIF_NOTSC))
202                 /*
203                  * Must flip the CPU state synchronously with
204                  * TIF_NOTSC in the current running context.
205                  */
206                 cr4_set_bits(X86_CR4_TSD);
207         preempt_enable();
208 }
209 
210 static void enable_TSC(void)
211 {
212         preempt_disable();
213         if (test_and_clear_thread_flag(TIF_NOTSC))
214                 /*
215                  * Must flip the CPU state synchronously with
216                  * TIF_NOTSC in the current running context.
217                  */
218                 cr4_clear_bits(X86_CR4_TSD);
219         preempt_enable();
220 }
221 
222 int get_tsc_mode(unsigned long adr)
223 {
224         unsigned int val;
225 
226         if (test_thread_flag(TIF_NOTSC))
227                 val = PR_TSC_SIGSEGV;
228         else
229                 val = PR_TSC_ENABLE;
230 
231         return put_user(val, (unsigned int __user *)adr);
232 }
233 
234 int set_tsc_mode(unsigned int val)
235 {
236         if (val == PR_TSC_SIGSEGV)
237                 disable_TSC();
238         else if (val == PR_TSC_ENABLE)
239                 enable_TSC();
240         else
241                 return -EINVAL;
242 
243         return 0;
244 }
245 
246 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
247 
248 static void set_cpuid_faulting(bool on)
249 {
250         u64 msrval;
251 
252         msrval = this_cpu_read(msr_misc_features_shadow);
253         msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
254         msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
255         this_cpu_write(msr_misc_features_shadow, msrval);
256         wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
257 }
258 
259 static void disable_cpuid(void)
260 {
261         preempt_disable();
262         if (!test_and_set_thread_flag(TIF_NOCPUID)) {
263                 /*
264                  * Must flip the CPU state synchronously with
265                  * TIF_NOCPUID in the current running context.
266                  */
267                 set_cpuid_faulting(true);
268         }
269         preempt_enable();
270 }
271 
272 static void enable_cpuid(void)
273 {
274         preempt_disable();
275         if (test_and_clear_thread_flag(TIF_NOCPUID)) {
276                 /*
277                  * Must flip the CPU state synchronously with
278                  * TIF_NOCPUID in the current running context.
279                  */
280                 set_cpuid_faulting(false);
281         }
282         preempt_enable();
283 }
284 
285 static int get_cpuid_mode(void)
286 {
287         return !test_thread_flag(TIF_NOCPUID);
288 }
289 
290 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
291 {
292         if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
293                 return -ENODEV;
294 
295         if (cpuid_enabled)
296                 enable_cpuid();
297         else
298                 disable_cpuid();
299 
300         return 0;
301 }
302 
303 /*
304  * Called immediately after a successful exec.
305  */
306 void arch_setup_new_exec(void)
307 {
308         /* If cpuid was previously disabled for this task, re-enable it. */
309         if (test_thread_flag(TIF_NOCPUID))
310                 enable_cpuid();
311 
312         /*
313          * Don't inherit TIF_SSBD across exec boundary when
314          * PR_SPEC_DISABLE_NOEXEC is used.
315          */
316         if (test_thread_flag(TIF_SSBD) &&
317             task_spec_ssb_noexec(current)) {
318                 clear_thread_flag(TIF_SSBD);
319                 task_clear_spec_ssb_disable(current);
320                 task_clear_spec_ssb_noexec(current);
321                 speculation_ctrl_update(task_thread_info(current)->flags);
322         }
323 }
324 
325 #ifdef CONFIG_X86_IOPL_IOPERM
326 static inline void tss_invalidate_io_bitmap(struct tss_struct *tss)
327 {
328         /*
329          * Invalidate the I/O bitmap by moving io_bitmap_base outside the
330          * TSS limit so any subsequent I/O access from user space will
331          * trigger a #GP.
332          *
333          * This is correct even when VMEXIT rewrites the TSS limit
334          * to 0x67 as the only requirement is that the base points
335          * outside the limit.
336          */
337         tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
338 }
339 
340 static inline void switch_to_bitmap(unsigned long tifp)
341 {
342         /*
343          * Invalidate I/O bitmap if the previous task used it. This prevents
344          * any possible leakage of an active I/O bitmap.
345          *
346          * If the next task has an I/O bitmap it will handle it on exit to
347          * user mode.
348          */
349         if (tifp & _TIF_IO_BITMAP)
350                 tss_invalidate_io_bitmap(this_cpu_ptr(&cpu_tss_rw));
351 }
352 
353 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
354 {
355         /*
356          * Copy at least the byte range of the incoming tasks bitmap which
357          * covers the permitted I/O ports.
358          *
359          * If the previous task which used an I/O bitmap had more bits
360          * permitted, then the copy needs to cover those as well so they
361          * get turned off.
362          */
363         memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
364                max(tss->io_bitmap.prev_max, iobm->max));
365 
366         /*
367          * Store the new max and the sequence number of this bitmap
368          * and a pointer to the bitmap itself.
369          */
370         tss->io_bitmap.prev_max = iobm->max;
371         tss->io_bitmap.prev_sequence = iobm->sequence;
372 }
373 
374 /**
375  * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376  */
377 void native_tss_update_io_bitmap(void)
378 {
379         struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
380         struct thread_struct *t = &current->thread;
381         u16 *base = &tss->x86_tss.io_bitmap_base;
382 
383         if (!test_thread_flag(TIF_IO_BITMAP)) {
384                 tss_invalidate_io_bitmap(tss);
385                 return;
386         }
387 
388         if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
389                 *base = IO_BITMAP_OFFSET_VALID_ALL;
390         } else {
391                 struct io_bitmap *iobm = t->io_bitmap;
392 
393                 /*
394                  * Only copy bitmap data when the sequence number differs. The
395                  * update time is accounted to the incoming task.
396                  */
397                 if (tss->io_bitmap.prev_sequence != iobm->sequence)
398                         tss_copy_io_bitmap(tss, iobm);
399 
400                 /* Enable the bitmap */
401                 *base = IO_BITMAP_OFFSET_VALID_MAP;
402         }
403 
404         /*
405          * Make sure that the TSS limit is covering the IO bitmap. It might have
406          * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
407          * access from user space to trigger a #GP because tbe bitmap is outside
408          * the TSS limit.
409          */
410         refresh_tss_limit();
411 }
412 #else /* CONFIG_X86_IOPL_IOPERM */
413 static inline void switch_to_bitmap(unsigned long tifp) { }
414 #endif
415 
416 #ifdef CONFIG_SMP
417 
418 struct ssb_state {
419         struct ssb_state        *shared_state;
420         raw_spinlock_t          lock;
421         unsigned int            disable_state;
422         unsigned long           local_state;
423 };
424 
425 #define LSTATE_SSB      0
426 
427 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
428 
429 void speculative_store_bypass_ht_init(void)
430 {
431         struct ssb_state *st = this_cpu_ptr(&ssb_state);
432         unsigned int this_cpu = smp_processor_id();
433         unsigned int cpu;
434 
435         st->local_state = 0;
436 
437         /*
438          * Shared state setup happens once on the first bringup
439          * of the CPU. It's not destroyed on CPU hotunplug.
440          */
441         if (st->shared_state)
442                 return;
443 
444         raw_spin_lock_init(&st->lock);
445 
446         /*
447          * Go over HT siblings and check whether one of them has set up the
448          * shared state pointer already.
449          */
450         for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
451                 if (cpu == this_cpu)
452                         continue;
453 
454                 if (!per_cpu(ssb_state, cpu).shared_state)
455                         continue;
456 
457                 /* Link it to the state of the sibling: */
458                 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
459                 return;
460         }
461 
462         /*
463          * First HT sibling to come up on the core.  Link shared state of
464          * the first HT sibling to itself. The siblings on the same core
465          * which come up later will see the shared state pointer and link
466          * themself to the state of this CPU.
467          */
468         st->shared_state = st;
469 }
470 
471 /*
472  * Logic is: First HT sibling enables SSBD for both siblings in the core
473  * and last sibling to disable it, disables it for the whole core. This how
474  * MSR_SPEC_CTRL works in "hardware":
475  *
476  *  CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
477  */
478 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
479 {
480         struct ssb_state *st = this_cpu_ptr(&ssb_state);
481         u64 msr = x86_amd_ls_cfg_base;
482 
483         if (!static_cpu_has(X86_FEATURE_ZEN)) {
484                 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
485                 wrmsrl(MSR_AMD64_LS_CFG, msr);
486                 return;
487         }
488 
489         if (tifn & _TIF_SSBD) {
490                 /*
491                  * Since this can race with prctl(), block reentry on the
492                  * same CPU.
493                  */
494                 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
495                         return;
496 
497                 msr |= x86_amd_ls_cfg_ssbd_mask;
498 
499                 raw_spin_lock(&st->shared_state->lock);
500                 /* First sibling enables SSBD: */
501                 if (!st->shared_state->disable_state)
502                         wrmsrl(MSR_AMD64_LS_CFG, msr);
503                 st->shared_state->disable_state++;
504                 raw_spin_unlock(&st->shared_state->lock);
505         } else {
506                 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
507                         return;
508 
509                 raw_spin_lock(&st->shared_state->lock);
510                 st->shared_state->disable_state--;
511                 if (!st->shared_state->disable_state)
512                         wrmsrl(MSR_AMD64_LS_CFG, msr);
513                 raw_spin_unlock(&st->shared_state->lock);
514         }
515 }
516 #else
517 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
518 {
519         u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
520 
521         wrmsrl(MSR_AMD64_LS_CFG, msr);
522 }
523 #endif
524 
525 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
526 {
527         /*
528          * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
529          * so ssbd_tif_to_spec_ctrl() just works.
530          */
531         wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
532 }
533 
534 /*
535  * Update the MSRs managing speculation control, during context switch.
536  *
537  * tifp: Previous task's thread flags
538  * tifn: Next task's thread flags
539  */
540 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
541                                                       unsigned long tifn)
542 {
543         unsigned long tif_diff = tifp ^ tifn;
544         u64 msr = x86_spec_ctrl_base;
545         bool updmsr = false;
546 
547         lockdep_assert_irqs_disabled();
548 
549         /* Handle change of TIF_SSBD depending on the mitigation method. */
550         if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
551                 if (tif_diff & _TIF_SSBD)
552                         amd_set_ssb_virt_state(tifn);
553         } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
554                 if (tif_diff & _TIF_SSBD)
555                         amd_set_core_ssb_state(tifn);
556         } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
557                    static_cpu_has(X86_FEATURE_AMD_SSBD)) {
558                 updmsr |= !!(tif_diff & _TIF_SSBD);
559                 msr |= ssbd_tif_to_spec_ctrl(tifn);
560         }
561 
562         /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
563         if (IS_ENABLED(CONFIG_SMP) &&
564             static_branch_unlikely(&switch_to_cond_stibp)) {
565                 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
566                 msr |= stibp_tif_to_spec_ctrl(tifn);
567         }
568 
569         if (updmsr)
570                 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
571 }
572 
573 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
574 {
575         if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
576                 if (task_spec_ssb_disable(tsk))
577                         set_tsk_thread_flag(tsk, TIF_SSBD);
578                 else
579                         clear_tsk_thread_flag(tsk, TIF_SSBD);
580 
581                 if (task_spec_ib_disable(tsk))
582                         set_tsk_thread_flag(tsk, TIF_SPEC_IB);
583                 else
584                         clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
585         }
586         /* Return the updated threadinfo flags*/
587         return task_thread_info(tsk)->flags;
588 }
589 
590 void speculation_ctrl_update(unsigned long tif)
591 {
592         unsigned long flags;
593 
594         /* Forced update. Make sure all relevant TIF flags are different */
595         local_irq_save(flags);
596         __speculation_ctrl_update(~tif, tif);
597         local_irq_restore(flags);
598 }
599 
600 /* Called from seccomp/prctl update */
601 void speculation_ctrl_update_current(void)
602 {
603         preempt_disable();
604         speculation_ctrl_update(speculation_ctrl_update_tif(current));
605         preempt_enable();
606 }
607 
608 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
609 {
610         unsigned long tifp, tifn;
611 
612         tifn = READ_ONCE(task_thread_info(next_p)->flags);
613         tifp = READ_ONCE(task_thread_info(prev_p)->flags);
614 
615         switch_to_bitmap(tifp);
616 
617         propagate_user_return_notify(prev_p, next_p);
618 
619         if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
620             arch_has_block_step()) {
621                 unsigned long debugctl, msk;
622 
623                 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
624                 debugctl &= ~DEBUGCTLMSR_BTF;
625                 msk = tifn & _TIF_BLOCKSTEP;
626                 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
627                 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
628         }
629 
630         if ((tifp ^ tifn) & _TIF_NOTSC)
631                 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
632 
633         if ((tifp ^ tifn) & _TIF_NOCPUID)
634                 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
635 
636         if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
637                 __speculation_ctrl_update(tifp, tifn);
638         } else {
639                 speculation_ctrl_update_tif(prev_p);
640                 tifn = speculation_ctrl_update_tif(next_p);
641 
642                 /* Enforce MSR update to ensure consistent state */
643                 __speculation_ctrl_update(~tifn, tifn);
644         }
645 }
646 
647 /*
648  * Idle related variables and functions
649  */
650 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
651 EXPORT_SYMBOL(boot_option_idle_override);
652 
653 static void (*x86_idle)(void);
654 
655 #ifndef CONFIG_SMP
656 static inline void play_dead(void)
657 {
658         BUG();
659 }
660 #endif
661 
662 void arch_cpu_idle_enter(void)
663 {
664         tsc_verify_tsc_adjust(false);
665         local_touch_nmi();
666 }
667 
668 void arch_cpu_idle_dead(void)
669 {
670         play_dead();
671 }
672 
673 /*
674  * Called from the generic idle code.
675  */
676 void arch_cpu_idle(void)
677 {
678         x86_idle();
679 }
680 
681 /*
682  * We use this if we don't have any better idle routine..
683  */
684 void __cpuidle default_idle(void)
685 {
686         trace_cpu_idle_rcuidle(1, smp_processor_id());
687         safe_halt();
688         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
689 }
690 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
691 EXPORT_SYMBOL(default_idle);
692 #endif
693 
694 #ifdef CONFIG_XEN
695 bool xen_set_default_idle(void)
696 {
697         bool ret = !!x86_idle;
698 
699         x86_idle = default_idle;
700 
701         return ret;
702 }
703 #endif
704 
705 void stop_this_cpu(void *dummy)
706 {
707         local_irq_disable();
708         /*
709          * Remove this CPU:
710          */
711         set_cpu_online(smp_processor_id(), false);
712         disable_local_APIC();
713         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
714 
715         /*
716          * Use wbinvd on processors that support SME. This provides support
717          * for performing a successful kexec when going from SME inactive
718          * to SME active (or vice-versa). The cache must be cleared so that
719          * if there are entries with the same physical address, both with and
720          * without the encryption bit, they don't race each other when flushed
721          * and potentially end up with the wrong entry being committed to
722          * memory.
723          */
724         if (boot_cpu_has(X86_FEATURE_SME))
725                 native_wbinvd();
726         for (;;) {
727                 /*
728                  * Use native_halt() so that memory contents don't change
729                  * (stack usage and variables) after possibly issuing the
730                  * native_wbinvd() above.
731                  */
732                 native_halt();
733         }
734 }
735 
736 /*
737  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
738  * states (local apic timer and TSC stop).
739  */
740 static void amd_e400_idle(void)
741 {
742         /*
743          * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
744          * gets set after static_cpu_has() places have been converted via
745          * alternatives.
746          */
747         if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
748                 default_idle();
749                 return;
750         }
751 
752         tick_broadcast_enter();
753 
754         default_idle();
755 
756         /*
757          * The switch back from broadcast mode needs to be called with
758          * interrupts disabled.
759          */
760         local_irq_disable();
761         tick_broadcast_exit();
762         local_irq_enable();
763 }
764 
765 /*
766  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
767  * We can't rely on cpuidle installing MWAIT, because it will not load
768  * on systems that support only C1 -- so the boot default must be MWAIT.
769  *
770  * Some AMD machines are the opposite, they depend on using HALT.
771  *
772  * So for default C1, which is used during boot until cpuidle loads,
773  * use MWAIT-C1 on Intel HW that has it, else use HALT.
774  */
775 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
776 {
777         if (c->x86_vendor != X86_VENDOR_INTEL)
778                 return 0;
779 
780         if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
781                 return 0;
782 
783         return 1;
784 }
785 
786 /*
787  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
788  * with interrupts enabled and no flags, which is backwards compatible with the
789  * original MWAIT implementation.
790  */
791 static __cpuidle void mwait_idle(void)
792 {
793         if (!current_set_polling_and_test()) {
794                 trace_cpu_idle_rcuidle(1, smp_processor_id());
795                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
796                         mb(); /* quirk */
797                         clflush((void *)&current_thread_info()->flags);
798                         mb(); /* quirk */
799                 }
800 
801                 __monitor((void *)&current_thread_info()->flags, 0, 0);
802                 if (!need_resched())
803                         __sti_mwait(0, 0);
804                 else
805                         local_irq_enable();
806                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
807         } else {
808                 local_irq_enable();
809         }
810         __current_clr_polling();
811 }
812 
813 void select_idle_routine(const struct cpuinfo_x86 *c)
814 {
815 #ifdef CONFIG_SMP
816         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
817                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
818 #endif
819         if (x86_idle || boot_option_idle_override == IDLE_POLL)
820                 return;
821 
822         if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
823                 pr_info("using AMD E400 aware idle routine\n");
824                 x86_idle = amd_e400_idle;
825         } else if (prefer_mwait_c1_over_halt(c)) {
826                 pr_info("using mwait in idle threads\n");
827                 x86_idle = mwait_idle;
828         } else
829                 x86_idle = default_idle;
830 }
831 
832 void amd_e400_c1e_apic_setup(void)
833 {
834         if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
835                 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
836                 local_irq_disable();
837                 tick_broadcast_force();
838                 local_irq_enable();
839         }
840 }
841 
842 void __init arch_post_acpi_subsys_init(void)
843 {
844         u32 lo, hi;
845 
846         if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
847                 return;
848 
849         /*
850          * AMD E400 detection needs to happen after ACPI has been enabled. If
851          * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
852          * MSR_K8_INT_PENDING_MSG.
853          */
854         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
855         if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
856                 return;
857 
858         boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
859 
860         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
861                 mark_tsc_unstable("TSC halt in AMD C1E");
862         pr_info("System has AMD C1E enabled\n");
863 }
864 
865 static int __init idle_setup(char *str)
866 {
867         if (!str)
868                 return -EINVAL;
869 
870         if (!strcmp(str, "poll")) {
871                 pr_info("using polling idle threads\n");
872                 boot_option_idle_override = IDLE_POLL;
873                 cpu_idle_poll_ctrl(true);
874         } else if (!strcmp(str, "halt")) {
875                 /*
876                  * When the boot option of idle=halt is added, halt is
877                  * forced to be used for CPU idle. In such case CPU C2/C3
878                  * won't be used again.
879                  * To continue to load the CPU idle driver, don't touch
880                  * the boot_option_idle_override.
881                  */
882                 x86_idle = default_idle;
883                 boot_option_idle_override = IDLE_HALT;
884         } else if (!strcmp(str, "nomwait")) {
885                 /*
886                  * If the boot option of "idle=nomwait" is added,
887                  * it means that mwait will be disabled for CPU C2/C3
888                  * states. In such case it won't touch the variable
889                  * of boot_option_idle_override.
890                  */
891                 boot_option_idle_override = IDLE_NOMWAIT;
892         } else
893                 return -1;
894 
895         return 0;
896 }
897 early_param("idle", idle_setup);
898 
899 unsigned long arch_align_stack(unsigned long sp)
900 {
901         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
902                 sp -= get_random_int() % 8192;
903         return sp & ~0xf;
904 }
905 
906 unsigned long arch_randomize_brk(struct mm_struct *mm)
907 {
908         return randomize_page(mm->brk, 0x02000000);
909 }
910 
911 /*
912  * Called from fs/proc with a reference on @p to find the function
913  * which called into schedule(). This needs to be done carefully
914  * because the task might wake up and we might look at a stack
915  * changing under us.
916  */
917 unsigned long get_wchan(struct task_struct *p)
918 {
919         unsigned long start, bottom, top, sp, fp, ip, ret = 0;
920         int count = 0;
921 
922         if (p == current || p->state == TASK_RUNNING)
923                 return 0;
924 
925         if (!try_get_task_stack(p))
926                 return 0;
927 
928         start = (unsigned long)task_stack_page(p);
929         if (!start)
930                 goto out;
931 
932         /*
933          * Layout of the stack page:
934          *
935          * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
936          * PADDING
937          * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
938          * stack
939          * ----------- bottom = start
940          *
941          * The tasks stack pointer points at the location where the
942          * framepointer is stored. The data on the stack is:
943          * ... IP FP ... IP FP
944          *
945          * We need to read FP and IP, so we need to adjust the upper
946          * bound by another unsigned long.
947          */
948         top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
949         top -= 2 * sizeof(unsigned long);
950         bottom = start;
951 
952         sp = READ_ONCE(p->thread.sp);
953         if (sp < bottom || sp > top)
954                 goto out;
955 
956         fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
957         do {
958                 if (fp < bottom || fp > top)
959                         goto out;
960                 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
961                 if (!in_sched_functions(ip)) {
962                         ret = ip;
963                         goto out;
964                 }
965                 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
966         } while (count++ < 16 && p->state != TASK_RUNNING);
967 
968 out:
969         put_task_stack(p);
970         return ret;
971 }
972 
973 long do_arch_prctl_common(struct task_struct *task, int option,
974                           unsigned long cpuid_enabled)
975 {
976         switch (option) {
977         case ARCH_GET_CPUID:
978                 return get_cpuid_mode();
979         case ARCH_SET_CPUID:
980                 return set_cpuid_mode(task, cpuid_enabled);
981         }
982 
983         return -EINVAL;
984 }
985 

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