1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/timer.h>
8 #include <linux/acpi_pmtmr.h>
9 #include <linux/cpufreq.h>
10 #include <linux/delay.h>
11 #include <linux/clocksource.h>
12 #include <linux/percpu.h>
13 #include <linux/timex.h>
14
15 #include <asm/hpet.h>
16 #include <asm/timer.h>
17 #include <asm/vgtod.h>
18 #include <asm/time.h>
19 #include <asm/delay.h>
20 #include <asm/hypervisor.h>
21 #include <asm/nmi.h>
22 #include <asm/x86_init.h>
23 #include <asm/geode.h>
24
25 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
26 EXPORT_SYMBOL(cpu_khz);
27
28 unsigned int __read_mostly tsc_khz;
29 EXPORT_SYMBOL(tsc_khz);
30
31 /*
32 * TSC can be unstable due to cpufreq or due to unsynced TSCs
33 */
34 static int __read_mostly tsc_unstable;
35
36 /* native_sched_clock() is called before tsc_init(), so
37 we must start with the TSC soft disabled to prevent
38 erroneous rdtsc usage on !cpu_has_tsc processors */
39 static int __read_mostly tsc_disabled = -1;
40
41 int tsc_clocksource_reliable;
42 /*
43 * Scheduler clock - returns current time in nanosec units.
44 */
45 u64 native_sched_clock(void)
46 {
47 u64 this_offset;
48
49 /*
50 * Fall back to jiffies if there's no TSC available:
51 * ( But note that we still use it if the TSC is marked
52 * unstable. We do this because unlike Time Of Day,
53 * the scheduler clock tolerates small errors and it's
54 * very important for it to be as fast as the platform
55 * can achieve it. )
56 */
57 if (unlikely(tsc_disabled)) {
58 /* No locking but a rare wrong value is not a big deal: */
59 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
60 }
61
62 /* read the Time Stamp Counter: */
63 rdtscll(this_offset);
64
65 /* return the value in ns */
66 return __cycles_2_ns(this_offset);
67 }
68
69 /* We need to define a real function for sched_clock, to override the
70 weak default version */
71 #ifdef CONFIG_PARAVIRT
72 unsigned long long sched_clock(void)
73 {
74 return paravirt_sched_clock();
75 }
76 #else
77 unsigned long long
78 sched_clock(void) __attribute__((alias("native_sched_clock")));
79 #endif
80
81 unsigned long long native_read_tsc(void)
82 {
83 return __native_read_tsc();
84 }
85 EXPORT_SYMBOL(native_read_tsc);
86
87 int check_tsc_unstable(void)
88 {
89 return tsc_unstable;
90 }
91 EXPORT_SYMBOL_GPL(check_tsc_unstable);
92
93 #ifdef CONFIG_X86_TSC
94 int __init notsc_setup(char *str)
95 {
96 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
97 tsc_disabled = 1;
98 return 1;
99 }
100 #else
101 /*
102 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
103 * in cpu/common.c
104 */
105 int __init notsc_setup(char *str)
106 {
107 setup_clear_cpu_cap(X86_FEATURE_TSC);
108 return 1;
109 }
110 #endif
111
112 __setup("notsc", notsc_setup);
113
114 static int no_sched_irq_time;
115
116 static int __init tsc_setup(char *str)
117 {
118 if (!strcmp(str, "reliable"))
119 tsc_clocksource_reliable = 1;
120 if (!strncmp(str, "noirqtime", 9))
121 no_sched_irq_time = 1;
122 return 1;
123 }
124
125 __setup("tsc=", tsc_setup);
126
127 #define MAX_RETRIES 5
128 #define SMI_TRESHOLD 50000
129
130 /*
131 * Read TSC and the reference counters. Take care of SMI disturbance
132 */
133 static u64 tsc_read_refs(u64 *p, int hpet)
134 {
135 u64 t1, t2;
136 int i;
137
138 for (i = 0; i < MAX_RETRIES; i++) {
139 t1 = get_cycles();
140 if (hpet)
141 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
142 else
143 *p = acpi_pm_read_early();
144 t2 = get_cycles();
145 if ((t2 - t1) < SMI_TRESHOLD)
146 return t2;
147 }
148 return ULLONG_MAX;
149 }
150
151 /*
152 * Calculate the TSC frequency from HPET reference
153 */
154 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
155 {
156 u64 tmp;
157
158 if (hpet2 < hpet1)
159 hpet2 += 0x100000000ULL;
160 hpet2 -= hpet1;
161 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
162 do_div(tmp, 1000000);
163 do_div(deltatsc, tmp);
164
165 return (unsigned long) deltatsc;
166 }
167
168 /*
169 * Calculate the TSC frequency from PMTimer reference
170 */
171 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
172 {
173 u64 tmp;
174
175 if (!pm1 && !pm2)
176 return ULONG_MAX;
177
178 if (pm2 < pm1)
179 pm2 += (u64)ACPI_PM_OVRRUN;
180 pm2 -= pm1;
181 tmp = pm2 * 1000000000LL;
182 do_div(tmp, PMTMR_TICKS_PER_SEC);
183 do_div(deltatsc, tmp);
184
185 return (unsigned long) deltatsc;
186 }
187
188 #define CAL_MS 10
189 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
190 #define CAL_PIT_LOOPS 1000
191
192 #define CAL2_MS 50
193 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
194 #define CAL2_PIT_LOOPS 5000
195
196
197 /*
198 * Try to calibrate the TSC against the Programmable
199 * Interrupt Timer and return the frequency of the TSC
200 * in kHz.
201 *
202 * Return ULONG_MAX on failure to calibrate.
203 */
204 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
205 {
206 u64 tsc, t1, t2, delta;
207 unsigned long tscmin, tscmax;
208 int pitcnt;
209
210 /* Set the Gate high, disable speaker */
211 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
212
213 /*
214 * Setup CTC channel 2* for mode 0, (interrupt on terminal
215 * count mode), binary count. Set the latch register to 50ms
216 * (LSB then MSB) to begin countdown.
217 */
218 outb(0xb0, 0x43);
219 outb(latch & 0xff, 0x42);
220 outb(latch >> 8, 0x42);
221
222 tsc = t1 = t2 = get_cycles();
223
224 pitcnt = 0;
225 tscmax = 0;
226 tscmin = ULONG_MAX;
227 while ((inb(0x61) & 0x20) == 0) {
228 t2 = get_cycles();
229 delta = t2 - tsc;
230 tsc = t2;
231 if ((unsigned long) delta < tscmin)
232 tscmin = (unsigned int) delta;
233 if ((unsigned long) delta > tscmax)
234 tscmax = (unsigned int) delta;
235 pitcnt++;
236 }
237
238 /*
239 * Sanity checks:
240 *
241 * If we were not able to read the PIT more than loopmin
242 * times, then we have been hit by a massive SMI
243 *
244 * If the maximum is 10 times larger than the minimum,
245 * then we got hit by an SMI as well.
246 */
247 if (pitcnt < loopmin || tscmax > 10 * tscmin)
248 return ULONG_MAX;
249
250 /* Calculate the PIT value */
251 delta = t2 - t1;
252 do_div(delta, ms);
253 return delta;
254 }
255
256 /*
257 * This reads the current MSB of the PIT counter, and
258 * checks if we are running on sufficiently fast and
259 * non-virtualized hardware.
260 *
261 * Our expectations are:
262 *
263 * - the PIT is running at roughly 1.19MHz
264 *
265 * - each IO is going to take about 1us on real hardware,
266 * but we allow it to be much faster (by a factor of 10) or
267 * _slightly_ slower (ie we allow up to a 2us read+counter
268 * update - anything else implies a unacceptably slow CPU
269 * or PIT for the fast calibration to work.
270 *
271 * - with 256 PIT ticks to read the value, we have 214us to
272 * see the same MSB (and overhead like doing a single TSC
273 * read per MSB value etc).
274 *
275 * - We're doing 2 reads per loop (LSB, MSB), and we expect
276 * them each to take about a microsecond on real hardware.
277 * So we expect a count value of around 100. But we'll be
278 * generous, and accept anything over 50.
279 *
280 * - if the PIT is stuck, and we see *many* more reads, we
281 * return early (and the next caller of pit_expect_msb()
282 * then consider it a failure when they don't see the
283 * next expected value).
284 *
285 * These expectations mean that we know that we have seen the
286 * transition from one expected value to another with a fairly
287 * high accuracy, and we didn't miss any events. We can thus
288 * use the TSC value at the transitions to calculate a pretty
289 * good value for the TSC frequencty.
290 */
291 static inline int pit_verify_msb(unsigned char val)
292 {
293 /* Ignore LSB */
294 inb(0x42);
295 return inb(0x42) == val;
296 }
297
298 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
299 {
300 int count;
301 u64 tsc = 0, prev_tsc = 0;
302
303 for (count = 0; count < 50000; count++) {
304 if (!pit_verify_msb(val))
305 break;
306 prev_tsc = tsc;
307 tsc = get_cycles();
308 }
309 *deltap = get_cycles() - prev_tsc;
310 *tscp = tsc;
311
312 /*
313 * We require _some_ success, but the quality control
314 * will be based on the error terms on the TSC values.
315 */
316 return count > 5;
317 }
318
319 /*
320 * How many MSB values do we want to see? We aim for
321 * a maximum error rate of 500ppm (in practice the
322 * real error is much smaller), but refuse to spend
323 * more than 50ms on it.
324 */
325 #define MAX_QUICK_PIT_MS 50
326 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
327
328 static unsigned long quick_pit_calibrate(void)
329 {
330 int i;
331 u64 tsc, delta;
332 unsigned long d1, d2;
333
334 /* Set the Gate high, disable speaker */
335 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
336
337 /*
338 * Counter 2, mode 0 (one-shot), binary count
339 *
340 * NOTE! Mode 2 decrements by two (and then the
341 * output is flipped each time, giving the same
342 * final output frequency as a decrement-by-one),
343 * so mode 0 is much better when looking at the
344 * individual counts.
345 */
346 outb(0xb0, 0x43);
347
348 /* Start at 0xffff */
349 outb(0xff, 0x42);
350 outb(0xff, 0x42);
351
352 /*
353 * The PIT starts counting at the next edge, so we
354 * need to delay for a microsecond. The easiest way
355 * to do that is to just read back the 16-bit counter
356 * once from the PIT.
357 */
358 pit_verify_msb(0);
359
360 if (pit_expect_msb(0xff, &tsc, &d1)) {
361 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
362 if (!pit_expect_msb(0xff-i, &delta, &d2))
363 break;
364
365 /*
366 * Iterate until the error is less than 500 ppm
367 */
368 delta -= tsc;
369 if (d1+d2 >= delta >> 11)
370 continue;
371
372 /*
373 * Check the PIT one more time to verify that
374 * all TSC reads were stable wrt the PIT.
375 *
376 * This also guarantees serialization of the
377 * last cycle read ('d2') in pit_expect_msb.
378 */
379 if (!pit_verify_msb(0xfe - i))
380 break;
381 goto success;
382 }
383 }
384 pr_info("Fast TSC calibration failed\n");
385 return 0;
386
387 success:
388 /*
389 * Ok, if we get here, then we've seen the
390 * MSB of the PIT decrement 'i' times, and the
391 * error has shrunk to less than 500 ppm.
392 *
393 * As a result, we can depend on there not being
394 * any odd delays anywhere, and the TSC reads are
395 * reliable (within the error).
396 *
397 * kHz = ticks / time-in-seconds / 1000;
398 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
399 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
400 */
401 delta *= PIT_TICK_RATE;
402 do_div(delta, i*256*1000);
403 pr_info("Fast TSC calibration using PIT\n");
404 return delta;
405 }
406
407 /**
408 * native_calibrate_tsc - calibrate the tsc on boot
409 */
410 unsigned long native_calibrate_tsc(void)
411 {
412 u64 tsc1, tsc2, delta, ref1, ref2;
413 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
414 unsigned long flags, latch, ms, fast_calibrate;
415 int hpet = is_hpet_enabled(), i, loopmin;
416
417 local_irq_save(flags);
418 fast_calibrate = quick_pit_calibrate();
419 local_irq_restore(flags);
420 if (fast_calibrate)
421 return fast_calibrate;
422
423 /*
424 * Run 5 calibration loops to get the lowest frequency value
425 * (the best estimate). We use two different calibration modes
426 * here:
427 *
428 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
429 * load a timeout of 50ms. We read the time right after we
430 * started the timer and wait until the PIT count down reaches
431 * zero. In each wait loop iteration we read the TSC and check
432 * the delta to the previous read. We keep track of the min
433 * and max values of that delta. The delta is mostly defined
434 * by the IO time of the PIT access, so we can detect when a
435 * SMI/SMM disturbance happened between the two reads. If the
436 * maximum time is significantly larger than the minimum time,
437 * then we discard the result and have another try.
438 *
439 * 2) Reference counter. If available we use the HPET or the
440 * PMTIMER as a reference to check the sanity of that value.
441 * We use separate TSC readouts and check inside of the
442 * reference read for a SMI/SMM disturbance. We dicard
443 * disturbed values here as well. We do that around the PIT
444 * calibration delay loop as we have to wait for a certain
445 * amount of time anyway.
446 */
447
448 /* Preset PIT loop values */
449 latch = CAL_LATCH;
450 ms = CAL_MS;
451 loopmin = CAL_PIT_LOOPS;
452
453 for (i = 0; i < 3; i++) {
454 unsigned long tsc_pit_khz;
455
456 /*
457 * Read the start value and the reference count of
458 * hpet/pmtimer when available. Then do the PIT
459 * calibration, which will take at least 50ms, and
460 * read the end value.
461 */
462 local_irq_save(flags);
463 tsc1 = tsc_read_refs(&ref1, hpet);
464 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
465 tsc2 = tsc_read_refs(&ref2, hpet);
466 local_irq_restore(flags);
467
468 /* Pick the lowest PIT TSC calibration so far */
469 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
470
471 /* hpet or pmtimer available ? */
472 if (ref1 == ref2)
473 continue;
474
475 /* Check, whether the sampling was disturbed by an SMI */
476 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
477 continue;
478
479 tsc2 = (tsc2 - tsc1) * 1000000LL;
480 if (hpet)
481 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
482 else
483 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
484
485 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
486
487 /* Check the reference deviation */
488 delta = ((u64) tsc_pit_min) * 100;
489 do_div(delta, tsc_ref_min);
490
491 /*
492 * If both calibration results are inside a 10% window
493 * then we can be sure, that the calibration
494 * succeeded. We break out of the loop right away. We
495 * use the reference value, as it is more precise.
496 */
497 if (delta >= 90 && delta <= 110) {
498 pr_info("PIT calibration matches %s. %d loops\n",
499 hpet ? "HPET" : "PMTIMER", i + 1);
500 return tsc_ref_min;
501 }
502
503 /*
504 * Check whether PIT failed more than once. This
505 * happens in virtualized environments. We need to
506 * give the virtual PC a slightly longer timeframe for
507 * the HPET/PMTIMER to make the result precise.
508 */
509 if (i == 1 && tsc_pit_min == ULONG_MAX) {
510 latch = CAL2_LATCH;
511 ms = CAL2_MS;
512 loopmin = CAL2_PIT_LOOPS;
513 }
514 }
515
516 /*
517 * Now check the results.
518 */
519 if (tsc_pit_min == ULONG_MAX) {
520 /* PIT gave no useful value */
521 pr_warn("Unable to calibrate against PIT\n");
522
523 /* We don't have an alternative source, disable TSC */
524 if (!hpet && !ref1 && !ref2) {
525 pr_notice("No reference (HPET/PMTIMER) available\n");
526 return 0;
527 }
528
529 /* The alternative source failed as well, disable TSC */
530 if (tsc_ref_min == ULONG_MAX) {
531 pr_warn("HPET/PMTIMER calibration failed\n");
532 return 0;
533 }
534
535 /* Use the alternative source */
536 pr_info("using %s reference calibration\n",
537 hpet ? "HPET" : "PMTIMER");
538
539 return tsc_ref_min;
540 }
541
542 /* We don't have an alternative source, use the PIT calibration value */
543 if (!hpet && !ref1 && !ref2) {
544 pr_info("Using PIT calibration value\n");
545 return tsc_pit_min;
546 }
547
548 /* The alternative source failed, use the PIT calibration value */
549 if (tsc_ref_min == ULONG_MAX) {
550 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
551 return tsc_pit_min;
552 }
553
554 /*
555 * The calibration values differ too much. In doubt, we use
556 * the PIT value as we know that there are PMTIMERs around
557 * running at double speed. At least we let the user know:
558 */
559 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
560 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
561 pr_info("Using PIT calibration value\n");
562 return tsc_pit_min;
563 }
564
565 int recalibrate_cpu_khz(void)
566 {
567 #ifndef CONFIG_SMP
568 unsigned long cpu_khz_old = cpu_khz;
569
570 if (cpu_has_tsc) {
571 tsc_khz = x86_platform.calibrate_tsc();
572 cpu_khz = tsc_khz;
573 cpu_data(0).loops_per_jiffy =
574 cpufreq_scale(cpu_data(0).loops_per_jiffy,
575 cpu_khz_old, cpu_khz);
576 return 0;
577 } else
578 return -ENODEV;
579 #else
580 return -ENODEV;
581 #endif
582 }
583
584 EXPORT_SYMBOL(recalibrate_cpu_khz);
585
586
587 /* Accelerators for sched_clock()
588 * convert from cycles(64bits) => nanoseconds (64bits)
589 * basic equation:
590 * ns = cycles / (freq / ns_per_sec)
591 * ns = cycles * (ns_per_sec / freq)
592 * ns = cycles * (10^9 / (cpu_khz * 10^3))
593 * ns = cycles * (10^6 / cpu_khz)
594 *
595 * Then we use scaling math (suggested by george@mvista.com) to get:
596 * ns = cycles * (10^6 * SC / cpu_khz) / SC
597 * ns = cycles * cyc2ns_scale / SC
598 *
599 * And since SC is a constant power of two, we can convert the div
600 * into a shift.
601 *
602 * We can use khz divisor instead of mhz to keep a better precision, since
603 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
604 * (mathieu.desnoyers@polymtl.ca)
605 *
606 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
607 */
608
609 DEFINE_PER_CPU(unsigned long, cyc2ns);
610 DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
611
612 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
613 {
614 unsigned long long tsc_now, ns_now, *offset;
615 unsigned long flags, *scale;
616
617 local_irq_save(flags);
618 sched_clock_idle_sleep_event();
619
620 scale = &per_cpu(cyc2ns, cpu);
621 offset = &per_cpu(cyc2ns_offset, cpu);
622
623 rdtscll(tsc_now);
624 ns_now = __cycles_2_ns(tsc_now);
625
626 if (cpu_khz) {
627 *scale = ((NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR) +
628 cpu_khz / 2) / cpu_khz;
629 *offset = ns_now - mult_frac(tsc_now, *scale,
630 (1UL << CYC2NS_SCALE_FACTOR));
631 }
632
633 sched_clock_idle_wakeup_event(0);
634 local_irq_restore(flags);
635 }
636
637 static unsigned long long cyc2ns_suspend;
638
639 void tsc_save_sched_clock_state(void)
640 {
641 if (!sched_clock_stable)
642 return;
643
644 cyc2ns_suspend = sched_clock();
645 }
646
647 /*
648 * Even on processors with invariant TSC, TSC gets reset in some the
649 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
650 * arbitrary value (still sync'd across cpu's) during resume from such sleep
651 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
652 * that sched_clock() continues from the point where it was left off during
653 * suspend.
654 */
655 void tsc_restore_sched_clock_state(void)
656 {
657 unsigned long long offset;
658 unsigned long flags;
659 int cpu;
660
661 if (!sched_clock_stable)
662 return;
663
664 local_irq_save(flags);
665
666 __this_cpu_write(cyc2ns_offset, 0);
667 offset = cyc2ns_suspend - sched_clock();
668
669 for_each_possible_cpu(cpu)
670 per_cpu(cyc2ns_offset, cpu) = offset;
671
672 local_irq_restore(flags);
673 }
674
675 #ifdef CONFIG_CPU_FREQ
676
677 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
678 * changes.
679 *
680 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
681 * not that important because current Opteron setups do not support
682 * scaling on SMP anyroads.
683 *
684 * Should fix up last_tsc too. Currently gettimeofday in the
685 * first tick after the change will be slightly wrong.
686 */
687
688 static unsigned int ref_freq;
689 static unsigned long loops_per_jiffy_ref;
690 static unsigned long tsc_khz_ref;
691
692 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
693 void *data)
694 {
695 struct cpufreq_freqs *freq = data;
696 unsigned long *lpj;
697
698 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
699 return 0;
700
701 lpj = &boot_cpu_data.loops_per_jiffy;
702 #ifdef CONFIG_SMP
703 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
704 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
705 #endif
706
707 if (!ref_freq) {
708 ref_freq = freq->old;
709 loops_per_jiffy_ref = *lpj;
710 tsc_khz_ref = tsc_khz;
711 }
712 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
713 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
714 (val == CPUFREQ_RESUMECHANGE)) {
715 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
716
717 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
718 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
719 mark_tsc_unstable("cpufreq changes");
720 }
721
722 set_cyc2ns_scale(tsc_khz, freq->cpu);
723
724 return 0;
725 }
726
727 static struct notifier_block time_cpufreq_notifier_block = {
728 .notifier_call = time_cpufreq_notifier
729 };
730
731 static int __init cpufreq_tsc(void)
732 {
733 if (!cpu_has_tsc)
734 return 0;
735 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
736 return 0;
737 cpufreq_register_notifier(&time_cpufreq_notifier_block,
738 CPUFREQ_TRANSITION_NOTIFIER);
739 return 0;
740 }
741
742 core_initcall(cpufreq_tsc);
743
744 #endif /* CONFIG_CPU_FREQ */
745
746 /* clocksource code */
747
748 static struct clocksource clocksource_tsc;
749
750 /*
751 * We compare the TSC to the cycle_last value in the clocksource
752 * structure to avoid a nasty time-warp. This can be observed in a
753 * very small window right after one CPU updated cycle_last under
754 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
755 * is smaller than the cycle_last reference value due to a TSC which
756 * is slighty behind. This delta is nowhere else observable, but in
757 * that case it results in a forward time jump in the range of hours
758 * due to the unsigned delta calculation of the time keeping core
759 * code, which is necessary to support wrapping clocksources like pm
760 * timer.
761 */
762 static cycle_t read_tsc(struct clocksource *cs)
763 {
764 cycle_t ret = (cycle_t)get_cycles();
765
766 return ret >= clocksource_tsc.cycle_last ?
767 ret : clocksource_tsc.cycle_last;
768 }
769
770 static void resume_tsc(struct clocksource *cs)
771 {
772 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
773 clocksource_tsc.cycle_last = 0;
774 }
775
776 static struct clocksource clocksource_tsc = {
777 .name = "tsc",
778 .rating = 300,
779 .read = read_tsc,
780 .resume = resume_tsc,
781 .mask = CLOCKSOURCE_MASK(64),
782 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
783 CLOCK_SOURCE_MUST_VERIFY,
784 #ifdef CONFIG_X86_64
785 .archdata = { .vclock_mode = VCLOCK_TSC },
786 #endif
787 };
788
789 void mark_tsc_unstable(char *reason)
790 {
791 if (!tsc_unstable) {
792 tsc_unstable = 1;
793 sched_clock_stable = 0;
794 disable_sched_clock_irqtime();
795 pr_info("Marking TSC unstable due to %s\n", reason);
796 /* Change only the rating, when not registered */
797 if (clocksource_tsc.mult)
798 clocksource_mark_unstable(&clocksource_tsc);
799 else {
800 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
801 clocksource_tsc.rating = 0;
802 }
803 }
804 }
805
806 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
807
808 static void __init check_system_tsc_reliable(void)
809 {
810 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
811 if (is_geode_lx()) {
812 /* RTSC counts during suspend */
813 #define RTSC_SUSP 0x100
814 unsigned long res_low, res_high;
815
816 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
817 /* Geode_LX - the OLPC CPU has a very reliable TSC */
818 if (res_low & RTSC_SUSP)
819 tsc_clocksource_reliable = 1;
820 }
821 #endif
822 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
823 tsc_clocksource_reliable = 1;
824 }
825
826 /*
827 * Make an educated guess if the TSC is trustworthy and synchronized
828 * over all CPUs.
829 */
830 __cpuinit int unsynchronized_tsc(void)
831 {
832 if (!cpu_has_tsc || tsc_unstable)
833 return 1;
834
835 #ifdef CONFIG_SMP
836 if (apic_is_clustered_box())
837 return 1;
838 #endif
839
840 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
841 return 0;
842
843 if (tsc_clocksource_reliable)
844 return 0;
845 /*
846 * Intel systems are normally all synchronized.
847 * Exceptions must mark TSC as unstable:
848 */
849 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
850 /* assume multi socket systems are not synchronized: */
851 if (num_possible_cpus() > 1)
852 return 1;
853 }
854
855 return 0;
856 }
857
858
859 static void tsc_refine_calibration_work(struct work_struct *work);
860 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
861 /**
862 * tsc_refine_calibration_work - Further refine tsc freq calibration
863 * @work - ignored.
864 *
865 * This functions uses delayed work over a period of a
866 * second to further refine the TSC freq value. Since this is
867 * timer based, instead of loop based, we don't block the boot
868 * process while this longer calibration is done.
869 *
870 * If there are any calibration anomalies (too many SMIs, etc),
871 * or the refined calibration is off by 1% of the fast early
872 * calibration, we throw out the new calibration and use the
873 * early calibration.
874 */
875 static void tsc_refine_calibration_work(struct work_struct *work)
876 {
877 static u64 tsc_start = -1, ref_start;
878 static int hpet;
879 u64 tsc_stop, ref_stop, delta;
880 unsigned long freq;
881
882 /* Don't bother refining TSC on unstable systems */
883 if (check_tsc_unstable())
884 goto out;
885
886 /*
887 * Since the work is started early in boot, we may be
888 * delayed the first time we expire. So set the workqueue
889 * again once we know timers are working.
890 */
891 if (tsc_start == -1) {
892 /*
893 * Only set hpet once, to avoid mixing hardware
894 * if the hpet becomes enabled later.
895 */
896 hpet = is_hpet_enabled();
897 schedule_delayed_work(&tsc_irqwork, HZ);
898 tsc_start = tsc_read_refs(&ref_start, hpet);
899 return;
900 }
901
902 tsc_stop = tsc_read_refs(&ref_stop, hpet);
903
904 /* hpet or pmtimer available ? */
905 if (ref_start == ref_stop)
906 goto out;
907
908 /* Check, whether the sampling was disturbed by an SMI */
909 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
910 goto out;
911
912 delta = tsc_stop - tsc_start;
913 delta *= 1000000LL;
914 if (hpet)
915 freq = calc_hpet_ref(delta, ref_start, ref_stop);
916 else
917 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
918
919 /* Make sure we're within 1% */
920 if (abs(tsc_khz - freq) > tsc_khz/100)
921 goto out;
922
923 tsc_khz = freq;
924 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
925 (unsigned long)tsc_khz / 1000,
926 (unsigned long)tsc_khz % 1000);
927
928 out:
929 clocksource_register_khz(&clocksource_tsc, tsc_khz);
930 }
931
932
933 static int __init init_tsc_clocksource(void)
934 {
935 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
936 return 0;
937
938 if (tsc_clocksource_reliable)
939 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
940 /* lower the rating if we already know its unstable: */
941 if (check_tsc_unstable()) {
942 clocksource_tsc.rating = 0;
943 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
944 }
945
946 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
947 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
948
949 /*
950 * Trust the results of the earlier calibration on systems
951 * exporting a reliable TSC.
952 */
953 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
954 clocksource_register_khz(&clocksource_tsc, tsc_khz);
955 return 0;
956 }
957
958 schedule_delayed_work(&tsc_irqwork, 0);
959 return 0;
960 }
961 /*
962 * We use device_initcall here, to ensure we run after the hpet
963 * is fully initialized, which may occur at fs_initcall time.
964 */
965 device_initcall(init_tsc_clocksource);
966
967 void __init tsc_init(void)
968 {
969 u64 lpj;
970 int cpu;
971
972 x86_init.timers.tsc_pre_init();
973
974 if (!cpu_has_tsc) {
975 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
976 return;
977 }
978
979 tsc_khz = x86_platform.calibrate_tsc();
980 cpu_khz = tsc_khz;
981
982 if (!tsc_khz) {
983 mark_tsc_unstable("could not calculate TSC khz");
984 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
985 return;
986 }
987
988 pr_info("Detected %lu.%03lu MHz processor\n",
989 (unsigned long)cpu_khz / 1000,
990 (unsigned long)cpu_khz % 1000);
991
992 /*
993 * Secondary CPUs do not run through tsc_init(), so set up
994 * all the scale factors for all CPUs, assuming the same
995 * speed as the bootup CPU. (cpufreq notifiers will fix this
996 * up if their speed diverges)
997 */
998 for_each_possible_cpu(cpu)
999 set_cyc2ns_scale(cpu_khz, cpu);
1000
1001 if (tsc_disabled > 0)
1002 return;
1003
1004 /* now allow native_sched_clock() to use rdtsc */
1005 tsc_disabled = 0;
1006
1007 if (!no_sched_irq_time)
1008 enable_sched_clock_irqtime();
1009
1010 lpj = ((u64)tsc_khz * 1000);
1011 do_div(lpj, HZ);
1012 lpj_fine = lpj;
1013
1014 use_tsc_delay();
1015
1016 if (unsynchronized_tsc())
1017 mark_tsc_unstable("TSCs unsynchronized");
1018
1019 check_system_tsc_reliable();
1020 }
1021
1022 #ifdef CONFIG_SMP
1023 /*
1024 * If we have a constant TSC and are using the TSC for the delay loop,
1025 * we can skip clock calibration if another cpu in the same socket has already
1026 * been calibrated. This assumes that CONSTANT_TSC applies to all
1027 * cpus in the socket - this should be a safe assumption.
1028 */
1029 unsigned long __cpuinit calibrate_delay_is_known(void)
1030 {
1031 int i, cpu = smp_processor_id();
1032
1033 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1034 return 0;
1035
1036 for_each_online_cpu(i)
1037 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1038 return cpu_data(i).loops_per_jiffy;
1039 return 0;
1040 }
1041 #endif
1042
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