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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/tsc.c

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  1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  2 
  3 #include <linux/kernel.h>
  4 #include <linux/sched.h>
  5 #include <linux/init.h>
  6 #include <linux/module.h>
  7 #include <linux/timer.h>
  8 #include <linux/acpi_pmtmr.h>
  9 #include <linux/cpufreq.h>
 10 #include <linux/delay.h>
 11 #include <linux/clocksource.h>
 12 #include <linux/percpu.h>
 13 #include <linux/timex.h>
 14 #include <linux/static_key.h>
 15 
 16 #include <asm/hpet.h>
 17 #include <asm/timer.h>
 18 #include <asm/vgtod.h>
 19 #include <asm/time.h>
 20 #include <asm/delay.h>
 21 #include <asm/hypervisor.h>
 22 #include <asm/nmi.h>
 23 #include <asm/x86_init.h>
 24 
 25 unsigned int __read_mostly cpu_khz;     /* TSC clocks / usec, not used here */
 26 EXPORT_SYMBOL(cpu_khz);
 27 
 28 unsigned int __read_mostly tsc_khz;
 29 EXPORT_SYMBOL(tsc_khz);
 30 
 31 /*
 32  * TSC can be unstable due to cpufreq or due to unsynced TSCs
 33  */
 34 static int __read_mostly tsc_unstable;
 35 
 36 /* native_sched_clock() is called before tsc_init(), so
 37    we must start with the TSC soft disabled to prevent
 38    erroneous rdtsc usage on !cpu_has_tsc processors */
 39 static int __read_mostly tsc_disabled = -1;
 40 
 41 static struct static_key __use_tsc = STATIC_KEY_INIT;
 42 
 43 int tsc_clocksource_reliable;
 44 
 45 /*
 46  * Use a ring-buffer like data structure, where a writer advances the head by
 47  * writing a new data entry and a reader advances the tail when it observes a
 48  * new entry.
 49  *
 50  * Writers are made to wait on readers until there's space to write a new
 51  * entry.
 52  *
 53  * This means that we can always use an {offset, mul} pair to compute a ns
 54  * value that is 'roughly' in the right direction, even if we're writing a new
 55  * {offset, mul} pair during the clock read.
 56  *
 57  * The down-side is that we can no longer guarantee strict monotonicity anymore
 58  * (assuming the TSC was that to begin with), because while we compute the
 59  * intersection point of the two clock slopes and make sure the time is
 60  * continuous at the point of switching; we can no longer guarantee a reader is
 61  * strictly before or after the switch point.
 62  *
 63  * It does mean a reader no longer needs to disable IRQs in order to avoid
 64  * CPU-Freq updates messing with his times, and similarly an NMI reader will
 65  * no longer run the risk of hitting half-written state.
 66  */
 67 
 68 struct cyc2ns {
 69         struct cyc2ns_data data[2];     /*  0 + 2*24 = 48 */
 70         struct cyc2ns_data *head;       /* 48 + 8    = 56 */
 71         struct cyc2ns_data *tail;       /* 56 + 8    = 64 */
 72 }; /* exactly fits one cacheline */
 73 
 74 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
 75 
 76 struct cyc2ns_data *cyc2ns_read_begin(void)
 77 {
 78         struct cyc2ns_data *head;
 79 
 80         preempt_disable();
 81 
 82         head = this_cpu_read(cyc2ns.head);
 83         /*
 84          * Ensure we observe the entry when we observe the pointer to it.
 85          * matches the wmb from cyc2ns_write_end().
 86          */
 87         smp_read_barrier_depends();
 88         head->__count++;
 89         barrier();
 90 
 91         return head;
 92 }
 93 
 94 void cyc2ns_read_end(struct cyc2ns_data *head)
 95 {
 96         barrier();
 97         /*
 98          * If we're the outer most nested read; update the tail pointer
 99          * when we're done. This notifies possible pending writers
100          * that we've observed the head pointer and that the other
101          * entry is now free.
102          */
103         if (!--head->__count) {
104                 /*
105                  * x86-TSO does not reorder writes with older reads;
106                  * therefore once this write becomes visible to another
107                  * cpu, we must be finished reading the cyc2ns_data.
108                  *
109                  * matches with cyc2ns_write_begin().
110                  */
111                 this_cpu_write(cyc2ns.tail, head);
112         }
113         preempt_enable();
114 }
115 
116 /*
117  * Begin writing a new @data entry for @cpu.
118  *
119  * Assumes some sort of write side lock; currently 'provided' by the assumption
120  * that cpufreq will call its notifiers sequentially.
121  */
122 static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
123 {
124         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
125         struct cyc2ns_data *data = c2n->data;
126 
127         if (data == c2n->head)
128                 data++;
129 
130         /* XXX send an IPI to @cpu in order to guarantee a read? */
131 
132         /*
133          * When we observe the tail write from cyc2ns_read_end(),
134          * the cpu must be done with that entry and its safe
135          * to start writing to it.
136          */
137         while (c2n->tail == data)
138                 cpu_relax();
139 
140         return data;
141 }
142 
143 static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
144 {
145         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
146 
147         /*
148          * Ensure the @data writes are visible before we publish the
149          * entry. Matches the data-depencency in cyc2ns_read_begin().
150          */
151         smp_wmb();
152 
153         ACCESS_ONCE(c2n->head) = data;
154 }
155 
156 /*
157  * Accelerators for sched_clock()
158  * convert from cycles(64bits) => nanoseconds (64bits)
159  *  basic equation:
160  *              ns = cycles / (freq / ns_per_sec)
161  *              ns = cycles * (ns_per_sec / freq)
162  *              ns = cycles * (10^9 / (cpu_khz * 10^3))
163  *              ns = cycles * (10^6 / cpu_khz)
164  *
165  *      Then we use scaling math (suggested by george@mvista.com) to get:
166  *              ns = cycles * (10^6 * SC / cpu_khz) / SC
167  *              ns = cycles * cyc2ns_scale / SC
168  *
169  *      And since SC is a constant power of two, we can convert the div
170  *  into a shift.
171  *
172  *  We can use khz divisor instead of mhz to keep a better precision, since
173  *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
174  *  (mathieu.desnoyers@polymtl.ca)
175  *
176  *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
177  */
178 
179 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
180 
181 static void cyc2ns_data_init(struct cyc2ns_data *data)
182 {
183         data->cyc2ns_mul = 0;
184         data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
185         data->cyc2ns_offset = 0;
186         data->__count = 0;
187 }
188 
189 static void cyc2ns_init(int cpu)
190 {
191         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
192 
193         cyc2ns_data_init(&c2n->data[0]);
194         cyc2ns_data_init(&c2n->data[1]);
195 
196         c2n->head = c2n->data;
197         c2n->tail = c2n->data;
198 }
199 
200 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
201 {
202         struct cyc2ns_data *data, *tail;
203         unsigned long long ns;
204 
205         /*
206          * See cyc2ns_read_*() for details; replicated in order to avoid
207          * an extra few instructions that came with the abstraction.
208          * Notable, it allows us to only do the __count and tail update
209          * dance when its actually needed.
210          */
211 
212         preempt_disable_notrace();
213         data = this_cpu_read(cyc2ns.head);
214         tail = this_cpu_read(cyc2ns.tail);
215 
216         if (likely(data == tail)) {
217                 ns = data->cyc2ns_offset;
218                 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
219         } else {
220                 data->__count++;
221 
222                 barrier();
223 
224                 ns = data->cyc2ns_offset;
225                 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
226 
227                 barrier();
228 
229                 if (!--data->__count)
230                         this_cpu_write(cyc2ns.tail, data);
231         }
232         preempt_enable_notrace();
233 
234         return ns;
235 }
236 
237 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
238 {
239         unsigned long long tsc_now, ns_now;
240         struct cyc2ns_data *data;
241         unsigned long flags;
242 
243         local_irq_save(flags);
244         sched_clock_idle_sleep_event();
245 
246         if (!cpu_khz)
247                 goto done;
248 
249         data = cyc2ns_write_begin(cpu);
250 
251         rdtscll(tsc_now);
252         ns_now = cycles_2_ns(tsc_now);
253 
254         /*
255          * Compute a new multiplier as per the above comment and ensure our
256          * time function is continuous; see the comment near struct
257          * cyc2ns_data.
258          */
259         data->cyc2ns_mul =
260                 DIV_ROUND_CLOSEST(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR,
261                                   cpu_khz);
262         data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
263         data->cyc2ns_offset = ns_now -
264                 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
265 
266         cyc2ns_write_end(cpu, data);
267 
268 done:
269         sched_clock_idle_wakeup_event(0);
270         local_irq_restore(flags);
271 }
272 /*
273  * Scheduler clock - returns current time in nanosec units.
274  */
275 u64 native_sched_clock(void)
276 {
277         u64 tsc_now;
278 
279         /*
280          * Fall back to jiffies if there's no TSC available:
281          * ( But note that we still use it if the TSC is marked
282          *   unstable. We do this because unlike Time Of Day,
283          *   the scheduler clock tolerates small errors and it's
284          *   very important for it to be as fast as the platform
285          *   can achieve it. )
286          */
287         if (!static_key_false(&__use_tsc)) {
288                 /* No locking but a rare wrong value is not a big deal: */
289                 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
290         }
291 
292         /* read the Time Stamp Counter: */
293         rdtscll(tsc_now);
294 
295         /* return the value in ns */
296         return cycles_2_ns(tsc_now);
297 }
298 
299 /* We need to define a real function for sched_clock, to override the
300    weak default version */
301 #ifdef CONFIG_PARAVIRT
302 unsigned long long sched_clock(void)
303 {
304         return paravirt_sched_clock();
305 }
306 #else
307 unsigned long long
308 sched_clock(void) __attribute__((alias("native_sched_clock")));
309 #endif
310 
311 unsigned long long native_read_tsc(void)
312 {
313         return __native_read_tsc();
314 }
315 EXPORT_SYMBOL(native_read_tsc);
316 
317 int check_tsc_unstable(void)
318 {
319         return tsc_unstable;
320 }
321 EXPORT_SYMBOL_GPL(check_tsc_unstable);
322 
323 int check_tsc_disabled(void)
324 {
325         return tsc_disabled;
326 }
327 EXPORT_SYMBOL_GPL(check_tsc_disabled);
328 
329 #ifdef CONFIG_X86_TSC
330 int __init notsc_setup(char *str)
331 {
332         pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
333         tsc_disabled = 1;
334         return 1;
335 }
336 #else
337 /*
338  * disable flag for tsc. Takes effect by clearing the TSC cpu flag
339  * in cpu/common.c
340  */
341 int __init notsc_setup(char *str)
342 {
343         setup_clear_cpu_cap(X86_FEATURE_TSC);
344         return 1;
345 }
346 #endif
347 
348 __setup("notsc", notsc_setup);
349 
350 static int no_sched_irq_time;
351 
352 static int __init tsc_setup(char *str)
353 {
354         if (!strcmp(str, "reliable"))
355                 tsc_clocksource_reliable = 1;
356         if (!strncmp(str, "noirqtime", 9))
357                 no_sched_irq_time = 1;
358         return 1;
359 }
360 
361 __setup("tsc=", tsc_setup);
362 
363 #define MAX_RETRIES     5
364 #define SMI_TRESHOLD    50000
365 
366 /*
367  * Read TSC and the reference counters. Take care of SMI disturbance
368  */
369 static u64 tsc_read_refs(u64 *p, int hpet)
370 {
371         u64 t1, t2;
372         int i;
373 
374         for (i = 0; i < MAX_RETRIES; i++) {
375                 t1 = get_cycles();
376                 if (hpet)
377                         *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
378                 else
379                         *p = acpi_pm_read_early();
380                 t2 = get_cycles();
381                 if ((t2 - t1) < SMI_TRESHOLD)
382                         return t2;
383         }
384         return ULLONG_MAX;
385 }
386 
387 /*
388  * Calculate the TSC frequency from HPET reference
389  */
390 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
391 {
392         u64 tmp;
393 
394         if (hpet2 < hpet1)
395                 hpet2 += 0x100000000ULL;
396         hpet2 -= hpet1;
397         tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
398         do_div(tmp, 1000000);
399         do_div(deltatsc, tmp);
400 
401         return (unsigned long) deltatsc;
402 }
403 
404 /*
405  * Calculate the TSC frequency from PMTimer reference
406  */
407 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
408 {
409         u64 tmp;
410 
411         if (!pm1 && !pm2)
412                 return ULONG_MAX;
413 
414         if (pm2 < pm1)
415                 pm2 += (u64)ACPI_PM_OVRRUN;
416         pm2 -= pm1;
417         tmp = pm2 * 1000000000LL;
418         do_div(tmp, PMTMR_TICKS_PER_SEC);
419         do_div(deltatsc, tmp);
420 
421         return (unsigned long) deltatsc;
422 }
423 
424 #define CAL_MS          10
425 #define CAL_LATCH       (PIT_TICK_RATE / (1000 / CAL_MS))
426 #define CAL_PIT_LOOPS   1000
427 
428 #define CAL2_MS         50
429 #define CAL2_LATCH      (PIT_TICK_RATE / (1000 / CAL2_MS))
430 #define CAL2_PIT_LOOPS  5000
431 
432 
433 /*
434  * Try to calibrate the TSC against the Programmable
435  * Interrupt Timer and return the frequency of the TSC
436  * in kHz.
437  *
438  * Return ULONG_MAX on failure to calibrate.
439  */
440 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
441 {
442         u64 tsc, t1, t2, delta;
443         unsigned long tscmin, tscmax;
444         int pitcnt;
445 
446         /* Set the Gate high, disable speaker */
447         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
448 
449         /*
450          * Setup CTC channel 2* for mode 0, (interrupt on terminal
451          * count mode), binary count. Set the latch register to 50ms
452          * (LSB then MSB) to begin countdown.
453          */
454         outb(0xb0, 0x43);
455         outb(latch & 0xff, 0x42);
456         outb(latch >> 8, 0x42);
457 
458         tsc = t1 = t2 = get_cycles();
459 
460         pitcnt = 0;
461         tscmax = 0;
462         tscmin = ULONG_MAX;
463         while ((inb(0x61) & 0x20) == 0) {
464                 t2 = get_cycles();
465                 delta = t2 - tsc;
466                 tsc = t2;
467                 if ((unsigned long) delta < tscmin)
468                         tscmin = (unsigned int) delta;
469                 if ((unsigned long) delta > tscmax)
470                         tscmax = (unsigned int) delta;
471                 pitcnt++;
472         }
473 
474         /*
475          * Sanity checks:
476          *
477          * If we were not able to read the PIT more than loopmin
478          * times, then we have been hit by a massive SMI
479          *
480          * If the maximum is 10 times larger than the minimum,
481          * then we got hit by an SMI as well.
482          */
483         if (pitcnt < loopmin || tscmax > 10 * tscmin)
484                 return ULONG_MAX;
485 
486         /* Calculate the PIT value */
487         delta = t2 - t1;
488         do_div(delta, ms);
489         return delta;
490 }
491 
492 /*
493  * This reads the current MSB of the PIT counter, and
494  * checks if we are running on sufficiently fast and
495  * non-virtualized hardware.
496  *
497  * Our expectations are:
498  *
499  *  - the PIT is running at roughly 1.19MHz
500  *
501  *  - each IO is going to take about 1us on real hardware,
502  *    but we allow it to be much faster (by a factor of 10) or
503  *    _slightly_ slower (ie we allow up to a 2us read+counter
504  *    update - anything else implies a unacceptably slow CPU
505  *    or PIT for the fast calibration to work.
506  *
507  *  - with 256 PIT ticks to read the value, we have 214us to
508  *    see the same MSB (and overhead like doing a single TSC
509  *    read per MSB value etc).
510  *
511  *  - We're doing 2 reads per loop (LSB, MSB), and we expect
512  *    them each to take about a microsecond on real hardware.
513  *    So we expect a count value of around 100. But we'll be
514  *    generous, and accept anything over 50.
515  *
516  *  - if the PIT is stuck, and we see *many* more reads, we
517  *    return early (and the next caller of pit_expect_msb()
518  *    then consider it a failure when they don't see the
519  *    next expected value).
520  *
521  * These expectations mean that we know that we have seen the
522  * transition from one expected value to another with a fairly
523  * high accuracy, and we didn't miss any events. We can thus
524  * use the TSC value at the transitions to calculate a pretty
525  * good value for the TSC frequencty.
526  */
527 static inline int pit_verify_msb(unsigned char val)
528 {
529         /* Ignore LSB */
530         inb(0x42);
531         return inb(0x42) == val;
532 }
533 
534 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
535 {
536         int count;
537         u64 tsc = 0, prev_tsc = 0;
538 
539         for (count = 0; count < 50000; count++) {
540                 if (!pit_verify_msb(val))
541                         break;
542                 prev_tsc = tsc;
543                 tsc = get_cycles();
544         }
545         *deltap = get_cycles() - prev_tsc;
546         *tscp = tsc;
547 
548         /*
549          * We require _some_ success, but the quality control
550          * will be based on the error terms on the TSC values.
551          */
552         return count > 5;
553 }
554 
555 /*
556  * How many MSB values do we want to see? We aim for
557  * a maximum error rate of 500ppm (in practice the
558  * real error is much smaller), but refuse to spend
559  * more than 50ms on it.
560  */
561 #define MAX_QUICK_PIT_MS 50
562 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
563 
564 static unsigned long quick_pit_calibrate(void)
565 {
566         int i;
567         u64 tsc, delta;
568         unsigned long d1, d2;
569 
570         /* Set the Gate high, disable speaker */
571         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
572 
573         /*
574          * Counter 2, mode 0 (one-shot), binary count
575          *
576          * NOTE! Mode 2 decrements by two (and then the
577          * output is flipped each time, giving the same
578          * final output frequency as a decrement-by-one),
579          * so mode 0 is much better when looking at the
580          * individual counts.
581          */
582         outb(0xb0, 0x43);
583 
584         /* Start at 0xffff */
585         outb(0xff, 0x42);
586         outb(0xff, 0x42);
587 
588         /*
589          * The PIT starts counting at the next edge, so we
590          * need to delay for a microsecond. The easiest way
591          * to do that is to just read back the 16-bit counter
592          * once from the PIT.
593          */
594         pit_verify_msb(0);
595 
596         if (pit_expect_msb(0xff, &tsc, &d1)) {
597                 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
598                         if (!pit_expect_msb(0xff-i, &delta, &d2))
599                                 break;
600 
601                         /*
602                          * Iterate until the error is less than 500 ppm
603                          */
604                         delta -= tsc;
605                         if (d1+d2 >= delta >> 11)
606                                 continue;
607 
608                         /*
609                          * Check the PIT one more time to verify that
610                          * all TSC reads were stable wrt the PIT.
611                          *
612                          * This also guarantees serialization of the
613                          * last cycle read ('d2') in pit_expect_msb.
614                          */
615                         if (!pit_verify_msb(0xfe - i))
616                                 break;
617                         goto success;
618                 }
619         }
620         pr_info("Fast TSC calibration failed\n");
621         return 0;
622 
623 success:
624         /*
625          * Ok, if we get here, then we've seen the
626          * MSB of the PIT decrement 'i' times, and the
627          * error has shrunk to less than 500 ppm.
628          *
629          * As a result, we can depend on there not being
630          * any odd delays anywhere, and the TSC reads are
631          * reliable (within the error).
632          *
633          * kHz = ticks / time-in-seconds / 1000;
634          * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
635          * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
636          */
637         delta *= PIT_TICK_RATE;
638         do_div(delta, i*256*1000);
639         pr_info("Fast TSC calibration using PIT\n");
640         return delta;
641 }
642 
643 /**
644  * native_calibrate_tsc - calibrate the tsc on boot
645  */
646 unsigned long native_calibrate_tsc(void)
647 {
648         u64 tsc1, tsc2, delta, ref1, ref2;
649         unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
650         unsigned long flags, latch, ms, fast_calibrate;
651         int hpet = is_hpet_enabled(), i, loopmin;
652 
653         /* Calibrate TSC using MSR for Intel Atom SoCs */
654         local_irq_save(flags);
655         fast_calibrate = try_msr_calibrate_tsc();
656         local_irq_restore(flags);
657         if (fast_calibrate)
658                 return fast_calibrate;
659 
660         local_irq_save(flags);
661         fast_calibrate = quick_pit_calibrate();
662         local_irq_restore(flags);
663         if (fast_calibrate)
664                 return fast_calibrate;
665 
666         /*
667          * Run 5 calibration loops to get the lowest frequency value
668          * (the best estimate). We use two different calibration modes
669          * here:
670          *
671          * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
672          * load a timeout of 50ms. We read the time right after we
673          * started the timer and wait until the PIT count down reaches
674          * zero. In each wait loop iteration we read the TSC and check
675          * the delta to the previous read. We keep track of the min
676          * and max values of that delta. The delta is mostly defined
677          * by the IO time of the PIT access, so we can detect when a
678          * SMI/SMM disturbance happened between the two reads. If the
679          * maximum time is significantly larger than the minimum time,
680          * then we discard the result and have another try.
681          *
682          * 2) Reference counter. If available we use the HPET or the
683          * PMTIMER as a reference to check the sanity of that value.
684          * We use separate TSC readouts and check inside of the
685          * reference read for a SMI/SMM disturbance. We dicard
686          * disturbed values here as well. We do that around the PIT
687          * calibration delay loop as we have to wait for a certain
688          * amount of time anyway.
689          */
690 
691         /* Preset PIT loop values */
692         latch = CAL_LATCH;
693         ms = CAL_MS;
694         loopmin = CAL_PIT_LOOPS;
695 
696         for (i = 0; i < 3; i++) {
697                 unsigned long tsc_pit_khz;
698 
699                 /*
700                  * Read the start value and the reference count of
701                  * hpet/pmtimer when available. Then do the PIT
702                  * calibration, which will take at least 50ms, and
703                  * read the end value.
704                  */
705                 local_irq_save(flags);
706                 tsc1 = tsc_read_refs(&ref1, hpet);
707                 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
708                 tsc2 = tsc_read_refs(&ref2, hpet);
709                 local_irq_restore(flags);
710 
711                 /* Pick the lowest PIT TSC calibration so far */
712                 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
713 
714                 /* hpet or pmtimer available ? */
715                 if (ref1 == ref2)
716                         continue;
717 
718                 /* Check, whether the sampling was disturbed by an SMI */
719                 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
720                         continue;
721 
722                 tsc2 = (tsc2 - tsc1) * 1000000LL;
723                 if (hpet)
724                         tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
725                 else
726                         tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
727 
728                 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
729 
730                 /* Check the reference deviation */
731                 delta = ((u64) tsc_pit_min) * 100;
732                 do_div(delta, tsc_ref_min);
733 
734                 /*
735                  * If both calibration results are inside a 10% window
736                  * then we can be sure, that the calibration
737                  * succeeded. We break out of the loop right away. We
738                  * use the reference value, as it is more precise.
739                  */
740                 if (delta >= 90 && delta <= 110) {
741                         pr_info("PIT calibration matches %s. %d loops\n",
742                                 hpet ? "HPET" : "PMTIMER", i + 1);
743                         return tsc_ref_min;
744                 }
745 
746                 /*
747                  * Check whether PIT failed more than once. This
748                  * happens in virtualized environments. We need to
749                  * give the virtual PC a slightly longer timeframe for
750                  * the HPET/PMTIMER to make the result precise.
751                  */
752                 if (i == 1 && tsc_pit_min == ULONG_MAX) {
753                         latch = CAL2_LATCH;
754                         ms = CAL2_MS;
755                         loopmin = CAL2_PIT_LOOPS;
756                 }
757         }
758 
759         /*
760          * Now check the results.
761          */
762         if (tsc_pit_min == ULONG_MAX) {
763                 /* PIT gave no useful value */
764                 pr_warn("Unable to calibrate against PIT\n");
765 
766                 /* We don't have an alternative source, disable TSC */
767                 if (!hpet && !ref1 && !ref2) {
768                         pr_notice("No reference (HPET/PMTIMER) available\n");
769                         return 0;
770                 }
771 
772                 /* The alternative source failed as well, disable TSC */
773                 if (tsc_ref_min == ULONG_MAX) {
774                         pr_warn("HPET/PMTIMER calibration failed\n");
775                         return 0;
776                 }
777 
778                 /* Use the alternative source */
779                 pr_info("using %s reference calibration\n",
780                         hpet ? "HPET" : "PMTIMER");
781 
782                 return tsc_ref_min;
783         }
784 
785         /* We don't have an alternative source, use the PIT calibration value */
786         if (!hpet && !ref1 && !ref2) {
787                 pr_info("Using PIT calibration value\n");
788                 return tsc_pit_min;
789         }
790 
791         /* The alternative source failed, use the PIT calibration value */
792         if (tsc_ref_min == ULONG_MAX) {
793                 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
794                 return tsc_pit_min;
795         }
796 
797         /*
798          * The calibration values differ too much. In doubt, we use
799          * the PIT value as we know that there are PMTIMERs around
800          * running at double speed. At least we let the user know:
801          */
802         pr_warn("PIT calibration deviates from %s: %lu %lu\n",
803                 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
804         pr_info("Using PIT calibration value\n");
805         return tsc_pit_min;
806 }
807 
808 int recalibrate_cpu_khz(void)
809 {
810 #ifndef CONFIG_SMP
811         unsigned long cpu_khz_old = cpu_khz;
812 
813         if (cpu_has_tsc) {
814                 tsc_khz = x86_platform.calibrate_tsc();
815                 cpu_khz = tsc_khz;
816                 cpu_data(0).loops_per_jiffy =
817                         cpufreq_scale(cpu_data(0).loops_per_jiffy,
818                                         cpu_khz_old, cpu_khz);
819                 return 0;
820         } else
821                 return -ENODEV;
822 #else
823         return -ENODEV;
824 #endif
825 }
826 
827 EXPORT_SYMBOL(recalibrate_cpu_khz);
828 
829 
830 static unsigned long long cyc2ns_suspend;
831 
832 void tsc_save_sched_clock_state(void)
833 {
834         if (!sched_clock_stable())
835                 return;
836 
837         cyc2ns_suspend = sched_clock();
838 }
839 
840 /*
841  * Even on processors with invariant TSC, TSC gets reset in some the
842  * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
843  * arbitrary value (still sync'd across cpu's) during resume from such sleep
844  * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
845  * that sched_clock() continues from the point where it was left off during
846  * suspend.
847  */
848 void tsc_restore_sched_clock_state(void)
849 {
850         unsigned long long offset;
851         unsigned long flags;
852         int cpu;
853 
854         if (!sched_clock_stable())
855                 return;
856 
857         local_irq_save(flags);
858 
859         /*
860          * We're comming out of suspend, there's no concurrency yet; don't
861          * bother being nice about the RCU stuff, just write to both
862          * data fields.
863          */
864 
865         this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
866         this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
867 
868         offset = cyc2ns_suspend - sched_clock();
869 
870         for_each_possible_cpu(cpu) {
871                 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
872                 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
873         }
874 
875         local_irq_restore(flags);
876 }
877 
878 #ifdef CONFIG_CPU_FREQ
879 
880 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
881  * changes.
882  *
883  * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
884  * not that important because current Opteron setups do not support
885  * scaling on SMP anyroads.
886  *
887  * Should fix up last_tsc too. Currently gettimeofday in the
888  * first tick after the change will be slightly wrong.
889  */
890 
891 static unsigned int  ref_freq;
892 static unsigned long loops_per_jiffy_ref;
893 static unsigned long tsc_khz_ref;
894 
895 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
896                                 void *data)
897 {
898         struct cpufreq_freqs *freq = data;
899         unsigned long *lpj;
900 
901         if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
902                 return 0;
903 
904         lpj = &boot_cpu_data.loops_per_jiffy;
905 #ifdef CONFIG_SMP
906         if (!(freq->flags & CPUFREQ_CONST_LOOPS))
907                 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
908 #endif
909 
910         if (!ref_freq) {
911                 ref_freq = freq->old;
912                 loops_per_jiffy_ref = *lpj;
913                 tsc_khz_ref = tsc_khz;
914         }
915         if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
916                         (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
917                 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
918 
919                 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
920                 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
921                         mark_tsc_unstable("cpufreq changes");
922 
923                 set_cyc2ns_scale(tsc_khz, freq->cpu);
924         }
925 
926         return 0;
927 }
928 
929 static struct notifier_block time_cpufreq_notifier_block = {
930         .notifier_call  = time_cpufreq_notifier
931 };
932 
933 static int __init cpufreq_tsc(void)
934 {
935         if (!cpu_has_tsc)
936                 return 0;
937         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
938                 return 0;
939         cpufreq_register_notifier(&time_cpufreq_notifier_block,
940                                 CPUFREQ_TRANSITION_NOTIFIER);
941         return 0;
942 }
943 
944 core_initcall(cpufreq_tsc);
945 
946 #endif /* CONFIG_CPU_FREQ */
947 
948 /* clocksource code */
949 
950 static struct clocksource clocksource_tsc;
951 
952 /*
953  * We used to compare the TSC to the cycle_last value in the clocksource
954  * structure to avoid a nasty time-warp. This can be observed in a
955  * very small window right after one CPU updated cycle_last under
956  * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
957  * is smaller than the cycle_last reference value due to a TSC which
958  * is slighty behind. This delta is nowhere else observable, but in
959  * that case it results in a forward time jump in the range of hours
960  * due to the unsigned delta calculation of the time keeping core
961  * code, which is necessary to support wrapping clocksources like pm
962  * timer.
963  *
964  * This sanity check is now done in the core timekeeping code.
965  * checking the result of read_tsc() - cycle_last for being negative.
966  * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
967  */
968 static cycle_t read_tsc(struct clocksource *cs)
969 {
970         return (cycle_t)get_cycles();
971 }
972 
973 /*
974  * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
975  */
976 static struct clocksource clocksource_tsc = {
977         .name                   = "tsc",
978         .rating                 = 300,
979         .read                   = read_tsc,
980         .mask                   = CLOCKSOURCE_MASK(64),
981         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
982                                   CLOCK_SOURCE_MUST_VERIFY,
983         .archdata               = { .vclock_mode = VCLOCK_TSC },
984 };
985 
986 void mark_tsc_unstable(char *reason)
987 {
988         if (!tsc_unstable) {
989                 tsc_unstable = 1;
990                 clear_sched_clock_stable();
991                 disable_sched_clock_irqtime();
992                 pr_info("Marking TSC unstable due to %s\n", reason);
993                 /* Change only the rating, when not registered */
994                 if (clocksource_tsc.mult)
995                         clocksource_mark_unstable(&clocksource_tsc);
996                 else {
997                         clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
998                         clocksource_tsc.rating = 0;
999                 }
1000         }
1001 }
1002 
1003 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1004 
1005 static void __init check_system_tsc_reliable(void)
1006 {
1007 #ifdef CONFIG_MGEODE_LX
1008         /* RTSC counts during suspend */
1009 #define RTSC_SUSP 0x100
1010         unsigned long res_low, res_high;
1011 
1012         rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1013         /* Geode_LX - the OLPC CPU has a very reliable TSC */
1014         if (res_low & RTSC_SUSP)
1015                 tsc_clocksource_reliable = 1;
1016 #endif
1017         if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1018                 tsc_clocksource_reliable = 1;
1019 }
1020 
1021 /*
1022  * Make an educated guess if the TSC is trustworthy and synchronized
1023  * over all CPUs.
1024  */
1025 int unsynchronized_tsc(void)
1026 {
1027         if (!cpu_has_tsc || tsc_unstable)
1028                 return 1;
1029 
1030 #ifdef CONFIG_SMP
1031         if (apic_is_clustered_box())
1032                 return 1;
1033 #endif
1034 
1035         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1036                 return 0;
1037 
1038         if (tsc_clocksource_reliable)
1039                 return 0;
1040         /*
1041          * Intel systems are normally all synchronized.
1042          * Exceptions must mark TSC as unstable:
1043          */
1044         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1045                 /* assume multi socket systems are not synchronized: */
1046                 if (num_possible_cpus() > 1)
1047                         return 1;
1048         }
1049 
1050         return 0;
1051 }
1052 
1053 
1054 static void tsc_refine_calibration_work(struct work_struct *work);
1055 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1056 /**
1057  * tsc_refine_calibration_work - Further refine tsc freq calibration
1058  * @work - ignored.
1059  *
1060  * This functions uses delayed work over a period of a
1061  * second to further refine the TSC freq value. Since this is
1062  * timer based, instead of loop based, we don't block the boot
1063  * process while this longer calibration is done.
1064  *
1065  * If there are any calibration anomalies (too many SMIs, etc),
1066  * or the refined calibration is off by 1% of the fast early
1067  * calibration, we throw out the new calibration and use the
1068  * early calibration.
1069  */
1070 static void tsc_refine_calibration_work(struct work_struct *work)
1071 {
1072         static u64 tsc_start = -1, ref_start;
1073         static int hpet;
1074         u64 tsc_stop, ref_stop, delta;
1075         unsigned long freq;
1076 
1077         /* Don't bother refining TSC on unstable systems */
1078         if (check_tsc_unstable())
1079                 goto out;
1080 
1081         /*
1082          * Since the work is started early in boot, we may be
1083          * delayed the first time we expire. So set the workqueue
1084          * again once we know timers are working.
1085          */
1086         if (tsc_start == -1) {
1087                 /*
1088                  * Only set hpet once, to avoid mixing hardware
1089                  * if the hpet becomes enabled later.
1090                  */
1091                 hpet = is_hpet_enabled();
1092                 schedule_delayed_work(&tsc_irqwork, HZ);
1093                 tsc_start = tsc_read_refs(&ref_start, hpet);
1094                 return;
1095         }
1096 
1097         tsc_stop = tsc_read_refs(&ref_stop, hpet);
1098 
1099         /* hpet or pmtimer available ? */
1100         if (ref_start == ref_stop)
1101                 goto out;
1102 
1103         /* Check, whether the sampling was disturbed by an SMI */
1104         if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1105                 goto out;
1106 
1107         delta = tsc_stop - tsc_start;
1108         delta *= 1000000LL;
1109         if (hpet)
1110                 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1111         else
1112                 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1113 
1114         /* Make sure we're within 1% */
1115         if (abs(tsc_khz - freq) > tsc_khz/100)
1116                 goto out;
1117 
1118         tsc_khz = freq;
1119         pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1120                 (unsigned long)tsc_khz / 1000,
1121                 (unsigned long)tsc_khz % 1000);
1122 
1123 out:
1124         clocksource_register_khz(&clocksource_tsc, tsc_khz);
1125 }
1126 
1127 
1128 static int __init init_tsc_clocksource(void)
1129 {
1130         if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1131                 return 0;
1132 
1133         if (tsc_clocksource_reliable)
1134                 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1135         /* lower the rating if we already know its unstable: */
1136         if (check_tsc_unstable()) {
1137                 clocksource_tsc.rating = 0;
1138                 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1139         }
1140 
1141         if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1142                 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1143 
1144         /*
1145          * Trust the results of the earlier calibration on systems
1146          * exporting a reliable TSC.
1147          */
1148         if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1149                 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1150                 return 0;
1151         }
1152 
1153         schedule_delayed_work(&tsc_irqwork, 0);
1154         return 0;
1155 }
1156 /*
1157  * We use device_initcall here, to ensure we run after the hpet
1158  * is fully initialized, which may occur at fs_initcall time.
1159  */
1160 device_initcall(init_tsc_clocksource);
1161 
1162 void __init tsc_init(void)
1163 {
1164         u64 lpj;
1165         int cpu;
1166 
1167         x86_init.timers.tsc_pre_init();
1168 
1169         if (!cpu_has_tsc) {
1170                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1171                 return;
1172         }
1173 
1174         tsc_khz = x86_platform.calibrate_tsc();
1175         cpu_khz = tsc_khz;
1176 
1177         if (!tsc_khz) {
1178                 mark_tsc_unstable("could not calculate TSC khz");
1179                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1180                 return;
1181         }
1182 
1183         pr_info("Detected %lu.%03lu MHz processor\n",
1184                 (unsigned long)cpu_khz / 1000,
1185                 (unsigned long)cpu_khz % 1000);
1186 
1187         /*
1188          * Secondary CPUs do not run through tsc_init(), so set up
1189          * all the scale factors for all CPUs, assuming the same
1190          * speed as the bootup CPU. (cpufreq notifiers will fix this
1191          * up if their speed diverges)
1192          */
1193         for_each_possible_cpu(cpu) {
1194                 cyc2ns_init(cpu);
1195                 set_cyc2ns_scale(cpu_khz, cpu);
1196         }
1197 
1198         if (tsc_disabled > 0)
1199                 return;
1200 
1201         /* now allow native_sched_clock() to use rdtsc */
1202 
1203         tsc_disabled = 0;
1204         static_key_slow_inc(&__use_tsc);
1205 
1206         if (!no_sched_irq_time)
1207                 enable_sched_clock_irqtime();
1208 
1209         lpj = ((u64)tsc_khz * 1000);
1210         do_div(lpj, HZ);
1211         lpj_fine = lpj;
1212 
1213         use_tsc_delay();
1214 
1215         if (unsynchronized_tsc())
1216                 mark_tsc_unstable("TSCs unsynchronized");
1217 
1218         check_system_tsc_reliable();
1219 }
1220 
1221 #ifdef CONFIG_SMP
1222 /*
1223  * If we have a constant TSC and are using the TSC for the delay loop,
1224  * we can skip clock calibration if another cpu in the same socket has already
1225  * been calibrated. This assumes that CONSTANT_TSC applies to all
1226  * cpus in the socket - this should be a safe assumption.
1227  */
1228 unsigned long calibrate_delay_is_known(void)
1229 {
1230         int i, cpu = smp_processor_id();
1231 
1232         if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1233                 return 0;
1234 
1235         for_each_online_cpu(i)
1236                 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1237                         return cpu_data(i).loops_per_jiffy;
1238         return 0;
1239 }
1240 #endif
1241 

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