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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/tsc.c

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  1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  2 
  3 #include <linux/kernel.h>
  4 #include <linux/sched.h>
  5 #include <linux/init.h>
  6 #include <linux/module.h>
  7 #include <linux/timer.h>
  8 #include <linux/acpi_pmtmr.h>
  9 #include <linux/cpufreq.h>
 10 #include <linux/delay.h>
 11 #include <linux/clocksource.h>
 12 #include <linux/percpu.h>
 13 #include <linux/timex.h>
 14 #include <linux/static_key.h>
 15 
 16 #include <asm/hpet.h>
 17 #include <asm/timer.h>
 18 #include <asm/vgtod.h>
 19 #include <asm/time.h>
 20 #include <asm/delay.h>
 21 #include <asm/hypervisor.h>
 22 #include <asm/nmi.h>
 23 #include <asm/x86_init.h>
 24 #include <asm/geode.h>
 25 
 26 unsigned int __read_mostly cpu_khz;     /* TSC clocks / usec, not used here */
 27 EXPORT_SYMBOL(cpu_khz);
 28 
 29 unsigned int __read_mostly tsc_khz;
 30 EXPORT_SYMBOL(tsc_khz);
 31 
 32 /*
 33  * TSC can be unstable due to cpufreq or due to unsynced TSCs
 34  */
 35 static int __read_mostly tsc_unstable;
 36 
 37 /* native_sched_clock() is called before tsc_init(), so
 38    we must start with the TSC soft disabled to prevent
 39    erroneous rdtsc usage on !cpu_has_tsc processors */
 40 static int __read_mostly tsc_disabled = -1;
 41 
 42 static struct static_key __use_tsc = STATIC_KEY_INIT;
 43 
 44 int tsc_clocksource_reliable;
 45 
 46 /*
 47  * Use a ring-buffer like data structure, where a writer advances the head by
 48  * writing a new data entry and a reader advances the tail when it observes a
 49  * new entry.
 50  *
 51  * Writers are made to wait on readers until there's space to write a new
 52  * entry.
 53  *
 54  * This means that we can always use an {offset, mul} pair to compute a ns
 55  * value that is 'roughly' in the right direction, even if we're writing a new
 56  * {offset, mul} pair during the clock read.
 57  *
 58  * The down-side is that we can no longer guarantee strict monotonicity anymore
 59  * (assuming the TSC was that to begin with), because while we compute the
 60  * intersection point of the two clock slopes and make sure the time is
 61  * continuous at the point of switching; we can no longer guarantee a reader is
 62  * strictly before or after the switch point.
 63  *
 64  * It does mean a reader no longer needs to disable IRQs in order to avoid
 65  * CPU-Freq updates messing with his times, and similarly an NMI reader will
 66  * no longer run the risk of hitting half-written state.
 67  */
 68 
 69 struct cyc2ns {
 70         struct cyc2ns_data data[2];     /*  0 + 2*24 = 48 */
 71         struct cyc2ns_data *head;       /* 48 + 8    = 56 */
 72         struct cyc2ns_data *tail;       /* 56 + 8    = 64 */
 73 }; /* exactly fits one cacheline */
 74 
 75 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
 76 
 77 struct cyc2ns_data *cyc2ns_read_begin(void)
 78 {
 79         struct cyc2ns_data *head;
 80 
 81         preempt_disable();
 82 
 83         head = this_cpu_read(cyc2ns.head);
 84         /*
 85          * Ensure we observe the entry when we observe the pointer to it.
 86          * matches the wmb from cyc2ns_write_end().
 87          */
 88         smp_read_barrier_depends();
 89         head->__count++;
 90         barrier();
 91 
 92         return head;
 93 }
 94 
 95 void cyc2ns_read_end(struct cyc2ns_data *head)
 96 {
 97         barrier();
 98         /*
 99          * If we're the outer most nested read; update the tail pointer
100          * when we're done. This notifies possible pending writers
101          * that we've observed the head pointer and that the other
102          * entry is now free.
103          */
104         if (!--head->__count) {
105                 /*
106                  * x86-TSO does not reorder writes with older reads;
107                  * therefore once this write becomes visible to another
108                  * cpu, we must be finished reading the cyc2ns_data.
109                  *
110                  * matches with cyc2ns_write_begin().
111                  */
112                 this_cpu_write(cyc2ns.tail, head);
113         }
114         preempt_enable();
115 }
116 
117 /*
118  * Begin writing a new @data entry for @cpu.
119  *
120  * Assumes some sort of write side lock; currently 'provided' by the assumption
121  * that cpufreq will call its notifiers sequentially.
122  */
123 static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
124 {
125         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
126         struct cyc2ns_data *data = c2n->data;
127 
128         if (data == c2n->head)
129                 data++;
130 
131         /* XXX send an IPI to @cpu in order to guarantee a read? */
132 
133         /*
134          * When we observe the tail write from cyc2ns_read_end(),
135          * the cpu must be done with that entry and its safe
136          * to start writing to it.
137          */
138         while (c2n->tail == data)
139                 cpu_relax();
140 
141         return data;
142 }
143 
144 static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
145 {
146         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
147 
148         /*
149          * Ensure the @data writes are visible before we publish the
150          * entry. Matches the data-depencency in cyc2ns_read_begin().
151          */
152         smp_wmb();
153 
154         ACCESS_ONCE(c2n->head) = data;
155 }
156 
157 /*
158  * Accelerators for sched_clock()
159  * convert from cycles(64bits) => nanoseconds (64bits)
160  *  basic equation:
161  *              ns = cycles / (freq / ns_per_sec)
162  *              ns = cycles * (ns_per_sec / freq)
163  *              ns = cycles * (10^9 / (cpu_khz * 10^3))
164  *              ns = cycles * (10^6 / cpu_khz)
165  *
166  *      Then we use scaling math (suggested by george@mvista.com) to get:
167  *              ns = cycles * (10^6 * SC / cpu_khz) / SC
168  *              ns = cycles * cyc2ns_scale / SC
169  *
170  *      And since SC is a constant power of two, we can convert the div
171  *  into a shift.
172  *
173  *  We can use khz divisor instead of mhz to keep a better precision, since
174  *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
175  *  (mathieu.desnoyers@polymtl.ca)
176  *
177  *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
178  */
179 
180 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
181 
182 static void cyc2ns_data_init(struct cyc2ns_data *data)
183 {
184         data->cyc2ns_mul = 0;
185         data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
186         data->cyc2ns_offset = 0;
187         data->__count = 0;
188 }
189 
190 static void cyc2ns_init(int cpu)
191 {
192         struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
193 
194         cyc2ns_data_init(&c2n->data[0]);
195         cyc2ns_data_init(&c2n->data[1]);
196 
197         c2n->head = c2n->data;
198         c2n->tail = c2n->data;
199 }
200 
201 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
202 {
203         struct cyc2ns_data *data, *tail;
204         unsigned long long ns;
205 
206         /*
207          * See cyc2ns_read_*() for details; replicated in order to avoid
208          * an extra few instructions that came with the abstraction.
209          * Notable, it allows us to only do the __count and tail update
210          * dance when its actually needed.
211          */
212 
213         preempt_disable_notrace();
214         data = this_cpu_read(cyc2ns.head);
215         tail = this_cpu_read(cyc2ns.tail);
216 
217         if (likely(data == tail)) {
218                 ns = data->cyc2ns_offset;
219                 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
220         } else {
221                 data->__count++;
222 
223                 barrier();
224 
225                 ns = data->cyc2ns_offset;
226                 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
227 
228                 barrier();
229 
230                 if (!--data->__count)
231                         this_cpu_write(cyc2ns.tail, data);
232         }
233         preempt_enable_notrace();
234 
235         return ns;
236 }
237 
238 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
239 {
240         unsigned long long tsc_now, ns_now;
241         struct cyc2ns_data *data;
242         unsigned long flags;
243 
244         local_irq_save(flags);
245         sched_clock_idle_sleep_event();
246 
247         if (!cpu_khz)
248                 goto done;
249 
250         data = cyc2ns_write_begin(cpu);
251 
252         rdtscll(tsc_now);
253         ns_now = cycles_2_ns(tsc_now);
254 
255         /*
256          * Compute a new multiplier as per the above comment and ensure our
257          * time function is continuous; see the comment near struct
258          * cyc2ns_data.
259          */
260         data->cyc2ns_mul =
261                 DIV_ROUND_CLOSEST(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR,
262                                   cpu_khz);
263         data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
264         data->cyc2ns_offset = ns_now -
265                 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
266 
267         cyc2ns_write_end(cpu, data);
268 
269 done:
270         sched_clock_idle_wakeup_event(0);
271         local_irq_restore(flags);
272 }
273 /*
274  * Scheduler clock - returns current time in nanosec units.
275  */
276 u64 native_sched_clock(void)
277 {
278         u64 tsc_now;
279 
280         /*
281          * Fall back to jiffies if there's no TSC available:
282          * ( But note that we still use it if the TSC is marked
283          *   unstable. We do this because unlike Time Of Day,
284          *   the scheduler clock tolerates small errors and it's
285          *   very important for it to be as fast as the platform
286          *   can achieve it. )
287          */
288         if (!static_key_false(&__use_tsc)) {
289                 /* No locking but a rare wrong value is not a big deal: */
290                 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
291         }
292 
293         /* read the Time Stamp Counter: */
294         rdtscll(tsc_now);
295 
296         /* return the value in ns */
297         return cycles_2_ns(tsc_now);
298 }
299 
300 /* We need to define a real function for sched_clock, to override the
301    weak default version */
302 #ifdef CONFIG_PARAVIRT
303 unsigned long long sched_clock(void)
304 {
305         return paravirt_sched_clock();
306 }
307 #else
308 unsigned long long
309 sched_clock(void) __attribute__((alias("native_sched_clock")));
310 #endif
311 
312 unsigned long long native_read_tsc(void)
313 {
314         return __native_read_tsc();
315 }
316 EXPORT_SYMBOL(native_read_tsc);
317 
318 int check_tsc_unstable(void)
319 {
320         return tsc_unstable;
321 }
322 EXPORT_SYMBOL_GPL(check_tsc_unstable);
323 
324 int check_tsc_disabled(void)
325 {
326         return tsc_disabled;
327 }
328 EXPORT_SYMBOL_GPL(check_tsc_disabled);
329 
330 #ifdef CONFIG_X86_TSC
331 int __init notsc_setup(char *str)
332 {
333         pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
334         tsc_disabled = 1;
335         return 1;
336 }
337 #else
338 /*
339  * disable flag for tsc. Takes effect by clearing the TSC cpu flag
340  * in cpu/common.c
341  */
342 int __init notsc_setup(char *str)
343 {
344         setup_clear_cpu_cap(X86_FEATURE_TSC);
345         return 1;
346 }
347 #endif
348 
349 __setup("notsc", notsc_setup);
350 
351 static int no_sched_irq_time;
352 
353 static int __init tsc_setup(char *str)
354 {
355         if (!strcmp(str, "reliable"))
356                 tsc_clocksource_reliable = 1;
357         if (!strncmp(str, "noirqtime", 9))
358                 no_sched_irq_time = 1;
359         return 1;
360 }
361 
362 __setup("tsc=", tsc_setup);
363 
364 #define MAX_RETRIES     5
365 #define SMI_TRESHOLD    50000
366 
367 /*
368  * Read TSC and the reference counters. Take care of SMI disturbance
369  */
370 static u64 tsc_read_refs(u64 *p, int hpet)
371 {
372         u64 t1, t2;
373         int i;
374 
375         for (i = 0; i < MAX_RETRIES; i++) {
376                 t1 = get_cycles();
377                 if (hpet)
378                         *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
379                 else
380                         *p = acpi_pm_read_early();
381                 t2 = get_cycles();
382                 if ((t2 - t1) < SMI_TRESHOLD)
383                         return t2;
384         }
385         return ULLONG_MAX;
386 }
387 
388 /*
389  * Calculate the TSC frequency from HPET reference
390  */
391 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
392 {
393         u64 tmp;
394 
395         if (hpet2 < hpet1)
396                 hpet2 += 0x100000000ULL;
397         hpet2 -= hpet1;
398         tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
399         do_div(tmp, 1000000);
400         do_div(deltatsc, tmp);
401 
402         return (unsigned long) deltatsc;
403 }
404 
405 /*
406  * Calculate the TSC frequency from PMTimer reference
407  */
408 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
409 {
410         u64 tmp;
411 
412         if (!pm1 && !pm2)
413                 return ULONG_MAX;
414 
415         if (pm2 < pm1)
416                 pm2 += (u64)ACPI_PM_OVRRUN;
417         pm2 -= pm1;
418         tmp = pm2 * 1000000000LL;
419         do_div(tmp, PMTMR_TICKS_PER_SEC);
420         do_div(deltatsc, tmp);
421 
422         return (unsigned long) deltatsc;
423 }
424 
425 #define CAL_MS          10
426 #define CAL_LATCH       (PIT_TICK_RATE / (1000 / CAL_MS))
427 #define CAL_PIT_LOOPS   1000
428 
429 #define CAL2_MS         50
430 #define CAL2_LATCH      (PIT_TICK_RATE / (1000 / CAL2_MS))
431 #define CAL2_PIT_LOOPS  5000
432 
433 
434 /*
435  * Try to calibrate the TSC against the Programmable
436  * Interrupt Timer and return the frequency of the TSC
437  * in kHz.
438  *
439  * Return ULONG_MAX on failure to calibrate.
440  */
441 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
442 {
443         u64 tsc, t1, t2, delta;
444         unsigned long tscmin, tscmax;
445         int pitcnt;
446 
447         /* Set the Gate high, disable speaker */
448         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
449 
450         /*
451          * Setup CTC channel 2* for mode 0, (interrupt on terminal
452          * count mode), binary count. Set the latch register to 50ms
453          * (LSB then MSB) to begin countdown.
454          */
455         outb(0xb0, 0x43);
456         outb(latch & 0xff, 0x42);
457         outb(latch >> 8, 0x42);
458 
459         tsc = t1 = t2 = get_cycles();
460 
461         pitcnt = 0;
462         tscmax = 0;
463         tscmin = ULONG_MAX;
464         while ((inb(0x61) & 0x20) == 0) {
465                 t2 = get_cycles();
466                 delta = t2 - tsc;
467                 tsc = t2;
468                 if ((unsigned long) delta < tscmin)
469                         tscmin = (unsigned int) delta;
470                 if ((unsigned long) delta > tscmax)
471                         tscmax = (unsigned int) delta;
472                 pitcnt++;
473         }
474 
475         /*
476          * Sanity checks:
477          *
478          * If we were not able to read the PIT more than loopmin
479          * times, then we have been hit by a massive SMI
480          *
481          * If the maximum is 10 times larger than the minimum,
482          * then we got hit by an SMI as well.
483          */
484         if (pitcnt < loopmin || tscmax > 10 * tscmin)
485                 return ULONG_MAX;
486 
487         /* Calculate the PIT value */
488         delta = t2 - t1;
489         do_div(delta, ms);
490         return delta;
491 }
492 
493 /*
494  * This reads the current MSB of the PIT counter, and
495  * checks if we are running on sufficiently fast and
496  * non-virtualized hardware.
497  *
498  * Our expectations are:
499  *
500  *  - the PIT is running at roughly 1.19MHz
501  *
502  *  - each IO is going to take about 1us on real hardware,
503  *    but we allow it to be much faster (by a factor of 10) or
504  *    _slightly_ slower (ie we allow up to a 2us read+counter
505  *    update - anything else implies a unacceptably slow CPU
506  *    or PIT for the fast calibration to work.
507  *
508  *  - with 256 PIT ticks to read the value, we have 214us to
509  *    see the same MSB (and overhead like doing a single TSC
510  *    read per MSB value etc).
511  *
512  *  - We're doing 2 reads per loop (LSB, MSB), and we expect
513  *    them each to take about a microsecond on real hardware.
514  *    So we expect a count value of around 100. But we'll be
515  *    generous, and accept anything over 50.
516  *
517  *  - if the PIT is stuck, and we see *many* more reads, we
518  *    return early (and the next caller of pit_expect_msb()
519  *    then consider it a failure when they don't see the
520  *    next expected value).
521  *
522  * These expectations mean that we know that we have seen the
523  * transition from one expected value to another with a fairly
524  * high accuracy, and we didn't miss any events. We can thus
525  * use the TSC value at the transitions to calculate a pretty
526  * good value for the TSC frequencty.
527  */
528 static inline int pit_verify_msb(unsigned char val)
529 {
530         /* Ignore LSB */
531         inb(0x42);
532         return inb(0x42) == val;
533 }
534 
535 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
536 {
537         int count;
538         u64 tsc = 0, prev_tsc = 0;
539 
540         for (count = 0; count < 50000; count++) {
541                 if (!pit_verify_msb(val))
542                         break;
543                 prev_tsc = tsc;
544                 tsc = get_cycles();
545         }
546         *deltap = get_cycles() - prev_tsc;
547         *tscp = tsc;
548 
549         /*
550          * We require _some_ success, but the quality control
551          * will be based on the error terms on the TSC values.
552          */
553         return count > 5;
554 }
555 
556 /*
557  * How many MSB values do we want to see? We aim for
558  * a maximum error rate of 500ppm (in practice the
559  * real error is much smaller), but refuse to spend
560  * more than 50ms on it.
561  */
562 #define MAX_QUICK_PIT_MS 50
563 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
564 
565 static unsigned long quick_pit_calibrate(void)
566 {
567         int i;
568         u64 tsc, delta;
569         unsigned long d1, d2;
570 
571         /* Set the Gate high, disable speaker */
572         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
573 
574         /*
575          * Counter 2, mode 0 (one-shot), binary count
576          *
577          * NOTE! Mode 2 decrements by two (and then the
578          * output is flipped each time, giving the same
579          * final output frequency as a decrement-by-one),
580          * so mode 0 is much better when looking at the
581          * individual counts.
582          */
583         outb(0xb0, 0x43);
584 
585         /* Start at 0xffff */
586         outb(0xff, 0x42);
587         outb(0xff, 0x42);
588 
589         /*
590          * The PIT starts counting at the next edge, so we
591          * need to delay for a microsecond. The easiest way
592          * to do that is to just read back the 16-bit counter
593          * once from the PIT.
594          */
595         pit_verify_msb(0);
596 
597         if (pit_expect_msb(0xff, &tsc, &d1)) {
598                 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
599                         if (!pit_expect_msb(0xff-i, &delta, &d2))
600                                 break;
601 
602                         delta -= tsc;
603 
604                         /*
605                          * Extrapolate the error and fail fast if the error will
606                          * never be below 500 ppm.
607                          */
608                         if (i == 1 &&
609                             d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
610                                 return 0;
611 
612                         /*
613                          * Iterate until the error is less than 500 ppm
614                          */
615                         if (d1+d2 >= delta >> 11)
616                                 continue;
617 
618                         /*
619                          * Check the PIT one more time to verify that
620                          * all TSC reads were stable wrt the PIT.
621                          *
622                          * This also guarantees serialization of the
623                          * last cycle read ('d2') in pit_expect_msb.
624                          */
625                         if (!pit_verify_msb(0xfe - i))
626                                 break;
627                         goto success;
628                 }
629         }
630         pr_info("Fast TSC calibration failed\n");
631         return 0;
632 
633 success:
634         /*
635          * Ok, if we get here, then we've seen the
636          * MSB of the PIT decrement 'i' times, and the
637          * error has shrunk to less than 500 ppm.
638          *
639          * As a result, we can depend on there not being
640          * any odd delays anywhere, and the TSC reads are
641          * reliable (within the error).
642          *
643          * kHz = ticks / time-in-seconds / 1000;
644          * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
645          * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
646          */
647         delta *= PIT_TICK_RATE;
648         do_div(delta, i*256*1000);
649         pr_info("Fast TSC calibration using PIT\n");
650         return delta;
651 }
652 
653 /**
654  * native_calibrate_tsc - calibrate the tsc on boot
655  */
656 unsigned long native_calibrate_tsc(void)
657 {
658         u64 tsc1, tsc2, delta, ref1, ref2;
659         unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
660         unsigned long flags, latch, ms, fast_calibrate;
661         int hpet = is_hpet_enabled(), i, loopmin;
662 
663         /* Calibrate TSC using MSR for Intel Atom SoCs */
664         local_irq_save(flags);
665         fast_calibrate = try_msr_calibrate_tsc();
666         local_irq_restore(flags);
667         if (fast_calibrate)
668                 return fast_calibrate;
669 
670         local_irq_save(flags);
671         fast_calibrate = quick_pit_calibrate();
672         local_irq_restore(flags);
673         if (fast_calibrate)
674                 return fast_calibrate;
675 
676         /*
677          * Run 5 calibration loops to get the lowest frequency value
678          * (the best estimate). We use two different calibration modes
679          * here:
680          *
681          * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
682          * load a timeout of 50ms. We read the time right after we
683          * started the timer and wait until the PIT count down reaches
684          * zero. In each wait loop iteration we read the TSC and check
685          * the delta to the previous read. We keep track of the min
686          * and max values of that delta. The delta is mostly defined
687          * by the IO time of the PIT access, so we can detect when a
688          * SMI/SMM disturbance happened between the two reads. If the
689          * maximum time is significantly larger than the minimum time,
690          * then we discard the result and have another try.
691          *
692          * 2) Reference counter. If available we use the HPET or the
693          * PMTIMER as a reference to check the sanity of that value.
694          * We use separate TSC readouts and check inside of the
695          * reference read for a SMI/SMM disturbance. We dicard
696          * disturbed values here as well. We do that around the PIT
697          * calibration delay loop as we have to wait for a certain
698          * amount of time anyway.
699          */
700 
701         /* Preset PIT loop values */
702         latch = CAL_LATCH;
703         ms = CAL_MS;
704         loopmin = CAL_PIT_LOOPS;
705 
706         for (i = 0; i < 3; i++) {
707                 unsigned long tsc_pit_khz;
708 
709                 /*
710                  * Read the start value and the reference count of
711                  * hpet/pmtimer when available. Then do the PIT
712                  * calibration, which will take at least 50ms, and
713                  * read the end value.
714                  */
715                 local_irq_save(flags);
716                 tsc1 = tsc_read_refs(&ref1, hpet);
717                 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
718                 tsc2 = tsc_read_refs(&ref2, hpet);
719                 local_irq_restore(flags);
720 
721                 /* Pick the lowest PIT TSC calibration so far */
722                 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
723 
724                 /* hpet or pmtimer available ? */
725                 if (ref1 == ref2)
726                         continue;
727 
728                 /* Check, whether the sampling was disturbed by an SMI */
729                 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
730                         continue;
731 
732                 tsc2 = (tsc2 - tsc1) * 1000000LL;
733                 if (hpet)
734                         tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
735                 else
736                         tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
737 
738                 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
739 
740                 /* Check the reference deviation */
741                 delta = ((u64) tsc_pit_min) * 100;
742                 do_div(delta, tsc_ref_min);
743 
744                 /*
745                  * If both calibration results are inside a 10% window
746                  * then we can be sure, that the calibration
747                  * succeeded. We break out of the loop right away. We
748                  * use the reference value, as it is more precise.
749                  */
750                 if (delta >= 90 && delta <= 110) {
751                         pr_info("PIT calibration matches %s. %d loops\n",
752                                 hpet ? "HPET" : "PMTIMER", i + 1);
753                         return tsc_ref_min;
754                 }
755 
756                 /*
757                  * Check whether PIT failed more than once. This
758                  * happens in virtualized environments. We need to
759                  * give the virtual PC a slightly longer timeframe for
760                  * the HPET/PMTIMER to make the result precise.
761                  */
762                 if (i == 1 && tsc_pit_min == ULONG_MAX) {
763                         latch = CAL2_LATCH;
764                         ms = CAL2_MS;
765                         loopmin = CAL2_PIT_LOOPS;
766                 }
767         }
768 
769         /*
770          * Now check the results.
771          */
772         if (tsc_pit_min == ULONG_MAX) {
773                 /* PIT gave no useful value */
774                 pr_warn("Unable to calibrate against PIT\n");
775 
776                 /* We don't have an alternative source, disable TSC */
777                 if (!hpet && !ref1 && !ref2) {
778                         pr_notice("No reference (HPET/PMTIMER) available\n");
779                         return 0;
780                 }
781 
782                 /* The alternative source failed as well, disable TSC */
783                 if (tsc_ref_min == ULONG_MAX) {
784                         pr_warn("HPET/PMTIMER calibration failed\n");
785                         return 0;
786                 }
787 
788                 /* Use the alternative source */
789                 pr_info("using %s reference calibration\n",
790                         hpet ? "HPET" : "PMTIMER");
791 
792                 return tsc_ref_min;
793         }
794 
795         /* We don't have an alternative source, use the PIT calibration value */
796         if (!hpet && !ref1 && !ref2) {
797                 pr_info("Using PIT calibration value\n");
798                 return tsc_pit_min;
799         }
800 
801         /* The alternative source failed, use the PIT calibration value */
802         if (tsc_ref_min == ULONG_MAX) {
803                 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
804                 return tsc_pit_min;
805         }
806 
807         /*
808          * The calibration values differ too much. In doubt, we use
809          * the PIT value as we know that there are PMTIMERs around
810          * running at double speed. At least we let the user know:
811          */
812         pr_warn("PIT calibration deviates from %s: %lu %lu\n",
813                 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
814         pr_info("Using PIT calibration value\n");
815         return tsc_pit_min;
816 }
817 
818 int recalibrate_cpu_khz(void)
819 {
820 #ifndef CONFIG_SMP
821         unsigned long cpu_khz_old = cpu_khz;
822 
823         if (cpu_has_tsc) {
824                 tsc_khz = x86_platform.calibrate_tsc();
825                 cpu_khz = tsc_khz;
826                 cpu_data(0).loops_per_jiffy =
827                         cpufreq_scale(cpu_data(0).loops_per_jiffy,
828                                         cpu_khz_old, cpu_khz);
829                 return 0;
830         } else
831                 return -ENODEV;
832 #else
833         return -ENODEV;
834 #endif
835 }
836 
837 EXPORT_SYMBOL(recalibrate_cpu_khz);
838 
839 
840 static unsigned long long cyc2ns_suspend;
841 
842 void tsc_save_sched_clock_state(void)
843 {
844         if (!sched_clock_stable())
845                 return;
846 
847         cyc2ns_suspend = sched_clock();
848 }
849 
850 /*
851  * Even on processors with invariant TSC, TSC gets reset in some the
852  * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
853  * arbitrary value (still sync'd across cpu's) during resume from such sleep
854  * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
855  * that sched_clock() continues from the point where it was left off during
856  * suspend.
857  */
858 void tsc_restore_sched_clock_state(void)
859 {
860         unsigned long long offset;
861         unsigned long flags;
862         int cpu;
863 
864         if (!sched_clock_stable())
865                 return;
866 
867         local_irq_save(flags);
868 
869         /*
870          * We're comming out of suspend, there's no concurrency yet; don't
871          * bother being nice about the RCU stuff, just write to both
872          * data fields.
873          */
874 
875         this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
876         this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
877 
878         offset = cyc2ns_suspend - sched_clock();
879 
880         for_each_possible_cpu(cpu) {
881                 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
882                 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
883         }
884 
885         local_irq_restore(flags);
886 }
887 
888 #ifdef CONFIG_CPU_FREQ
889 
890 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
891  * changes.
892  *
893  * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
894  * not that important because current Opteron setups do not support
895  * scaling on SMP anyroads.
896  *
897  * Should fix up last_tsc too. Currently gettimeofday in the
898  * first tick after the change will be slightly wrong.
899  */
900 
901 static unsigned int  ref_freq;
902 static unsigned long loops_per_jiffy_ref;
903 static unsigned long tsc_khz_ref;
904 
905 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
906                                 void *data)
907 {
908         struct cpufreq_freqs *freq = data;
909         unsigned long *lpj;
910 
911         if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
912                 return 0;
913 
914         lpj = &boot_cpu_data.loops_per_jiffy;
915 #ifdef CONFIG_SMP
916         if (!(freq->flags & CPUFREQ_CONST_LOOPS))
917                 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
918 #endif
919 
920         if (!ref_freq) {
921                 ref_freq = freq->old;
922                 loops_per_jiffy_ref = *lpj;
923                 tsc_khz_ref = tsc_khz;
924         }
925         if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
926                         (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
927                 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
928 
929                 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
930                 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
931                         mark_tsc_unstable("cpufreq changes");
932 
933                 set_cyc2ns_scale(tsc_khz, freq->cpu);
934         }
935 
936         return 0;
937 }
938 
939 static struct notifier_block time_cpufreq_notifier_block = {
940         .notifier_call  = time_cpufreq_notifier
941 };
942 
943 static int __init cpufreq_tsc(void)
944 {
945         if (!cpu_has_tsc)
946                 return 0;
947         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
948                 return 0;
949         cpufreq_register_notifier(&time_cpufreq_notifier_block,
950                                 CPUFREQ_TRANSITION_NOTIFIER);
951         return 0;
952 }
953 
954 core_initcall(cpufreq_tsc);
955 
956 #endif /* CONFIG_CPU_FREQ */
957 
958 /* clocksource code */
959 
960 static struct clocksource clocksource_tsc;
961 
962 /*
963  * We used to compare the TSC to the cycle_last value in the clocksource
964  * structure to avoid a nasty time-warp. This can be observed in a
965  * very small window right after one CPU updated cycle_last under
966  * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
967  * is smaller than the cycle_last reference value due to a TSC which
968  * is slighty behind. This delta is nowhere else observable, but in
969  * that case it results in a forward time jump in the range of hours
970  * due to the unsigned delta calculation of the time keeping core
971  * code, which is necessary to support wrapping clocksources like pm
972  * timer.
973  *
974  * This sanity check is now done in the core timekeeping code.
975  * checking the result of read_tsc() - cycle_last for being negative.
976  * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
977  */
978 static cycle_t read_tsc(struct clocksource *cs)
979 {
980         return (cycle_t)get_cycles();
981 }
982 
983 /*
984  * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
985  */
986 static struct clocksource clocksource_tsc = {
987         .name                   = "tsc",
988         .rating                 = 300,
989         .read                   = read_tsc,
990         .mask                   = CLOCKSOURCE_MASK(64),
991         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
992                                   CLOCK_SOURCE_MUST_VERIFY,
993         .archdata               = { .vclock_mode = VCLOCK_TSC },
994 };
995 
996 void mark_tsc_unstable(char *reason)
997 {
998         if (!tsc_unstable) {
999                 tsc_unstable = 1;
1000                 clear_sched_clock_stable();
1001                 disable_sched_clock_irqtime();
1002                 pr_info("Marking TSC unstable due to %s\n", reason);
1003                 /* Change only the rating, when not registered */
1004                 if (clocksource_tsc.mult)
1005                         clocksource_mark_unstable(&clocksource_tsc);
1006                 else {
1007                         clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1008                         clocksource_tsc.rating = 0;
1009                 }
1010         }
1011 }
1012 
1013 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1014 
1015 static void __init check_system_tsc_reliable(void)
1016 {
1017 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1018         if (is_geode_lx()) {
1019                 /* RTSC counts during suspend */
1020 #define RTSC_SUSP 0x100
1021                 unsigned long res_low, res_high;
1022 
1023                 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1024                 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1025                 if (res_low & RTSC_SUSP)
1026                         tsc_clocksource_reliable = 1;
1027         }
1028 #endif
1029         if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1030                 tsc_clocksource_reliable = 1;
1031 }
1032 
1033 /*
1034  * Make an educated guess if the TSC is trustworthy and synchronized
1035  * over all CPUs.
1036  */
1037 int unsynchronized_tsc(void)
1038 {
1039         if (!cpu_has_tsc || tsc_unstable)
1040                 return 1;
1041 
1042 #ifdef CONFIG_SMP
1043         if (apic_is_clustered_box())
1044                 return 1;
1045 #endif
1046 
1047         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1048                 return 0;
1049 
1050         if (tsc_clocksource_reliable)
1051                 return 0;
1052         /*
1053          * Intel systems are normally all synchronized.
1054          * Exceptions must mark TSC as unstable:
1055          */
1056         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1057                 /* assume multi socket systems are not synchronized: */
1058                 if (num_possible_cpus() > 1)
1059                         return 1;
1060         }
1061 
1062         return 0;
1063 }
1064 
1065 
1066 static void tsc_refine_calibration_work(struct work_struct *work);
1067 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1068 /**
1069  * tsc_refine_calibration_work - Further refine tsc freq calibration
1070  * @work - ignored.
1071  *
1072  * This functions uses delayed work over a period of a
1073  * second to further refine the TSC freq value. Since this is
1074  * timer based, instead of loop based, we don't block the boot
1075  * process while this longer calibration is done.
1076  *
1077  * If there are any calibration anomalies (too many SMIs, etc),
1078  * or the refined calibration is off by 1% of the fast early
1079  * calibration, we throw out the new calibration and use the
1080  * early calibration.
1081  */
1082 static void tsc_refine_calibration_work(struct work_struct *work)
1083 {
1084         static u64 tsc_start = -1, ref_start;
1085         static int hpet;
1086         u64 tsc_stop, ref_stop, delta;
1087         unsigned long freq;
1088 
1089         /* Don't bother refining TSC on unstable systems */
1090         if (check_tsc_unstable())
1091                 goto out;
1092 
1093         /*
1094          * Since the work is started early in boot, we may be
1095          * delayed the first time we expire. So set the workqueue
1096          * again once we know timers are working.
1097          */
1098         if (tsc_start == -1) {
1099                 /*
1100                  * Only set hpet once, to avoid mixing hardware
1101                  * if the hpet becomes enabled later.
1102                  */
1103                 hpet = is_hpet_enabled();
1104                 schedule_delayed_work(&tsc_irqwork, HZ);
1105                 tsc_start = tsc_read_refs(&ref_start, hpet);
1106                 return;
1107         }
1108 
1109         tsc_stop = tsc_read_refs(&ref_stop, hpet);
1110 
1111         /* hpet or pmtimer available ? */
1112         if (ref_start == ref_stop)
1113                 goto out;
1114 
1115         /* Check, whether the sampling was disturbed by an SMI */
1116         if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1117                 goto out;
1118 
1119         delta = tsc_stop - tsc_start;
1120         delta *= 1000000LL;
1121         if (hpet)
1122                 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1123         else
1124                 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1125 
1126         /* Make sure we're within 1% */
1127         if (abs(tsc_khz - freq) > tsc_khz/100)
1128                 goto out;
1129 
1130         tsc_khz = freq;
1131         pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1132                 (unsigned long)tsc_khz / 1000,
1133                 (unsigned long)tsc_khz % 1000);
1134 
1135 out:
1136         clocksource_register_khz(&clocksource_tsc, tsc_khz);
1137 }
1138 
1139 
1140 static int __init init_tsc_clocksource(void)
1141 {
1142         if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1143                 return 0;
1144 
1145         if (tsc_clocksource_reliable)
1146                 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1147         /* lower the rating if we already know its unstable: */
1148         if (check_tsc_unstable()) {
1149                 clocksource_tsc.rating = 0;
1150                 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1151         }
1152 
1153         if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1154                 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1155 
1156         /*
1157          * Trust the results of the earlier calibration on systems
1158          * exporting a reliable TSC.
1159          */
1160         if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1161                 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1162                 return 0;
1163         }
1164 
1165         schedule_delayed_work(&tsc_irqwork, 0);
1166         return 0;
1167 }
1168 /*
1169  * We use device_initcall here, to ensure we run after the hpet
1170  * is fully initialized, which may occur at fs_initcall time.
1171  */
1172 device_initcall(init_tsc_clocksource);
1173 
1174 void __init tsc_init(void)
1175 {
1176         u64 lpj;
1177         int cpu;
1178 
1179         x86_init.timers.tsc_pre_init();
1180 
1181         if (!cpu_has_tsc) {
1182                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1183                 return;
1184         }
1185 
1186         tsc_khz = x86_platform.calibrate_tsc();
1187         cpu_khz = tsc_khz;
1188 
1189         if (!tsc_khz) {
1190                 mark_tsc_unstable("could not calculate TSC khz");
1191                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1192                 return;
1193         }
1194 
1195         pr_info("Detected %lu.%03lu MHz processor\n",
1196                 (unsigned long)cpu_khz / 1000,
1197                 (unsigned long)cpu_khz % 1000);
1198 
1199         /*
1200          * Secondary CPUs do not run through tsc_init(), so set up
1201          * all the scale factors for all CPUs, assuming the same
1202          * speed as the bootup CPU. (cpufreq notifiers will fix this
1203          * up if their speed diverges)
1204          */
1205         for_each_possible_cpu(cpu) {
1206                 cyc2ns_init(cpu);
1207                 set_cyc2ns_scale(cpu_khz, cpu);
1208         }
1209 
1210         if (tsc_disabled > 0)
1211                 return;
1212 
1213         /* now allow native_sched_clock() to use rdtsc */
1214 
1215         tsc_disabled = 0;
1216         static_key_slow_inc(&__use_tsc);
1217 
1218         if (!no_sched_irq_time)
1219                 enable_sched_clock_irqtime();
1220 
1221         lpj = ((u64)tsc_khz * 1000);
1222         do_div(lpj, HZ);
1223         lpj_fine = lpj;
1224 
1225         use_tsc_delay();
1226 
1227         if (unsynchronized_tsc())
1228                 mark_tsc_unstable("TSCs unsynchronized");
1229 
1230         check_system_tsc_reliable();
1231 }
1232 
1233 #ifdef CONFIG_SMP
1234 /*
1235  * If we have a constant TSC and are using the TSC for the delay loop,
1236  * we can skip clock calibration if another cpu in the same socket has already
1237  * been calibrated. This assumes that CONSTANT_TSC applies to all
1238  * cpus in the socket - this should be a safe assumption.
1239  */
1240 unsigned long calibrate_delay_is_known(void)
1241 {
1242         int i, cpu = smp_processor_id();
1243 
1244         if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1245                 return 0;
1246 
1247         for_each_online_cpu(i)
1248                 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1249                         return cpu_data(i).loops_per_jiffy;
1250         return 0;
1251 }
1252 #endif
1253 

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