~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/tsc_msr.c

Version: ~ [ linux-5.6-rc1 ] ~ [ linux-5.5.2 ] ~ [ linux-5.4.17 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.102 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.170 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.213 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.213 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.81 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
  3  *
  4  * TSC in Intel Atom SoC runs at a constant rate which can be figured
  5  * by this formula:
  6  * <maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
  7  * See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
  8  * for details.
  9  * Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR
 10  * based calibration is the only option.
 11  *
 12  *
 13  * Copyright (C) 2013 Intel Corporation
 14  * Author: Bin Gao <bin.gao@intel.com>
 15  *
 16  * This file is released under the GPLv2.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <asm/processor.h>
 21 #include <asm/setup.h>
 22 #include <asm/apic.h>
 23 #include <asm/param.h>
 24 
 25 /* CPU reference clock frequency: in KHz */
 26 #define FREQ_83         83200
 27 #define FREQ_100        99840
 28 #define FREQ_133        133200
 29 #define FREQ_166        166400
 30 
 31 #define MAX_NUM_FREQS   8
 32 
 33 /*
 34  * According to Intel 64 and IA-32 System Programming Guide,
 35  * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
 36  * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
 37  * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
 38  * so we need manually differentiate SoC families. This is what the
 39  * field msr_plat does.
 40  */
 41 struct freq_desc {
 42         u8 x86_family;  /* CPU family */
 43         u8 x86_model;   /* model */
 44         u8 msr_plat;    /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
 45         u32 freqs[MAX_NUM_FREQS];
 46 };
 47 
 48 static struct freq_desc freq_desc_tables[] = {
 49         /* PNW */
 50         { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
 51         /* CLV+ */
 52         { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
 53         /* TNG */
 54         { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
 55         /* VLV2 */
 56         { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 57         /* ANN */
 58         { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
 59 };
 60 
 61 static int match_cpu(u8 family, u8 model)
 62 {
 63         int i;
 64 
 65         for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
 66                 if ((family == freq_desc_tables[i].x86_family) &&
 67                         (model == freq_desc_tables[i].x86_model))
 68                         return i;
 69         }
 70 
 71         return -1;
 72 }
 73 
 74 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
 75 #define id_to_freq(cpu_index, freq_id) \
 76         (freq_desc_tables[cpu_index].freqs[freq_id])
 77 
 78 /*
 79  * Do MSR calibration only for known/supported CPUs.
 80  *
 81  * Returns the calibration value or 0 if MSR calibration failed.
 82  */
 83 unsigned long try_msr_calibrate_tsc(void)
 84 {
 85         u32 lo, hi, ratio, freq_id, freq;
 86         unsigned long res;
 87         int cpu_index;
 88 
 89         cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
 90         if (cpu_index < 0)
 91                 return 0;
 92 
 93         if (freq_desc_tables[cpu_index].msr_plat) {
 94                 rdmsr(MSR_PLATFORM_INFO, lo, hi);
 95                 ratio = (lo >> 8) & 0x1f;
 96         } else {
 97                 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 98                 ratio = (hi >> 8) & 0x1f;
 99         }
100         pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
101 
102         if (!ratio)
103                 goto fail;
104 
105         /* Get FSB FREQ ID */
106         rdmsr(MSR_FSB_FREQ, lo, hi);
107         freq_id = lo & 0x7;
108         freq = id_to_freq(cpu_index, freq_id);
109         pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
110                                 freq_id, freq);
111         if (!freq)
112                 goto fail;
113 
114         /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
115         res = freq * ratio;
116         pr_info("TSC runs at %lu KHz\n", res);
117 
118 #ifdef CONFIG_X86_LOCAL_APIC
119         lapic_timer_frequency = (freq * 1000) / HZ;
120         pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
121 #endif
122         return res;
123 
124 fail:
125         pr_warn("Fast TSC calibration using MSR failed\n");
126         return 0;
127 }
128 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp