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Linux/arch/x86/kernel/tsc_sync.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * check TSC synchronization.
  4  *
  5  * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
  6  *
  7  * We check whether all boot CPUs have their TSC's synchronized,
  8  * print a warning if not and turn off the TSC clock-source.
  9  *
 10  * The warp-check is point-to-point between two CPUs, the CPU
 11  * initiating the bootup is the 'source CPU', the freshly booting
 12  * CPU is the 'target CPU'.
 13  *
 14  * Only two CPUs may participate - they can enter in any order.
 15  * ( The serial nature of the boot logic and the CPU hotplug lock
 16  *   protects against more than 2 CPUs entering this code. )
 17  */
 18 #include <linux/topology.h>
 19 #include <linux/spinlock.h>
 20 #include <linux/kernel.h>
 21 #include <linux/smp.h>
 22 #include <linux/nmi.h>
 23 #include <asm/tsc.h>
 24 
 25 struct tsc_adjust {
 26         s64             bootval;
 27         s64             adjusted;
 28         unsigned long   nextcheck;
 29         bool            warned;
 30 };
 31 
 32 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
 33 
 34 /*
 35  * TSC's on different sockets may be reset asynchronously.
 36  * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
 37  */
 38 bool __read_mostly tsc_async_resets;
 39 
 40 void mark_tsc_async_resets(char *reason)
 41 {
 42         if (tsc_async_resets)
 43                 return;
 44         tsc_async_resets = true;
 45         pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
 46 }
 47 
 48 void tsc_verify_tsc_adjust(bool resume)
 49 {
 50         struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
 51         s64 curval;
 52 
 53         if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
 54                 return;
 55 
 56         /* Skip unnecessary error messages if TSC already unstable */
 57         if (check_tsc_unstable())
 58                 return;
 59 
 60         /* Rate limit the MSR check */
 61         if (!resume && time_before(jiffies, adj->nextcheck))
 62                 return;
 63 
 64         adj->nextcheck = jiffies + HZ;
 65 
 66         rdmsrl(MSR_IA32_TSC_ADJUST, curval);
 67         if (adj->adjusted == curval)
 68                 return;
 69 
 70         /* Restore the original value */
 71         wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
 72 
 73         if (!adj->warned || resume) {
 74                 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
 75                         smp_processor_id(), adj->adjusted, curval);
 76                 adj->warned = true;
 77         }
 78 }
 79 
 80 static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
 81                                    unsigned int cpu, bool bootcpu)
 82 {
 83         /*
 84          * First online CPU in a package stores the boot value in the
 85          * adjustment value. This value might change later via the sync
 86          * mechanism. If that fails we still can yell about boot values not
 87          * being consistent.
 88          *
 89          * On the boot cpu we just force set the ADJUST value to 0 if it's
 90          * non zero. We don't do that on non boot cpus because physical
 91          * hotplug should have set the ADJUST register to a value > 0 so
 92          * the TSC is in sync with the already running cpus.
 93          *
 94          * Also don't force the ADJUST value to zero if that is a valid value
 95          * for socket 0 as determined by the system arch.  This is required
 96          * when multiple sockets are reset asynchronously with each other
 97          * and socket 0 may not have an TSC ADJUST value of 0.
 98          */
 99         if (bootcpu && bootval != 0) {
100                 if (likely(!tsc_async_resets)) {
101                         pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
102                                 cpu, bootval);
103                         wrmsrl(MSR_IA32_TSC_ADJUST, 0);
104                         bootval = 0;
105                 } else {
106                         pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
107                                 cpu, bootval);
108                 }
109         }
110         cur->adjusted = bootval;
111 }
112 
113 #ifndef CONFIG_SMP
114 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
115 {
116         struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
117         s64 bootval;
118 
119         if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
120                 return false;
121 
122         /* Skip unnecessary error messages if TSC already unstable */
123         if (check_tsc_unstable())
124                 return false;
125 
126         rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
127         cur->bootval = bootval;
128         cur->nextcheck = jiffies + HZ;
129         tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
130         return false;
131 }
132 
133 #else /* !CONFIG_SMP */
134 
135 /*
136  * Store and check the TSC ADJUST MSR if available
137  */
138 bool tsc_store_and_check_tsc_adjust(bool bootcpu)
139 {
140         struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
141         unsigned int refcpu, cpu = smp_processor_id();
142         struct cpumask *mask;
143         s64 bootval;
144 
145         if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
146                 return false;
147 
148         rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
149         cur->bootval = bootval;
150         cur->nextcheck = jiffies + HZ;
151         cur->warned = false;
152 
153         /*
154          * If a non-zero TSC value for socket 0 may be valid then the default
155          * adjusted value cannot assumed to be zero either.
156          */
157         if (tsc_async_resets)
158                 cur->adjusted = bootval;
159 
160         /*
161          * Check whether this CPU is the first in a package to come up. In
162          * this case do not check the boot value against another package
163          * because the new package might have been physically hotplugged,
164          * where TSC_ADJUST is expected to be different. When called on the
165          * boot CPU topology_core_cpumask() might not be available yet.
166          */
167         mask = topology_core_cpumask(cpu);
168         refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
169 
170         if (refcpu >= nr_cpu_ids) {
171                 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
172                                        bootcpu);
173                 return false;
174         }
175 
176         ref = per_cpu_ptr(&tsc_adjust, refcpu);
177         /*
178          * Compare the boot value and complain if it differs in the
179          * package.
180          */
181         if (bootval != ref->bootval)
182                 printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
183 
184         /*
185          * The TSC_ADJUST values in a package must be the same. If the boot
186          * value on this newly upcoming CPU differs from the adjustment
187          * value of the already online CPU in this package, set it to that
188          * adjusted value.
189          */
190         if (bootval != ref->adjusted) {
191                 cur->adjusted = ref->adjusted;
192                 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
193         }
194         /*
195          * We have the TSCs forced to be in sync on this package. Skip sync
196          * test:
197          */
198         return true;
199 }
200 
201 /*
202  * Entry/exit counters that make sure that both CPUs
203  * run the measurement code at once:
204  */
205 static atomic_t start_count;
206 static atomic_t stop_count;
207 static atomic_t skip_test;
208 static atomic_t test_runs;
209 
210 /*
211  * We use a raw spinlock in this exceptional case, because
212  * we want to have the fastest, inlined, non-debug version
213  * of a critical section, to be able to prove TSC time-warps:
214  */
215 static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
216 
217 static cycles_t last_tsc;
218 static cycles_t max_warp;
219 static int nr_warps;
220 static int random_warps;
221 
222 /*
223  * TSC-warp measurement loop running on both CPUs.  This is not called
224  * if there is no TSC.
225  */
226 static cycles_t check_tsc_warp(unsigned int timeout)
227 {
228         cycles_t start, now, prev, end, cur_max_warp = 0;
229         int i, cur_warps = 0;
230 
231         start = rdtsc_ordered();
232         /*
233          * The measurement runs for 'timeout' msecs:
234          */
235         end = start + (cycles_t) tsc_khz * timeout;
236         now = start;
237 
238         for (i = 0; ; i++) {
239                 /*
240                  * We take the global lock, measure TSC, save the
241                  * previous TSC that was measured (possibly on
242                  * another CPU) and update the previous TSC timestamp.
243                  */
244                 arch_spin_lock(&sync_lock);
245                 prev = last_tsc;
246                 now = rdtsc_ordered();
247                 last_tsc = now;
248                 arch_spin_unlock(&sync_lock);
249 
250                 /*
251                  * Be nice every now and then (and also check whether
252                  * measurement is done [we also insert a 10 million
253                  * loops safety exit, so we dont lock up in case the
254                  * TSC readout is totally broken]):
255                  */
256                 if (unlikely(!(i & 7))) {
257                         if (now > end || i > 10000000)
258                                 break;
259                         cpu_relax();
260                         touch_nmi_watchdog();
261                 }
262                 /*
263                  * Outside the critical section we can now see whether
264                  * we saw a time-warp of the TSC going backwards:
265                  */
266                 if (unlikely(prev > now)) {
267                         arch_spin_lock(&sync_lock);
268                         max_warp = max(max_warp, prev - now);
269                         cur_max_warp = max_warp;
270                         /*
271                          * Check whether this bounces back and forth. Only
272                          * one CPU should observe time going backwards.
273                          */
274                         if (cur_warps != nr_warps)
275                                 random_warps++;
276                         nr_warps++;
277                         cur_warps = nr_warps;
278                         arch_spin_unlock(&sync_lock);
279                 }
280         }
281         WARN(!(now-start),
282                 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
283                         now-start, end-start);
284         return cur_max_warp;
285 }
286 
287 /*
288  * If the target CPU coming online doesn't have any of its core-siblings
289  * online, a timeout of 20msec will be used for the TSC-warp measurement
290  * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
291  * information about this socket already (and this information grows as we
292  * have more and more logical-siblings in that socket).
293  *
294  * Ideally we should be able to skip the TSC sync check on the other
295  * core-siblings, if the first logical CPU in a socket passed the sync test.
296  * But as the TSC is per-logical CPU and can potentially be modified wrongly
297  * by the bios, TSC sync test for smaller duration should be able
298  * to catch such errors. Also this will catch the condition where all the
299  * cores in the socket doesn't get reset at the same time.
300  */
301 static inline unsigned int loop_timeout(int cpu)
302 {
303         return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
304 }
305 
306 /*
307  * Source CPU calls into this - it waits for the freshly booted
308  * target CPU to arrive and then starts the measurement:
309  */
310 void check_tsc_sync_source(int cpu)
311 {
312         int cpus = 2;
313 
314         /*
315          * No need to check if we already know that the TSC is not
316          * synchronized or if we have no TSC.
317          */
318         if (unsynchronized_tsc())
319                 return;
320 
321         /*
322          * Set the maximum number of test runs to
323          *  1 if the CPU does not provide the TSC_ADJUST MSR
324          *  3 if the MSR is available, so the target can try to adjust
325          */
326         if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
327                 atomic_set(&test_runs, 1);
328         else
329                 atomic_set(&test_runs, 3);
330 retry:
331         /*
332          * Wait for the target to start or to skip the test:
333          */
334         while (atomic_read(&start_count) != cpus - 1) {
335                 if (atomic_read(&skip_test) > 0) {
336                         atomic_set(&skip_test, 0);
337                         return;
338                 }
339                 cpu_relax();
340         }
341 
342         /*
343          * Trigger the target to continue into the measurement too:
344          */
345         atomic_inc(&start_count);
346 
347         check_tsc_warp(loop_timeout(cpu));
348 
349         while (atomic_read(&stop_count) != cpus-1)
350                 cpu_relax();
351 
352         /*
353          * If the test was successful set the number of runs to zero and
354          * stop. If not, decrement the number of runs an check if we can
355          * retry. In case of random warps no retry is attempted.
356          */
357         if (!nr_warps) {
358                 atomic_set(&test_runs, 0);
359 
360                 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
361                         smp_processor_id(), cpu);
362 
363         } else if (atomic_dec_and_test(&test_runs) || random_warps) {
364                 /* Force it to 0 if random warps brought us here */
365                 atomic_set(&test_runs, 0);
366 
367                 pr_warning("TSC synchronization [CPU#%d -> CPU#%d]:\n",
368                         smp_processor_id(), cpu);
369                 pr_warning("Measured %Ld cycles TSC warp between CPUs, "
370                            "turning off TSC clock.\n", max_warp);
371                 if (random_warps)
372                         pr_warning("TSC warped randomly between CPUs\n");
373                 mark_tsc_unstable("check_tsc_sync_source failed");
374         }
375 
376         /*
377          * Reset it - just in case we boot another CPU later:
378          */
379         atomic_set(&start_count, 0);
380         random_warps = 0;
381         nr_warps = 0;
382         max_warp = 0;
383         last_tsc = 0;
384 
385         /*
386          * Let the target continue with the bootup:
387          */
388         atomic_inc(&stop_count);
389 
390         /*
391          * Retry, if there is a chance to do so.
392          */
393         if (atomic_read(&test_runs) > 0)
394                 goto retry;
395 }
396 
397 /*
398  * Freshly booted CPUs call into this:
399  */
400 void check_tsc_sync_target(void)
401 {
402         struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
403         unsigned int cpu = smp_processor_id();
404         cycles_t cur_max_warp, gbl_max_warp;
405         int cpus = 2;
406 
407         /* Also aborts if there is no TSC. */
408         if (unsynchronized_tsc())
409                 return;
410 
411         /*
412          * Store, verify and sanitize the TSC adjust register. If
413          * successful skip the test.
414          *
415          * The test is also skipped when the TSC is marked reliable. This
416          * is true for SoCs which have no fallback clocksource. On these
417          * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
418          * register might have been wreckaged by the BIOS..
419          */
420         if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable) {
421                 atomic_inc(&skip_test);
422                 return;
423         }
424 
425 retry:
426         /*
427          * Register this CPU's participation and wait for the
428          * source CPU to start the measurement:
429          */
430         atomic_inc(&start_count);
431         while (atomic_read(&start_count) != cpus)
432                 cpu_relax();
433 
434         cur_max_warp = check_tsc_warp(loop_timeout(cpu));
435 
436         /*
437          * Store the maximum observed warp value for a potential retry:
438          */
439         gbl_max_warp = max_warp;
440 
441         /*
442          * Ok, we are done:
443          */
444         atomic_inc(&stop_count);
445 
446         /*
447          * Wait for the source CPU to print stuff:
448          */
449         while (atomic_read(&stop_count) != cpus)
450                 cpu_relax();
451 
452         /*
453          * Reset it for the next sync test:
454          */
455         atomic_set(&stop_count, 0);
456 
457         /*
458          * Check the number of remaining test runs. If not zero, the test
459          * failed and a retry with adjusted TSC is possible. If zero the
460          * test was either successful or failed terminally.
461          */
462         if (!atomic_read(&test_runs))
463                 return;
464 
465         /*
466          * If the warp value of this CPU is 0, then the other CPU
467          * observed time going backwards so this TSC was ahead and
468          * needs to move backwards.
469          */
470         if (!cur_max_warp)
471                 cur_max_warp = -gbl_max_warp;
472 
473         /*
474          * Add the result to the previous adjustment value.
475          *
476          * The adjustement value is slightly off by the overhead of the
477          * sync mechanism (observed values are ~200 TSC cycles), but this
478          * really depends on CPU, node distance and frequency. So
479          * compensating for this is hard to get right. Experiments show
480          * that the warp is not longer detectable when the observed warp
481          * value is used. In the worst case the adjustment needs to go
482          * through a 3rd run for fine tuning.
483          */
484         cur->adjusted += cur_max_warp;
485 
486         pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
487                 cpu, cur_max_warp, cur->adjusted);
488 
489         wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
490         goto retry;
491 
492 }
493 
494 #endif /* CONFIG_SMP */
495 

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