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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/lapic.c

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  1 
  2 /*
  3  * Local APIC virtualization
  4  *
  5  * Copyright (C) 2006 Qumranet, Inc.
  6  * Copyright (C) 2007 Novell
  7  * Copyright (C) 2007 Intel
  8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
  9  *
 10  * Authors:
 11  *   Dor Laor <dor.laor@qumranet.com>
 12  *   Gregory Haskins <ghaskins@novell.com>
 13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
 14  *
 15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
 16  *
 17  * This work is licensed under the terms of the GNU GPL, version 2.  See
 18  * the COPYING file in the top-level directory.
 19  */
 20 
 21 #include <linux/kvm_host.h>
 22 #include <linux/kvm.h>
 23 #include <linux/mm.h>
 24 #include <linux/highmem.h>
 25 #include <linux/smp.h>
 26 #include <linux/hrtimer.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/math64.h>
 30 #include <linux/slab.h>
 31 #include <asm/processor.h>
 32 #include <asm/msr.h>
 33 #include <asm/page.h>
 34 #include <asm/current.h>
 35 #include <asm/apicdef.h>
 36 #include <asm/delay.h>
 37 #include <linux/atomic.h>
 38 #include <linux/jump_label.h>
 39 #include "kvm_cache_regs.h"
 40 #include "irq.h"
 41 #include "trace.h"
 42 #include "x86.h"
 43 #include "cpuid.h"
 44 
 45 #ifndef CONFIG_X86_64
 46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
 47 #else
 48 #define mod_64(x, y) ((x) % (y))
 49 #endif
 50 
 51 #define PRId64 "d"
 52 #define PRIx64 "llx"
 53 #define PRIu64 "u"
 54 #define PRIo64 "o"
 55 
 56 #define APIC_BUS_CYCLE_NS 1
 57 
 58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
 59 #define apic_debug(fmt, arg...)
 60 
 61 #define APIC_LVT_NUM                    6
 62 /* 14 is the version for Xeon and Pentium 8.4.8*/
 63 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
 64 #define LAPIC_MMIO_LENGTH               (1 << 12)
 65 /* followed define is not in apicdef.h */
 66 #define APIC_SHORT_MASK                 0xc0000
 67 #define APIC_DEST_NOSHORT               0x0
 68 #define APIC_DEST_MASK                  0x800
 69 #define MAX_APIC_VECTOR                 256
 70 #define APIC_VECTORS_PER_REG            32
 71 
 72 #define APIC_BROADCAST                  0xFF
 73 #define X2APIC_BROADCAST                0xFFFFFFFFul
 74 
 75 #define VEC_POS(v) ((v) & (32 - 1))
 76 #define REG_POS(v) (((v) >> 5) << 4)
 77 
 78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 79 {
 80         *((u32 *) (apic->regs + reg_off)) = val;
 81 }
 82 
 83 static inline int apic_test_vector(int vec, void *bitmap)
 84 {
 85         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 86 }
 87 
 88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
 89 {
 90         struct kvm_lapic *apic = vcpu->arch.apic;
 91 
 92         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
 93                 apic_test_vector(vector, apic->regs + APIC_IRR);
 94 }
 95 
 96 static inline void apic_set_vector(int vec, void *bitmap)
 97 {
 98         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 99 }
100 
101 static inline void apic_clear_vector(int vec, void *bitmap)
102 {
103         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104 }
105 
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 {
108         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109 }
110 
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 {
113         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114 }
115 
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
118 
119 static inline int apic_enabled(struct kvm_lapic *apic)
120 {
121         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
122 }
123 
124 #define LVT_MASK        \
125         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126 
127 #define LINT_MASK       \
128         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 {
133         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
134 }
135 
136 /* The logical map is definitely wrong if we have multiple
137  * modes at the same time.  (Physical map is always right.)
138  */
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140 {
141         return !(map->mode & (map->mode - 1));
142 }
143 
144 static inline void
145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146 {
147         unsigned lid_bits;
148 
149         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER !=  4);
150         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT    !=  8);
151         BUILD_BUG_ON(KVM_APIC_MODE_X2APIC        != 16);
152         lid_bits = map->mode;
153 
154         *cid = dest_id >> lid_bits;
155         *lid = dest_id & ((1 << lid_bits) - 1);
156 }
157 
158 static void recalculate_apic_map(struct kvm *kvm)
159 {
160         struct kvm_apic_map *new, *old = NULL;
161         struct kvm_vcpu *vcpu;
162         int i;
163 
164         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165 
166         mutex_lock(&kvm->arch.apic_map_lock);
167 
168         if (!new)
169                 goto out;
170 
171         kvm_for_each_vcpu(i, vcpu, kvm) {
172                 struct kvm_lapic *apic = vcpu->arch.apic;
173                 u16 cid, lid;
174                 u32 ldr, aid;
175 
176                 if (!kvm_apic_present(vcpu))
177                         continue;
178 
179                 aid = kvm_apic_id(apic);
180                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
181 
182                 if (aid < ARRAY_SIZE(new->phys_map))
183                         new->phys_map[aid] = apic;
184 
185                 if (apic_x2apic_mode(apic)) {
186                         new->mode |= KVM_APIC_MODE_X2APIC;
187                 } else if (ldr) {
188                         ldr = GET_APIC_LOGICAL_ID(ldr);
189                         if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191                         else
192                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193                 }
194 
195                 if (!kvm_apic_logical_map_valid(new))
196                         continue;
197 
198                 apic_logical_id(new, ldr, &cid, &lid);
199 
200                 if (lid && cid < ARRAY_SIZE(new->logical_map))
201                         new->logical_map[cid][ffs(lid) - 1] = apic;
202         }
203 out:
204         old = rcu_dereference_protected(kvm->arch.apic_map,
205                         lockdep_is_held(&kvm->arch.apic_map_lock));
206         rcu_assign_pointer(kvm->arch.apic_map, new);
207         mutex_unlock(&kvm->arch.apic_map_lock);
208 
209         if (old)
210                 kfree_rcu(old, rcu);
211 
212         kvm_vcpu_request_scan_ioapic(kvm);
213 }
214 
215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216 {
217         bool enabled = val & APIC_SPIV_APIC_ENABLED;
218 
219         apic_set_reg(apic, APIC_SPIV, val);
220 
221         if (enabled != apic->sw_enabled) {
222                 apic->sw_enabled = enabled;
223                 if (enabled) {
224                         static_key_slow_dec_deferred(&apic_sw_disabled);
225                         recalculate_apic_map(apic->vcpu->kvm);
226                 } else
227                         static_key_slow_inc(&apic_sw_disabled.key);
228         }
229 }
230 
231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232 {
233         apic_set_reg(apic, APIC_ID, id << 24);
234         recalculate_apic_map(apic->vcpu->kvm);
235 }
236 
237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238 {
239         apic_set_reg(apic, APIC_LDR, id);
240         recalculate_apic_map(apic->vcpu->kvm);
241 }
242 
243 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244 {
245         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246 
247         apic_set_reg(apic, APIC_ID, id << 24);
248         apic_set_reg(apic, APIC_LDR, ldr);
249         recalculate_apic_map(apic->vcpu->kvm);
250 }
251 
252 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253 {
254         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
255 }
256 
257 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258 {
259         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
260 }
261 
262 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263 {
264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
265 }
266 
267 static inline int apic_lvtt_period(struct kvm_lapic *apic)
268 {
269         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
270 }
271 
272 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273 {
274         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
275 }
276 
277 static inline int apic_lvt_nmi_mode(u32 lvt_val)
278 {
279         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280 }
281 
282 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283 {
284         struct kvm_lapic *apic = vcpu->arch.apic;
285         struct kvm_cpuid_entry2 *feat;
286         u32 v = APIC_VERSION;
287 
288         if (!kvm_vcpu_has_lapic(vcpu))
289                 return;
290 
291         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293                 v |= APIC_LVR_DIRECTED_EOI;
294         apic_set_reg(apic, APIC_LVR, v);
295 }
296 
297 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
298         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
299         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
300         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
301         LINT_MASK, LINT_MASK,   /* LVT0-1 */
302         LVT_MASK                /* LVTERR */
303 };
304 
305 static int find_highest_vector(void *bitmap)
306 {
307         int vec;
308         u32 *reg;
309 
310         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312                 reg = bitmap + REG_POS(vec);
313                 if (*reg)
314                         return fls(*reg) - 1 + vec;
315         }
316 
317         return -1;
318 }
319 
320 static u8 count_vectors(void *bitmap)
321 {
322         int vec;
323         u32 *reg;
324         u8 count = 0;
325 
326         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327                 reg = bitmap + REG_POS(vec);
328                 count += hweight32(*reg);
329         }
330 
331         return count;
332 }
333 
334 void __kvm_apic_update_irr(u32 *pir, void *regs)
335 {
336         u32 i, pir_val;
337 
338         for (i = 0; i <= 7; i++) {
339                 pir_val = xchg(&pir[i], 0);
340                 if (pir_val)
341                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
342         }
343 }
344 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345 
346 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347 {
348         struct kvm_lapic *apic = vcpu->arch.apic;
349 
350         __kvm_apic_update_irr(pir, apic->regs);
351 
352         kvm_make_request(KVM_REQ_EVENT, vcpu);
353 }
354 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
355 
356 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
357 {
358         apic_set_vector(vec, apic->regs + APIC_IRR);
359         /*
360          * irr_pending must be true if any interrupt is pending; set it after
361          * APIC_IRR to avoid race with apic_clear_irr
362          */
363         apic->irr_pending = true;
364 }
365 
366 static inline int apic_search_irr(struct kvm_lapic *apic)
367 {
368         return find_highest_vector(apic->regs + APIC_IRR);
369 }
370 
371 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
372 {
373         int result;
374 
375         /*
376          * Note that irr_pending is just a hint. It will be always
377          * true with virtual interrupt delivery enabled.
378          */
379         if (!apic->irr_pending)
380                 return -1;
381 
382         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
383         result = apic_search_irr(apic);
384         ASSERT(result == -1 || result >= 16);
385 
386         return result;
387 }
388 
389 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
390 {
391         struct kvm_vcpu *vcpu;
392 
393         vcpu = apic->vcpu;
394 
395         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
396                 /* try to update RVI */
397                 apic_clear_vector(vec, apic->regs + APIC_IRR);
398                 kvm_make_request(KVM_REQ_EVENT, vcpu);
399         } else {
400                 apic->irr_pending = false;
401                 apic_clear_vector(vec, apic->regs + APIC_IRR);
402                 if (apic_search_irr(apic) != -1)
403                         apic->irr_pending = true;
404         }
405 }
406 
407 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
408 {
409         struct kvm_vcpu *vcpu;
410 
411         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
412                 return;
413 
414         vcpu = apic->vcpu;
415 
416         /*
417          * With APIC virtualization enabled, all caching is disabled
418          * because the processor can modify ISR under the hood.  Instead
419          * just set SVI.
420          */
421         if (unlikely(kvm_x86_ops->hwapic_isr_update))
422                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
423         else {
424                 ++apic->isr_count;
425                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
426                 /*
427                  * ISR (in service register) bit is set when injecting an interrupt.
428                  * The highest vector is injected. Thus the latest bit set matches
429                  * the highest bit in ISR.
430                  */
431                 apic->highest_isr_cache = vec;
432         }
433 }
434 
435 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
436 {
437         int result;
438 
439         /*
440          * Note that isr_count is always 1, and highest_isr_cache
441          * is always -1, with APIC virtualization enabled.
442          */
443         if (!apic->isr_count)
444                 return -1;
445         if (likely(apic->highest_isr_cache != -1))
446                 return apic->highest_isr_cache;
447 
448         result = find_highest_vector(apic->regs + APIC_ISR);
449         ASSERT(result == -1 || result >= 16);
450 
451         return result;
452 }
453 
454 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
455 {
456         struct kvm_vcpu *vcpu;
457         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
458                 return;
459 
460         vcpu = apic->vcpu;
461 
462         /*
463          * We do get here for APIC virtualization enabled if the guest
464          * uses the Hyper-V APIC enlightenment.  In this case we may need
465          * to trigger a new interrupt delivery by writing the SVI field;
466          * on the other hand isr_count and highest_isr_cache are unused
467          * and must be left alone.
468          */
469         if (unlikely(kvm_x86_ops->hwapic_isr_update))
470                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
471                                                apic_find_highest_isr(apic));
472         else {
473                 --apic->isr_count;
474                 BUG_ON(apic->isr_count < 0);
475                 apic->highest_isr_cache = -1;
476         }
477 }
478 
479 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
480 {
481         int highest_irr;
482 
483         /* This may race with setting of irr in __apic_accept_irq() and
484          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
485          * will cause vmexit immediately and the value will be recalculated
486          * on the next vmentry.
487          */
488         if (!kvm_vcpu_has_lapic(vcpu))
489                 return 0;
490         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
491 
492         return highest_irr;
493 }
494 
495 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
496                              int vector, int level, int trig_mode,
497                              unsigned long *dest_map);
498 
499 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
500                 unsigned long *dest_map)
501 {
502         struct kvm_lapic *apic = vcpu->arch.apic;
503 
504         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
505                         irq->level, irq->trig_mode, dest_map);
506 }
507 
508 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
509 {
510 
511         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
512                                       sizeof(val));
513 }
514 
515 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
516 {
517 
518         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
519                                       sizeof(*val));
520 }
521 
522 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
523 {
524         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
525 }
526 
527 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
528 {
529         u8 val;
530         if (pv_eoi_get_user(vcpu, &val) < 0)
531                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
532                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
533         return val & 0x1;
534 }
535 
536 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
537 {
538         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
539                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
540                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
541                 return;
542         }
543         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
544 }
545 
546 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
547 {
548         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
549                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
550                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
551                 return;
552         }
553         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
554 }
555 
556 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
557 {
558         struct kvm_lapic *apic = vcpu->arch.apic;
559         int i;
560 
561         for (i = 0; i < 8; i++)
562                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
563 }
564 
565 static void apic_update_ppr(struct kvm_lapic *apic)
566 {
567         u32 tpr, isrv, ppr, old_ppr;
568         int isr;
569 
570         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
571         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
572         isr = apic_find_highest_isr(apic);
573         isrv = (isr != -1) ? isr : 0;
574 
575         if ((tpr & 0xf0) >= (isrv & 0xf0))
576                 ppr = tpr & 0xff;
577         else
578                 ppr = isrv & 0xf0;
579 
580         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
581                    apic, ppr, isr, isrv);
582 
583         if (old_ppr != ppr) {
584                 apic_set_reg(apic, APIC_PROCPRI, ppr);
585                 if (ppr < old_ppr)
586                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
587         }
588 }
589 
590 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
591 {
592         apic_set_reg(apic, APIC_TASKPRI, tpr);
593         apic_update_ppr(apic);
594 }
595 
596 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
597 {
598         if (apic_x2apic_mode(apic))
599                 return mda == X2APIC_BROADCAST;
600 
601         return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
602 }
603 
604 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
605 {
606         if (kvm_apic_broadcast(apic, mda))
607                 return true;
608 
609         if (apic_x2apic_mode(apic))
610                 return mda == kvm_apic_id(apic);
611 
612         return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
613 }
614 
615 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
616 {
617         u32 logical_id;
618 
619         if (kvm_apic_broadcast(apic, mda))
620                 return true;
621 
622         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
623 
624         if (apic_x2apic_mode(apic))
625                 return ((logical_id >> 16) == (mda >> 16))
626                        && (logical_id & mda & 0xffff) != 0;
627 
628         logical_id = GET_APIC_LOGICAL_ID(logical_id);
629         mda = GET_APIC_DEST_FIELD(mda);
630 
631         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
632         case APIC_DFR_FLAT:
633                 return (logical_id & mda) != 0;
634         case APIC_DFR_CLUSTER:
635                 return ((logical_id >> 4) == (mda >> 4))
636                        && (logical_id & mda & 0xf) != 0;
637         default:
638                 apic_debug("Bad DFR vcpu %d: %08x\n",
639                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
640                 return false;
641         }
642 }
643 
644 /* KVM APIC implementation has two quirks
645  *  - dest always begins at 0 while xAPIC MDA has offset 24,
646  *  - IOxAPIC messages have to be delivered (directly) to x2APIC.
647  */
648 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
649                                               struct kvm_lapic *target)
650 {
651         bool ipi = source != NULL;
652         bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
653 
654         if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
655                 return X2APIC_BROADCAST;
656 
657         return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
658 }
659 
660 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
661                            int short_hand, unsigned int dest, int dest_mode)
662 {
663         struct kvm_lapic *target = vcpu->arch.apic;
664         u32 mda = kvm_apic_mda(dest, source, target);
665 
666         apic_debug("target %p, source %p, dest 0x%x, "
667                    "dest_mode 0x%x, short_hand 0x%x\n",
668                    target, source, dest, dest_mode, short_hand);
669 
670         ASSERT(target);
671         switch (short_hand) {
672         case APIC_DEST_NOSHORT:
673                 if (dest_mode == APIC_DEST_PHYSICAL)
674                         return kvm_apic_match_physical_addr(target, mda);
675                 else
676                         return kvm_apic_match_logical_addr(target, mda);
677         case APIC_DEST_SELF:
678                 return target == source;
679         case APIC_DEST_ALLINC:
680                 return true;
681         case APIC_DEST_ALLBUT:
682                 return target != source;
683         default:
684                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
685                            short_hand);
686                 return false;
687         }
688 }
689 
690 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
691                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
692 {
693         struct kvm_apic_map *map;
694         unsigned long bitmap = 1;
695         struct kvm_lapic **dst;
696         int i;
697         bool ret, x2apic_ipi;
698 
699         *r = -1;
700 
701         if (irq->shorthand == APIC_DEST_SELF) {
702                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
703                 return true;
704         }
705 
706         if (irq->shorthand)
707                 return false;
708 
709         x2apic_ipi = src && apic_x2apic_mode(src);
710         if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
711                 return false;
712 
713         ret = true;
714         rcu_read_lock();
715         map = rcu_dereference(kvm->arch.apic_map);
716 
717         if (!map) {
718                 ret = false;
719                 goto out;
720         }
721 
722         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
723                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
724                         goto out;
725 
726                 dst = &map->phys_map[irq->dest_id];
727         } else {
728                 u16 cid;
729 
730                 if (!kvm_apic_logical_map_valid(map)) {
731                         ret = false;
732                         goto out;
733                 }
734 
735                 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
736 
737                 if (cid >= ARRAY_SIZE(map->logical_map))
738                         goto out;
739 
740                 dst = map->logical_map[cid];
741 
742                 if (kvm_lowest_prio_delivery(irq)) {
743                         int l = -1;
744                         for_each_set_bit(i, &bitmap, 16) {
745                                 if (!dst[i])
746                                         continue;
747                                 if (l < 0)
748                                         l = i;
749                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
750                                         l = i;
751                         }
752 
753                         bitmap = (l >= 0) ? 1 << l : 0;
754                 }
755         }
756 
757         for_each_set_bit(i, &bitmap, 16) {
758                 if (!dst[i])
759                         continue;
760                 if (*r < 0)
761                         *r = 0;
762                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
763         }
764 out:
765         rcu_read_unlock();
766         return ret;
767 }
768 
769 /*
770  * Add a pending IRQ into lapic.
771  * Return 1 if successfully added and 0 if discarded.
772  */
773 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
774                              int vector, int level, int trig_mode,
775                              unsigned long *dest_map)
776 {
777         int result = 0;
778         struct kvm_vcpu *vcpu = apic->vcpu;
779 
780         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
781                                   trig_mode, vector);
782         switch (delivery_mode) {
783         case APIC_DM_LOWEST:
784                 vcpu->arch.apic_arb_prio++;
785         case APIC_DM_FIXED:
786                 /* FIXME add logic for vcpu on reset */
787                 if (unlikely(!apic_enabled(apic)))
788                         break;
789 
790                 result = 1;
791 
792                 if (dest_map)
793                         __set_bit(vcpu->vcpu_id, dest_map);
794 
795                 if (kvm_x86_ops->deliver_posted_interrupt)
796                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
797                 else {
798                         apic_set_irr(vector, apic);
799 
800                         kvm_make_request(KVM_REQ_EVENT, vcpu);
801                         kvm_vcpu_kick(vcpu);
802                 }
803                 break;
804 
805         case APIC_DM_REMRD:
806                 result = 1;
807                 vcpu->arch.pv.pv_unhalted = 1;
808                 kvm_make_request(KVM_REQ_EVENT, vcpu);
809                 kvm_vcpu_kick(vcpu);
810                 break;
811 
812         case APIC_DM_SMI:
813                 result = 1;
814                 kvm_make_request(KVM_REQ_SMI, vcpu);
815                 kvm_vcpu_kick(vcpu);
816                 break;
817 
818         case APIC_DM_NMI:
819                 result = 1;
820                 kvm_inject_nmi(vcpu);
821                 kvm_vcpu_kick(vcpu);
822                 break;
823 
824         case APIC_DM_INIT:
825                 if (!trig_mode || level) {
826                         result = 1;
827                         /* assumes that there are only KVM_APIC_INIT/SIPI */
828                         apic->pending_events = (1UL << KVM_APIC_INIT);
829                         /* make sure pending_events is visible before sending
830                          * the request */
831                         smp_wmb();
832                         kvm_make_request(KVM_REQ_EVENT, vcpu);
833                         kvm_vcpu_kick(vcpu);
834                 } else {
835                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
836                                    vcpu->vcpu_id);
837                 }
838                 break;
839 
840         case APIC_DM_STARTUP:
841                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
842                            vcpu->vcpu_id, vector);
843                 result = 1;
844                 apic->sipi_vector = vector;
845                 /* make sure sipi_vector is visible for the receiver */
846                 smp_wmb();
847                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
848                 kvm_make_request(KVM_REQ_EVENT, vcpu);
849                 kvm_vcpu_kick(vcpu);
850                 break;
851 
852         case APIC_DM_EXTINT:
853                 /*
854                  * Should only be called by kvm_apic_local_deliver() with LVT0,
855                  * before NMI watchdog was enabled. Already handled by
856                  * kvm_apic_accept_pic_intr().
857                  */
858                 break;
859 
860         default:
861                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
862                        delivery_mode);
863                 break;
864         }
865         return result;
866 }
867 
868 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
869 {
870         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
871 }
872 
873 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
874 {
875         if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
876                 int trigger_mode;
877                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
878                         trigger_mode = IOAPIC_LEVEL_TRIG;
879                 else
880                         trigger_mode = IOAPIC_EDGE_TRIG;
881                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
882         }
883 }
884 
885 static int apic_set_eoi(struct kvm_lapic *apic)
886 {
887         int vector = apic_find_highest_isr(apic);
888 
889         trace_kvm_eoi(apic, vector);
890 
891         /*
892          * Not every write EOI will has corresponding ISR,
893          * one example is when Kernel check timer on setup_IO_APIC
894          */
895         if (vector == -1)
896                 return vector;
897 
898         apic_clear_isr(vector, apic);
899         apic_update_ppr(apic);
900 
901         kvm_ioapic_send_eoi(apic, vector);
902         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
903         return vector;
904 }
905 
906 /*
907  * this interface assumes a trap-like exit, which has already finished
908  * desired side effect including vISR and vPPR update.
909  */
910 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
911 {
912         struct kvm_lapic *apic = vcpu->arch.apic;
913 
914         trace_kvm_eoi(apic, vector);
915 
916         kvm_ioapic_send_eoi(apic, vector);
917         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
918 }
919 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
920 
921 static void apic_send_ipi(struct kvm_lapic *apic)
922 {
923         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
924         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
925         struct kvm_lapic_irq irq;
926 
927         irq.vector = icr_low & APIC_VECTOR_MASK;
928         irq.delivery_mode = icr_low & APIC_MODE_MASK;
929         irq.dest_mode = icr_low & APIC_DEST_MASK;
930         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
931         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
932         irq.shorthand = icr_low & APIC_SHORT_MASK;
933         irq.msi_redir_hint = false;
934         if (apic_x2apic_mode(apic))
935                 irq.dest_id = icr_high;
936         else
937                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
938 
939         trace_kvm_apic_ipi(icr_low, irq.dest_id);
940 
941         apic_debug("icr_high 0x%x, icr_low 0x%x, "
942                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
943                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
944                    "msi_redir_hint 0x%x\n",
945                    icr_high, icr_low, irq.shorthand, irq.dest_id,
946                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
947                    irq.vector, irq.msi_redir_hint);
948 
949         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
950 }
951 
952 static u32 apic_get_tmcct(struct kvm_lapic *apic)
953 {
954         ktime_t remaining;
955         s64 ns;
956         u32 tmcct;
957 
958         ASSERT(apic != NULL);
959 
960         /* if initial count is 0, current count should also be 0 */
961         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
962                 apic->lapic_timer.period == 0)
963                 return 0;
964 
965         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
966         if (ktime_to_ns(remaining) < 0)
967                 remaining = ktime_set(0, 0);
968 
969         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
970         tmcct = div64_u64(ns,
971                          (APIC_BUS_CYCLE_NS * apic->divide_count));
972 
973         return tmcct;
974 }
975 
976 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
977 {
978         struct kvm_vcpu *vcpu = apic->vcpu;
979         struct kvm_run *run = vcpu->run;
980 
981         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
982         run->tpr_access.rip = kvm_rip_read(vcpu);
983         run->tpr_access.is_write = write;
984 }
985 
986 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
987 {
988         if (apic->vcpu->arch.tpr_access_reporting)
989                 __report_tpr_access(apic, write);
990 }
991 
992 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
993 {
994         u32 val = 0;
995 
996         if (offset >= LAPIC_MMIO_LENGTH)
997                 return 0;
998 
999         switch (offset) {
1000         case APIC_ID:
1001                 if (apic_x2apic_mode(apic))
1002                         val = kvm_apic_id(apic);
1003                 else
1004                         val = kvm_apic_id(apic) << 24;
1005                 break;
1006         case APIC_ARBPRI:
1007                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1008                 break;
1009 
1010         case APIC_TMCCT:        /* Timer CCR */
1011                 if (apic_lvtt_tscdeadline(apic))
1012                         return 0;
1013 
1014                 val = apic_get_tmcct(apic);
1015                 break;
1016         case APIC_PROCPRI:
1017                 apic_update_ppr(apic);
1018                 val = kvm_apic_get_reg(apic, offset);
1019                 break;
1020         case APIC_TASKPRI:
1021                 report_tpr_access(apic, false);
1022                 /* fall thru */
1023         default:
1024                 val = kvm_apic_get_reg(apic, offset);
1025                 break;
1026         }
1027 
1028         return val;
1029 }
1030 
1031 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1032 {
1033         return container_of(dev, struct kvm_lapic, dev);
1034 }
1035 
1036 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1037                 void *data)
1038 {
1039         unsigned char alignment = offset & 0xf;
1040         u32 result;
1041         /* this bitmask has a bit cleared for each reserved register */
1042         static const u64 rmask = 0x43ff01ffffffe70cULL;
1043 
1044         if ((alignment + len) > 4) {
1045                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1046                            offset, len);
1047                 return 1;
1048         }
1049 
1050         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1051                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1052                            offset);
1053                 return 1;
1054         }
1055 
1056         result = __apic_read(apic, offset & ~0xf);
1057 
1058         trace_kvm_apic_read(offset, result);
1059 
1060         switch (len) {
1061         case 1:
1062         case 2:
1063         case 4:
1064                 memcpy(data, (char *)&result + alignment, len);
1065                 break;
1066         default:
1067                 printk(KERN_ERR "Local APIC read with len = %x, "
1068                        "should be 1,2, or 4 instead\n", len);
1069                 break;
1070         }
1071         return 0;
1072 }
1073 
1074 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1075 {
1076         return kvm_apic_hw_enabled(apic) &&
1077             addr >= apic->base_address &&
1078             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1079 }
1080 
1081 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1082                            gpa_t address, int len, void *data)
1083 {
1084         struct kvm_lapic *apic = to_lapic(this);
1085         u32 offset = address - apic->base_address;
1086 
1087         if (!apic_mmio_in_range(apic, address))
1088                 return -EOPNOTSUPP;
1089 
1090         apic_reg_read(apic, offset, len, data);
1091 
1092         return 0;
1093 }
1094 
1095 static void update_divide_count(struct kvm_lapic *apic)
1096 {
1097         u32 tmp1, tmp2, tdcr;
1098 
1099         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1100         tmp1 = tdcr & 0xf;
1101         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1102         apic->divide_count = 0x1 << (tmp2 & 0x7);
1103 
1104         apic_debug("timer divide count is 0x%x\n",
1105                                    apic->divide_count);
1106 }
1107 
1108 static void apic_update_lvtt(struct kvm_lapic *apic)
1109 {
1110         u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1111                         apic->lapic_timer.timer_mode_mask;
1112 
1113         if (apic->lapic_timer.timer_mode != timer_mode) {
1114                 apic->lapic_timer.timer_mode = timer_mode;
1115                 hrtimer_cancel(&apic->lapic_timer.timer);
1116         }
1117 }
1118 
1119 static void apic_timer_expired(struct kvm_lapic *apic)
1120 {
1121         struct kvm_vcpu *vcpu = apic->vcpu;
1122         wait_queue_head_t *q = &vcpu->wq;
1123         struct kvm_timer *ktimer = &apic->lapic_timer;
1124 
1125         if (atomic_read(&apic->lapic_timer.pending))
1126                 return;
1127 
1128         atomic_inc(&apic->lapic_timer.pending);
1129         kvm_set_pending_timer(vcpu);
1130 
1131         if (waitqueue_active(q))
1132                 wake_up_interruptible(q);
1133 
1134         if (apic_lvtt_tscdeadline(apic))
1135                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1136 }
1137 
1138 /*
1139  * On APICv, this test will cause a busy wait
1140  * during a higher-priority task.
1141  */
1142 
1143 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1144 {
1145         struct kvm_lapic *apic = vcpu->arch.apic;
1146         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1147 
1148         if (kvm_apic_hw_enabled(apic)) {
1149                 int vec = reg & APIC_VECTOR_MASK;
1150                 void *bitmap = apic->regs + APIC_ISR;
1151 
1152                 if (kvm_x86_ops->deliver_posted_interrupt)
1153                         bitmap = apic->regs + APIC_IRR;
1154 
1155                 if (apic_test_vector(vec, bitmap))
1156                         return true;
1157         }
1158         return false;
1159 }
1160 
1161 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1162 {
1163         struct kvm_lapic *apic = vcpu->arch.apic;
1164         u64 guest_tsc, tsc_deadline;
1165 
1166         if (!kvm_vcpu_has_lapic(vcpu))
1167                 return;
1168 
1169         if (apic->lapic_timer.expired_tscdeadline == 0)
1170                 return;
1171 
1172         if (!lapic_timer_int_injected(vcpu))
1173                 return;
1174 
1175         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1176         apic->lapic_timer.expired_tscdeadline = 0;
1177         guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
1178         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1179 
1180         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1181         if (guest_tsc < tsc_deadline)
1182                 __delay(tsc_deadline - guest_tsc);
1183 }
1184 
1185 static void start_apic_timer(struct kvm_lapic *apic)
1186 {
1187         ktime_t now;
1188 
1189         atomic_set(&apic->lapic_timer.pending, 0);
1190 
1191         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1192                 /* lapic timer in oneshot or periodic mode */
1193                 now = apic->lapic_timer.timer.base->get_time();
1194                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1195                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1196 
1197                 if (!apic->lapic_timer.period)
1198                         return;
1199                 /*
1200                  * Do not allow the guest to program periodic timers with small
1201                  * interval, since the hrtimers are not throttled by the host
1202                  * scheduler.
1203                  */
1204                 if (apic_lvtt_period(apic)) {
1205                         s64 min_period = min_timer_period_us * 1000LL;
1206 
1207                         if (apic->lapic_timer.period < min_period) {
1208                                 pr_info_ratelimited(
1209                                     "kvm: vcpu %i: requested %lld ns "
1210                                     "lapic timer period limited to %lld ns\n",
1211                                     apic->vcpu->vcpu_id,
1212                                     apic->lapic_timer.period, min_period);
1213                                 apic->lapic_timer.period = min_period;
1214                         }
1215                 }
1216 
1217                 hrtimer_start(&apic->lapic_timer.timer,
1218                               ktime_add_ns(now, apic->lapic_timer.period),
1219                               HRTIMER_MODE_ABS);
1220 
1221                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1222                            PRIx64 ", "
1223                            "timer initial count 0x%x, period %lldns, "
1224                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1225                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1226                            kvm_apic_get_reg(apic, APIC_TMICT),
1227                            apic->lapic_timer.period,
1228                            ktime_to_ns(ktime_add_ns(now,
1229                                         apic->lapic_timer.period)));
1230         } else if (apic_lvtt_tscdeadline(apic)) {
1231                 /* lapic timer in tsc deadline mode */
1232                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1233                 u64 ns = 0;
1234                 ktime_t expire;
1235                 struct kvm_vcpu *vcpu = apic->vcpu;
1236                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1237                 unsigned long flags;
1238 
1239                 if (unlikely(!tscdeadline || !this_tsc_khz))
1240                         return;
1241 
1242                 local_irq_save(flags);
1243 
1244                 now = apic->lapic_timer.timer.base->get_time();
1245                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
1246                 if (likely(tscdeadline > guest_tsc)) {
1247                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1248                         do_div(ns, this_tsc_khz);
1249                         expire = ktime_add_ns(now, ns);
1250                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1251                         hrtimer_start(&apic->lapic_timer.timer,
1252                                       expire, HRTIMER_MODE_ABS);
1253                 } else
1254                         apic_timer_expired(apic);
1255 
1256                 local_irq_restore(flags);
1257         }
1258 }
1259 
1260 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1261 {
1262         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1263 
1264         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1265                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1266                 if (lvt0_in_nmi_mode) {
1267                         apic_debug("Receive NMI setting on APIC_LVT0 "
1268                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1269                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1270                 } else
1271                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1272         }
1273 }
1274 
1275 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1276 {
1277         int ret = 0;
1278 
1279         trace_kvm_apic_write(reg, val);
1280 
1281         switch (reg) {
1282         case APIC_ID:           /* Local APIC ID */
1283                 if (!apic_x2apic_mode(apic))
1284                         kvm_apic_set_id(apic, val >> 24);
1285                 else
1286                         ret = 1;
1287                 break;
1288 
1289         case APIC_TASKPRI:
1290                 report_tpr_access(apic, true);
1291                 apic_set_tpr(apic, val & 0xff);
1292                 break;
1293 
1294         case APIC_EOI:
1295                 apic_set_eoi(apic);
1296                 break;
1297 
1298         case APIC_LDR:
1299                 if (!apic_x2apic_mode(apic))
1300                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1301                 else
1302                         ret = 1;
1303                 break;
1304 
1305         case APIC_DFR:
1306                 if (!apic_x2apic_mode(apic)) {
1307                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1308                         recalculate_apic_map(apic->vcpu->kvm);
1309                 } else
1310                         ret = 1;
1311                 break;
1312 
1313         case APIC_SPIV: {
1314                 u32 mask = 0x3ff;
1315                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1316                         mask |= APIC_SPIV_DIRECTED_EOI;
1317                 apic_set_spiv(apic, val & mask);
1318                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1319                         int i;
1320                         u32 lvt_val;
1321 
1322                         for (i = 0; i < APIC_LVT_NUM; i++) {
1323                                 lvt_val = kvm_apic_get_reg(apic,
1324                                                        APIC_LVTT + 0x10 * i);
1325                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1326                                              lvt_val | APIC_LVT_MASKED);
1327                         }
1328                         apic_update_lvtt(apic);
1329                         atomic_set(&apic->lapic_timer.pending, 0);
1330 
1331                 }
1332                 break;
1333         }
1334         case APIC_ICR:
1335                 /* No delay here, so we always clear the pending bit */
1336                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1337                 apic_send_ipi(apic);
1338                 break;
1339 
1340         case APIC_ICR2:
1341                 if (!apic_x2apic_mode(apic))
1342                         val &= 0xff000000;
1343                 apic_set_reg(apic, APIC_ICR2, val);
1344                 break;
1345 
1346         case APIC_LVT0:
1347                 apic_manage_nmi_watchdog(apic, val);
1348         case APIC_LVTTHMR:
1349         case APIC_LVTPC:
1350         case APIC_LVT1:
1351         case APIC_LVTERR:
1352                 /* TODO: Check vector */
1353                 if (!kvm_apic_sw_enabled(apic))
1354                         val |= APIC_LVT_MASKED;
1355 
1356                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1357                 apic_set_reg(apic, reg, val);
1358 
1359                 break;
1360 
1361         case APIC_LVTT:
1362                 if (!kvm_apic_sw_enabled(apic))
1363                         val |= APIC_LVT_MASKED;
1364                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1365                 apic_set_reg(apic, APIC_LVTT, val);
1366                 apic_update_lvtt(apic);
1367                 break;
1368 
1369         case APIC_TMICT:
1370                 if (apic_lvtt_tscdeadline(apic))
1371                         break;
1372 
1373                 hrtimer_cancel(&apic->lapic_timer.timer);
1374                 apic_set_reg(apic, APIC_TMICT, val);
1375                 start_apic_timer(apic);
1376                 break;
1377 
1378         case APIC_TDCR:
1379                 if (val & 4)
1380                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1381                 apic_set_reg(apic, APIC_TDCR, val);
1382                 update_divide_count(apic);
1383                 break;
1384 
1385         case APIC_ESR:
1386                 if (apic_x2apic_mode(apic) && val != 0) {
1387                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1388                         ret = 1;
1389                 }
1390                 break;
1391 
1392         case APIC_SELF_IPI:
1393                 if (apic_x2apic_mode(apic)) {
1394                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1395                 } else
1396                         ret = 1;
1397                 break;
1398         default:
1399                 ret = 1;
1400                 break;
1401         }
1402         if (ret)
1403                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1404         return ret;
1405 }
1406 
1407 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1408                             gpa_t address, int len, const void *data)
1409 {
1410         struct kvm_lapic *apic = to_lapic(this);
1411         unsigned int offset = address - apic->base_address;
1412         u32 val;
1413 
1414         if (!apic_mmio_in_range(apic, address))
1415                 return -EOPNOTSUPP;
1416 
1417         /*
1418          * APIC register must be aligned on 128-bits boundary.
1419          * 32/64/128 bits registers must be accessed thru 32 bits.
1420          * Refer SDM 8.4.1
1421          */
1422         if (len != 4 || (offset & 0xf)) {
1423                 /* Don't shout loud, $infamous_os would cause only noise. */
1424                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1425                 return 0;
1426         }
1427 
1428         val = *(u32*)data;
1429 
1430         /* too common printing */
1431         if (offset != APIC_EOI)
1432                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1433                            "0x%x\n", __func__, offset, len, val);
1434 
1435         apic_reg_write(apic, offset & 0xff0, val);
1436 
1437         return 0;
1438 }
1439 
1440 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1441 {
1442         if (kvm_vcpu_has_lapic(vcpu))
1443                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1444 }
1445 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1446 
1447 /* emulate APIC access in a trap manner */
1448 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1449 {
1450         u32 val = 0;
1451 
1452         /* hw has done the conditional check and inst decode */
1453         offset &= 0xff0;
1454 
1455         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1456 
1457         /* TODO: optimize to just emulate side effect w/o one more write */
1458         apic_reg_write(vcpu->arch.apic, offset, val);
1459 }
1460 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1461 
1462 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1463 {
1464         struct kvm_lapic *apic = vcpu->arch.apic;
1465 
1466         if (!vcpu->arch.apic)
1467                 return;
1468 
1469         hrtimer_cancel(&apic->lapic_timer.timer);
1470 
1471         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1472                 static_key_slow_dec_deferred(&apic_hw_disabled);
1473 
1474         if (!apic->sw_enabled)
1475                 static_key_slow_dec_deferred(&apic_sw_disabled);
1476 
1477         if (apic->regs)
1478                 free_page((unsigned long)apic->regs);
1479 
1480         kfree(apic);
1481 }
1482 
1483 /*
1484  *----------------------------------------------------------------------
1485  * LAPIC interface
1486  *----------------------------------------------------------------------
1487  */
1488 
1489 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1490 {
1491         struct kvm_lapic *apic = vcpu->arch.apic;
1492 
1493         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1494                         apic_lvtt_period(apic))
1495                 return 0;
1496 
1497         return apic->lapic_timer.tscdeadline;
1498 }
1499 
1500 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1501 {
1502         struct kvm_lapic *apic = vcpu->arch.apic;
1503 
1504         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1505                         apic_lvtt_period(apic))
1506                 return;
1507 
1508         hrtimer_cancel(&apic->lapic_timer.timer);
1509         apic->lapic_timer.tscdeadline = data;
1510         start_apic_timer(apic);
1511 }
1512 
1513 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1514 {
1515         struct kvm_lapic *apic = vcpu->arch.apic;
1516 
1517         if (!kvm_vcpu_has_lapic(vcpu))
1518                 return;
1519 
1520         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1521                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1522 }
1523 
1524 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1525 {
1526         u64 tpr;
1527 
1528         if (!kvm_vcpu_has_lapic(vcpu))
1529                 return 0;
1530 
1531         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1532 
1533         return (tpr & 0xf0) >> 4;
1534 }
1535 
1536 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1537 {
1538         u64 old_value = vcpu->arch.apic_base;
1539         struct kvm_lapic *apic = vcpu->arch.apic;
1540 
1541         if (!apic) {
1542                 value |= MSR_IA32_APICBASE_BSP;
1543                 vcpu->arch.apic_base = value;
1544                 return;
1545         }
1546 
1547         vcpu->arch.apic_base = value;
1548 
1549         /* update jump label if enable bit changes */
1550         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1551                 if (value & MSR_IA32_APICBASE_ENABLE)
1552                         static_key_slow_dec_deferred(&apic_hw_disabled);
1553                 else
1554                         static_key_slow_inc(&apic_hw_disabled.key);
1555                 recalculate_apic_map(vcpu->kvm);
1556         }
1557 
1558         if ((old_value ^ value) & X2APIC_ENABLE) {
1559                 if (value & X2APIC_ENABLE) {
1560                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1561                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1562                 } else
1563                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1564         }
1565 
1566         apic->base_address = apic->vcpu->arch.apic_base &
1567                              MSR_IA32_APICBASE_BASE;
1568 
1569         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1570              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1571                 pr_warn_once("APIC base relocation is unsupported by KVM");
1572 
1573         /* with FSB delivery interrupt, we can restart APIC functionality */
1574         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1575                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1576 
1577 }
1578 
1579 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1580 {
1581         struct kvm_lapic *apic;
1582         int i;
1583 
1584         apic_debug("%s\n", __func__);
1585 
1586         ASSERT(vcpu);
1587         apic = vcpu->arch.apic;
1588         ASSERT(apic != NULL);
1589 
1590         /* Stop the timer in case it's a reset to an active apic */
1591         hrtimer_cancel(&apic->lapic_timer.timer);
1592 
1593         if (!init_event)
1594                 kvm_apic_set_id(apic, vcpu->vcpu_id);
1595         kvm_apic_set_version(apic->vcpu);
1596 
1597         for (i = 0; i < APIC_LVT_NUM; i++)
1598                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1599         apic_update_lvtt(apic);
1600         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1601                 apic_set_reg(apic, APIC_LVT0,
1602                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1603         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1604 
1605         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1606         apic_set_spiv(apic, 0xff);
1607         apic_set_reg(apic, APIC_TASKPRI, 0);
1608         if (!apic_x2apic_mode(apic))
1609                 kvm_apic_set_ldr(apic, 0);
1610         apic_set_reg(apic, APIC_ESR, 0);
1611         apic_set_reg(apic, APIC_ICR, 0);
1612         apic_set_reg(apic, APIC_ICR2, 0);
1613         apic_set_reg(apic, APIC_TDCR, 0);
1614         apic_set_reg(apic, APIC_TMICT, 0);
1615         for (i = 0; i < 8; i++) {
1616                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1617                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1618                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1619         }
1620         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1621         apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1622         apic->highest_isr_cache = -1;
1623         update_divide_count(apic);
1624         atomic_set(&apic->lapic_timer.pending, 0);
1625         if (kvm_vcpu_is_bsp(vcpu))
1626                 kvm_lapic_set_base(vcpu,
1627                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1628         vcpu->arch.pv_eoi.msr_val = 0;
1629         apic_update_ppr(apic);
1630 
1631         vcpu->arch.apic_arb_prio = 0;
1632         vcpu->arch.apic_attention = 0;
1633 
1634         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1635                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1636                    vcpu, kvm_apic_id(apic),
1637                    vcpu->arch.apic_base, apic->base_address);
1638 }
1639 
1640 /*
1641  *----------------------------------------------------------------------
1642  * timer interface
1643  *----------------------------------------------------------------------
1644  */
1645 
1646 static bool lapic_is_periodic(struct kvm_lapic *apic)
1647 {
1648         return apic_lvtt_period(apic);
1649 }
1650 
1651 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1652 {
1653         struct kvm_lapic *apic = vcpu->arch.apic;
1654 
1655         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1656                         apic_lvt_enabled(apic, APIC_LVTT))
1657                 return atomic_read(&apic->lapic_timer.pending);
1658 
1659         return 0;
1660 }
1661 
1662 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1663 {
1664         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1665         int vector, mode, trig_mode;
1666 
1667         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1668                 vector = reg & APIC_VECTOR_MASK;
1669                 mode = reg & APIC_MODE_MASK;
1670                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1671                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1672                                         NULL);
1673         }
1674         return 0;
1675 }
1676 
1677 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1678 {
1679         struct kvm_lapic *apic = vcpu->arch.apic;
1680 
1681         if (apic)
1682                 kvm_apic_local_deliver(apic, APIC_LVT0);
1683 }
1684 
1685 static const struct kvm_io_device_ops apic_mmio_ops = {
1686         .read     = apic_mmio_read,
1687         .write    = apic_mmio_write,
1688 };
1689 
1690 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1691 {
1692         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1693         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1694 
1695         apic_timer_expired(apic);
1696 
1697         if (lapic_is_periodic(apic)) {
1698                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1699                 return HRTIMER_RESTART;
1700         } else
1701                 return HRTIMER_NORESTART;
1702 }
1703 
1704 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1705 {
1706         struct kvm_lapic *apic;
1707 
1708         ASSERT(vcpu != NULL);
1709         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1710 
1711         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1712         if (!apic)
1713                 goto nomem;
1714 
1715         vcpu->arch.apic = apic;
1716 
1717         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1718         if (!apic->regs) {
1719                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1720                        vcpu->vcpu_id);
1721                 goto nomem_free_apic;
1722         }
1723         apic->vcpu = vcpu;
1724 
1725         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1726                      HRTIMER_MODE_ABS);
1727         apic->lapic_timer.timer.function = apic_timer_fn;
1728 
1729         /*
1730          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1731          * thinking that APIC satet has changed.
1732          */
1733         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1734         kvm_lapic_set_base(vcpu,
1735                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1736 
1737         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1738         kvm_lapic_reset(vcpu, false);
1739         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1740 
1741         return 0;
1742 nomem_free_apic:
1743         kfree(apic);
1744 nomem:
1745         return -ENOMEM;
1746 }
1747 
1748 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1749 {
1750         struct kvm_lapic *apic = vcpu->arch.apic;
1751         int highest_irr;
1752 
1753         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1754                 return -1;
1755 
1756         apic_update_ppr(apic);
1757         highest_irr = apic_find_highest_irr(apic);
1758         if ((highest_irr == -1) ||
1759             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1760                 return -1;
1761         return highest_irr;
1762 }
1763 
1764 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1765 {
1766         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1767         int r = 0;
1768 
1769         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1770                 r = 1;
1771         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1772             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1773                 r = 1;
1774         return r;
1775 }
1776 
1777 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1778 {
1779         struct kvm_lapic *apic = vcpu->arch.apic;
1780 
1781         if (!kvm_vcpu_has_lapic(vcpu))
1782                 return;
1783 
1784         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1785                 kvm_apic_local_deliver(apic, APIC_LVTT);
1786                 if (apic_lvtt_tscdeadline(apic))
1787                         apic->lapic_timer.tscdeadline = 0;
1788                 atomic_set(&apic->lapic_timer.pending, 0);
1789         }
1790 }
1791 
1792 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1793 {
1794         int vector = kvm_apic_has_interrupt(vcpu);
1795         struct kvm_lapic *apic = vcpu->arch.apic;
1796 
1797         if (vector == -1)
1798                 return -1;
1799 
1800         /*
1801          * We get here even with APIC virtualization enabled, if doing
1802          * nested virtualization and L1 runs with the "acknowledge interrupt
1803          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1804          * because the process would deliver it through the IDT.
1805          */
1806 
1807         apic_set_isr(vector, apic);
1808         apic_update_ppr(apic);
1809         apic_clear_irr(vector, apic);
1810         return vector;
1811 }
1812 
1813 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1814                 struct kvm_lapic_state *s)
1815 {
1816         struct kvm_lapic *apic = vcpu->arch.apic;
1817 
1818         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1819         /* set SPIV separately to get count of SW disabled APICs right */
1820         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1821         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1822         /* call kvm_apic_set_id() to put apic into apic_map */
1823         kvm_apic_set_id(apic, kvm_apic_id(apic));
1824         kvm_apic_set_version(vcpu);
1825 
1826         apic_update_ppr(apic);
1827         hrtimer_cancel(&apic->lapic_timer.timer);
1828         apic_update_lvtt(apic);
1829         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1830         update_divide_count(apic);
1831         start_apic_timer(apic);
1832         apic->irr_pending = true;
1833         apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1834                                 1 : count_vectors(apic->regs + APIC_ISR);
1835         apic->highest_isr_cache = -1;
1836         if (kvm_x86_ops->hwapic_irr_update)
1837                 kvm_x86_ops->hwapic_irr_update(vcpu,
1838                                 apic_find_highest_irr(apic));
1839         if (unlikely(kvm_x86_ops->hwapic_isr_update))
1840                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1841                                 apic_find_highest_isr(apic));
1842         kvm_make_request(KVM_REQ_EVENT, vcpu);
1843         kvm_rtc_eoi_tracking_restore_one(vcpu);
1844 }
1845 
1846 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1847 {
1848         struct hrtimer *timer;
1849 
1850         if (!kvm_vcpu_has_lapic(vcpu))
1851                 return;
1852 
1853         timer = &vcpu->arch.apic->lapic_timer.timer;
1854         if (hrtimer_cancel(timer))
1855                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1856 }
1857 
1858 /*
1859  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1860  *
1861  * Detect whether guest triggered PV EOI since the
1862  * last entry. If yes, set EOI on guests's behalf.
1863  * Clear PV EOI in guest memory in any case.
1864  */
1865 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1866                                         struct kvm_lapic *apic)
1867 {
1868         bool pending;
1869         int vector;
1870         /*
1871          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1872          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1873          *
1874          * KVM_APIC_PV_EOI_PENDING is unset:
1875          *      -> host disabled PV EOI.
1876          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1877          *      -> host enabled PV EOI, guest did not execute EOI yet.
1878          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1879          *      -> host enabled PV EOI, guest executed EOI.
1880          */
1881         BUG_ON(!pv_eoi_enabled(vcpu));
1882         pending = pv_eoi_get_pending(vcpu);
1883         /*
1884          * Clear pending bit in any case: it will be set again on vmentry.
1885          * While this might not be ideal from performance point of view,
1886          * this makes sure pv eoi is only enabled when we know it's safe.
1887          */
1888         pv_eoi_clr_pending(vcpu);
1889         if (pending)
1890                 return;
1891         vector = apic_set_eoi(apic);
1892         trace_kvm_pv_eoi(apic, vector);
1893 }
1894 
1895 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1896 {
1897         u32 data;
1898 
1899         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1900                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1901 
1902         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1903                 return;
1904 
1905         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1906                                   sizeof(u32)))
1907                 return;
1908 
1909         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1910 }
1911 
1912 /*
1913  * apic_sync_pv_eoi_to_guest - called before vmentry
1914  *
1915  * Detect whether it's safe to enable PV EOI and
1916  * if yes do so.
1917  */
1918 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1919                                         struct kvm_lapic *apic)
1920 {
1921         if (!pv_eoi_enabled(vcpu) ||
1922             /* IRR set or many bits in ISR: could be nested. */
1923             apic->irr_pending ||
1924             /* Cache not set: could be safe but we don't bother. */
1925             apic->highest_isr_cache == -1 ||
1926             /* Need EOI to update ioapic. */
1927             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1928                 /*
1929                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1930                  * so we need not do anything here.
1931                  */
1932                 return;
1933         }
1934 
1935         pv_eoi_set_pending(apic->vcpu);
1936 }
1937 
1938 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1939 {
1940         u32 data, tpr;
1941         int max_irr, max_isr;
1942         struct kvm_lapic *apic = vcpu->arch.apic;
1943 
1944         apic_sync_pv_eoi_to_guest(vcpu, apic);
1945 
1946         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1947                 return;
1948 
1949         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1950         max_irr = apic_find_highest_irr(apic);
1951         if (max_irr < 0)
1952                 max_irr = 0;
1953         max_isr = apic_find_highest_isr(apic);
1954         if (max_isr < 0)
1955                 max_isr = 0;
1956         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1957 
1958         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1959                                 sizeof(u32));
1960 }
1961 
1962 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1963 {
1964         if (vapic_addr) {
1965                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1966                                         &vcpu->arch.apic->vapic_cache,
1967                                         vapic_addr, sizeof(u32)))
1968                         return -EINVAL;
1969                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1970         } else {
1971                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1972         }
1973 
1974         vcpu->arch.apic->vapic_addr = vapic_addr;
1975         return 0;
1976 }
1977 
1978 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1979 {
1980         struct kvm_lapic *apic = vcpu->arch.apic;
1981         u32 reg = (msr - APIC_BASE_MSR) << 4;
1982 
1983         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1984                 return 1;
1985 
1986         if (reg == APIC_ICR2)
1987                 return 1;
1988 
1989         /* if this is ICR write vector before command */
1990         if (reg == APIC_ICR)
1991                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1992         return apic_reg_write(apic, reg, (u32)data);
1993 }
1994 
1995 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1996 {
1997         struct kvm_lapic *apic = vcpu->arch.apic;
1998         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1999 
2000         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
2001                 return 1;
2002 
2003         if (reg == APIC_DFR || reg == APIC_ICR2) {
2004                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2005                            reg);
2006                 return 1;
2007         }
2008 
2009         if (apic_reg_read(apic, reg, 4, &low))
2010                 return 1;
2011         if (reg == APIC_ICR)
2012                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2013 
2014         *data = (((u64)high) << 32) | low;
2015 
2016         return 0;
2017 }
2018 
2019 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2020 {
2021         struct kvm_lapic *apic = vcpu->arch.apic;
2022 
2023         if (!kvm_vcpu_has_lapic(vcpu))
2024                 return 1;
2025 
2026         /* if this is ICR write vector before command */
2027         if (reg == APIC_ICR)
2028                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2029         return apic_reg_write(apic, reg, (u32)data);
2030 }
2031 
2032 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2033 {
2034         struct kvm_lapic *apic = vcpu->arch.apic;
2035         u32 low, high = 0;
2036 
2037         if (!kvm_vcpu_has_lapic(vcpu))
2038                 return 1;
2039 
2040         if (apic_reg_read(apic, reg, 4, &low))
2041                 return 1;
2042         if (reg == APIC_ICR)
2043                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2044 
2045         *data = (((u64)high) << 32) | low;
2046 
2047         return 0;
2048 }
2049 
2050 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2051 {
2052         u64 addr = data & ~KVM_MSR_ENABLED;
2053         if (!IS_ALIGNED(addr, 4))
2054                 return 1;
2055 
2056         vcpu->arch.pv_eoi.msr_val = data;
2057         if (!pv_eoi_enabled(vcpu))
2058                 return 0;
2059         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2060                                          addr, sizeof(u8));
2061 }
2062 
2063 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2064 {
2065         struct kvm_lapic *apic = vcpu->arch.apic;
2066         u8 sipi_vector;
2067         unsigned long pe;
2068 
2069         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2070                 return;
2071 
2072         /*
2073          * INITs are latched while in SMM.  Because an SMM CPU cannot
2074          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2075          * and delay processing of INIT until the next RSM.
2076          */
2077         if (is_smm(vcpu)) {
2078                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2079                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2080                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2081                 return;
2082         }
2083 
2084         pe = xchg(&apic->pending_events, 0);
2085         if (test_bit(KVM_APIC_INIT, &pe)) {
2086                 kvm_lapic_reset(vcpu, true);
2087                 kvm_vcpu_reset(vcpu, true);
2088                 if (kvm_vcpu_is_bsp(apic->vcpu))
2089                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2090                 else
2091                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2092         }
2093         if (test_bit(KVM_APIC_SIPI, &pe) &&
2094             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2095                 /* evaluate pending_events before reading the vector */
2096                 smp_rmb();
2097                 sipi_vector = apic->sipi_vector;
2098                 apic_debug("vcpu %d received sipi with vector # %x\n",
2099                          vcpu->vcpu_id, sipi_vector);
2100                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2101                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2102         }
2103 }
2104 
2105 void kvm_lapic_init(void)
2106 {
2107         /* do not patch jump label more than once per second */
2108         jump_label_rate_limit(&apic_hw_disabled, HZ);
2109         jump_label_rate_limit(&apic_sw_disabled, HZ);
2110 }
2111 

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