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Linux/arch/x86/kvm/mmu.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * MMU support
  8  *
  9  * Copyright (C) 2006 Qumranet, Inc.
 10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 11  *
 12  * Authors:
 13  *   Yaniv Kamay  <yaniv@qumranet.com>
 14  *   Avi Kivity   <avi@qumranet.com>
 15  *
 16  * This work is licensed under the terms of the GNU GPL, version 2.  See
 17  * the COPYING file in the top-level directory.
 18  *
 19  */
 20 
 21 #include "irq.h"
 22 #include "mmu.h"
 23 #include "x86.h"
 24 #include "kvm_cache_regs.h"
 25 
 26 #include <linux/kvm_host.h>
 27 #include <linux/types.h>
 28 #include <linux/string.h>
 29 #include <linux/mm.h>
 30 #include <linux/highmem.h>
 31 #include <linux/module.h>
 32 #include <linux/swap.h>
 33 #include <linux/hugetlb.h>
 34 #include <linux/compiler.h>
 35 #include <linux/srcu.h>
 36 #include <linux/slab.h>
 37 #include <linux/uaccess.h>
 38 
 39 #include <asm/page.h>
 40 #include <asm/cmpxchg.h>
 41 #include <asm/io.h>
 42 #include <asm/vmx.h>
 43 
 44 /*
 45  * When setting this variable to true it enables Two-Dimensional-Paging
 46  * where the hardware walks 2 page tables:
 47  * 1. the guest-virtual to guest-physical
 48  * 2. while doing 1. it walks guest-physical to host-physical
 49  * If the hardware supports that we don't need to do shadow paging.
 50  */
 51 bool tdp_enabled = false;
 52 
 53 enum {
 54         AUDIT_PRE_PAGE_FAULT,
 55         AUDIT_POST_PAGE_FAULT,
 56         AUDIT_PRE_PTE_WRITE,
 57         AUDIT_POST_PTE_WRITE,
 58         AUDIT_PRE_SYNC,
 59         AUDIT_POST_SYNC
 60 };
 61 
 62 #undef MMU_DEBUG
 63 
 64 #ifdef MMU_DEBUG
 65 
 66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
 67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
 68 
 69 #else
 70 
 71 #define pgprintk(x...) do { } while (0)
 72 #define rmap_printk(x...) do { } while (0)
 73 
 74 #endif
 75 
 76 #ifdef MMU_DEBUG
 77 static bool dbg = 0;
 78 module_param(dbg, bool, 0644);
 79 #endif
 80 
 81 #ifndef MMU_DEBUG
 82 #define ASSERT(x) do { } while (0)
 83 #else
 84 #define ASSERT(x)                                                       \
 85         if (!(x)) {                                                     \
 86                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
 87                        __FILE__, __LINE__, #x);                         \
 88         }
 89 #endif
 90 
 91 #define PTE_PREFETCH_NUM                8
 92 
 93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
 94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 95 
 96 #define PT64_LEVEL_BITS 9
 97 
 98 #define PT64_LEVEL_SHIFT(level) \
 99                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100 
101 #define PT64_INDEX(address, level)\
102         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103 
104 
105 #define PT32_LEVEL_BITS 10
106 
107 #define PT32_LEVEL_SHIFT(level) \
108                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109 
110 #define PT32_LVL_OFFSET_MASK(level) \
111         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112                                                 * PT32_LEVEL_BITS))) - 1))
113 
114 #define PT32_INDEX(address, level)\
115         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116 
117 
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123                                                 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126                                                 * PT64_LEVEL_BITS))) - 1))
127 
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133                                             * PT32_LEVEL_BITS))) - 1))
134 
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
136                         | PT64_NX_MASK)
137 
138 #define ACC_EXEC_MASK    1
139 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
140 #define ACC_USER_MASK    PT_USER_MASK
141 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
142 
143 #include <trace/events/kvm.h>
144 
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
147 
148 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
150 
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
152 
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
155 
156 struct pte_list_desc {
157         u64 *sptes[PTE_LIST_EXT];
158         struct pte_list_desc *more;
159 };
160 
161 struct kvm_shadow_walk_iterator {
162         u64 addr;
163         hpa_t shadow_addr;
164         u64 *sptep;
165         int level;
166         unsigned index;
167 };
168 
169 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
170         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
171              shadow_walk_okay(&(_walker));                      \
172              shadow_walk_next(&(_walker)))
173 
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
175         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
176              shadow_walk_okay(&(_walker)) &&                            \
177                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
178              __shadow_walk_next(&(_walker), spte))
179 
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
183 
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
190 
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
193 
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
195 {
196         shadow_mmio_mask = mmio_mask;
197 }
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
199 
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
201 {
202         access &= ACC_WRITE_MASK | ACC_USER_MASK;
203 
204         trace_mark_mmio_spte(sptep, gfn, access);
205         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
206 }
207 
208 static bool is_mmio_spte(u64 spte)
209 {
210         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
211 }
212 
213 static gfn_t get_mmio_spte_gfn(u64 spte)
214 {
215         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
216 }
217 
218 static unsigned get_mmio_spte_access(u64 spte)
219 {
220         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
221 }
222 
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
224 {
225         if (unlikely(is_noslot_pfn(pfn))) {
226                 mark_mmio_spte(sptep, gfn, access);
227                 return true;
228         }
229 
230         return false;
231 }
232 
233 static inline u64 rsvd_bits(int s, int e)
234 {
235         return ((1ULL << (e - s + 1)) - 1) << s;
236 }
237 
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
240 {
241         shadow_user_mask = user_mask;
242         shadow_accessed_mask = accessed_mask;
243         shadow_dirty_mask = dirty_mask;
244         shadow_nx_mask = nx_mask;
245         shadow_x_mask = x_mask;
246 }
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
248 
249 static int is_cpuid_PSE36(void)
250 {
251         return 1;
252 }
253 
254 static int is_nx(struct kvm_vcpu *vcpu)
255 {
256         return vcpu->arch.efer & EFER_NX;
257 }
258 
259 static int is_shadow_present_pte(u64 pte)
260 {
261         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
262 }
263 
264 static int is_large_pte(u64 pte)
265 {
266         return pte & PT_PAGE_SIZE_MASK;
267 }
268 
269 static int is_dirty_gpte(unsigned long pte)
270 {
271         return pte & PT_DIRTY_MASK;
272 }
273 
274 static int is_rmap_spte(u64 pte)
275 {
276         return is_shadow_present_pte(pte);
277 }
278 
279 static int is_last_spte(u64 pte, int level)
280 {
281         if (level == PT_PAGE_TABLE_LEVEL)
282                 return 1;
283         if (is_large_pte(pte))
284                 return 1;
285         return 0;
286 }
287 
288 static pfn_t spte_to_pfn(u64 pte)
289 {
290         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
291 }
292 
293 static gfn_t pse36_gfn_delta(u32 gpte)
294 {
295         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
296 
297         return (gpte & PT32_DIR_PSE36_MASK) << shift;
298 }
299 
300 #ifdef CONFIG_X86_64
301 static void __set_spte(u64 *sptep, u64 spte)
302 {
303         *sptep = spte;
304 }
305 
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
307 {
308         *sptep = spte;
309 }
310 
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
312 {
313         return xchg(sptep, spte);
314 }
315 
316 static u64 __get_spte_lockless(u64 *sptep)
317 {
318         return ACCESS_ONCE(*sptep);
319 }
320 
321 static bool __check_direct_spte_mmio_pf(u64 spte)
322 {
323         /* It is valid if the spte is zapped. */
324         return spte == 0ull;
325 }
326 #else
327 union split_spte {
328         struct {
329                 u32 spte_low;
330                 u32 spte_high;
331         };
332         u64 spte;
333 };
334 
335 static void count_spte_clear(u64 *sptep, u64 spte)
336 {
337         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
338 
339         if (is_shadow_present_pte(spte))
340                 return;
341 
342         /* Ensure the spte is completely set before we increase the count */
343         smp_wmb();
344         sp->clear_spte_count++;
345 }
346 
347 static void __set_spte(u64 *sptep, u64 spte)
348 {
349         union split_spte *ssptep, sspte;
350 
351         ssptep = (union split_spte *)sptep;
352         sspte = (union split_spte)spte;
353 
354         ssptep->spte_high = sspte.spte_high;
355 
356         /*
357          * If we map the spte from nonpresent to present, We should store
358          * the high bits firstly, then set present bit, so cpu can not
359          * fetch this spte while we are setting the spte.
360          */
361         smp_wmb();
362 
363         ssptep->spte_low = sspte.spte_low;
364 }
365 
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
367 {
368         union split_spte *ssptep, sspte;
369 
370         ssptep = (union split_spte *)sptep;
371         sspte = (union split_spte)spte;
372 
373         ssptep->spte_low = sspte.spte_low;
374 
375         /*
376          * If we map the spte from present to nonpresent, we should clear
377          * present bit firstly to avoid vcpu fetch the old high bits.
378          */
379         smp_wmb();
380 
381         ssptep->spte_high = sspte.spte_high;
382         count_spte_clear(sptep, spte);
383 }
384 
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
386 {
387         union split_spte *ssptep, sspte, orig;
388 
389         ssptep = (union split_spte *)sptep;
390         sspte = (union split_spte)spte;
391 
392         /* xchg acts as a barrier before the setting of the high bits */
393         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394         orig.spte_high = ssptep->spte_high;
395         ssptep->spte_high = sspte.spte_high;
396         count_spte_clear(sptep, spte);
397 
398         return orig.spte;
399 }
400 
401 /*
402  * The idea using the light way get the spte on x86_32 guest is from
403  * gup_get_pte(arch/x86/mm/gup.c).
404  * The difference is we can not catch the spte tlb flush if we leave
405  * guest mode, so we emulate it by increase clear_spte_count when spte
406  * is cleared.
407  */
408 static u64 __get_spte_lockless(u64 *sptep)
409 {
410         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
411         union split_spte spte, *orig = (union split_spte *)sptep;
412         int count;
413 
414 retry:
415         count = sp->clear_spte_count;
416         smp_rmb();
417 
418         spte.spte_low = orig->spte_low;
419         smp_rmb();
420 
421         spte.spte_high = orig->spte_high;
422         smp_rmb();
423 
424         if (unlikely(spte.spte_low != orig->spte_low ||
425               count != sp->clear_spte_count))
426                 goto retry;
427 
428         return spte.spte;
429 }
430 
431 static bool __check_direct_spte_mmio_pf(u64 spte)
432 {
433         union split_spte sspte = (union split_spte)spte;
434         u32 high_mmio_mask = shadow_mmio_mask >> 32;
435 
436         /* It is valid if the spte is zapped. */
437         if (spte == 0ull)
438                 return true;
439 
440         /* It is valid if the spte is being zapped. */
441         if (sspte.spte_low == 0ull &&
442             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
443                 return true;
444 
445         return false;
446 }
447 #endif
448 
449 static bool spte_is_locklessly_modifiable(u64 spte)
450 {
451         return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
452                 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
453 }
454 
455 static bool spte_has_volatile_bits(u64 spte)
456 {
457         /*
458          * Always atomicly update spte if it can be updated
459          * out of mmu-lock, it can ensure dirty bit is not lost,
460          * also, it can help us to get a stable is_writable_pte()
461          * to ensure tlb flush is not missed.
462          */
463         if (spte_is_locklessly_modifiable(spte))
464                 return true;
465 
466         if (!shadow_accessed_mask)
467                 return false;
468 
469         if (!is_shadow_present_pte(spte))
470                 return false;
471 
472         if ((spte & shadow_accessed_mask) &&
473               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
474                 return false;
475 
476         return true;
477 }
478 
479 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
480 {
481         return (old_spte & bit_mask) && !(new_spte & bit_mask);
482 }
483 
484 /* Rules for using mmu_spte_set:
485  * Set the sptep from nonpresent to present.
486  * Note: the sptep being assigned *must* be either not present
487  * or in a state where the hardware will not attempt to update
488  * the spte.
489  */
490 static void mmu_spte_set(u64 *sptep, u64 new_spte)
491 {
492         WARN_ON(is_shadow_present_pte(*sptep));
493         __set_spte(sptep, new_spte);
494 }
495 
496 /* Rules for using mmu_spte_update:
497  * Update the state bits, it means the mapped pfn is not changged.
498  *
499  * Whenever we overwrite a writable spte with a read-only one we
500  * should flush remote TLBs. Otherwise rmap_write_protect
501  * will find a read-only spte, even though the writable spte
502  * might be cached on a CPU's TLB, the return value indicates this
503  * case.
504  */
505 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 {
507         u64 old_spte = *sptep;
508         bool ret = false;
509 
510         WARN_ON(!is_rmap_spte(new_spte));
511 
512         if (!is_shadow_present_pte(old_spte)) {
513                 mmu_spte_set(sptep, new_spte);
514                 return ret;
515         }
516 
517         if (!spte_has_volatile_bits(old_spte))
518                 __update_clear_spte_fast(sptep, new_spte);
519         else
520                 old_spte = __update_clear_spte_slow(sptep, new_spte);
521 
522         /*
523          * For the spte updated out of mmu-lock is safe, since
524          * we always atomicly update it, see the comments in
525          * spte_has_volatile_bits().
526          */
527         if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
528                 ret = true;
529 
530         if (!shadow_accessed_mask)
531                 return ret;
532 
533         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
534                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
535         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
536                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
537 
538         return ret;
539 }
540 
541 /*
542  * Rules for using mmu_spte_clear_track_bits:
543  * It sets the sptep from present to nonpresent, and track the
544  * state bits, it is used to clear the last level sptep.
545  */
546 static int mmu_spte_clear_track_bits(u64 *sptep)
547 {
548         pfn_t pfn;
549         u64 old_spte = *sptep;
550 
551         if (!spte_has_volatile_bits(old_spte))
552                 __update_clear_spte_fast(sptep, 0ull);
553         else
554                 old_spte = __update_clear_spte_slow(sptep, 0ull);
555 
556         if (!is_rmap_spte(old_spte))
557                 return 0;
558 
559         pfn = spte_to_pfn(old_spte);
560 
561         /*
562          * KVM does not hold the refcount of the page used by
563          * kvm mmu, before reclaiming the page, we should
564          * unmap it from mmu first.
565          */
566         WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
567 
568         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
569                 kvm_set_pfn_accessed(pfn);
570         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
571                 kvm_set_pfn_dirty(pfn);
572         return 1;
573 }
574 
575 /*
576  * Rules for using mmu_spte_clear_no_track:
577  * Directly clear spte without caring the state bits of sptep,
578  * it is used to set the upper level spte.
579  */
580 static void mmu_spte_clear_no_track(u64 *sptep)
581 {
582         __update_clear_spte_fast(sptep, 0ull);
583 }
584 
585 static u64 mmu_spte_get_lockless(u64 *sptep)
586 {
587         return __get_spte_lockless(sptep);
588 }
589 
590 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
591 {
592         /*
593          * Prevent page table teardown by making any free-er wait during
594          * kvm_flush_remote_tlbs() IPI to all active vcpus.
595          */
596         local_irq_disable();
597         vcpu->mode = READING_SHADOW_PAGE_TABLES;
598         /*
599          * Make sure a following spte read is not reordered ahead of the write
600          * to vcpu->mode.
601          */
602         smp_mb();
603 }
604 
605 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
606 {
607         /*
608          * Make sure the write to vcpu->mode is not reordered in front of
609          * reads to sptes.  If it does, kvm_commit_zap_page() can see us
610          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
611          */
612         smp_mb();
613         vcpu->mode = OUTSIDE_GUEST_MODE;
614         local_irq_enable();
615 }
616 
617 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
618                                   struct kmem_cache *base_cache, int min)
619 {
620         void *obj;
621 
622         if (cache->nobjs >= min)
623                 return 0;
624         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
625                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
626                 if (!obj)
627                         return -ENOMEM;
628                 cache->objects[cache->nobjs++] = obj;
629         }
630         return 0;
631 }
632 
633 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
634 {
635         return cache->nobjs;
636 }
637 
638 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
639                                   struct kmem_cache *cache)
640 {
641         while (mc->nobjs)
642                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
643 }
644 
645 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
646                                        int min)
647 {
648         void *page;
649 
650         if (cache->nobjs >= min)
651                 return 0;
652         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
653                 page = (void *)__get_free_page(GFP_KERNEL);
654                 if (!page)
655                         return -ENOMEM;
656                 cache->objects[cache->nobjs++] = page;
657         }
658         return 0;
659 }
660 
661 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
662 {
663         while (mc->nobjs)
664                 free_page((unsigned long)mc->objects[--mc->nobjs]);
665 }
666 
667 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
668 {
669         int r;
670 
671         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
672                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
673         if (r)
674                 goto out;
675         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
676         if (r)
677                 goto out;
678         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
679                                    mmu_page_header_cache, 4);
680 out:
681         return r;
682 }
683 
684 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 {
686         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
687                                 pte_list_desc_cache);
688         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
689         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
690                                 mmu_page_header_cache);
691 }
692 
693 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
694 {
695         void *p;
696 
697         BUG_ON(!mc->nobjs);
698         p = mc->objects[--mc->nobjs];
699         return p;
700 }
701 
702 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
703 {
704         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
705 }
706 
707 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
708 {
709         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
710 }
711 
712 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
713 {
714         if (!sp->role.direct)
715                 return sp->gfns[index];
716 
717         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
718 }
719 
720 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
721 {
722         if (sp->role.direct)
723                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
724         else
725                 sp->gfns[index] = gfn;
726 }
727 
728 /*
729  * Return the pointer to the large page information for a given gfn,
730  * handling slots that are not large page aligned.
731  */
732 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
733                                               struct kvm_memory_slot *slot,
734                                               int level)
735 {
736         unsigned long idx;
737 
738         idx = gfn_to_index(gfn, slot->base_gfn, level);
739         return &slot->arch.lpage_info[level - 2][idx];
740 }
741 
742 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
743 {
744         struct kvm_memory_slot *slot;
745         struct kvm_lpage_info *linfo;
746         int i;
747 
748         slot = gfn_to_memslot(kvm, gfn);
749         for (i = PT_DIRECTORY_LEVEL;
750              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
751                 linfo = lpage_info_slot(gfn, slot, i);
752                 linfo->write_count += 1;
753         }
754         kvm->arch.indirect_shadow_pages++;
755 }
756 
757 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
758 {
759         struct kvm_memory_slot *slot;
760         struct kvm_lpage_info *linfo;
761         int i;
762 
763         slot = gfn_to_memslot(kvm, gfn);
764         for (i = PT_DIRECTORY_LEVEL;
765              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
766                 linfo = lpage_info_slot(gfn, slot, i);
767                 linfo->write_count -= 1;
768                 WARN_ON(linfo->write_count < 0);
769         }
770         kvm->arch.indirect_shadow_pages--;
771 }
772 
773 static int has_wrprotected_page(struct kvm *kvm,
774                                 gfn_t gfn,
775                                 int level)
776 {
777         struct kvm_memory_slot *slot;
778         struct kvm_lpage_info *linfo;
779 
780         slot = gfn_to_memslot(kvm, gfn);
781         if (slot) {
782                 linfo = lpage_info_slot(gfn, slot, level);
783                 return linfo->write_count;
784         }
785 
786         return 1;
787 }
788 
789 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
790 {
791         unsigned long page_size;
792         int i, ret = 0;
793 
794         page_size = kvm_host_page_size(kvm, gfn);
795 
796         for (i = PT_PAGE_TABLE_LEVEL;
797              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
798                 if (page_size >= KVM_HPAGE_SIZE(i))
799                         ret = i;
800                 else
801                         break;
802         }
803 
804         return ret;
805 }
806 
807 static struct kvm_memory_slot *
808 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
809                             bool no_dirty_log)
810 {
811         struct kvm_memory_slot *slot;
812 
813         slot = gfn_to_memslot(vcpu->kvm, gfn);
814         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
815               (no_dirty_log && slot->dirty_bitmap))
816                 slot = NULL;
817 
818         return slot;
819 }
820 
821 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
822 {
823         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
824 }
825 
826 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
827 {
828         int host_level, level, max_level;
829 
830         host_level = host_mapping_level(vcpu->kvm, large_gfn);
831 
832         if (host_level == PT_PAGE_TABLE_LEVEL)
833                 return host_level;
834 
835         max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
836 
837         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
839                         break;
840 
841         return level - 1;
842 }
843 
844 /*
845  * Pte mapping structures:
846  *
847  * If pte_list bit zero is zero, then pte_list point to the spte.
848  *
849  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850  * pte_list_desc containing more mappings.
851  *
852  * Returns the number of pte entries before the spte was added or zero if
853  * the spte was not added.
854  *
855  */
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857                         unsigned long *pte_list)
858 {
859         struct pte_list_desc *desc;
860         int i, count = 0;
861 
862         if (!*pte_list) {
863                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864                 *pte_list = (unsigned long)spte;
865         } else if (!(*pte_list & 1)) {
866                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867                 desc = mmu_alloc_pte_list_desc(vcpu);
868                 desc->sptes[0] = (u64 *)*pte_list;
869                 desc->sptes[1] = spte;
870                 *pte_list = (unsigned long)desc | 1;
871                 ++count;
872         } else {
873                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
876                         desc = desc->more;
877                         count += PTE_LIST_EXT;
878                 }
879                 if (desc->sptes[PTE_LIST_EXT-1]) {
880                         desc->more = mmu_alloc_pte_list_desc(vcpu);
881                         desc = desc->more;
882                 }
883                 for (i = 0; desc->sptes[i]; ++i)
884                         ++count;
885                 desc->sptes[i] = spte;
886         }
887         return count;
888 }
889 
890 static void
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892                            int i, struct pte_list_desc *prev_desc)
893 {
894         int j;
895 
896         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
897                 ;
898         desc->sptes[i] = desc->sptes[j];
899         desc->sptes[j] = NULL;
900         if (j != 0)
901                 return;
902         if (!prev_desc && !desc->more)
903                 *pte_list = (unsigned long)desc->sptes[0];
904         else
905                 if (prev_desc)
906                         prev_desc->more = desc->more;
907                 else
908                         *pte_list = (unsigned long)desc->more | 1;
909         mmu_free_pte_list_desc(desc);
910 }
911 
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
913 {
914         struct pte_list_desc *desc;
915         struct pte_list_desc *prev_desc;
916         int i;
917 
918         if (!*pte_list) {
919                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
920                 BUG();
921         } else if (!(*pte_list & 1)) {
922                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
923                 if ((u64 *)*pte_list != spte) {
924                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
925                         BUG();
926                 }
927                 *pte_list = 0;
928         } else {
929                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
930                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
931                 prev_desc = NULL;
932                 while (desc) {
933                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934                                 if (desc->sptes[i] == spte) {
935                                         pte_list_desc_remove_entry(pte_list,
936                                                                desc, i,
937                                                                prev_desc);
938                                         return;
939                                 }
940                         prev_desc = desc;
941                         desc = desc->more;
942                 }
943                 pr_err("pte_list_remove: %p many->many\n", spte);
944                 BUG();
945         }
946 }
947 
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
950 {
951         struct pte_list_desc *desc;
952         int i;
953 
954         if (!*pte_list)
955                 return;
956 
957         if (!(*pte_list & 1))
958                 return fn((u64 *)*pte_list);
959 
960         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
961         while (desc) {
962                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
963                         fn(desc->sptes[i]);
964                 desc = desc->more;
965         }
966 }
967 
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969                                     struct kvm_memory_slot *slot)
970 {
971         unsigned long idx;
972 
973         idx = gfn_to_index(gfn, slot->base_gfn, level);
974         return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
975 }
976 
977 /*
978  * Take gfn and return the reverse mapping to it.
979  */
980 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
981 {
982         struct kvm_memory_slot *slot;
983 
984         slot = gfn_to_memslot(kvm, gfn);
985         return __gfn_to_rmap(gfn, level, slot);
986 }
987 
988 static bool rmap_can_add(struct kvm_vcpu *vcpu)
989 {
990         struct kvm_mmu_memory_cache *cache;
991 
992         cache = &vcpu->arch.mmu_pte_list_desc_cache;
993         return mmu_memory_cache_free_objects(cache);
994 }
995 
996 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
997 {
998         struct kvm_mmu_page *sp;
999         unsigned long *rmapp;
1000 
1001         sp = page_header(__pa(spte));
1002         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1003         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1004         return pte_list_add(vcpu, spte, rmapp);
1005 }
1006 
1007 static void rmap_remove(struct kvm *kvm, u64 *spte)
1008 {
1009         struct kvm_mmu_page *sp;
1010         gfn_t gfn;
1011         unsigned long *rmapp;
1012 
1013         sp = page_header(__pa(spte));
1014         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1015         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1016         pte_list_remove(spte, rmapp);
1017 }
1018 
1019 /*
1020  * Used by the following functions to iterate through the sptes linked by a
1021  * rmap.  All fields are private and not assumed to be used outside.
1022  */
1023 struct rmap_iterator {
1024         /* private fields */
1025         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1026         int pos;                        /* index of the sptep */
1027 };
1028 
1029 /*
1030  * Iteration must be started by this function.  This should also be used after
1031  * removing/dropping sptes from the rmap link because in such cases the
1032  * information in the itererator may not be valid.
1033  *
1034  * Returns sptep if found, NULL otherwise.
1035  */
1036 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1037 {
1038         if (!rmap)
1039                 return NULL;
1040 
1041         if (!(rmap & 1)) {
1042                 iter->desc = NULL;
1043                 return (u64 *)rmap;
1044         }
1045 
1046         iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1047         iter->pos = 0;
1048         return iter->desc->sptes[iter->pos];
1049 }
1050 
1051 /*
1052  * Must be used with a valid iterator: e.g. after rmap_get_first().
1053  *
1054  * Returns sptep if found, NULL otherwise.
1055  */
1056 static u64 *rmap_get_next(struct rmap_iterator *iter)
1057 {
1058         if (iter->desc) {
1059                 if (iter->pos < PTE_LIST_EXT - 1) {
1060                         u64 *sptep;
1061 
1062                         ++iter->pos;
1063                         sptep = iter->desc->sptes[iter->pos];
1064                         if (sptep)
1065                                 return sptep;
1066                 }
1067 
1068                 iter->desc = iter->desc->more;
1069 
1070                 if (iter->desc) {
1071                         iter->pos = 0;
1072                         /* desc->sptes[0] cannot be NULL */
1073                         return iter->desc->sptes[iter->pos];
1074                 }
1075         }
1076 
1077         return NULL;
1078 }
1079 
1080 static void drop_spte(struct kvm *kvm, u64 *sptep)
1081 {
1082         if (mmu_spte_clear_track_bits(sptep))
1083                 rmap_remove(kvm, sptep);
1084 }
1085 
1086 
1087 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1088 {
1089         if (is_large_pte(*sptep)) {
1090                 WARN_ON(page_header(__pa(sptep))->role.level ==
1091                         PT_PAGE_TABLE_LEVEL);
1092                 drop_spte(kvm, sptep);
1093                 --kvm->stat.lpages;
1094                 return true;
1095         }
1096 
1097         return false;
1098 }
1099 
1100 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1101 {
1102         if (__drop_large_spte(vcpu->kvm, sptep))
1103                 kvm_flush_remote_tlbs(vcpu->kvm);
1104 }
1105 
1106 /*
1107  * Write-protect on the specified @sptep, @pt_protect indicates whether
1108  * spte writ-protection is caused by protecting shadow page table.
1109  * @flush indicates whether tlb need be flushed.
1110  *
1111  * Note: write protection is difference between drity logging and spte
1112  * protection:
1113  * - for dirty logging, the spte can be set to writable at anytime if
1114  *   its dirty bitmap is properly set.
1115  * - for spte protection, the spte can be writable only after unsync-ing
1116  *   shadow page.
1117  *
1118  * Return true if the spte is dropped.
1119  */
1120 static bool
1121 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1122 {
1123         u64 spte = *sptep;
1124 
1125         if (!is_writable_pte(spte) &&
1126               !(pt_protect && spte_is_locklessly_modifiable(spte)))
1127                 return false;
1128 
1129         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1130 
1131         if (__drop_large_spte(kvm, sptep)) {
1132                 *flush |= true;
1133                 return true;
1134         }
1135 
1136         if (pt_protect)
1137                 spte &= ~SPTE_MMU_WRITEABLE;
1138         spte = spte & ~PT_WRITABLE_MASK;
1139 
1140         *flush |= mmu_spte_update(sptep, spte);
1141         return false;
1142 }
1143 
1144 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1145                                  bool pt_protect)
1146 {
1147         u64 *sptep;
1148         struct rmap_iterator iter;
1149         bool flush = false;
1150 
1151         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1152                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1153                 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1154                         sptep = rmap_get_first(*rmapp, &iter);
1155                         continue;
1156                 }
1157 
1158                 sptep = rmap_get_next(&iter);
1159         }
1160 
1161         return flush;
1162 }
1163 
1164 /**
1165  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1166  * @kvm: kvm instance
1167  * @slot: slot to protect
1168  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1169  * @mask: indicates which pages we should protect
1170  *
1171  * Used when we do not need to care about huge page mappings: e.g. during dirty
1172  * logging we do not have any such mappings.
1173  */
1174 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1175                                      struct kvm_memory_slot *slot,
1176                                      gfn_t gfn_offset, unsigned long mask)
1177 {
1178         unsigned long *rmapp;
1179 
1180         while (mask) {
1181                 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1182                                       PT_PAGE_TABLE_LEVEL, slot);
1183                 __rmap_write_protect(kvm, rmapp, false);
1184 
1185                 /* clear the first set bit */
1186                 mask &= mask - 1;
1187         }
1188 }
1189 
1190 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1191 {
1192         struct kvm_memory_slot *slot;
1193         unsigned long *rmapp;
1194         int i;
1195         bool write_protected = false;
1196 
1197         slot = gfn_to_memslot(kvm, gfn);
1198 
1199         for (i = PT_PAGE_TABLE_LEVEL;
1200              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1201                 rmapp = __gfn_to_rmap(gfn, i, slot);
1202                 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1203         }
1204 
1205         return write_protected;
1206 }
1207 
1208 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1209                            struct kvm_memory_slot *slot, unsigned long data)
1210 {
1211         u64 *sptep;
1212         struct rmap_iterator iter;
1213         int need_tlb_flush = 0;
1214 
1215         while ((sptep = rmap_get_first(*rmapp, &iter))) {
1216                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1217                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1218 
1219                 drop_spte(kvm, sptep);
1220                 need_tlb_flush = 1;
1221         }
1222 
1223         return need_tlb_flush;
1224 }
1225 
1226 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1227                              struct kvm_memory_slot *slot, unsigned long data)
1228 {
1229         u64 *sptep;
1230         struct rmap_iterator iter;
1231         int need_flush = 0;
1232         u64 new_spte;
1233         pte_t *ptep = (pte_t *)data;
1234         pfn_t new_pfn;
1235 
1236         WARN_ON(pte_huge(*ptep));
1237         new_pfn = pte_pfn(*ptep);
1238 
1239         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1240                 BUG_ON(!is_shadow_present_pte(*sptep));
1241                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1242 
1243                 need_flush = 1;
1244 
1245                 if (pte_write(*ptep)) {
1246                         drop_spte(kvm, sptep);
1247                         sptep = rmap_get_first(*rmapp, &iter);
1248                 } else {
1249                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1250                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1251 
1252                         new_spte &= ~PT_WRITABLE_MASK;
1253                         new_spte &= ~SPTE_HOST_WRITEABLE;
1254                         new_spte &= ~shadow_accessed_mask;
1255 
1256                         mmu_spte_clear_track_bits(sptep);
1257                         mmu_spte_set(sptep, new_spte);
1258                         sptep = rmap_get_next(&iter);
1259                 }
1260         }
1261 
1262         if (need_flush)
1263                 kvm_flush_remote_tlbs(kvm);
1264 
1265         return 0;
1266 }
1267 
1268 static int kvm_handle_hva_range(struct kvm *kvm,
1269                                 unsigned long start,
1270                                 unsigned long end,
1271                                 unsigned long data,
1272                                 int (*handler)(struct kvm *kvm,
1273                                                unsigned long *rmapp,
1274                                                struct kvm_memory_slot *slot,
1275                                                unsigned long data))
1276 {
1277         int j;
1278         int ret = 0;
1279         struct kvm_memslots *slots;
1280         struct kvm_memory_slot *memslot;
1281 
1282         slots = kvm_memslots(kvm);
1283 
1284         kvm_for_each_memslot(memslot, slots) {
1285                 unsigned long hva_start, hva_end;
1286                 gfn_t gfn_start, gfn_end;
1287 
1288                 hva_start = max(start, memslot->userspace_addr);
1289                 hva_end = min(end, memslot->userspace_addr +
1290                                         (memslot->npages << PAGE_SHIFT));
1291                 if (hva_start >= hva_end)
1292                         continue;
1293                 /*
1294                  * {gfn(page) | page intersects with [hva_start, hva_end)} =
1295                  * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1296                  */
1297                 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1298                 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1299 
1300                 for (j = PT_PAGE_TABLE_LEVEL;
1301                      j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1302                         unsigned long idx, idx_end;
1303                         unsigned long *rmapp;
1304 
1305                         /*
1306                          * {idx(page_j) | page_j intersects with
1307                          *  [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1308                          */
1309                         idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1310                         idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1311 
1312                         rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1313 
1314                         for (; idx <= idx_end; ++idx)
1315                                 ret |= handler(kvm, rmapp++, memslot, data);
1316                 }
1317         }
1318 
1319         return ret;
1320 }
1321 
1322 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1323                           unsigned long data,
1324                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1325                                          struct kvm_memory_slot *slot,
1326                                          unsigned long data))
1327 {
1328         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1329 }
1330 
1331 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1332 {
1333         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1334 }
1335 
1336 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1337 {
1338         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1339 }
1340 
1341 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1342 {
1343         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1344 }
1345 
1346 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1347                          struct kvm_memory_slot *slot, unsigned long data)
1348 {
1349         u64 *sptep;
1350         struct rmap_iterator uninitialized_var(iter);
1351         int young = 0;
1352 
1353         /*
1354          * In case of absence of EPT Access and Dirty Bits supports,
1355          * emulate the accessed bit for EPT, by checking if this page has
1356          * an EPT mapping, and clearing it if it does. On the next access,
1357          * a new EPT mapping will be established.
1358          * This has some overhead, but not as much as the cost of swapping
1359          * out actively used pages or breaking up actively used hugepages.
1360          */
1361         if (!shadow_accessed_mask) {
1362                 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1363                 goto out;
1364         }
1365 
1366         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1367              sptep = rmap_get_next(&iter)) {
1368                 BUG_ON(!is_shadow_present_pte(*sptep));
1369 
1370                 if (*sptep & shadow_accessed_mask) {
1371                         young = 1;
1372                         clear_bit((ffs(shadow_accessed_mask) - 1),
1373                                  (unsigned long *)sptep);
1374                 }
1375         }
1376 out:
1377         /* @data has hva passed to kvm_age_hva(). */
1378         trace_kvm_age_page(data, slot, young);
1379         return young;
1380 }
1381 
1382 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1383                               struct kvm_memory_slot *slot, unsigned long data)
1384 {
1385         u64 *sptep;
1386         struct rmap_iterator iter;
1387         int young = 0;
1388 
1389         /*
1390          * If there's no access bit in the secondary pte set by the
1391          * hardware it's up to gup-fast/gup to set the access bit in
1392          * the primary pte or in the page structure.
1393          */
1394         if (!shadow_accessed_mask)
1395                 goto out;
1396 
1397         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1398              sptep = rmap_get_next(&iter)) {
1399                 BUG_ON(!is_shadow_present_pte(*sptep));
1400 
1401                 if (*sptep & shadow_accessed_mask) {
1402                         young = 1;
1403                         break;
1404                 }
1405         }
1406 out:
1407         return young;
1408 }
1409 
1410 #define RMAP_RECYCLE_THRESHOLD 1000
1411 
1412 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1413 {
1414         unsigned long *rmapp;
1415         struct kvm_mmu_page *sp;
1416 
1417         sp = page_header(__pa(spte));
1418 
1419         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1420 
1421         kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1422         kvm_flush_remote_tlbs(vcpu->kvm);
1423 }
1424 
1425 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1426 {
1427         return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1428 }
1429 
1430 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1431 {
1432         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1433 }
1434 
1435 #ifdef MMU_DEBUG
1436 static int is_empty_shadow_page(u64 *spt)
1437 {
1438         u64 *pos;
1439         u64 *end;
1440 
1441         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1442                 if (is_shadow_present_pte(*pos)) {
1443                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1444                                pos, *pos);
1445                         return 0;
1446                 }
1447         return 1;
1448 }
1449 #endif
1450 
1451 /*
1452  * This value is the sum of all of the kvm instances's
1453  * kvm->arch.n_used_mmu_pages values.  We need a global,
1454  * aggregate version in order to make the slab shrinker
1455  * faster
1456  */
1457 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1458 {
1459         kvm->arch.n_used_mmu_pages += nr;
1460         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1461 }
1462 
1463 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1464 {
1465         ASSERT(is_empty_shadow_page(sp->spt));
1466         hlist_del(&sp->hash_link);
1467         list_del(&sp->link);
1468         free_page((unsigned long)sp->spt);
1469         if (!sp->role.direct)
1470                 free_page((unsigned long)sp->gfns);
1471         kmem_cache_free(mmu_page_header_cache, sp);
1472 }
1473 
1474 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1475 {
1476         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1477 }
1478 
1479 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1480                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1481 {
1482         if (!parent_pte)
1483                 return;
1484 
1485         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1486 }
1487 
1488 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1489                                        u64 *parent_pte)
1490 {
1491         pte_list_remove(parent_pte, &sp->parent_ptes);
1492 }
1493 
1494 static void drop_parent_pte(struct kvm_mmu_page *sp,
1495                             u64 *parent_pte)
1496 {
1497         mmu_page_remove_parent_pte(sp, parent_pte);
1498         mmu_spte_clear_no_track(parent_pte);
1499 }
1500 
1501 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1502                                                u64 *parent_pte, int direct)
1503 {
1504         struct kvm_mmu_page *sp;
1505         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1506         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1507         if (!direct)
1508                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1509         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1510         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1511         sp->parent_ptes = 0;
1512         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1513         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1514         return sp;
1515 }
1516 
1517 static void mark_unsync(u64 *spte);
1518 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1519 {
1520         pte_list_walk(&sp->parent_ptes, mark_unsync);
1521 }
1522 
1523 static void mark_unsync(u64 *spte)
1524 {
1525         struct kvm_mmu_page *sp;
1526         unsigned int index;
1527 
1528         sp = page_header(__pa(spte));
1529         index = spte - sp->spt;
1530         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1531                 return;
1532         if (sp->unsync_children++)
1533                 return;
1534         kvm_mmu_mark_parents_unsync(sp);
1535 }
1536 
1537 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1538                                struct kvm_mmu_page *sp)
1539 {
1540         return 1;
1541 }
1542 
1543 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1544 {
1545 }
1546 
1547 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1548                                  struct kvm_mmu_page *sp, u64 *spte,
1549                                  const void *pte)
1550 {
1551         WARN_ON(1);
1552 }
1553 
1554 #define KVM_PAGE_ARRAY_NR 16
1555 
1556 struct kvm_mmu_pages {
1557         struct mmu_page_and_offset {
1558                 struct kvm_mmu_page *sp;
1559                 unsigned int idx;
1560         } page[KVM_PAGE_ARRAY_NR];
1561         unsigned int nr;
1562 };
1563 
1564 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1565                          int idx)
1566 {
1567         int i;
1568 
1569         if (sp->unsync)
1570                 for (i=0; i < pvec->nr; i++)
1571                         if (pvec->page[i].sp == sp)
1572                                 return 0;
1573 
1574         pvec->page[pvec->nr].sp = sp;
1575         pvec->page[pvec->nr].idx = idx;
1576         pvec->nr++;
1577         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1578 }
1579 
1580 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1581                            struct kvm_mmu_pages *pvec)
1582 {
1583         int i, ret, nr_unsync_leaf = 0;
1584 
1585         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1586                 struct kvm_mmu_page *child;
1587                 u64 ent = sp->spt[i];
1588 
1589                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1590                         goto clear_child_bitmap;
1591 
1592                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1593 
1594                 if (child->unsync_children) {
1595                         if (mmu_pages_add(pvec, child, i))
1596                                 return -ENOSPC;
1597 
1598                         ret = __mmu_unsync_walk(child, pvec);
1599                         if (!ret)
1600                                 goto clear_child_bitmap;
1601                         else if (ret > 0)
1602                                 nr_unsync_leaf += ret;
1603                         else
1604                                 return ret;
1605                 } else if (child->unsync) {
1606                         nr_unsync_leaf++;
1607                         if (mmu_pages_add(pvec, child, i))
1608                                 return -ENOSPC;
1609                 } else
1610                          goto clear_child_bitmap;
1611 
1612                 continue;
1613 
1614 clear_child_bitmap:
1615                 __clear_bit(i, sp->unsync_child_bitmap);
1616                 sp->unsync_children--;
1617                 WARN_ON((int)sp->unsync_children < 0);
1618         }
1619 
1620 
1621         return nr_unsync_leaf;
1622 }
1623 
1624 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1625                            struct kvm_mmu_pages *pvec)
1626 {
1627         if (!sp->unsync_children)
1628                 return 0;
1629 
1630         mmu_pages_add(pvec, sp, 0);
1631         return __mmu_unsync_walk(sp, pvec);
1632 }
1633 
1634 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1635 {
1636         WARN_ON(!sp->unsync);
1637         trace_kvm_mmu_sync_page(sp);
1638         sp->unsync = 0;
1639         --kvm->stat.mmu_unsync;
1640 }
1641 
1642 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1643                                     struct list_head *invalid_list);
1644 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1645                                     struct list_head *invalid_list);
1646 
1647 #define for_each_gfn_sp(kvm, sp, gfn)                                   \
1648   hlist_for_each_entry(sp,                                              \
1649    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1650         if ((sp)->gfn != (gfn)) {} else
1651 
1652 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn)                    \
1653   hlist_for_each_entry(sp,                                              \
1654    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1655                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1656                         (sp)->role.invalid) {} else
1657 
1658 /* @sp->gfn should be write-protected at the call site */
1659 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1660                            struct list_head *invalid_list, bool clear_unsync)
1661 {
1662         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1663                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1664                 return 1;
1665         }
1666 
1667         if (clear_unsync)
1668                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1669 
1670         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1671                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1672                 return 1;
1673         }
1674 
1675         kvm_mmu_flush_tlb(vcpu);
1676         return 0;
1677 }
1678 
1679 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1680                                    struct kvm_mmu_page *sp)
1681 {
1682         LIST_HEAD(invalid_list);
1683         int ret;
1684 
1685         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1686         if (ret)
1687                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1688 
1689         return ret;
1690 }
1691 
1692 #ifdef CONFIG_KVM_MMU_AUDIT
1693 #include "mmu_audit.c"
1694 #else
1695 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1696 static void mmu_audit_disable(void) { }
1697 #endif
1698 
1699 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1700                          struct list_head *invalid_list)
1701 {
1702         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1703 }
1704 
1705 /* @gfn should be write-protected at the call site */
1706 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1707 {
1708         struct kvm_mmu_page *s;
1709         LIST_HEAD(invalid_list);
1710         bool flush = false;
1711 
1712         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1713                 if (!s->unsync)
1714                         continue;
1715 
1716                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1717                 kvm_unlink_unsync_page(vcpu->kvm, s);
1718                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1719                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1720                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1721                         continue;
1722                 }
1723                 flush = true;
1724         }
1725 
1726         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1727         if (flush)
1728                 kvm_mmu_flush_tlb(vcpu);
1729 }
1730 
1731 struct mmu_page_path {
1732         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1733         unsigned int idx[PT64_ROOT_LEVEL-1];
1734 };
1735 
1736 #define for_each_sp(pvec, sp, parents, i)                       \
1737                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1738                         sp = pvec.page[i].sp;                   \
1739                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1740                         i = mmu_pages_next(&pvec, &parents, i))
1741 
1742 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1743                           struct mmu_page_path *parents,
1744                           int i)
1745 {
1746         int n;
1747 
1748         for (n = i+1; n < pvec->nr; n++) {
1749                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1750 
1751                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1752                         parents->idx[0] = pvec->page[n].idx;
1753                         return n;
1754                 }
1755 
1756                 parents->parent[sp->role.level-2] = sp;
1757                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1758         }
1759 
1760         return n;
1761 }
1762 
1763 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1764 {
1765         struct kvm_mmu_page *sp;
1766         unsigned int level = 0;
1767 
1768         do {
1769                 unsigned int idx = parents->idx[level];
1770 
1771                 sp = parents->parent[level];
1772                 if (!sp)
1773                         return;
1774 
1775                 --sp->unsync_children;
1776                 WARN_ON((int)sp->unsync_children < 0);
1777                 __clear_bit(idx, sp->unsync_child_bitmap);
1778                 level++;
1779         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1780 }
1781 
1782 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1783                                struct mmu_page_path *parents,
1784                                struct kvm_mmu_pages *pvec)
1785 {
1786         parents->parent[parent->role.level-1] = NULL;
1787         pvec->nr = 0;
1788 }
1789 
1790 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1791                               struct kvm_mmu_page *parent)
1792 {
1793         int i;
1794         struct kvm_mmu_page *sp;
1795         struct mmu_page_path parents;
1796         struct kvm_mmu_pages pages;
1797         LIST_HEAD(invalid_list);
1798 
1799         kvm_mmu_pages_init(parent, &parents, &pages);
1800         while (mmu_unsync_walk(parent, &pages)) {
1801                 bool protected = false;
1802 
1803                 for_each_sp(pages, sp, parents, i)
1804                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1805 
1806                 if (protected)
1807                         kvm_flush_remote_tlbs(vcpu->kvm);
1808 
1809                 for_each_sp(pages, sp, parents, i) {
1810                         kvm_sync_page(vcpu, sp, &invalid_list);
1811                         mmu_pages_clear_parents(&parents);
1812                 }
1813                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1814                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1815                 kvm_mmu_pages_init(parent, &parents, &pages);
1816         }
1817 }
1818 
1819 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1820 {
1821         int i;
1822 
1823         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1824                 sp->spt[i] = 0ull;
1825 }
1826 
1827 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1828 {
1829         sp->write_flooding_count = 0;
1830 }
1831 
1832 static void clear_sp_write_flooding_count(u64 *spte)
1833 {
1834         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1835 
1836         __clear_sp_write_flooding_count(sp);
1837 }
1838 
1839 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1840                                              gfn_t gfn,
1841                                              gva_t gaddr,
1842                                              unsigned level,
1843                                              int direct,
1844                                              unsigned access,
1845                                              u64 *parent_pte)
1846 {
1847         union kvm_mmu_page_role role;
1848         unsigned quadrant;
1849         struct kvm_mmu_page *sp;
1850         bool need_sync = false;
1851 
1852         role = vcpu->arch.mmu.base_role;
1853         role.level = level;
1854         role.direct = direct;
1855         if (role.direct)
1856                 role.cr4_pae = 0;
1857         role.access = access;
1858         if (!vcpu->arch.mmu.direct_map
1859             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1860                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1861                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1862                 role.quadrant = quadrant;
1863         }
1864         for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1865                 if (!need_sync && sp->unsync)
1866                         need_sync = true;
1867 
1868                 if (sp->role.word != role.word)
1869                         continue;
1870 
1871                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1872                         break;
1873 
1874                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1875                 if (sp->unsync_children) {
1876                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1877                         kvm_mmu_mark_parents_unsync(sp);
1878                 } else if (sp->unsync)
1879                         kvm_mmu_mark_parents_unsync(sp);
1880 
1881                 __clear_sp_write_flooding_count(sp);
1882                 trace_kvm_mmu_get_page(sp, false);
1883                 return sp;
1884         }
1885         ++vcpu->kvm->stat.mmu_cache_miss;
1886         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1887         if (!sp)
1888                 return sp;
1889         sp->gfn = gfn;
1890         sp->role = role;
1891         hlist_add_head(&sp->hash_link,
1892                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1893         if (!direct) {
1894                 if (rmap_write_protect(vcpu->kvm, gfn))
1895                         kvm_flush_remote_tlbs(vcpu->kvm);
1896                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1897                         kvm_sync_pages(vcpu, gfn);
1898 
1899                 account_shadowed(vcpu->kvm, gfn);
1900         }
1901         init_shadow_page_table(sp);
1902         trace_kvm_mmu_get_page(sp, true);
1903         return sp;
1904 }
1905 
1906 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1907                              struct kvm_vcpu *vcpu, u64 addr)
1908 {
1909         iterator->addr = addr;
1910         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1911         iterator->level = vcpu->arch.mmu.shadow_root_level;
1912 
1913         if (iterator->level == PT64_ROOT_LEVEL &&
1914             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1915             !vcpu->arch.mmu.direct_map)
1916                 --iterator->level;
1917 
1918         if (iterator->level == PT32E_ROOT_LEVEL) {
1919                 iterator->shadow_addr
1920                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1921                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1922                 --iterator->level;
1923                 if (!iterator->shadow_addr)
1924                         iterator->level = 0;
1925         }
1926 }
1927 
1928 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1929 {
1930         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1931                 return false;
1932 
1933         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1934         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1935         return true;
1936 }
1937 
1938 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1939                                u64 spte)
1940 {
1941         if (is_last_spte(spte, iterator->level)) {
1942                 iterator->level = 0;
1943                 return;
1944         }
1945 
1946         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1947         --iterator->level;
1948 }
1949 
1950 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1951 {
1952         return __shadow_walk_next(iterator, *iterator->sptep);
1953 }
1954 
1955 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1956 {
1957         u64 spte;
1958 
1959         spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
1960                shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
1961 
1962         mmu_spte_set(sptep, spte);
1963 }
1964 
1965 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1966                                    unsigned direct_access)
1967 {
1968         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1969                 struct kvm_mmu_page *child;
1970 
1971                 /*
1972                  * For the direct sp, if the guest pte's dirty bit
1973                  * changed form clean to dirty, it will corrupt the
1974                  * sp's access: allow writable in the read-only sp,
1975                  * so we should update the spte at this point to get
1976                  * a new sp with the correct access.
1977                  */
1978                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1979                 if (child->role.access == direct_access)
1980                         return;
1981 
1982                 drop_parent_pte(child, sptep);
1983                 kvm_flush_remote_tlbs(vcpu->kvm);
1984         }
1985 }
1986 
1987 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1988                              u64 *spte)
1989 {
1990         u64 pte;
1991         struct kvm_mmu_page *child;
1992 
1993         pte = *spte;
1994         if (is_shadow_present_pte(pte)) {
1995                 if (is_last_spte(pte, sp->role.level)) {
1996                         drop_spte(kvm, spte);
1997                         if (is_large_pte(pte))
1998                                 --kvm->stat.lpages;
1999                 } else {
2000                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2001                         drop_parent_pte(child, spte);
2002                 }
2003                 return true;
2004         }
2005 
2006         if (is_mmio_spte(pte))
2007                 mmu_spte_clear_no_track(spte);
2008 
2009         return false;
2010 }
2011 
2012 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2013                                          struct kvm_mmu_page *sp)
2014 {
2015         unsigned i;
2016 
2017         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2018                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2019 }
2020 
2021 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2022 {
2023         mmu_page_remove_parent_pte(sp, parent_pte);
2024 }
2025 
2026 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2027 {
2028         u64 *sptep;
2029         struct rmap_iterator iter;
2030 
2031         while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2032                 drop_parent_pte(sp, sptep);
2033 }
2034 
2035 static int mmu_zap_unsync_children(struct kvm *kvm,
2036                                    struct kvm_mmu_page *parent,
2037                                    struct list_head *invalid_list)
2038 {
2039         int i, zapped = 0;
2040         struct mmu_page_path parents;
2041         struct kvm_mmu_pages pages;
2042 
2043         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2044                 return 0;
2045 
2046         kvm_mmu_pages_init(parent, &parents, &pages);
2047         while (mmu_unsync_walk(parent, &pages)) {
2048                 struct kvm_mmu_page *sp;
2049 
2050                 for_each_sp(pages, sp, parents, i) {
2051                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2052                         mmu_pages_clear_parents(&parents);
2053                         zapped++;
2054                 }
2055                 kvm_mmu_pages_init(parent, &parents, &pages);
2056         }
2057 
2058         return zapped;
2059 }
2060 
2061 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2062                                     struct list_head *invalid_list)
2063 {
2064         int ret;
2065 
2066         trace_kvm_mmu_prepare_zap_page(sp);
2067         ++kvm->stat.mmu_shadow_zapped;
2068         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2069         kvm_mmu_page_unlink_children(kvm, sp);
2070         kvm_mmu_unlink_parents(kvm, sp);
2071         if (!sp->role.invalid && !sp->role.direct)
2072                 unaccount_shadowed(kvm, sp->gfn);
2073         if (sp->unsync)
2074                 kvm_unlink_unsync_page(kvm, sp);
2075         if (!sp->root_count) {
2076                 /* Count self */
2077                 ret++;
2078                 list_move(&sp->link, invalid_list);
2079                 kvm_mod_used_mmu_pages(kvm, -1);
2080         } else {
2081                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2082                 kvm_reload_remote_mmus(kvm);
2083         }
2084 
2085         sp->role.invalid = 1;
2086         return ret;
2087 }
2088 
2089 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2090                                     struct list_head *invalid_list)
2091 {
2092         struct kvm_mmu_page *sp;
2093 
2094         if (list_empty(invalid_list))
2095                 return;
2096 
2097         /*
2098          * wmb: make sure everyone sees our modifications to the page tables
2099          * rmb: make sure we see changes to vcpu->mode
2100          */
2101         smp_mb();
2102 
2103         /*
2104          * Wait for all vcpus to exit guest mode and/or lockless shadow
2105          * page table walks.
2106          */
2107         kvm_flush_remote_tlbs(kvm);
2108 
2109         do {
2110                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2111                 WARN_ON(!sp->role.invalid || sp->root_count);
2112                 kvm_mmu_free_page(sp);
2113         } while (!list_empty(invalid_list));
2114 }
2115 
2116 /*
2117  * Changing the number of mmu pages allocated to the vm
2118  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2119  */
2120 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2121 {
2122         LIST_HEAD(invalid_list);
2123         /*
2124          * If we set the number of mmu pages to be smaller be than the
2125          * number of actived pages , we must to free some mmu pages before we
2126          * change the value
2127          */
2128 
2129         spin_lock(&kvm->mmu_lock);
2130 
2131         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2132                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2133                         !list_empty(&kvm->arch.active_mmu_pages)) {
2134                         struct kvm_mmu_page *page;
2135 
2136                         page = container_of(kvm->arch.active_mmu_pages.prev,
2137                                             struct kvm_mmu_page, link);
2138                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2139                 }
2140                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2141                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2142         }
2143 
2144         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2145 
2146         spin_unlock(&kvm->mmu_lock);
2147 }
2148 
2149 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2150 {
2151         struct kvm_mmu_page *sp;
2152         LIST_HEAD(invalid_list);
2153         int r;
2154 
2155         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2156         r = 0;
2157         spin_lock(&kvm->mmu_lock);
2158         for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2159                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2160                          sp->role.word);
2161                 r = 1;
2162                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2163         }
2164         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2165         spin_unlock(&kvm->mmu_lock);
2166 
2167         return r;
2168 }
2169 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2170 
2171 /*
2172  * The function is based on mtrr_type_lookup() in
2173  * arch/x86/kernel/cpu/mtrr/generic.c
2174  */
2175 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2176                          u64 start, u64 end)
2177 {
2178         int i;
2179         u64 base, mask;
2180         u8 prev_match, curr_match;
2181         int num_var_ranges = KVM_NR_VAR_MTRR;
2182 
2183         if (!mtrr_state->enabled)
2184                 return 0xFF;
2185 
2186         /* Make end inclusive end, instead of exclusive */
2187         end--;
2188 
2189         /* Look in fixed ranges. Just return the type as per start */
2190         if (mtrr_state->have_fixed && (start < 0x100000)) {
2191                 int idx;
2192 
2193                 if (start < 0x80000) {
2194                         idx = 0;
2195                         idx += (start >> 16);
2196                         return mtrr_state->fixed_ranges[idx];
2197                 } else if (start < 0xC0000) {
2198                         idx = 1 * 8;
2199                         idx += ((start - 0x80000) >> 14);
2200                         return mtrr_state->fixed_ranges[idx];
2201                 } else if (start < 0x1000000) {
2202                         idx = 3 * 8;
2203                         idx += ((start - 0xC0000) >> 12);
2204                         return mtrr_state->fixed_ranges[idx];
2205                 }
2206         }
2207 
2208         /*
2209          * Look in variable ranges
2210          * Look of multiple ranges matching this address and pick type
2211          * as per MTRR precedence
2212          */
2213         if (!(mtrr_state->enabled & 2))
2214                 return mtrr_state->def_type;
2215 
2216         prev_match = 0xFF;
2217         for (i = 0; i < num_var_ranges; ++i) {
2218                 unsigned short start_state, end_state;
2219 
2220                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2221                         continue;
2222 
2223                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2224                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2225                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2226                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2227 
2228                 start_state = ((start & mask) == (base & mask));
2229                 end_state = ((end & mask) == (base & mask));
2230                 if (start_state != end_state)
2231                         return 0xFE;
2232 
2233                 if ((start & mask) != (base & mask))
2234                         continue;
2235 
2236                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2237                 if (prev_match == 0xFF) {
2238                         prev_match = curr_match;
2239                         continue;
2240                 }
2241 
2242                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2243                     curr_match == MTRR_TYPE_UNCACHABLE)
2244                         return MTRR_TYPE_UNCACHABLE;
2245 
2246                 if ((prev_match == MTRR_TYPE_WRBACK &&
2247                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2248                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2249                      curr_match == MTRR_TYPE_WRBACK)) {
2250                         prev_match = MTRR_TYPE_WRTHROUGH;
2251                         curr_match = MTRR_TYPE_WRTHROUGH;
2252                 }
2253 
2254                 if (prev_match != curr_match)
2255                         return MTRR_TYPE_UNCACHABLE;
2256         }
2257 
2258         if (prev_match != 0xFF)
2259                 return prev_match;
2260 
2261         return mtrr_state->def_type;
2262 }
2263 
2264 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2265 {
2266         u8 mtrr;
2267 
2268         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2269                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2270         if (mtrr == 0xfe || mtrr == 0xff)
2271                 mtrr = MTRR_TYPE_WRBACK;
2272         return mtrr;
2273 }
2274 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2275 
2276 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2277 {
2278         trace_kvm_mmu_unsync_page(sp);
2279         ++vcpu->kvm->stat.mmu_unsync;
2280         sp->unsync = 1;
2281 
2282         kvm_mmu_mark_parents_unsync(sp);
2283 }
2284 
2285 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2286 {
2287         struct kvm_mmu_page *s;
2288 
2289         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2290                 if (s->unsync)
2291                         continue;
2292                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2293                 __kvm_unsync_page(vcpu, s);
2294         }
2295 }
2296 
2297 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2298                                   bool can_unsync)
2299 {
2300         struct kvm_mmu_page *s;
2301         bool need_unsync = false;
2302 
2303         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2304                 if (!can_unsync)
2305                         return 1;
2306 
2307                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2308                         return 1;
2309 
2310                 if (!s->unsync)
2311                         need_unsync = true;
2312         }
2313         if (need_unsync)
2314                 kvm_unsync_pages(vcpu, gfn);
2315         return 0;
2316 }
2317 
2318 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2319                     unsigned pte_access, int level,
2320                     gfn_t gfn, pfn_t pfn, bool speculative,
2321                     bool can_unsync, bool host_writable)
2322 {
2323         u64 spte;
2324         int ret = 0;
2325 
2326         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2327                 return 0;
2328 
2329         spte = PT_PRESENT_MASK;
2330         if (!speculative)
2331                 spte |= shadow_accessed_mask;
2332 
2333         if (pte_access & ACC_EXEC_MASK)
2334                 spte |= shadow_x_mask;
2335         else
2336                 spte |= shadow_nx_mask;
2337 
2338         if (pte_access & ACC_USER_MASK)
2339                 spte |= shadow_user_mask;
2340 
2341         if (level > PT_PAGE_TABLE_LEVEL)
2342                 spte |= PT_PAGE_SIZE_MASK;
2343         if (tdp_enabled)
2344                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2345                         kvm_is_mmio_pfn(pfn));
2346 
2347         if (host_writable)
2348                 spte |= SPTE_HOST_WRITEABLE;
2349         else
2350                 pte_access &= ~ACC_WRITE_MASK;
2351 
2352         spte |= (u64)pfn << PAGE_SHIFT;
2353 
2354         if (pte_access & ACC_WRITE_MASK) {
2355 
2356                 /*
2357                  * Other vcpu creates new sp in the window between
2358                  * mapping_level() and acquiring mmu-lock. We can
2359                  * allow guest to retry the access, the mapping can
2360                  * be fixed if guest refault.
2361                  */
2362                 if (level > PT_PAGE_TABLE_LEVEL &&
2363                     has_wrprotected_page(vcpu->kvm, gfn, level))
2364                         goto done;
2365 
2366                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2367 
2368                 /*
2369                  * Optimization: for pte sync, if spte was writable the hash
2370                  * lookup is unnecessary (and expensive). Write protection
2371                  * is responsibility of mmu_get_page / kvm_sync_page.
2372                  * Same reasoning can be applied to dirty page accounting.
2373                  */
2374                 if (!can_unsync && is_writable_pte(*sptep))
2375                         goto set_pte;
2376 
2377                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2378                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2379                                  __func__, gfn);
2380                         ret = 1;
2381                         pte_access &= ~ACC_WRITE_MASK;
2382                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2383                 }
2384         }
2385 
2386         if (pte_access & ACC_WRITE_MASK)
2387                 mark_page_dirty(vcpu->kvm, gfn);
2388 
2389 set_pte:
2390         if (mmu_spte_update(sptep, spte))
2391                 kvm_flush_remote_tlbs(vcpu->kvm);
2392 done:
2393         return ret;
2394 }
2395 
2396 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2397                          unsigned pte_access, int write_fault, int *emulate,
2398                          int level, gfn_t gfn, pfn_t pfn, bool speculative,
2399                          bool host_writable)
2400 {
2401         int was_rmapped = 0;
2402         int rmap_count;
2403 
2404         pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2405                  *sptep, write_fault, gfn);
2406 
2407         if (is_rmap_spte(*sptep)) {
2408                 /*
2409                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2410                  * the parent of the now unreachable PTE.
2411                  */
2412                 if (level > PT_PAGE_TABLE_LEVEL &&
2413                     !is_large_pte(*sptep)) {
2414                         struct kvm_mmu_page *child;
2415                         u64 pte = *sptep;
2416 
2417                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2418                         drop_parent_pte(child, sptep);
2419                         kvm_flush_remote_tlbs(vcpu->kvm);
2420                 } else if (pfn != spte_to_pfn(*sptep)) {
2421                         pgprintk("hfn old %llx new %llx\n",
2422                                  spte_to_pfn(*sptep), pfn);
2423                         drop_spte(vcpu->kvm, sptep);
2424                         kvm_flush_remote_tlbs(vcpu->kvm);
2425                 } else
2426                         was_rmapped = 1;
2427         }
2428 
2429         if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2430               true, host_writable)) {
2431                 if (write_fault)
2432                         *emulate = 1;
2433                 kvm_mmu_flush_tlb(vcpu);
2434         }
2435 
2436         if (unlikely(is_mmio_spte(*sptep) && emulate))
2437                 *emulate = 1;
2438 
2439         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2440         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2441                  is_large_pte(*sptep)? "2MB" : "4kB",
2442                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2443                  *sptep, sptep);
2444         if (!was_rmapped && is_large_pte(*sptep))
2445                 ++vcpu->kvm->stat.lpages;
2446 
2447         if (is_shadow_present_pte(*sptep)) {
2448                 if (!was_rmapped) {
2449                         rmap_count = rmap_add(vcpu, sptep, gfn);
2450                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2451                                 rmap_recycle(vcpu, sptep, gfn);
2452                 }
2453         }
2454 
2455         kvm_release_pfn_clean(pfn);
2456 }
2457 
2458 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2459 {
2460         mmu_free_roots(vcpu);
2461 }
2462 
2463 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2464 {
2465         int bit7;
2466 
2467         bit7 = (gpte >> 7) & 1;
2468         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2469 }
2470 
2471 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2472                                      bool no_dirty_log)
2473 {
2474         struct kvm_memory_slot *slot;
2475 
2476         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2477         if (!slot)
2478                 return KVM_PFN_ERR_FAULT;
2479 
2480         return gfn_to_pfn_memslot_atomic(slot, gfn);
2481 }
2482 
2483 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2484                                   struct kvm_mmu_page *sp, u64 *spte,
2485                                   u64 gpte)
2486 {
2487         if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2488                 goto no_present;
2489 
2490         if (!is_present_gpte(gpte))
2491                 goto no_present;
2492 
2493         if (!(gpte & PT_ACCESSED_MASK))
2494                 goto no_present;
2495 
2496         return false;
2497 
2498 no_present:
2499         drop_spte(vcpu->kvm, spte);
2500         return true;
2501 }
2502 
2503 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2504                                     struct kvm_mmu_page *sp,
2505                                     u64 *start, u64 *end)
2506 {
2507         struct page *pages[PTE_PREFETCH_NUM];
2508         unsigned access = sp->role.access;
2509         int i, ret;
2510         gfn_t gfn;
2511 
2512         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2513         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2514                 return -1;
2515 
2516         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2517         if (ret <= 0)
2518                 return -1;
2519 
2520         for (i = 0; i < ret; i++, gfn++, start++)
2521                 mmu_set_spte(vcpu, start, access, 0, NULL,
2522                              sp->role.level, gfn, page_to_pfn(pages[i]),
2523                              true, true);
2524 
2525         return 0;
2526 }
2527 
2528 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2529                                   struct kvm_mmu_page *sp, u64 *sptep)
2530 {
2531         u64 *spte, *start = NULL;
2532         int i;
2533 
2534         WARN_ON(!sp->role.direct);
2535 
2536         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2537         spte = sp->spt + i;
2538 
2539         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2540                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2541                         if (!start)
2542                                 continue;
2543                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2544                                 break;
2545                         start = NULL;
2546                 } else if (!start)
2547                         start = spte;
2548         }
2549 }
2550 
2551 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2552 {
2553         struct kvm_mmu_page *sp;
2554 
2555         /*
2556          * Since it's no accessed bit on EPT, it's no way to
2557          * distinguish between actually accessed translations
2558          * and prefetched, so disable pte prefetch if EPT is
2559          * enabled.
2560          */
2561         if (!shadow_accessed_mask)
2562                 return;
2563 
2564         sp = page_header(__pa(sptep));
2565         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2566                 return;
2567 
2568         __direct_pte_prefetch(vcpu, sp, sptep);
2569 }
2570 
2571 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2572                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2573                         bool prefault)
2574 {
2575         struct kvm_shadow_walk_iterator iterator;
2576         struct kvm_mmu_page *sp;
2577         int emulate = 0;
2578         gfn_t pseudo_gfn;
2579 
2580         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2581                 if (iterator.level == level) {
2582                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2583                                      write, &emulate, level, gfn, pfn,
2584                                      prefault, map_writable);
2585                         direct_pte_prefetch(vcpu, iterator.sptep);
2586                         ++vcpu->stat.pf_fixed;
2587                         break;
2588                 }
2589 
2590                 if (!is_shadow_present_pte(*iterator.sptep)) {
2591                         u64 base_addr = iterator.addr;
2592 
2593                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2594                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2595                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2596                                               iterator.level - 1,
2597                                               1, ACC_ALL, iterator.sptep);
2598 
2599                         link_shadow_page(iterator.sptep, sp);
2600                 }
2601         }
2602         return emulate;
2603 }
2604 
2605 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2606 {
2607         siginfo_t info;
2608 
2609         info.si_signo   = SIGBUS;
2610         info.si_errno   = 0;
2611         info.si_code    = BUS_MCEERR_AR;
2612         info.si_addr    = (void __user *)address;
2613         info.si_addr_lsb = PAGE_SHIFT;
2614 
2615         send_sig_info(SIGBUS, &info, tsk);
2616 }
2617 
2618 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2619 {
2620         /*
2621          * Do not cache the mmio info caused by writing the readonly gfn
2622          * into the spte otherwise read access on readonly gfn also can
2623          * caused mmio page fault and treat it as mmio access.
2624          * Return 1 to tell kvm to emulate it.
2625          */
2626         if (pfn == KVM_PFN_ERR_RO_FAULT)
2627                 return 1;
2628 
2629         if (pfn == KVM_PFN_ERR_HWPOISON) {
2630                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2631                 return 0;
2632         }
2633 
2634         return -EFAULT;
2635 }
2636 
2637 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2638                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2639 {
2640         pfn_t pfn = *pfnp;
2641         gfn_t gfn = *gfnp;
2642         int level = *levelp;
2643 
2644         /*
2645          * Check if it's a transparent hugepage. If this would be an
2646          * hugetlbfs page, level wouldn't be set to
2647          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2648          * here.
2649          */
2650         if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2651             level == PT_PAGE_TABLE_LEVEL &&
2652             PageTransCompound(pfn_to_page(pfn)) &&
2653             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2654                 unsigned long mask;
2655                 /*
2656                  * mmu_notifier_retry was successful and we hold the
2657                  * mmu_lock here, so the pmd can't become splitting
2658                  * from under us, and in turn
2659                  * __split_huge_page_refcount() can't run from under
2660                  * us and we can safely transfer the refcount from
2661                  * PG_tail to PG_head as we switch the pfn to tail to
2662                  * head.
2663                  */
2664                 *levelp = level = PT_DIRECTORY_LEVEL;
2665                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2666                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2667                 if (pfn & mask) {
2668                         gfn &= ~mask;
2669                         *gfnp = gfn;
2670                         kvm_release_pfn_clean(pfn);
2671                         pfn &= ~mask;
2672                         kvm_get_pfn(pfn);
2673                         *pfnp = pfn;
2674                 }
2675         }
2676 }
2677 
2678 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2679                                 pfn_t pfn, unsigned access, int *ret_val)
2680 {
2681         bool ret = true;
2682 
2683         /* The pfn is invalid, report the error! */
2684         if (unlikely(is_error_pfn(pfn))) {
2685                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2686                 goto exit;
2687         }
2688 
2689         if (unlikely(is_noslot_pfn(pfn)))
2690                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2691 
2692         ret = false;
2693 exit:
2694         return ret;
2695 }
2696 
2697 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2698 {
2699         /*
2700          * #PF can be fast only if the shadow page table is present and it
2701          * is caused by write-protect, that means we just need change the
2702          * W bit of the spte which can be done out of mmu-lock.
2703          */
2704         if (!(error_code & PFERR_PRESENT_MASK) ||
2705               !(error_code & PFERR_WRITE_MASK))
2706                 return false;
2707 
2708         return true;
2709 }
2710 
2711 static bool
2712 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2713 {
2714         struct kvm_mmu_page *sp = page_header(__pa(sptep));
2715         gfn_t gfn;
2716 
2717         WARN_ON(!sp->role.direct);
2718 
2719         /*
2720          * The gfn of direct spte is stable since it is calculated
2721          * by sp->gfn.
2722          */
2723         gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2724 
2725         if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2726                 mark_page_dirty(vcpu->kvm, gfn);
2727 
2728         return true;
2729 }
2730 
2731 /*
2732  * Return value:
2733  * - true: let the vcpu to access on the same address again.
2734  * - false: let the real page fault path to fix it.
2735  */
2736 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2737                             u32 error_code)
2738 {
2739         struct kvm_shadow_walk_iterator iterator;
2740         bool ret = false;
2741         u64 spte = 0ull;
2742 
2743         if (!page_fault_can_be_fast(vcpu, error_code))
2744                 return false;
2745 
2746         walk_shadow_page_lockless_begin(vcpu);
2747         for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2748                 if (!is_shadow_present_pte(spte) || iterator.level < level)
2749                         break;
2750 
2751         /*
2752          * If the mapping has been changed, let the vcpu fault on the
2753          * same address again.
2754          */
2755         if (!is_rmap_spte(spte)) {
2756                 ret = true;
2757                 goto exit;
2758         }
2759 
2760         if (!is_last_spte(spte, level))
2761                 goto exit;
2762 
2763         /*
2764          * Check if it is a spurious fault caused by TLB lazily flushed.
2765          *
2766          * Need not check the access of upper level table entries since
2767          * they are always ACC_ALL.
2768          */
2769          if (is_writable_pte(spte)) {
2770                 ret = true;
2771                 goto exit;
2772         }
2773 
2774         /*
2775          * Currently, to simplify the code, only the spte write-protected
2776          * by dirty-log can be fast fixed.
2777          */
2778         if (!spte_is_locklessly_modifiable(spte))
2779                 goto exit;
2780 
2781         /*
2782          * Currently, fast page fault only works for direct mapping since
2783          * the gfn is not stable for indirect shadow page.
2784          * See Documentation/virtual/kvm/locking.txt to get more detail.
2785          */
2786         ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2787 exit:
2788         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2789                               spte, ret);
2790         walk_shadow_page_lockless_end(vcpu);
2791 
2792         return ret;
2793 }
2794 
2795 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2796                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2797 
2798 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2799                          gfn_t gfn, bool prefault)
2800 {
2801         int r;
2802         int level;
2803         int force_pt_level;
2804         pfn_t pfn;
2805         unsigned long mmu_seq;
2806         bool map_writable, write = error_code & PFERR_WRITE_MASK;
2807 
2808         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2809         if (likely(!force_pt_level)) {
2810                 level = mapping_level(vcpu, gfn);
2811                 /*
2812                  * This path builds a PAE pagetable - so we can map
2813                  * 2mb pages at maximum. Therefore check if the level
2814                  * is larger than that.
2815                  */
2816                 if (level > PT_DIRECTORY_LEVEL)
2817                         level = PT_DIRECTORY_LEVEL;
2818 
2819                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2820         } else
2821                 level = PT_PAGE_TABLE_LEVEL;
2822 
2823         if (fast_page_fault(vcpu, v, level, error_code))
2824                 return 0;
2825 
2826         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2827         smp_rmb();
2828 
2829         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2830                 return 0;
2831 
2832         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2833                 return r;
2834 
2835         spin_lock(&vcpu->kvm->mmu_lock);
2836         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2837                 goto out_unlock;
2838         kvm_mmu_free_some_pages(vcpu);
2839         if (likely(!force_pt_level))
2840                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2841         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2842                          prefault);
2843         spin_unlock(&vcpu->kvm->mmu_lock);
2844 
2845 
2846         return r;
2847 
2848 out_unlock:
2849         spin_unlock(&vcpu->kvm->mmu_lock);
2850         kvm_release_pfn_clean(pfn);
2851         return 0;
2852 }
2853 
2854 
2855 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2856 {
2857         int i;
2858         struct kvm_mmu_page *sp;
2859         LIST_HEAD(invalid_list);
2860 
2861         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2862                 return;
2863         spin_lock(&vcpu->kvm->mmu_lock);
2864         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2865             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2866              vcpu->arch.mmu.direct_map)) {
2867                 hpa_t root = vcpu->arch.mmu.root_hpa;
2868 
2869                 sp = page_header(root);
2870                 --sp->root_count;
2871                 if (!sp->root_count && sp->role.invalid) {
2872                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2873                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2874                 }
2875                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2876                 spin_unlock(&vcpu->kvm->mmu_lock);
2877                 return;
2878         }
2879         for (i = 0; i < 4; ++i) {
2880                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2881 
2882                 if (root) {
2883                         root &= PT64_BASE_ADDR_MASK;
2884                         sp = page_header(root);
2885                         --sp->root_count;
2886                         if (!sp->root_count && sp->role.invalid)
2887                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2888                                                          &invalid_list);
2889                 }
2890                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2891         }
2892         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2893         spin_unlock(&vcpu->kvm->mmu_lock);
2894         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2895 }
2896 
2897 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2898 {
2899         int ret = 0;
2900 
2901         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2902                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2903                 ret = 1;
2904         }
2905 
2906         return ret;
2907 }
2908 
2909 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2910 {
2911         struct kvm_mmu_page *sp;
2912         unsigned i;
2913 
2914         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2915                 spin_lock(&vcpu->kvm->mmu_lock);
2916                 kvm_mmu_free_some_pages(vcpu);
2917                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2918                                       1, ACC_ALL, NULL);
2919                 ++sp->root_count;
2920                 spin_unlock(&vcpu->kvm->mmu_lock);
2921                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2922         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2923                 for (i = 0; i < 4; ++i) {
2924                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2925 
2926                         ASSERT(!VALID_PAGE(root));
2927                         spin_lock(&vcpu->kvm->mmu_lock);
2928                         kvm_mmu_free_some_pages(vcpu);
2929                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2930                                               i << 30,
2931                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2932                                               NULL);
2933                         root = __pa(sp->spt);
2934                         ++sp->root_count;
2935                         spin_unlock(&vcpu->kvm->mmu_lock);
2936                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2937                 }
2938                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2939         } else
2940                 BUG();
2941 
2942         return 0;
2943 }
2944 
2945 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2946 {
2947         struct kvm_mmu_page *sp;
2948         u64 pdptr, pm_mask;
2949         gfn_t root_gfn;
2950         int i;
2951 
2952         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2953 
2954         if (mmu_check_root(vcpu, root_gfn))
2955                 return 1;
2956 
2957         /*
2958          * Do we shadow a long mode page table? If so we need to
2959          * write-protect the guests page table root.
2960          */
2961         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2962                 hpa_t root = vcpu->arch.mmu.root_hpa;
2963 
2964                 ASSERT(!VALID_PAGE(root));
2965 
2966                 spin_lock(&vcpu->kvm->mmu_lock);
2967                 kvm_mmu_free_some_pages(vcpu);
2968                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2969                                       0, ACC_ALL, NULL);
2970                 root = __pa(sp->spt);
2971                 ++sp->root_count;
2972                 spin_unlock(&vcpu->kvm->mmu_lock);
2973                 vcpu->arch.mmu.root_hpa = root;
2974                 return 0;
2975         }
2976 
2977         /*
2978          * We shadow a 32 bit page table. This may be a legacy 2-level
2979          * or a PAE 3-level page table. In either case we need to be aware that
2980          * the shadow page table may be a PAE or a long mode page table.
2981          */
2982         pm_mask = PT_PRESENT_MASK;
2983         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2984                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2985 
2986         for (i = 0; i < 4; ++i) {
2987                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2988 
2989                 ASSERT(!VALID_PAGE(root));
2990                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2991                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2992                         if (!is_present_gpte(pdptr)) {
2993                                 vcpu->arch.mmu.pae_root[i] = 0;
2994                                 continue;
2995                         }
2996                         root_gfn = pdptr >> PAGE_SHIFT;
2997                         if (mmu_check_root(vcpu, root_gfn))
2998                                 return 1;
2999                 }
3000                 spin_lock(&vcpu->kvm->mmu_lock);
3001                 kvm_mmu_free_some_pages(vcpu);
3002                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3003                                       PT32_ROOT_LEVEL, 0,
3004                                       ACC_ALL, NULL);
3005                 root = __pa(sp->spt);
3006                 ++sp->root_count;
3007                 spin_unlock(&vcpu->kvm->mmu_lock);
3008 
3009                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3010         }
3011         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3012 
3013         /*
3014          * If we shadow a 32 bit page table with a long mode page
3015          * table we enter this path.
3016          */
3017         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3018                 if (vcpu->arch.mmu.lm_root == NULL) {
3019                         /*
3020                          * The additional page necessary for this is only
3021                          * allocated on demand.
3022                          */
3023 
3024                         u64 *lm_root;
3025 
3026                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3027                         if (lm_root == NULL)
3028                                 return 1;
3029 
3030                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3031 
3032                         vcpu->arch.mmu.lm_root = lm_root;
3033                 }
3034 
3035                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3036         }
3037 
3038         return 0;
3039 }
3040 
3041 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3042 {
3043         if (vcpu->arch.mmu.direct_map)
3044                 return mmu_alloc_direct_roots(vcpu);
3045         else
3046                 return mmu_alloc_shadow_roots(vcpu);
3047 }
3048 
3049 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3050 {
3051         int i;
3052         struct kvm_mmu_page *sp;
3053 
3054         if (vcpu->arch.mmu.direct_map)
3055                 return;
3056 
3057         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3058                 return;
3059 
3060         vcpu_clear_mmio_info(vcpu, ~0ul);
3061         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3062         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3063                 hpa_t root = vcpu->arch.mmu.root_hpa;
3064                 sp = page_header(root);
3065                 mmu_sync_children(vcpu, sp);
3066                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3067                 return;
3068         }
3069         for (i = 0; i < 4; ++i) {
3070                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3071 
3072                 if (root && VALID_PAGE(root)) {
3073                         root &= PT64_BASE_ADDR_MASK;
3074                         sp = page_header(root);
3075                         mmu_sync_children(vcpu, sp);
3076                 }
3077         }
3078         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3079 }
3080 
3081 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3082 {
3083         spin_lock(&vcpu->kvm->mmu_lock);
3084         mmu_sync_roots(vcpu);
3085         spin_unlock(&vcpu->kvm->mmu_lock);
3086 }
3087 
3088 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3089                                   u32 access, struct x86_exception *exception)
3090 {
3091         if (exception)
3092                 exception->error_code = 0;
3093         return vaddr;
3094 }
3095 
3096 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3097                                          u32 access,
3098                                          struct x86_exception *exception)
3099 {
3100         if (exception)
3101                 exception->error_code = 0;
3102         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3103 }
3104 
3105 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3106 {
3107         if (direct)
3108                 return vcpu_match_mmio_gpa(vcpu, addr);
3109 
3110         return vcpu_match_mmio_gva(vcpu, addr);
3111 }
3112 
3113 
3114 /*
3115  * On direct hosts, the last spte is only allows two states
3116  * for mmio page fault:
3117  *   - It is the mmio spte
3118  *   - It is zapped or it is being zapped.
3119  *
3120  * This function completely checks the spte when the last spte
3121  * is not the mmio spte.
3122  */
3123 static bool check_direct_spte_mmio_pf(u64 spte)
3124 {
3125         return __check_direct_spte_mmio_pf(spte);
3126 }
3127 
3128 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3129 {
3130         struct kvm_shadow_walk_iterator iterator;
3131         u64 spte = 0ull;
3132 
3133         walk_shadow_page_lockless_begin(vcpu);
3134         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3135                 if (!is_shadow_present_pte(spte))
3136                         break;
3137         walk_shadow_page_lockless_end(vcpu);
3138 
3139         return spte;
3140 }
3141 
3142 /*
3143  * If it is a real mmio page fault, return 1 and emulat the instruction
3144  * directly, return 0 to let CPU fault again on the address, -1 is
3145  * returned if bug is detected.
3146  */
3147 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3148 {
3149         u64 spte;
3150 
3151         if (quickly_check_mmio_pf(vcpu, addr, direct))
3152                 return 1;
3153 
3154         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3155 
3156         if (is_mmio_spte(spte)) {
3157                 gfn_t gfn = get_mmio_spte_gfn(spte);
3158                 unsigned access = get_mmio_spte_access(spte);
3159 
3160                 if (direct)
3161                         addr = 0;
3162 
3163                 trace_handle_mmio_page_fault(addr, gfn, access);
3164                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3165                 return 1;
3166         }
3167 
3168         /*
3169          * It's ok if the gva is remapped by other cpus on shadow guest,
3170          * it's a BUG if the gfn is not a mmio page.
3171          */
3172         if (direct && !check_direct_spte_mmio_pf(spte))
3173                 return -1;
3174 
3175         /*
3176          * If the page table is zapped by other cpus, let CPU fault again on
3177          * the address.
3178          */
3179         return 0;
3180 }
3181 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3182 
3183 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3184                                   u32 error_code, bool direct)
3185 {
3186         int ret;
3187 
3188         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3189         WARN_ON(ret < 0);
3190         return ret;
3191 }
3192 
3193 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3194                                 u32 error_code, bool prefault)
3195 {
3196         gfn_t gfn;
3197         int r;
3198 
3199         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3200 
3201         if (unlikely(error_code & PFERR_RSVD_MASK))
3202                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3203 
3204         r = mmu_topup_memory_caches(vcpu);
3205         if (r)
3206                 return r;
3207 
3208         ASSERT(vcpu);
3209         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3210 
3211         gfn = gva >> PAGE_SHIFT;
3212 
3213         return nonpaging_map(vcpu, gva & PAGE_MASK,
3214                              error_code, gfn, prefault);
3215 }
3216 
3217 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3218 {
3219         struct kvm_arch_async_pf arch;
3220 
3221         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3222         arch.gfn = gfn;
3223         arch.direct_map = vcpu->arch.mmu.direct_map;
3224         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3225 
3226         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3227 }
3228 
3229 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3230 {
3231         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3232                      kvm_event_needs_reinjection(vcpu)))
3233                 return false;
3234 
3235         return kvm_x86_ops->interrupt_allowed(vcpu);
3236 }
3237 
3238 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3239                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3240 {
3241         bool async;
3242 
3243         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3244 
3245         if (!async)
3246                 return false; /* *pfn has correct page already */
3247 
3248         if (!prefault && can_do_async_pf(vcpu)) {
3249                 trace_kvm_try_async_get_page(gva, gfn);
3250                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3251                         trace_kvm_async_pf_doublefault(gva, gfn);
3252                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3253                         return true;
3254                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3255                         return true;
3256         }
3257 
3258         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3259 
3260         return false;
3261 }
3262 
3263 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3264                           bool prefault)
3265 {
3266         pfn_t pfn;
3267         int r;
3268         int level;
3269         int force_pt_level;
3270         gfn_t gfn = gpa >> PAGE_SHIFT;
3271         unsigned long mmu_seq;
3272         int write = error_code & PFERR_WRITE_MASK;
3273         bool map_writable;
3274 
3275         ASSERT(vcpu);
3276         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3277 
3278         if (unlikely(error_code & PFERR_RSVD_MASK))
3279                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3280 
3281         r = mmu_topup_memory_caches(vcpu);
3282         if (r)
3283                 return r;
3284 
3285         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3286         if (likely(!force_pt_level)) {
3287                 level = mapping_level(vcpu, gfn);
3288                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3289         } else
3290                 level = PT_PAGE_TABLE_LEVEL;
3291 
3292         if (fast_page_fault(vcpu, gpa, level, error_code))
3293                 return 0;
3294 
3295         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3296         smp_rmb();
3297 
3298         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3299                 return 0;
3300 
3301         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3302                 return r;
3303 
3304         spin_lock(&vcpu->kvm->mmu_lock);
3305         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3306                 goto out_unlock;
3307         kvm_mmu_free_some_pages(vcpu);
3308         if (likely(!force_pt_level))
3309                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3310         r = __direct_map(vcpu, gpa, write, map_writable,
3311                          level, gfn, pfn, prefault);
3312         spin_unlock(&vcpu->kvm->mmu_lock);
3313 
3314         return r;
3315 
3316 out_unlock:
3317         spin_unlock(&vcpu->kvm->mmu_lock);
3318         kvm_release_pfn_clean(pfn);
3319         return 0;
3320 }
3321 
3322 static void nonpaging_free(struct kvm_vcpu *vcpu)
3323 {
3324         mmu_free_roots(vcpu);
3325 }
3326 
3327 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3328                                   struct kvm_mmu *context)
3329 {
3330         context->new_cr3 = nonpaging_new_cr3;
3331         context->page_fault = nonpaging_page_fault;
3332         context->gva_to_gpa = nonpaging_gva_to_gpa;
3333         context->free = nonpaging_free;
3334         context->sync_page = nonpaging_sync_page;
3335         context->invlpg = nonpaging_invlpg;
3336         context->update_pte = nonpaging_update_pte;
3337         context->root_level = 0;
3338         context->shadow_root_level = PT32E_ROOT_LEVEL;
3339         context->root_hpa = INVALID_PAGE;
3340         context->direct_map = true;
3341         context->nx = false;
3342         return 0;
3343 }
3344 
3345 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3346 {
3347         ++vcpu->stat.tlb_flush;
3348         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3349 }
3350 
3351 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3352 {
3353         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3354         mmu_free_roots(vcpu);
3355 }
3356 
3357 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3358 {
3359         return kvm_read_cr3(vcpu);
3360 }
3361 
3362 static void inject_page_fault(struct kvm_vcpu *vcpu,
3363                               struct x86_exception *fault)
3364 {
3365         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3366 }
3367 
3368 static void paging_free(struct kvm_vcpu *vcpu)
3369 {
3370         nonpaging_free(vcpu);
3371 }
3372 
3373 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3374 {
3375         unsigned mask;
3376 
3377         BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3378 
3379         mask = (unsigned)~ACC_WRITE_MASK;
3380         /* Allow write access to dirty gptes */
3381         mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3382         *access &= mask;
3383 }
3384 
3385 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3386                            int *nr_present)
3387 {
3388         if (unlikely(is_mmio_spte(*sptep))) {
3389                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3390                         mmu_spte_clear_no_track(sptep);
3391                         return true;
3392                 }
3393 
3394                 (*nr_present)++;
3395                 mark_mmio_spte(sptep, gfn, access);
3396                 return true;
3397         }
3398 
3399         return false;
3400 }
3401 
3402 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3403 {
3404         unsigned access;
3405 
3406         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3407         access &= ~(gpte >> PT64_NX_SHIFT);
3408 
3409         return access;
3410 }
3411 
3412 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3413 {
3414         unsigned index;
3415 
3416         index = level - 1;
3417         index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3418         return mmu->last_pte_bitmap & (1 << index);
3419 }
3420 
3421 #define PTTYPE 64
3422 #include "paging_tmpl.h"
3423 #undef PTTYPE
3424 
3425 #define PTTYPE 32
3426 #include "paging_tmpl.h"
3427 #undef PTTYPE
3428 
3429 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3430                                   struct kvm_mmu *context)
3431 {
3432         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3433         u64 exb_bit_rsvd = 0;
3434 
3435         if (!context->nx)
3436                 exb_bit_rsvd = rsvd_bits(63, 63);
3437         switch (context->root_level) {
3438         case PT32_ROOT_LEVEL:
3439                 /* no rsvd bits for 2 level 4K page table entries */
3440                 context->rsvd_bits_mask[0][1] = 0;
3441                 context->rsvd_bits_mask[0][0] = 0;
3442                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3443 
3444                 if (!is_pse(vcpu)) {
3445                         context->rsvd_bits_mask[1][1] = 0;
3446                         break;
3447                 }
3448 
3449                 if (is_cpuid_PSE36())
3450                         /* 36bits PSE 4MB page */
3451                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3452                 else
3453                         /* 32 bits PSE 4MB page */
3454                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3455                 break;
3456         case PT32E_ROOT_LEVEL:
3457                 context->rsvd_bits_mask[0][2] =
3458                         rsvd_bits(maxphyaddr, 63) |
3459                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3460                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3461                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3462                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3463                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3464                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3465                         rsvd_bits(maxphyaddr, 62) |
3466                         rsvd_bits(13, 20);              /* large page */
3467                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3468                 break;
3469         case PT64_ROOT_LEVEL:
3470                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3471                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3472                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3473                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3474                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3475                         rsvd_bits(maxphyaddr, 51);
3476                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3477                         rsvd_bits(maxphyaddr, 51);
3478                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3479                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3480                         rsvd_bits(maxphyaddr, 51) |
3481                         rsvd_bits(13, 29);
3482                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3483                         rsvd_bits(maxphyaddr, 51) |
3484                         rsvd_bits(13, 20);              /* large page */
3485                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3486                 break;
3487         }
3488 }
3489 
3490 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3491 {
3492         unsigned bit, byte, pfec;
3493         u8 map;
3494         bool fault, x, w, u, wf, uf, ff, smep;
3495 
3496         smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3497         for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3498                 pfec = byte << 1;
3499                 map = 0;
3500                 wf = pfec & PFERR_WRITE_MASK;
3501                 uf = pfec & PFERR_USER_MASK;
3502                 ff = pfec & PFERR_FETCH_MASK;
3503                 for (bit = 0; bit < 8; ++bit) {
3504                         x = bit & ACC_EXEC_MASK;
3505                         w = bit & ACC_WRITE_MASK;
3506                         u = bit & ACC_USER_MASK;
3507 
3508                         /* Not really needed: !nx will cause pte.nx to fault */
3509                         x |= !mmu->nx;
3510                         /* Allow supervisor writes if !cr0.wp */
3511                         w |= !is_write_protection(vcpu) && !uf;
3512                         /* Disallow supervisor fetches of user code if cr4.smep */
3513                         x &= !(smep && u && !uf);
3514 
3515                         fault = (ff && !x) || (uf && !u) || (wf && !w);
3516                         map |= fault << bit;
3517                 }
3518                 mmu->permissions[byte] = map;
3519         }
3520 }
3521 
3522 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3523 {
3524         u8 map;
3525         unsigned level, root_level = mmu->root_level;
3526         const unsigned ps_set_index = 1 << 2;  /* bit 2 of index: ps */
3527 
3528         if (root_level == PT32E_ROOT_LEVEL)
3529                 --root_level;
3530         /* PT_PAGE_TABLE_LEVEL always terminates */
3531         map = 1 | (1 << ps_set_index);
3532         for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3533                 if (level <= PT_PDPE_LEVEL
3534                     && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3535                         map |= 1 << (ps_set_index | (level - 1));
3536         }
3537         mmu->last_pte_bitmap = map;
3538 }
3539 
3540 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3541                                         struct kvm_mmu *context,
3542                                         int level)
3543 {
3544         context->nx = is_nx(vcpu);
3545         context->root_level = level;
3546 
3547         reset_rsvds_bits_mask(vcpu, context);
3548         update_permission_bitmask(vcpu, context);
3549         update_last_pte_bitmap(vcpu, context);
3550 
3551         ASSERT(is_pae(vcpu));
3552         context->new_cr3 = paging_new_cr3;
3553         context->page_fault = paging64_page_fault;
3554         context->gva_to_gpa = paging64_gva_to_gpa;
3555         context->sync_page = paging64_sync_page;
3556         context->invlpg = paging64_invlpg;
3557         context->update_pte = paging64_update_pte;
3558         context->free = paging_free;
3559         context->shadow_root_level = level;
3560         context->root_hpa = INVALID_PAGE;
3561         context->direct_map = false;
3562         return 0;
3563 }
3564 
3565 static int paging64_init_context(struct kvm_vcpu *vcpu,
3566                                  struct kvm_mmu *context)
3567 {
3568         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3569 }
3570 
3571 static int paging32_init_context(struct kvm_vcpu *vcpu,
3572                                  struct kvm_mmu *context)
3573 {
3574         context->nx = false;
3575         context->root_level = PT32_ROOT_LEVEL;
3576 
3577         reset_rsvds_bits_mask(vcpu, context);
3578         update_permission_bitmask(vcpu, context);
3579         update_last_pte_bitmap(vcpu, context);
3580 
3581         context->new_cr3 = paging_new_cr3;
3582         context->page_fault = paging32_page_fault;
3583         context->gva_to_gpa = paging32_gva_to_gpa;
3584         context->free = paging_free;
3585         context->sync_page = paging32_sync_page;
3586         context->invlpg = paging32_invlpg;
3587         context->update_pte = paging32_update_pte;
3588         context->shadow_root_level = PT32E_ROOT_LEVEL;
3589         context->root_hpa = INVALID_PAGE;
3590         context->direct_map = false;
3591         return 0;
3592 }
3593 
3594 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3595                                   struct kvm_mmu *context)
3596 {
3597         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3598 }
3599 
3600 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3601 {
3602         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3603 
3604         context->base_role.word = 0;
3605         context->new_cr3 = nonpaging_new_cr3;
3606         context->page_fault = tdp_page_fault;
3607         context->free = nonpaging_free;
3608         context->sync_page = nonpaging_sync_page;
3609         context->invlpg = nonpaging_invlpg;
3610         context->update_pte = nonpaging_update_pte;
3611         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3612         context->root_hpa = INVALID_PAGE;
3613         context->direct_map = true;
3614         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3615         context->get_cr3 = get_cr3;
3616         context->get_pdptr = kvm_pdptr_read;
3617         context->inject_page_fault = kvm_inject_page_fault;
3618 
3619         if (!is_paging(vcpu)) {
3620                 context->nx = false;
3621                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3622                 context->root_level = 0;
3623         } else if (is_long_mode(vcpu)) {
3624                 context->nx = is_nx(vcpu);
3625                 context->root_level = PT64_ROOT_LEVEL;
3626                 reset_rsvds_bits_mask(vcpu, context);
3627                 context->gva_to_gpa = paging64_gva_to_gpa;
3628         } else if (is_pae(vcpu)) {
3629                 context->nx = is_nx(vcpu);
3630                 context->root_level = PT32E_ROOT_LEVEL;
3631                 reset_rsvds_bits_mask(vcpu, context);
3632                 context->gva_to_gpa = paging64_gva_to_gpa;
3633         } else {
3634                 context->nx = false;
3635                 context->root_level = PT32_ROOT_LEVEL;
3636                 reset_rsvds_bits_mask(vcpu, context);
3637                 context->gva_to_gpa = paging32_gva_to_gpa;
3638         }
3639 
3640         update_permission_bitmask(vcpu, context);
3641         update_last_pte_bitmap(vcpu, context);
3642 
3643         return 0;
3644 }
3645 
3646 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3647 {
3648         int r;
3649         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3650         ASSERT(vcpu);
3651         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3652 
3653         if (!is_paging(vcpu))
3654                 r = nonpaging_init_context(vcpu, context);
3655         else if (is_long_mode(vcpu))
3656                 r = paging64_init_context(vcpu, context);
3657         else if (is_pae(vcpu))
3658                 r = paging32E_init_context(vcpu, context);
3659         else
3660                 r = paging32_init_context(vcpu, context);
3661 
3662         vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3663         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3664         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3665         vcpu->arch.mmu.base_role.smep_andnot_wp
3666                 = smep && !is_write_protection(vcpu);
3667 
3668         return r;
3669 }
3670 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3671 
3672 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3673 {
3674         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3675 
3676         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3677         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3678         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3679         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3680 
3681         return r;
3682 }
3683 
3684 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3685 {
3686         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3687 
3688         g_context->get_cr3           = get_cr3;
3689         g_context->get_pdptr         = kvm_pdptr_read;
3690         g_context->inject_page_fault = kvm_inject_page_fault;
3691 
3692         /*
3693          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3694          * translation of l2_gpa to l1_gpa addresses is done using the
3695          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3696          * functions between mmu and nested_mmu are swapped.
3697          */
3698         if (!is_paging(vcpu)) {
3699                 g_context->nx = false;
3700                 g_context->root_level = 0;
3701                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3702         } else if (is_long_mode(vcpu)) {
3703                 g_context->nx = is_nx(vcpu);
3704                 g_context->root_level = PT64_ROOT_LEVEL;
3705                 reset_rsvds_bits_mask(vcpu, g_context);
3706                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3707         } else if (is_pae(vcpu)) {
3708                 g_context->nx = is_nx(vcpu);
3709                 g_context->root_level = PT32E_ROOT_LEVEL;
3710                 reset_rsvds_bits_mask(vcpu, g_context);
3711                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3712         } else {
3713                 g_context->nx = false;
3714                 g_context->root_level = PT32_ROOT_LEVEL;
3715                 reset_rsvds_bits_mask(vcpu, g_context);
3716                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3717         }
3718 
3719         update_permission_bitmask(vcpu, g_context);
3720         update_last_pte_bitmap(vcpu, g_context);
3721 
3722         return 0;
3723 }
3724 
3725 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3726 {
3727         if (mmu_is_nested(vcpu))
3728                 return init_kvm_nested_mmu(vcpu);
3729         else if (tdp_enabled)
3730                 return init_kvm_tdp_mmu(vcpu);
3731         else
3732                 return init_kvm_softmmu(vcpu);
3733 }
3734 
3735 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3736 {
3737         ASSERT(vcpu);
3738         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3739                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3740                 vcpu->arch.mmu.free(vcpu);
3741 }
3742 
3743 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3744 {
3745         destroy_kvm_mmu(vcpu);
3746         return init_kvm_mmu(vcpu);
3747 }
3748 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3749 
3750 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3751 {
3752         int r;
3753 
3754         r = mmu_topup_memory_caches(vcpu);
3755         if (r)
3756                 goto out;
3757         r = mmu_alloc_roots(vcpu);
3758         spin_lock(&vcpu->kvm->mmu_lock);
3759         mmu_sync_roots(vcpu);
3760         spin_unlock(&vcpu->kvm->mmu_lock);
3761         if (r)
3762                 goto out;
3763         /* set_cr3() should ensure TLB has been flushed */
3764         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3765 out:
3766         return r;
3767 }
3768 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3769 
3770 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3771 {
3772         mmu_free_roots(vcpu);
3773 }
3774 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3775 
3776 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3777                                   struct kvm_mmu_page *sp, u64 *spte,
3778                                   const void *new)
3779 {
3780         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3781                 ++vcpu->kvm->stat.mmu_pde_zapped;
3782                 return;
3783         }
3784 
3785         ++vcpu->kvm->stat.mmu_pte_updated;
3786         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3787 }
3788 
3789 static bool need_remote_flush(u64 old, u64 new)
3790 {
3791         if (!is_shadow_present_pte(old))
3792                 return false;
3793         if (!is_shadow_present_pte(new))
3794                 return true;
3795         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3796                 return true;
3797         old ^= PT64_NX_MASK;
3798         new ^= PT64_NX_MASK;
3799         return (old & ~new & PT64_PERM_MASK) != 0;
3800 }
3801 
3802 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3803                                     bool remote_flush, bool local_flush)
3804 {
3805         if (zap_page)
3806                 return;
3807 
3808         if (remote_flush)
3809                 kvm_flush_remote_tlbs(vcpu->kvm);
3810         else if (local_flush)
3811                 kvm_mmu_flush_tlb(vcpu);
3812 }
3813 
3814 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3815                                     const u8 *new, int *bytes)
3816 {
3817         u64 gentry;
3818         int r;
3819 
3820         /*
3821          * Assume that the pte write on a page table of the same type
3822          * as the current vcpu paging mode since we update the sptes only
3823          * when they have the same mode.
3824          */
3825         if (is_pae(vcpu) && *bytes == 4) {
3826                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3827                 *gpa &= ~(gpa_t)7;
3828                 *bytes = 8;
3829                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3830                 if (r)
3831                         gentry = 0;
3832                 new = (const u8 *)&gentry;
3833         }
3834 
3835         switch (*bytes) {
3836         case 4:
3837                 gentry = *(const u32 *)new;
3838                 break;
3839         case 8:
3840                 gentry = *(const u64 *)new;
3841                 break;
3842         default:
3843                 gentry = 0;
3844                 break;
3845         }
3846 
3847         return gentry;
3848 }
3849 
3850 /*
3851  * If we're seeing too many writes to a page, it may no longer be a page table,
3852  * or we may be forking, in which case it is better to unmap the page.
3853  */
3854 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3855 {
3856         /*
3857          * Skip write-flooding detected for the sp whose level is 1, because
3858          * it can become unsync, then the guest page is not write-protected.
3859          */
3860         if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3861                 return false;
3862 
3863         return ++sp->write_flooding_count >= 3;
3864 }
3865 
3866 /*
3867  * Misaligned accesses are too much trouble to fix up; also, they usually
3868  * indicate a page is not used as a page table.
3869  */
3870 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3871                                     int bytes)
3872 {
3873         unsigned offset, pte_size, misaligned;
3874 
3875         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3876                  gpa, bytes, sp->role.word);
3877 
3878         offset = offset_in_page(gpa);
3879         pte_size = sp->role.cr4_pae ? 8 : 4;
3880 
3881         /*
3882          * Sometimes, the OS only writes the last one bytes to update status
3883          * bits, for example, in linux, andb instruction is used in clear_bit().
3884          */
3885         if (!(offset & (pte_size - 1)) && bytes == 1)
3886                 return false;
3887 
3888         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3889         misaligned |= bytes < 4;
3890 
3891         return misaligned;
3892 }
3893 
3894 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3895 {
3896         unsigned page_offset, quadrant;
3897         u64 *spte;
3898         int level;
3899 
3900         page_offset = offset_in_page(gpa);
3901         level = sp->role.level;
3902         *nspte = 1;
3903         if (!sp->role.cr4_pae) {
3904                 page_offset <<= 1;      /* 32->64 */
3905                 /*
3906                  * A 32-bit pde maps 4MB while the shadow pdes map
3907                  * only 2MB.  So we need to double the offset again
3908                  * and zap two pdes instead of one.
3909                  */
3910                 if (level == PT32_ROOT_LEVEL) {
3911                         page_offset &= ~7; /* kill rounding error */
3912                         page_offset <<= 1;
3913                         *nspte = 2;
3914                 }
3915                 quadrant = page_offset >> PAGE_SHIFT;
3916                 page_offset &= ~PAGE_MASK;
3917                 if (quadrant != sp->role.quadrant)
3918                         return NULL;
3919         }
3920 
3921         spte = &sp->spt[page_offset / sizeof(*spte)];
3922         return spte;
3923 }
3924 
3925 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3926                        const u8 *new, int bytes)
3927 {
3928         gfn_t gfn = gpa >> PAGE_SHIFT;
3929         union kvm_mmu_page_role mask = { .word = 0 };
3930         struct kvm_mmu_page *sp;
3931         LIST_HEAD(invalid_list);
3932         u64 entry, gentry, *spte;
3933         int npte;
3934         bool remote_flush, local_flush, zap_page;
3935 
3936         /*
3937          * If we don't have indirect shadow pages, it means no page is
3938          * write-protected, so we can exit simply.
3939          */
3940         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3941                 return;
3942 
3943         zap_page = remote_flush = local_flush = false;
3944 
3945         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3946 
3947         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3948 
3949         /*
3950          * No need to care whether allocation memory is successful
3951          * or not since pte prefetch is skiped if it does not have
3952          * enough objects in the cache.
3953          */
3954         mmu_topup_memory_caches(vcpu);
3955 
3956         spin_lock(&vcpu->kvm->mmu_lock);
3957         ++vcpu->kvm->stat.mmu_pte_write;
3958         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3959 
3960         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3961         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
3962                 if (detect_write_misaligned(sp, gpa, bytes) ||
3963                       detect_write_flooding(sp)) {
3964                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3965                                                      &invalid_list);
3966                         ++vcpu->kvm->stat.mmu_flooded;
3967                         continue;
3968                 }
3969 
3970                 spte = get_written_sptes(sp, gpa, &npte);
3971                 if (!spte)
3972                         continue;
3973 
3974                 local_flush = true;
3975                 while (npte--) {
3976                         entry = *spte;
3977                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3978                         if (gentry &&
3979                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3980                               & mask.word) && rmap_can_add(vcpu))
3981                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3982                         if (need_remote_flush(entry, *spte))
3983                                 remote_flush = true;
3984                         ++spte;
3985                 }
3986         }
3987         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3988         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3989         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3990         spin_unlock(&vcpu->kvm->mmu_lock);
3991 }
3992 
3993 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3994 {
3995         gpa_t gpa;
3996         int r;
3997 
3998         if (vcpu->arch.mmu.direct_map)
3999                 return 0;
4000 
4001         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4002 
4003         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4004 
4005         return r;
4006 }
4007 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4008 
4009 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
4010 {
4011         LIST_HEAD(invalid_list);
4012 
4013         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
4014                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4015                 struct kvm_mmu_page *sp;
4016 
4017                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4018                                   struct kvm_mmu_page, link);
4019                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4020                 ++vcpu->kvm->stat.mmu_recycled;
4021         }
4022         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4023 }
4024 
4025 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4026 {
4027         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4028                 return vcpu_match_mmio_gpa(vcpu, addr);
4029 
4030         return vcpu_match_mmio_gva(vcpu, addr);
4031 }
4032 
4033 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4034                        void *insn, int insn_len)
4035 {
4036         int r, emulation_type = EMULTYPE_RETRY;
4037         enum emulation_result er;
4038 
4039         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4040         if (r < 0)
4041                 goto out;
4042 
4043         if (!r) {
4044                 r = 1;
4045                 goto out;
4046         }
4047 
4048         if (is_mmio_page_fault(vcpu, cr2))
4049                 emulation_type = 0;
4050 
4051         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4052 
4053         switch (er) {
4054         case EMULATE_DONE:
4055                 return 1;
4056         case EMULATE_DO_MMIO:
4057                 ++vcpu->stat.mmio_exits;
4058                 /* fall through */
4059         case EMULATE_FAIL:
4060                 return 0;
4061         default:
4062                 BUG();
4063         }
4064 out:
4065         return r;
4066 }
4067 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4068 
4069 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4070 {
4071         vcpu->arch.mmu.invlpg(vcpu, gva);
4072         kvm_mmu_flush_tlb(vcpu);
4073         ++vcpu->stat.invlpg;
4074 }
4075 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4076 
4077 void kvm_enable_tdp(void)
4078 {
4079         tdp_enabled = true;
4080 }
4081 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4082 
4083 void kvm_disable_tdp(void)
4084 {
4085         tdp_enabled = false;
4086 }
4087 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4088 
4089 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4090 {
4091         free_page((unsigned long)vcpu->arch.mmu.pae_root);
4092         if (vcpu->arch.mmu.lm_root != NULL)
4093                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4094 }
4095 
4096 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4097 {
4098         struct page *page;
4099         int i;
4100 
4101         ASSERT(vcpu);
4102 
4103         /*
4104          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4105          * Therefore we need to allocate shadow page tables in the first
4106          * 4GB of memory, which happens to fit the DMA32 zone.
4107          */
4108         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4109         if (!page)
4110                 return -ENOMEM;
4111 
4112         vcpu->arch.mmu.pae_root = page_address(page);
4113         for (i = 0; i < 4; ++i)
4114                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4115 
4116         return 0;
4117 }
4118 
4119 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4120 {
4121         ASSERT(vcpu);
4122 
4123         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4124         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4125         vcpu->arch.mmu.translate_gpa = translate_gpa;
4126         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4127 
4128         return alloc_mmu_pages(vcpu);
4129 }
4130 
4131 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4132 {
4133         ASSERT(vcpu);
4134         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4135 
4136         return init_kvm_mmu(vcpu);
4137 }
4138 
4139 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4140 {
4141         struct kvm_memory_slot *memslot;
4142         gfn_t last_gfn;
4143         int i;
4144 
4145         memslot = id_to_memslot(kvm->memslots, slot);
4146         last_gfn = memslot->base_gfn + memslot->npages - 1;
4147 
4148         spin_lock(&kvm->mmu_lock);
4149 
4150         for (i = PT_PAGE_TABLE_LEVEL;
4151              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4152                 unsigned long *rmapp;
4153                 unsigned long last_index, index;
4154 
4155                 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4156                 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4157 
4158                 for (index = 0; index <= last_index; ++index, ++rmapp) {
4159                         if (*rmapp)
4160                                 __rmap_write_protect(kvm, rmapp, false);
4161 
4162                         if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4163                                 kvm_flush_remote_tlbs(kvm);
4164                                 cond_resched_lock(&kvm->mmu_lock);
4165                         }
4166                 }
4167         }
4168 
4169         kvm_flush_remote_tlbs(kvm);
4170         spin_unlock(&kvm->mmu_lock);
4171 }
4172 
4173 void kvm_mmu_zap_all(struct kvm *kvm)
4174 {
4175         struct kvm_mmu_page *sp, *node;
4176         LIST_HEAD(invalid_list);
4177 
4178         spin_lock(&kvm->mmu_lock);
4179 restart:
4180         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4181                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4182                         goto restart;
4183 
4184         kvm_mmu_commit_zap_page(kvm, &invalid_list);
4185         spin_unlock(&kvm->mmu_lock);
4186 }
4187 
4188 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4189                                                 struct list_head *invalid_list)
4190 {
4191         struct kvm_mmu_page *page;
4192 
4193         if (list_empty(&kvm->arch.active_mmu_pages))
4194                 return;
4195 
4196         page = container_of(kvm->arch.active_mmu_pages.prev,
4197                             struct kvm_mmu_page, link);
4198         kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4199 }
4200 
4201 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4202 {
4203         struct kvm *kvm;
4204         int nr_to_scan = sc->nr_to_scan;
4205 
4206         if (nr_to_scan == 0)
4207                 goto out;
4208 
4209         raw_spin_lock(&kvm_lock);
4210 
4211         list_for_each_entry(kvm, &vm_list, vm_list) {
4212                 int idx;
4213                 LIST_HEAD(invalid_list);
4214 
4215                 /*
4216                  * Never scan more than sc->nr_to_scan VM instances.
4217                  * Will not hit this condition practically since we do not try
4218                  * to shrink more than one VM and it is very unlikely to see
4219                  * !n_used_mmu_pages so many times.
4220                  */
4221                 if (!nr_to_scan--)
4222                         break;
4223                 /*
4224                  * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4225                  * here. We may skip a VM instance errorneosly, but we do not
4226                  * want to shrink a VM that only started to populate its MMU
4227                  * anyway.
4228                  */
4229                 if (!kvm->arch.n_used_mmu_pages)
4230                         continue;
4231 
4232                 idx = srcu_read_lock(&kvm->srcu);
4233                 spin_lock(&kvm->mmu_lock);
4234 
4235                 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4236                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4237 
4238                 spin_unlock(&kvm->mmu_lock);
4239                 srcu_read_unlock(&kvm->srcu, idx);
4240 
4241                 list_move_tail(&kvm->vm_list, &vm_list);
4242                 break;
4243         }
4244 
4245         raw_spin_unlock(&kvm_lock);
4246 
4247 out:
4248         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4249 }
4250 
4251 static struct shrinker mmu_shrinker = {
4252         .shrink = mmu_shrink,
4253         .seeks = DEFAULT_SEEKS * 10,
4254 };
4255 
4256 static void mmu_destroy_caches(void)
4257 {
4258         if (pte_list_desc_cache)
4259                 kmem_cache_destroy(pte_list_desc_cache);
4260         if (mmu_page_header_cache)
4261                 kmem_cache_destroy(mmu_page_header_cache);
4262 }
4263 
4264 int kvm_mmu_module_init(void)
4265 {
4266         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4267                                             sizeof(struct pte_list_desc),
4268                                             0, 0, NULL);
4269         if (!pte_list_desc_cache)
4270                 goto nomem;
4271 
4272         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4273                                                   sizeof(struct kvm_mmu_page),
4274                                                   0, 0, NULL);
4275         if (!mmu_page_header_cache)
4276                 goto nomem;
4277 
4278         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4279                 goto nomem;
4280 
4281         register_shrinker(&mmu_shrinker);
4282 
4283         return 0;
4284 
4285 nomem:
4286         mmu_destroy_caches();
4287         return -ENOMEM;
4288 }
4289 
4290 /*
4291  * Caculate mmu pages needed for kvm.
4292  */
4293 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4294 {
4295         unsigned int nr_mmu_pages;
4296         unsigned int  nr_pages = 0;
4297         struct kvm_memslots *slots;
4298         struct kvm_memory_slot *memslot;
4299 
4300         slots = kvm_memslots(kvm);
4301 
4302         kvm_for_each_memslot(memslot, slots)
4303                 nr_pages += memslot->npages;
4304 
4305         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4306         nr_mmu_pages = max(nr_mmu_pages,
4307                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4308 
4309         return nr_mmu_pages;
4310 }
4311 
4312 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4313 {
4314         struct kvm_shadow_walk_iterator iterator;
4315         u64 spte;
4316         int nr_sptes = 0;
4317 
4318         walk_shadow_page_lockless_begin(vcpu);
4319         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4320                 sptes[iterator.level-1] = spte;
4321                 nr_sptes++;
4322                 if (!is_shadow_present_pte(spte))
4323                         break;
4324         }
4325         walk_shadow_page_lockless_end(vcpu);
4326 
4327         return nr_sptes;
4328 }
4329 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4330 
4331 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4332 {
4333         ASSERT(vcpu);
4334 
4335         destroy_kvm_mmu(vcpu);
4336         free_mmu_pages(vcpu);
4337         mmu_free_memory_caches(vcpu);
4338 }
4339 
4340 void kvm_mmu_module_exit(void)
4341 {
4342         mmu_destroy_caches();
4343         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4344         unregister_shrinker(&mmu_shrinker);
4345         mmu_audit_disable();
4346 }
4347 

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