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Linux/arch/x86/kvm/mmu.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * MMU support
  8  *
  9  * Copyright (C) 2006 Qumranet, Inc.
 10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 11  *
 12  * Authors:
 13  *   Yaniv Kamay  <yaniv@qumranet.com>
 14  *   Avi Kivity   <avi@qumranet.com>
 15  *
 16  * This work is licensed under the terms of the GNU GPL, version 2.  See
 17  * the COPYING file in the top-level directory.
 18  *
 19  */
 20 
 21 #include "irq.h"
 22 #include "mmu.h"
 23 #include "x86.h"
 24 #include "kvm_cache_regs.h"
 25 #include "cpuid.h"
 26 
 27 #include <linux/kvm_host.h>
 28 #include <linux/types.h>
 29 #include <linux/string.h>
 30 #include <linux/mm.h>
 31 #include <linux/highmem.h>
 32 #include <linux/moduleparam.h>
 33 #include <linux/export.h>
 34 #include <linux/swap.h>
 35 #include <linux/hugetlb.h>
 36 #include <linux/compiler.h>
 37 #include <linux/srcu.h>
 38 #include <linux/slab.h>
 39 #include <linux/sched/signal.h>
 40 #include <linux/uaccess.h>
 41 #include <linux/hash.h>
 42 #include <linux/kern_levels.h>
 43 
 44 #include <asm/page.h>
 45 #include <asm/pat.h>
 46 #include <asm/cmpxchg.h>
 47 #include <asm/io.h>
 48 #include <asm/vmx.h>
 49 #include <asm/kvm_page_track.h>
 50 #include "trace.h"
 51 
 52 /*
 53  * When setting this variable to true it enables Two-Dimensional-Paging
 54  * where the hardware walks 2 page tables:
 55  * 1. the guest-virtual to guest-physical
 56  * 2. while doing 1. it walks guest-physical to host-physical
 57  * If the hardware supports that we don't need to do shadow paging.
 58  */
 59 bool tdp_enabled = false;
 60 
 61 enum {
 62         AUDIT_PRE_PAGE_FAULT,
 63         AUDIT_POST_PAGE_FAULT,
 64         AUDIT_PRE_PTE_WRITE,
 65         AUDIT_POST_PTE_WRITE,
 66         AUDIT_PRE_SYNC,
 67         AUDIT_POST_SYNC
 68 };
 69 
 70 #undef MMU_DEBUG
 71 
 72 #ifdef MMU_DEBUG
 73 static bool dbg = 0;
 74 module_param(dbg, bool, 0644);
 75 
 76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
 77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
 78 #define MMU_WARN_ON(x) WARN_ON(x)
 79 #else
 80 #define pgprintk(x...) do { } while (0)
 81 #define rmap_printk(x...) do { } while (0)
 82 #define MMU_WARN_ON(x) do { } while (0)
 83 #endif
 84 
 85 #define PTE_PREFETCH_NUM                8
 86 
 87 #define PT_FIRST_AVAIL_BITS_SHIFT 10
 88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 89 
 90 #define PT64_LEVEL_BITS 9
 91 
 92 #define PT64_LEVEL_SHIFT(level) \
 93                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
 94 
 95 #define PT64_INDEX(address, level)\
 96         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
 97 
 98 
 99 #define PT32_LEVEL_BITS 10
100 
101 #define PT32_LEVEL_SHIFT(level) \
102                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
103 
104 #define PT32_LVL_OFFSET_MASK(level) \
105         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
106                                                 * PT32_LEVEL_BITS))) - 1))
107 
108 #define PT32_INDEX(address, level)\
109         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
110 
111 
112 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
113 #define PT64_DIR_BASE_ADDR_MASK \
114         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
115 #define PT64_LVL_ADDR_MASK(level) \
116         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
117                                                 * PT64_LEVEL_BITS))) - 1))
118 #define PT64_LVL_OFFSET_MASK(level) \
119         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
120                                                 * PT64_LEVEL_BITS))) - 1))
121 
122 #define PT32_BASE_ADDR_MASK PAGE_MASK
123 #define PT32_DIR_BASE_ADDR_MASK \
124         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
125 #define PT32_LVL_ADDR_MASK(level) \
126         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127                                             * PT32_LEVEL_BITS))) - 1))
128 
129 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
130                         | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
131 
132 #define ACC_EXEC_MASK    1
133 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
134 #define ACC_USER_MASK    PT_USER_MASK
135 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
136 
137 /* The mask for the R/X bits in EPT PTEs */
138 #define PT64_EPT_READABLE_MASK                  0x1ull
139 #define PT64_EPT_EXECUTABLE_MASK                0x4ull
140 
141 #include <trace/events/kvm.h>
142 
143 #define CREATE_TRACE_POINTS
144 #include "mmutrace.h"
145 
146 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
147 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
148 
149 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
150 
151 /* make pte_list_desc fit well in cache line */
152 #define PTE_LIST_EXT 3
153 
154 /*
155  * Return values of handle_mmio_page_fault and mmu.page_fault:
156  * RET_PF_RETRY: let CPU fault again on the address.
157  * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
158  *
159  * For handle_mmio_page_fault only:
160  * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
161  */
162 enum {
163         RET_PF_RETRY = 0,
164         RET_PF_EMULATE = 1,
165         RET_PF_INVALID = 2,
166 };
167 
168 struct pte_list_desc {
169         u64 *sptes[PTE_LIST_EXT];
170         struct pte_list_desc *more;
171 };
172 
173 struct kvm_shadow_walk_iterator {
174         u64 addr;
175         hpa_t shadow_addr;
176         u64 *sptep;
177         int level;
178         unsigned index;
179 };
180 
181 static const union kvm_mmu_page_role mmu_base_role_mask = {
182         .cr0_wp = 1,
183         .cr4_pae = 1,
184         .nxe = 1,
185         .smep_andnot_wp = 1,
186         .smap_andnot_wp = 1,
187         .smm = 1,
188         .guest_mode = 1,
189         .ad_disabled = 1,
190 };
191 
192 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker)     \
193         for (shadow_walk_init_using_root(&(_walker), (_vcpu),              \
194                                          (_root), (_addr));                \
195              shadow_walk_okay(&(_walker));                                 \
196              shadow_walk_next(&(_walker)))
197 
198 #define for_each_shadow_entry(_vcpu, _addr, _walker)            \
199         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
200              shadow_walk_okay(&(_walker));                      \
201              shadow_walk_next(&(_walker)))
202 
203 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
204         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
205              shadow_walk_okay(&(_walker)) &&                            \
206                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
207              __shadow_walk_next(&(_walker), spte))
208 
209 static struct kmem_cache *pte_list_desc_cache;
210 static struct kmem_cache *mmu_page_header_cache;
211 static struct percpu_counter kvm_total_used_mmu_pages;
212 
213 static u64 __read_mostly shadow_nx_mask;
214 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
215 static u64 __read_mostly shadow_user_mask;
216 static u64 __read_mostly shadow_accessed_mask;
217 static u64 __read_mostly shadow_dirty_mask;
218 static u64 __read_mostly shadow_mmio_mask;
219 static u64 __read_mostly shadow_mmio_value;
220 static u64 __read_mostly shadow_present_mask;
221 static u64 __read_mostly shadow_me_mask;
222 
223 /*
224  * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
225  * Non-present SPTEs with shadow_acc_track_value set are in place for access
226  * tracking.
227  */
228 static u64 __read_mostly shadow_acc_track_mask;
229 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
230 
231 /*
232  * The mask/shift to use for saving the original R/X bits when marking the PTE
233  * as not-present for access tracking purposes. We do not save the W bit as the
234  * PTEs being access tracked also need to be dirty tracked, so the W bit will be
235  * restored only when a write is attempted to the page.
236  */
237 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
238                                                     PT64_EPT_EXECUTABLE_MASK;
239 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
240 
241 /*
242  * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
243  * to guard against L1TF attacks.
244  */
245 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
246 
247 /*
248  * The number of high-order 1 bits to use in the mask above.
249  */
250 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
251 
252 /*
253  * In some cases, we need to preserve the GFN of a non-present or reserved
254  * SPTE when we usurp the upper five bits of the physical address space to
255  * defend against L1TF, e.g. for MMIO SPTEs.  To preserve the GFN, we'll
256  * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
257  * left into the reserved bits, i.e. the GFN in the SPTE will be split into
258  * high and low parts.  This mask covers the lower bits of the GFN.
259  */
260 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
261 
262 
263 static void mmu_spte_set(u64 *sptep, u64 spte);
264 static union kvm_mmu_page_role
265 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
266 
267 
268 static inline bool kvm_available_flush_tlb_with_range(void)
269 {
270         return kvm_x86_ops->tlb_remote_flush_with_range;
271 }
272 
273 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
274                 struct kvm_tlb_range *range)
275 {
276         int ret = -ENOTSUPP;
277 
278         if (range && kvm_x86_ops->tlb_remote_flush_with_range)
279                 ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range);
280 
281         if (ret)
282                 kvm_flush_remote_tlbs(kvm);
283 }
284 
285 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
286                 u64 start_gfn, u64 pages)
287 {
288         struct kvm_tlb_range range;
289 
290         range.start_gfn = start_gfn;
291         range.pages = pages;
292 
293         kvm_flush_remote_tlbs_with_range(kvm, &range);
294 }
295 
296 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
297 {
298         BUG_ON((mmio_mask & mmio_value) != mmio_value);
299         shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
300         shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
301 }
302 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
303 
304 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
305 {
306         return sp->role.ad_disabled;
307 }
308 
309 static inline bool spte_ad_enabled(u64 spte)
310 {
311         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
312         return !(spte & shadow_acc_track_value);
313 }
314 
315 static inline u64 spte_shadow_accessed_mask(u64 spte)
316 {
317         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
318         return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
319 }
320 
321 static inline u64 spte_shadow_dirty_mask(u64 spte)
322 {
323         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
324         return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
325 }
326 
327 static inline bool is_access_track_spte(u64 spte)
328 {
329         return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
330 }
331 
332 /*
333  * the low bit of the generation number is always presumed to be zero.
334  * This disables mmio caching during memslot updates.  The concept is
335  * similar to a seqcount but instead of retrying the access we just punt
336  * and ignore the cache.
337  *
338  * spte bits 3-11 are used as bits 1-9 of the generation number,
339  * the bits 52-61 are used as bits 10-19 of the generation number.
340  */
341 #define MMIO_SPTE_GEN_LOW_SHIFT         2
342 #define MMIO_SPTE_GEN_HIGH_SHIFT        52
343 
344 #define MMIO_GEN_SHIFT                  20
345 #define MMIO_GEN_LOW_SHIFT              10
346 #define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 2)
347 #define MMIO_GEN_MASK                   ((1 << MMIO_GEN_SHIFT) - 1)
348 
349 static u64 generation_mmio_spte_mask(unsigned int gen)
350 {
351         u64 mask;
352 
353         WARN_ON(gen & ~MMIO_GEN_MASK);
354 
355         mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
356         mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
357         return mask;
358 }
359 
360 static unsigned int get_mmio_spte_generation(u64 spte)
361 {
362         unsigned int gen;
363 
364         spte &= ~shadow_mmio_mask;
365 
366         gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
367         gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
368         return gen;
369 }
370 
371 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
372 {
373         return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
374 }
375 
376 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
377                            unsigned access)
378 {
379         unsigned int gen = kvm_current_mmio_generation(vcpu);
380         u64 mask = generation_mmio_spte_mask(gen);
381         u64 gpa = gfn << PAGE_SHIFT;
382 
383         access &= ACC_WRITE_MASK | ACC_USER_MASK;
384         mask |= shadow_mmio_value | access;
385         mask |= gpa | shadow_nonpresent_or_rsvd_mask;
386         mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
387                 << shadow_nonpresent_or_rsvd_mask_len;
388 
389         trace_mark_mmio_spte(sptep, gfn, access, gen);
390         mmu_spte_set(sptep, mask);
391 }
392 
393 static bool is_mmio_spte(u64 spte)
394 {
395         return (spte & shadow_mmio_mask) == shadow_mmio_value;
396 }
397 
398 static gfn_t get_mmio_spte_gfn(u64 spte)
399 {
400         u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
401 
402         gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
403                & shadow_nonpresent_or_rsvd_mask;
404 
405         return gpa >> PAGE_SHIFT;
406 }
407 
408 static unsigned get_mmio_spte_access(u64 spte)
409 {
410         u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
411         return (spte & ~mask) & ~PAGE_MASK;
412 }
413 
414 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
415                           kvm_pfn_t pfn, unsigned access)
416 {
417         if (unlikely(is_noslot_pfn(pfn))) {
418                 mark_mmio_spte(vcpu, sptep, gfn, access);
419                 return true;
420         }
421 
422         return false;
423 }
424 
425 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
426 {
427         unsigned int kvm_gen, spte_gen;
428 
429         kvm_gen = kvm_current_mmio_generation(vcpu);
430         spte_gen = get_mmio_spte_generation(spte);
431 
432         trace_check_mmio_spte(spte, kvm_gen, spte_gen);
433         return likely(kvm_gen == spte_gen);
434 }
435 
436 /*
437  * Sets the shadow PTE masks used by the MMU.
438  *
439  * Assumptions:
440  *  - Setting either @accessed_mask or @dirty_mask requires setting both
441  *  - At least one of @accessed_mask or @acc_track_mask must be set
442  */
443 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
444                 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
445                 u64 acc_track_mask, u64 me_mask)
446 {
447         BUG_ON(!dirty_mask != !accessed_mask);
448         BUG_ON(!accessed_mask && !acc_track_mask);
449         BUG_ON(acc_track_mask & shadow_acc_track_value);
450 
451         shadow_user_mask = user_mask;
452         shadow_accessed_mask = accessed_mask;
453         shadow_dirty_mask = dirty_mask;
454         shadow_nx_mask = nx_mask;
455         shadow_x_mask = x_mask;
456         shadow_present_mask = p_mask;
457         shadow_acc_track_mask = acc_track_mask;
458         shadow_me_mask = me_mask;
459 }
460 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
461 
462 static void kvm_mmu_reset_all_pte_masks(void)
463 {
464         u8 low_phys_bits;
465 
466         shadow_user_mask = 0;
467         shadow_accessed_mask = 0;
468         shadow_dirty_mask = 0;
469         shadow_nx_mask = 0;
470         shadow_x_mask = 0;
471         shadow_mmio_mask = 0;
472         shadow_present_mask = 0;
473         shadow_acc_track_mask = 0;
474 
475         /*
476          * If the CPU has 46 or less physical address bits, then set an
477          * appropriate mask to guard against L1TF attacks. Otherwise, it is
478          * assumed that the CPU is not vulnerable to L1TF.
479          */
480         low_phys_bits = boot_cpu_data.x86_phys_bits;
481         if (boot_cpu_data.x86_phys_bits <
482             52 - shadow_nonpresent_or_rsvd_mask_len) {
483                 shadow_nonpresent_or_rsvd_mask =
484                         rsvd_bits(boot_cpu_data.x86_phys_bits -
485                                   shadow_nonpresent_or_rsvd_mask_len,
486                                   boot_cpu_data.x86_phys_bits - 1);
487                 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
488         }
489         shadow_nonpresent_or_rsvd_lower_gfn_mask =
490                 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
491 }
492 
493 static int is_cpuid_PSE36(void)
494 {
495         return 1;
496 }
497 
498 static int is_nx(struct kvm_vcpu *vcpu)
499 {
500         return vcpu->arch.efer & EFER_NX;
501 }
502 
503 static int is_shadow_present_pte(u64 pte)
504 {
505         return (pte != 0) && !is_mmio_spte(pte);
506 }
507 
508 static int is_large_pte(u64 pte)
509 {
510         return pte & PT_PAGE_SIZE_MASK;
511 }
512 
513 static int is_last_spte(u64 pte, int level)
514 {
515         if (level == PT_PAGE_TABLE_LEVEL)
516                 return 1;
517         if (is_large_pte(pte))
518                 return 1;
519         return 0;
520 }
521 
522 static bool is_executable_pte(u64 spte)
523 {
524         return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
525 }
526 
527 static kvm_pfn_t spte_to_pfn(u64 pte)
528 {
529         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
530 }
531 
532 static gfn_t pse36_gfn_delta(u32 gpte)
533 {
534         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
535 
536         return (gpte & PT32_DIR_PSE36_MASK) << shift;
537 }
538 
539 #ifdef CONFIG_X86_64
540 static void __set_spte(u64 *sptep, u64 spte)
541 {
542         WRITE_ONCE(*sptep, spte);
543 }
544 
545 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
546 {
547         WRITE_ONCE(*sptep, spte);
548 }
549 
550 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
551 {
552         return xchg(sptep, spte);
553 }
554 
555 static u64 __get_spte_lockless(u64 *sptep)
556 {
557         return READ_ONCE(*sptep);
558 }
559 #else
560 union split_spte {
561         struct {
562                 u32 spte_low;
563                 u32 spte_high;
564         };
565         u64 spte;
566 };
567 
568 static void count_spte_clear(u64 *sptep, u64 spte)
569 {
570         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
571 
572         if (is_shadow_present_pte(spte))
573                 return;
574 
575         /* Ensure the spte is completely set before we increase the count */
576         smp_wmb();
577         sp->clear_spte_count++;
578 }
579 
580 static void __set_spte(u64 *sptep, u64 spte)
581 {
582         union split_spte *ssptep, sspte;
583 
584         ssptep = (union split_spte *)sptep;
585         sspte = (union split_spte)spte;
586 
587         ssptep->spte_high = sspte.spte_high;
588 
589         /*
590          * If we map the spte from nonpresent to present, We should store
591          * the high bits firstly, then set present bit, so cpu can not
592          * fetch this spte while we are setting the spte.
593          */
594         smp_wmb();
595 
596         WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
597 }
598 
599 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
600 {
601         union split_spte *ssptep, sspte;
602 
603         ssptep = (union split_spte *)sptep;
604         sspte = (union split_spte)spte;
605 
606         WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
607 
608         /*
609          * If we map the spte from present to nonpresent, we should clear
610          * present bit firstly to avoid vcpu fetch the old high bits.
611          */
612         smp_wmb();
613 
614         ssptep->spte_high = sspte.spte_high;
615         count_spte_clear(sptep, spte);
616 }
617 
618 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
619 {
620         union split_spte *ssptep, sspte, orig;
621 
622         ssptep = (union split_spte *)sptep;
623         sspte = (union split_spte)spte;
624 
625         /* xchg acts as a barrier before the setting of the high bits */
626         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
627         orig.spte_high = ssptep->spte_high;
628         ssptep->spte_high = sspte.spte_high;
629         count_spte_clear(sptep, spte);
630 
631         return orig.spte;
632 }
633 
634 /*
635  * The idea using the light way get the spte on x86_32 guest is from
636  * gup_get_pte(arch/x86/mm/gup.c).
637  *
638  * An spte tlb flush may be pending, because kvm_set_pte_rmapp
639  * coalesces them and we are running out of the MMU lock.  Therefore
640  * we need to protect against in-progress updates of the spte.
641  *
642  * Reading the spte while an update is in progress may get the old value
643  * for the high part of the spte.  The race is fine for a present->non-present
644  * change (because the high part of the spte is ignored for non-present spte),
645  * but for a present->present change we must reread the spte.
646  *
647  * All such changes are done in two steps (present->non-present and
648  * non-present->present), hence it is enough to count the number of
649  * present->non-present updates: if it changed while reading the spte,
650  * we might have hit the race.  This is done using clear_spte_count.
651  */
652 static u64 __get_spte_lockless(u64 *sptep)
653 {
654         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
655         union split_spte spte, *orig = (union split_spte *)sptep;
656         int count;
657 
658 retry:
659         count = sp->clear_spte_count;
660         smp_rmb();
661 
662         spte.spte_low = orig->spte_low;
663         smp_rmb();
664 
665         spte.spte_high = orig->spte_high;
666         smp_rmb();
667 
668         if (unlikely(spte.spte_low != orig->spte_low ||
669               count != sp->clear_spte_count))
670                 goto retry;
671 
672         return spte.spte;
673 }
674 #endif
675 
676 static bool spte_can_locklessly_be_made_writable(u64 spte)
677 {
678         return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
679                 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
680 }
681 
682 static bool spte_has_volatile_bits(u64 spte)
683 {
684         if (!is_shadow_present_pte(spte))
685                 return false;
686 
687         /*
688          * Always atomically update spte if it can be updated
689          * out of mmu-lock, it can ensure dirty bit is not lost,
690          * also, it can help us to get a stable is_writable_pte()
691          * to ensure tlb flush is not missed.
692          */
693         if (spte_can_locklessly_be_made_writable(spte) ||
694             is_access_track_spte(spte))
695                 return true;
696 
697         if (spte_ad_enabled(spte)) {
698                 if ((spte & shadow_accessed_mask) == 0 ||
699                     (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
700                         return true;
701         }
702 
703         return false;
704 }
705 
706 static bool is_accessed_spte(u64 spte)
707 {
708         u64 accessed_mask = spte_shadow_accessed_mask(spte);
709 
710         return accessed_mask ? spte & accessed_mask
711                              : !is_access_track_spte(spte);
712 }
713 
714 static bool is_dirty_spte(u64 spte)
715 {
716         u64 dirty_mask = spte_shadow_dirty_mask(spte);
717 
718         return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
719 }
720 
721 /* Rules for using mmu_spte_set:
722  * Set the sptep from nonpresent to present.
723  * Note: the sptep being assigned *must* be either not present
724  * or in a state where the hardware will not attempt to update
725  * the spte.
726  */
727 static void mmu_spte_set(u64 *sptep, u64 new_spte)
728 {
729         WARN_ON(is_shadow_present_pte(*sptep));
730         __set_spte(sptep, new_spte);
731 }
732 
733 /*
734  * Update the SPTE (excluding the PFN), but do not track changes in its
735  * accessed/dirty status.
736  */
737 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
738 {
739         u64 old_spte = *sptep;
740 
741         WARN_ON(!is_shadow_present_pte(new_spte));
742 
743         if (!is_shadow_present_pte(old_spte)) {
744                 mmu_spte_set(sptep, new_spte);
745                 return old_spte;
746         }
747 
748         if (!spte_has_volatile_bits(old_spte))
749                 __update_clear_spte_fast(sptep, new_spte);
750         else
751                 old_spte = __update_clear_spte_slow(sptep, new_spte);
752 
753         WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
754 
755         return old_spte;
756 }
757 
758 /* Rules for using mmu_spte_update:
759  * Update the state bits, it means the mapped pfn is not changed.
760  *
761  * Whenever we overwrite a writable spte with a read-only one we
762  * should flush remote TLBs. Otherwise rmap_write_protect
763  * will find a read-only spte, even though the writable spte
764  * might be cached on a CPU's TLB, the return value indicates this
765  * case.
766  *
767  * Returns true if the TLB needs to be flushed
768  */
769 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
770 {
771         bool flush = false;
772         u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
773 
774         if (!is_shadow_present_pte(old_spte))
775                 return false;
776 
777         /*
778          * For the spte updated out of mmu-lock is safe, since
779          * we always atomically update it, see the comments in
780          * spte_has_volatile_bits().
781          */
782         if (spte_can_locklessly_be_made_writable(old_spte) &&
783               !is_writable_pte(new_spte))
784                 flush = true;
785 
786         /*
787          * Flush TLB when accessed/dirty states are changed in the page tables,
788          * to guarantee consistency between TLB and page tables.
789          */
790 
791         if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
792                 flush = true;
793                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
794         }
795 
796         if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
797                 flush = true;
798                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
799         }
800 
801         return flush;
802 }
803 
804 /*
805  * Rules for using mmu_spte_clear_track_bits:
806  * It sets the sptep from present to nonpresent, and track the
807  * state bits, it is used to clear the last level sptep.
808  * Returns non-zero if the PTE was previously valid.
809  */
810 static int mmu_spte_clear_track_bits(u64 *sptep)
811 {
812         kvm_pfn_t pfn;
813         u64 old_spte = *sptep;
814 
815         if (!spte_has_volatile_bits(old_spte))
816                 __update_clear_spte_fast(sptep, 0ull);
817         else
818                 old_spte = __update_clear_spte_slow(sptep, 0ull);
819 
820         if (!is_shadow_present_pte(old_spte))
821                 return 0;
822 
823         pfn = spte_to_pfn(old_spte);
824 
825         /*
826          * KVM does not hold the refcount of the page used by
827          * kvm mmu, before reclaiming the page, we should
828          * unmap it from mmu first.
829          */
830         WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
831 
832         if (is_accessed_spte(old_spte))
833                 kvm_set_pfn_accessed(pfn);
834 
835         if (is_dirty_spte(old_spte))
836                 kvm_set_pfn_dirty(pfn);
837 
838         return 1;
839 }
840 
841 /*
842  * Rules for using mmu_spte_clear_no_track:
843  * Directly clear spte without caring the state bits of sptep,
844  * it is used to set the upper level spte.
845  */
846 static void mmu_spte_clear_no_track(u64 *sptep)
847 {
848         __update_clear_spte_fast(sptep, 0ull);
849 }
850 
851 static u64 mmu_spte_get_lockless(u64 *sptep)
852 {
853         return __get_spte_lockless(sptep);
854 }
855 
856 static u64 mark_spte_for_access_track(u64 spte)
857 {
858         if (spte_ad_enabled(spte))
859                 return spte & ~shadow_accessed_mask;
860 
861         if (is_access_track_spte(spte))
862                 return spte;
863 
864         /*
865          * Making an Access Tracking PTE will result in removal of write access
866          * from the PTE. So, verify that we will be able to restore the write
867          * access in the fast page fault path later on.
868          */
869         WARN_ONCE((spte & PT_WRITABLE_MASK) &&
870                   !spte_can_locklessly_be_made_writable(spte),
871                   "kvm: Writable SPTE is not locklessly dirty-trackable\n");
872 
873         WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
874                           shadow_acc_track_saved_bits_shift),
875                   "kvm: Access Tracking saved bit locations are not zero\n");
876 
877         spte |= (spte & shadow_acc_track_saved_bits_mask) <<
878                 shadow_acc_track_saved_bits_shift;
879         spte &= ~shadow_acc_track_mask;
880 
881         return spte;
882 }
883 
884 /* Restore an acc-track PTE back to a regular PTE */
885 static u64 restore_acc_track_spte(u64 spte)
886 {
887         u64 new_spte = spte;
888         u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
889                          & shadow_acc_track_saved_bits_mask;
890 
891         WARN_ON_ONCE(spte_ad_enabled(spte));
892         WARN_ON_ONCE(!is_access_track_spte(spte));
893 
894         new_spte &= ~shadow_acc_track_mask;
895         new_spte &= ~(shadow_acc_track_saved_bits_mask <<
896                       shadow_acc_track_saved_bits_shift);
897         new_spte |= saved_bits;
898 
899         return new_spte;
900 }
901 
902 /* Returns the Accessed status of the PTE and resets it at the same time. */
903 static bool mmu_spte_age(u64 *sptep)
904 {
905         u64 spte = mmu_spte_get_lockless(sptep);
906 
907         if (!is_accessed_spte(spte))
908                 return false;
909 
910         if (spte_ad_enabled(spte)) {
911                 clear_bit((ffs(shadow_accessed_mask) - 1),
912                           (unsigned long *)sptep);
913         } else {
914                 /*
915                  * Capture the dirty status of the page, so that it doesn't get
916                  * lost when the SPTE is marked for access tracking.
917                  */
918                 if (is_writable_pte(spte))
919                         kvm_set_pfn_dirty(spte_to_pfn(spte));
920 
921                 spte = mark_spte_for_access_track(spte);
922                 mmu_spte_update_no_track(sptep, spte);
923         }
924 
925         return true;
926 }
927 
928 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
929 {
930         /*
931          * Prevent page table teardown by making any free-er wait during
932          * kvm_flush_remote_tlbs() IPI to all active vcpus.
933          */
934         local_irq_disable();
935 
936         /*
937          * Make sure a following spte read is not reordered ahead of the write
938          * to vcpu->mode.
939          */
940         smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
941 }
942 
943 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
944 {
945         /*
946          * Make sure the write to vcpu->mode is not reordered in front of
947          * reads to sptes.  If it does, kvm_mmu_commit_zap_page() can see us
948          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
949          */
950         smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
951         local_irq_enable();
952 }
953 
954 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
955                                   struct kmem_cache *base_cache, int min)
956 {
957         void *obj;
958 
959         if (cache->nobjs >= min)
960                 return 0;
961         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
962                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
963                 if (!obj)
964                         return cache->nobjs >= min ? 0 : -ENOMEM;
965                 cache->objects[cache->nobjs++] = obj;
966         }
967         return 0;
968 }
969 
970 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
971 {
972         return cache->nobjs;
973 }
974 
975 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
976                                   struct kmem_cache *cache)
977 {
978         while (mc->nobjs)
979                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
980 }
981 
982 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
983                                        int min)
984 {
985         void *page;
986 
987         if (cache->nobjs >= min)
988                 return 0;
989         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
990                 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
991                 if (!page)
992                         return cache->nobjs >= min ? 0 : -ENOMEM;
993                 cache->objects[cache->nobjs++] = page;
994         }
995         return 0;
996 }
997 
998 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
999 {
1000         while (mc->nobjs)
1001                 free_page((unsigned long)mc->objects[--mc->nobjs]);
1002 }
1003 
1004 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1005 {
1006         int r;
1007 
1008         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1009                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1010         if (r)
1011                 goto out;
1012         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1013         if (r)
1014                 goto out;
1015         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1016                                    mmu_page_header_cache, 4);
1017 out:
1018         return r;
1019 }
1020 
1021 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1022 {
1023         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1024                                 pte_list_desc_cache);
1025         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1026         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1027                                 mmu_page_header_cache);
1028 }
1029 
1030 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1031 {
1032         void *p;
1033 
1034         BUG_ON(!mc->nobjs);
1035         p = mc->objects[--mc->nobjs];
1036         return p;
1037 }
1038 
1039 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1040 {
1041         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1042 }
1043 
1044 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1045 {
1046         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1047 }
1048 
1049 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1050 {
1051         if (!sp->role.direct)
1052                 return sp->gfns[index];
1053 
1054         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1055 }
1056 
1057 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1058 {
1059         if (sp->role.direct)
1060                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
1061         else
1062                 sp->gfns[index] = gfn;
1063 }
1064 
1065 /*
1066  * Return the pointer to the large page information for a given gfn,
1067  * handling slots that are not large page aligned.
1068  */
1069 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1070                                               struct kvm_memory_slot *slot,
1071                                               int level)
1072 {
1073         unsigned long idx;
1074 
1075         idx = gfn_to_index(gfn, slot->base_gfn, level);
1076         return &slot->arch.lpage_info[level - 2][idx];
1077 }
1078 
1079 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1080                                             gfn_t gfn, int count)
1081 {
1082         struct kvm_lpage_info *linfo;
1083         int i;
1084 
1085         for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1086                 linfo = lpage_info_slot(gfn, slot, i);
1087                 linfo->disallow_lpage += count;
1088                 WARN_ON(linfo->disallow_lpage < 0);
1089         }
1090 }
1091 
1092 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1093 {
1094         update_gfn_disallow_lpage_count(slot, gfn, 1);
1095 }
1096 
1097 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1098 {
1099         update_gfn_disallow_lpage_count(slot, gfn, -1);
1100 }
1101 
1102 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1103 {
1104         struct kvm_memslots *slots;
1105         struct kvm_memory_slot *slot;
1106         gfn_t gfn;
1107 
1108         kvm->arch.indirect_shadow_pages++;
1109         gfn = sp->gfn;
1110         slots = kvm_memslots_for_spte_role(kvm, sp->role);
1111         slot = __gfn_to_memslot(slots, gfn);
1112 
1113         /* the non-leaf shadow pages are keeping readonly. */
1114         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1115                 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1116                                                     KVM_PAGE_TRACK_WRITE);
1117 
1118         kvm_mmu_gfn_disallow_lpage(slot, gfn);
1119 }
1120 
1121 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1122 {
1123         struct kvm_memslots *slots;
1124         struct kvm_memory_slot *slot;
1125         gfn_t gfn;
1126 
1127         kvm->arch.indirect_shadow_pages--;
1128         gfn = sp->gfn;
1129         slots = kvm_memslots_for_spte_role(kvm, sp->role);
1130         slot = __gfn_to_memslot(slots, gfn);
1131         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1132                 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1133                                                        KVM_PAGE_TRACK_WRITE);
1134 
1135         kvm_mmu_gfn_allow_lpage(slot, gfn);
1136 }
1137 
1138 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1139                                           struct kvm_memory_slot *slot)
1140 {
1141         struct kvm_lpage_info *linfo;
1142 
1143         if (slot) {
1144                 linfo = lpage_info_slot(gfn, slot, level);
1145                 return !!linfo->disallow_lpage;
1146         }
1147 
1148         return true;
1149 }
1150 
1151 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1152                                         int level)
1153 {
1154         struct kvm_memory_slot *slot;
1155 
1156         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1157         return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1158 }
1159 
1160 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1161 {
1162         unsigned long page_size;
1163         int i, ret = 0;
1164 
1165         page_size = kvm_host_page_size(kvm, gfn);
1166 
1167         for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1168                 if (page_size >= KVM_HPAGE_SIZE(i))
1169                         ret = i;
1170                 else
1171                         break;
1172         }
1173 
1174         return ret;
1175 }
1176 
1177 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1178                                           bool no_dirty_log)
1179 {
1180         if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1181                 return false;
1182         if (no_dirty_log && slot->dirty_bitmap)
1183                 return false;
1184 
1185         return true;
1186 }
1187 
1188 static struct kvm_memory_slot *
1189 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1190                             bool no_dirty_log)
1191 {
1192         struct kvm_memory_slot *slot;
1193 
1194         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1195         if (!memslot_valid_for_gpte(slot, no_dirty_log))
1196                 slot = NULL;
1197 
1198         return slot;
1199 }
1200 
1201 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1202                          bool *force_pt_level)
1203 {
1204         int host_level, level, max_level;
1205         struct kvm_memory_slot *slot;
1206 
1207         if (unlikely(*force_pt_level))
1208                 return PT_PAGE_TABLE_LEVEL;
1209 
1210         slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1211         *force_pt_level = !memslot_valid_for_gpte(slot, true);
1212         if (unlikely(*force_pt_level))
1213                 return PT_PAGE_TABLE_LEVEL;
1214 
1215         host_level = host_mapping_level(vcpu->kvm, large_gfn);
1216 
1217         if (host_level == PT_PAGE_TABLE_LEVEL)
1218                 return host_level;
1219 
1220         max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1221 
1222         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1223                 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1224                         break;
1225 
1226         return level - 1;
1227 }
1228 
1229 /*
1230  * About rmap_head encoding:
1231  *
1232  * If the bit zero of rmap_head->val is clear, then it points to the only spte
1233  * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1234  * pte_list_desc containing more mappings.
1235  */
1236 
1237 /*
1238  * Returns the number of pointers in the rmap chain, not counting the new one.
1239  */
1240 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1241                         struct kvm_rmap_head *rmap_head)
1242 {
1243         struct pte_list_desc *desc;
1244         int i, count = 0;
1245 
1246         if (!rmap_head->val) {
1247                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1248                 rmap_head->val = (unsigned long)spte;
1249         } else if (!(rmap_head->val & 1)) {
1250                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1251                 desc = mmu_alloc_pte_list_desc(vcpu);
1252                 desc->sptes[0] = (u64 *)rmap_head->val;
1253                 desc->sptes[1] = spte;
1254                 rmap_head->val = (unsigned long)desc | 1;
1255                 ++count;
1256         } else {
1257                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1258                 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1259                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1260                         desc = desc->more;
1261                         count += PTE_LIST_EXT;
1262                 }
1263                 if (desc->sptes[PTE_LIST_EXT-1]) {
1264                         desc->more = mmu_alloc_pte_list_desc(vcpu);
1265                         desc = desc->more;
1266                 }
1267                 for (i = 0; desc->sptes[i]; ++i)
1268                         ++count;
1269                 desc->sptes[i] = spte;
1270         }
1271         return count;
1272 }
1273 
1274 static void
1275 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1276                            struct pte_list_desc *desc, int i,
1277                            struct pte_list_desc *prev_desc)
1278 {
1279         int j;
1280 
1281         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1282                 ;
1283         desc->sptes[i] = desc->sptes[j];
1284         desc->sptes[j] = NULL;
1285         if (j != 0)
1286                 return;
1287         if (!prev_desc && !desc->more)
1288                 rmap_head->val = (unsigned long)desc->sptes[0];
1289         else
1290                 if (prev_desc)
1291                         prev_desc->more = desc->more;
1292                 else
1293                         rmap_head->val = (unsigned long)desc->more | 1;
1294         mmu_free_pte_list_desc(desc);
1295 }
1296 
1297 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1298 {
1299         struct pte_list_desc *desc;
1300         struct pte_list_desc *prev_desc;
1301         int i;
1302 
1303         if (!rmap_head->val) {
1304                 pr_err("%s: %p 0->BUG\n", __func__, spte);
1305                 BUG();
1306         } else if (!(rmap_head->val & 1)) {
1307                 rmap_printk("%s:  %p 1->0\n", __func__, spte);
1308                 if ((u64 *)rmap_head->val != spte) {
1309                         pr_err("%s:  %p 1->BUG\n", __func__, spte);
1310                         BUG();
1311                 }
1312                 rmap_head->val = 0;
1313         } else {
1314                 rmap_printk("%s:  %p many->many\n", __func__, spte);
1315                 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1316                 prev_desc = NULL;
1317                 while (desc) {
1318                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1319                                 if (desc->sptes[i] == spte) {
1320                                         pte_list_desc_remove_entry(rmap_head,
1321                                                         desc, i, prev_desc);
1322                                         return;
1323                                 }
1324                         }
1325                         prev_desc = desc;
1326                         desc = desc->more;
1327                 }
1328                 pr_err("%s: %p many->many\n", __func__, spte);
1329                 BUG();
1330         }
1331 }
1332 
1333 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1334 {
1335         mmu_spte_clear_track_bits(sptep);
1336         __pte_list_remove(sptep, rmap_head);
1337 }
1338 
1339 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1340                                            struct kvm_memory_slot *slot)
1341 {
1342         unsigned long idx;
1343 
1344         idx = gfn_to_index(gfn, slot->base_gfn, level);
1345         return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1346 }
1347 
1348 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1349                                          struct kvm_mmu_page *sp)
1350 {
1351         struct kvm_memslots *slots;
1352         struct kvm_memory_slot *slot;
1353 
1354         slots = kvm_memslots_for_spte_role(kvm, sp->role);
1355         slot = __gfn_to_memslot(slots, gfn);
1356         return __gfn_to_rmap(gfn, sp->role.level, slot);
1357 }
1358 
1359 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1360 {
1361         struct kvm_mmu_memory_cache *cache;
1362 
1363         cache = &vcpu->arch.mmu_pte_list_desc_cache;
1364         return mmu_memory_cache_free_objects(cache);
1365 }
1366 
1367 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1368 {
1369         struct kvm_mmu_page *sp;
1370         struct kvm_rmap_head *rmap_head;
1371 
1372         sp = page_header(__pa(spte));
1373         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1374         rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1375         return pte_list_add(vcpu, spte, rmap_head);
1376 }
1377 
1378 static void rmap_remove(struct kvm *kvm, u64 *spte)
1379 {
1380         struct kvm_mmu_page *sp;
1381         gfn_t gfn;
1382         struct kvm_rmap_head *rmap_head;
1383 
1384         sp = page_header(__pa(spte));
1385         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1386         rmap_head = gfn_to_rmap(kvm, gfn, sp);
1387         __pte_list_remove(spte, rmap_head);
1388 }
1389 
1390 /*
1391  * Used by the following functions to iterate through the sptes linked by a
1392  * rmap.  All fields are private and not assumed to be used outside.
1393  */
1394 struct rmap_iterator {
1395         /* private fields */
1396         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1397         int pos;                        /* index of the sptep */
1398 };
1399 
1400 /*
1401  * Iteration must be started by this function.  This should also be used after
1402  * removing/dropping sptes from the rmap link because in such cases the
1403  * information in the itererator may not be valid.
1404  *
1405  * Returns sptep if found, NULL otherwise.
1406  */
1407 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1408                            struct rmap_iterator *iter)
1409 {
1410         u64 *sptep;
1411 
1412         if (!rmap_head->val)
1413                 return NULL;
1414 
1415         if (!(rmap_head->val & 1)) {
1416                 iter->desc = NULL;
1417                 sptep = (u64 *)rmap_head->val;
1418                 goto out;
1419         }
1420 
1421         iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1422         iter->pos = 0;
1423         sptep = iter->desc->sptes[iter->pos];
1424 out:
1425         BUG_ON(!is_shadow_present_pte(*sptep));
1426         return sptep;
1427 }
1428 
1429 /*
1430  * Must be used with a valid iterator: e.g. after rmap_get_first().
1431  *
1432  * Returns sptep if found, NULL otherwise.
1433  */
1434 static u64 *rmap_get_next(struct rmap_iterator *iter)
1435 {
1436         u64 *sptep;
1437 
1438         if (iter->desc) {
1439                 if (iter->pos < PTE_LIST_EXT - 1) {
1440                         ++iter->pos;
1441                         sptep = iter->desc->sptes[iter->pos];
1442                         if (sptep)
1443                                 goto out;
1444                 }
1445 
1446                 iter->desc = iter->desc->more;
1447 
1448                 if (iter->desc) {
1449                         iter->pos = 0;
1450                         /* desc->sptes[0] cannot be NULL */
1451                         sptep = iter->desc->sptes[iter->pos];
1452                         goto out;
1453                 }
1454         }
1455 
1456         return NULL;
1457 out:
1458         BUG_ON(!is_shadow_present_pte(*sptep));
1459         return sptep;
1460 }
1461 
1462 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_)                 \
1463         for (_spte_ = rmap_get_first(_rmap_head_, _iter_);              \
1464              _spte_; _spte_ = rmap_get_next(_iter_))
1465 
1466 static void drop_spte(struct kvm *kvm, u64 *sptep)
1467 {
1468         if (mmu_spte_clear_track_bits(sptep))
1469                 rmap_remove(kvm, sptep);
1470 }
1471 
1472 
1473 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1474 {
1475         if (is_large_pte(*sptep)) {
1476                 WARN_ON(page_header(__pa(sptep))->role.level ==
1477                         PT_PAGE_TABLE_LEVEL);
1478                 drop_spte(kvm, sptep);
1479                 --kvm->stat.lpages;
1480                 return true;
1481         }
1482 
1483         return false;
1484 }
1485 
1486 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1487 {
1488         if (__drop_large_spte(vcpu->kvm, sptep)) {
1489                 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1490 
1491                 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1492                         KVM_PAGES_PER_HPAGE(sp->role.level));
1493         }
1494 }
1495 
1496 /*
1497  * Write-protect on the specified @sptep, @pt_protect indicates whether
1498  * spte write-protection is caused by protecting shadow page table.
1499  *
1500  * Note: write protection is difference between dirty logging and spte
1501  * protection:
1502  * - for dirty logging, the spte can be set to writable at anytime if
1503  *   its dirty bitmap is properly set.
1504  * - for spte protection, the spte can be writable only after unsync-ing
1505  *   shadow page.
1506  *
1507  * Return true if tlb need be flushed.
1508  */
1509 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1510 {
1511         u64 spte = *sptep;
1512 
1513         if (!is_writable_pte(spte) &&
1514               !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1515                 return false;
1516 
1517         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1518 
1519         if (pt_protect)
1520                 spte &= ~SPTE_MMU_WRITEABLE;
1521         spte = spte & ~PT_WRITABLE_MASK;
1522 
1523         return mmu_spte_update(sptep, spte);
1524 }
1525 
1526 static bool __rmap_write_protect(struct kvm *kvm,
1527                                  struct kvm_rmap_head *rmap_head,
1528                                  bool pt_protect)
1529 {
1530         u64 *sptep;
1531         struct rmap_iterator iter;
1532         bool flush = false;
1533 
1534         for_each_rmap_spte(rmap_head, &iter, sptep)
1535                 flush |= spte_write_protect(sptep, pt_protect);
1536 
1537         return flush;
1538 }
1539 
1540 static bool spte_clear_dirty(u64 *sptep)
1541 {
1542         u64 spte = *sptep;
1543 
1544         rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1545 
1546         spte &= ~shadow_dirty_mask;
1547 
1548         return mmu_spte_update(sptep, spte);
1549 }
1550 
1551 static bool wrprot_ad_disabled_spte(u64 *sptep)
1552 {
1553         bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1554                                                (unsigned long *)sptep);
1555         if (was_writable)
1556                 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1557 
1558         return was_writable;
1559 }
1560 
1561 /*
1562  * Gets the GFN ready for another round of dirty logging by clearing the
1563  *      - D bit on ad-enabled SPTEs, and
1564  *      - W bit on ad-disabled SPTEs.
1565  * Returns true iff any D or W bits were cleared.
1566  */
1567 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1568 {
1569         u64 *sptep;
1570         struct rmap_iterator iter;
1571         bool flush = false;
1572 
1573         for_each_rmap_spte(rmap_head, &iter, sptep)
1574                 if (spte_ad_enabled(*sptep))
1575                         flush |= spte_clear_dirty(sptep);
1576                 else
1577                         flush |= wrprot_ad_disabled_spte(sptep);
1578 
1579         return flush;
1580 }
1581 
1582 static bool spte_set_dirty(u64 *sptep)
1583 {
1584         u64 spte = *sptep;
1585 
1586         rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1587 
1588         spte |= shadow_dirty_mask;
1589 
1590         return mmu_spte_update(sptep, spte);
1591 }
1592 
1593 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1594 {
1595         u64 *sptep;
1596         struct rmap_iterator iter;
1597         bool flush = false;
1598 
1599         for_each_rmap_spte(rmap_head, &iter, sptep)
1600                 if (spte_ad_enabled(*sptep))
1601                         flush |= spte_set_dirty(sptep);
1602 
1603         return flush;
1604 }
1605 
1606 /**
1607  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1608  * @kvm: kvm instance
1609  * @slot: slot to protect
1610  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1611  * @mask: indicates which pages we should protect
1612  *
1613  * Used when we do not need to care about huge page mappings: e.g. during dirty
1614  * logging we do not have any such mappings.
1615  */
1616 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1617                                      struct kvm_memory_slot *slot,
1618                                      gfn_t gfn_offset, unsigned long mask)
1619 {
1620         struct kvm_rmap_head *rmap_head;
1621 
1622         while (mask) {
1623                 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1624                                           PT_PAGE_TABLE_LEVEL, slot);
1625                 __rmap_write_protect(kvm, rmap_head, false);
1626 
1627                 /* clear the first set bit */
1628                 mask &= mask - 1;
1629         }
1630 }
1631 
1632 /**
1633  * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1634  * protect the page if the D-bit isn't supported.
1635  * @kvm: kvm instance
1636  * @slot: slot to clear D-bit
1637  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1638  * @mask: indicates which pages we should clear D-bit
1639  *
1640  * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1641  */
1642 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1643                                      struct kvm_memory_slot *slot,
1644                                      gfn_t gfn_offset, unsigned long mask)
1645 {
1646         struct kvm_rmap_head *rmap_head;
1647 
1648         while (mask) {
1649                 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1650                                           PT_PAGE_TABLE_LEVEL, slot);
1651                 __rmap_clear_dirty(kvm, rmap_head);
1652 
1653                 /* clear the first set bit */
1654                 mask &= mask - 1;
1655         }
1656 }
1657 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1658 
1659 /**
1660  * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1661  * PT level pages.
1662  *
1663  * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1664  * enable dirty logging for them.
1665  *
1666  * Used when we do not need to care about huge page mappings: e.g. during dirty
1667  * logging we do not have any such mappings.
1668  */
1669 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1670                                 struct kvm_memory_slot *slot,
1671                                 gfn_t gfn_offset, unsigned long mask)
1672 {
1673         if (kvm_x86_ops->enable_log_dirty_pt_masked)
1674                 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1675                                 mask);
1676         else
1677                 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1678 }
1679 
1680 /**
1681  * kvm_arch_write_log_dirty - emulate dirty page logging
1682  * @vcpu: Guest mode vcpu
1683  *
1684  * Emulate arch specific page modification logging for the
1685  * nested hypervisor
1686  */
1687 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1688 {
1689         if (kvm_x86_ops->write_log_dirty)
1690                 return kvm_x86_ops->write_log_dirty(vcpu);
1691 
1692         return 0;
1693 }
1694 
1695 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1696                                     struct kvm_memory_slot *slot, u64 gfn)
1697 {
1698         struct kvm_rmap_head *rmap_head;
1699         int i;
1700         bool write_protected = false;
1701 
1702         for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1703                 rmap_head = __gfn_to_rmap(gfn, i, slot);
1704                 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1705         }
1706 
1707         return write_protected;
1708 }
1709 
1710 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1711 {
1712         struct kvm_memory_slot *slot;
1713 
1714         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1715         return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1716 }
1717 
1718 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1719 {
1720         u64 *sptep;
1721         struct rmap_iterator iter;
1722         bool flush = false;
1723 
1724         while ((sptep = rmap_get_first(rmap_head, &iter))) {
1725                 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1726 
1727                 pte_list_remove(rmap_head, sptep);
1728                 flush = true;
1729         }
1730 
1731         return flush;
1732 }
1733 
1734 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1735                            struct kvm_memory_slot *slot, gfn_t gfn, int level,
1736                            unsigned long data)
1737 {
1738         return kvm_zap_rmapp(kvm, rmap_head);
1739 }
1740 
1741 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1742                              struct kvm_memory_slot *slot, gfn_t gfn, int level,
1743                              unsigned long data)
1744 {
1745         u64 *sptep;
1746         struct rmap_iterator iter;
1747         int need_flush = 0;
1748         u64 new_spte;
1749         pte_t *ptep = (pte_t *)data;
1750         kvm_pfn_t new_pfn;
1751 
1752         WARN_ON(pte_huge(*ptep));
1753         new_pfn = pte_pfn(*ptep);
1754 
1755 restart:
1756         for_each_rmap_spte(rmap_head, &iter, sptep) {
1757                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1758                             sptep, *sptep, gfn, level);
1759 
1760                 need_flush = 1;
1761 
1762                 if (pte_write(*ptep)) {
1763                         pte_list_remove(rmap_head, sptep);
1764                         goto restart;
1765                 } else {
1766                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1767                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1768 
1769                         new_spte &= ~PT_WRITABLE_MASK;
1770                         new_spte &= ~SPTE_HOST_WRITEABLE;
1771 
1772                         new_spte = mark_spte_for_access_track(new_spte);
1773 
1774                         mmu_spte_clear_track_bits(sptep);
1775                         mmu_spte_set(sptep, new_spte);
1776                 }
1777         }
1778 
1779         if (need_flush && kvm_available_flush_tlb_with_range()) {
1780                 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1781                 return 0;
1782         }
1783 
1784         return need_flush;
1785 }
1786 
1787 struct slot_rmap_walk_iterator {
1788         /* input fields. */
1789         struct kvm_memory_slot *slot;
1790         gfn_t start_gfn;
1791         gfn_t end_gfn;
1792         int start_level;
1793         int end_level;
1794 
1795         /* output fields. */
1796         gfn_t gfn;
1797         struct kvm_rmap_head *rmap;
1798         int level;
1799 
1800         /* private field. */
1801         struct kvm_rmap_head *end_rmap;
1802 };
1803 
1804 static void
1805 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1806 {
1807         iterator->level = level;
1808         iterator->gfn = iterator->start_gfn;
1809         iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1810         iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1811                                            iterator->slot);
1812 }
1813 
1814 static void
1815 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1816                     struct kvm_memory_slot *slot, int start_level,
1817                     int end_level, gfn_t start_gfn, gfn_t end_gfn)
1818 {
1819         iterator->slot = slot;
1820         iterator->start_level = start_level;
1821         iterator->end_level = end_level;
1822         iterator->start_gfn = start_gfn;
1823         iterator->end_gfn = end_gfn;
1824 
1825         rmap_walk_init_level(iterator, iterator->start_level);
1826 }
1827 
1828 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1829 {
1830         return !!iterator->rmap;
1831 }
1832 
1833 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1834 {
1835         if (++iterator->rmap <= iterator->end_rmap) {
1836                 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1837                 return;
1838         }
1839 
1840         if (++iterator->level > iterator->end_level) {
1841                 iterator->rmap = NULL;
1842                 return;
1843         }
1844 
1845         rmap_walk_init_level(iterator, iterator->level);
1846 }
1847 
1848 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_,    \
1849            _start_gfn, _end_gfn, _iter_)                                \
1850         for (slot_rmap_walk_init(_iter_, _slot_, _start_level_,         \
1851                                  _end_level_, _start_gfn, _end_gfn);    \
1852              slot_rmap_walk_okay(_iter_);                               \
1853              slot_rmap_walk_next(_iter_))
1854 
1855 static int kvm_handle_hva_range(struct kvm *kvm,
1856                                 unsigned long start,
1857                                 unsigned long end,
1858                                 unsigned long data,
1859                                 int (*handler)(struct kvm *kvm,
1860                                                struct kvm_rmap_head *rmap_head,
1861                                                struct kvm_memory_slot *slot,
1862                                                gfn_t gfn,
1863                                                int level,
1864                                                unsigned long data))
1865 {
1866         struct kvm_memslots *slots;
1867         struct kvm_memory_slot *memslot;
1868         struct slot_rmap_walk_iterator iterator;
1869         int ret = 0;
1870         int i;
1871 
1872         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1873                 slots = __kvm_memslots(kvm, i);
1874                 kvm_for_each_memslot(memslot, slots) {
1875                         unsigned long hva_start, hva_end;
1876                         gfn_t gfn_start, gfn_end;
1877 
1878                         hva_start = max(start, memslot->userspace_addr);
1879                         hva_end = min(end, memslot->userspace_addr +
1880                                       (memslot->npages << PAGE_SHIFT));
1881                         if (hva_start >= hva_end)
1882                                 continue;
1883                         /*
1884                          * {gfn(page) | page intersects with [hva_start, hva_end)} =
1885                          * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1886                          */
1887                         gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1888                         gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1889 
1890                         for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1891                                                  PT_MAX_HUGEPAGE_LEVEL,
1892                                                  gfn_start, gfn_end - 1,
1893                                                  &iterator)
1894                                 ret |= handler(kvm, iterator.rmap, memslot,
1895                                                iterator.gfn, iterator.level, data);
1896                 }
1897         }
1898 
1899         return ret;
1900 }
1901 
1902 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1903                           unsigned long data,
1904                           int (*handler)(struct kvm *kvm,
1905                                          struct kvm_rmap_head *rmap_head,
1906                                          struct kvm_memory_slot *slot,
1907                                          gfn_t gfn, int level,
1908                                          unsigned long data))
1909 {
1910         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1911 }
1912 
1913 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1914 {
1915         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1916 }
1917 
1918 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1919 {
1920         return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1921 }
1922 
1923 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1924                          struct kvm_memory_slot *slot, gfn_t gfn, int level,
1925                          unsigned long data)
1926 {
1927         u64 *sptep;
1928         struct rmap_iterator uninitialized_var(iter);
1929         int young = 0;
1930 
1931         for_each_rmap_spte(rmap_head, &iter, sptep)
1932                 young |= mmu_spte_age(sptep);
1933 
1934         trace_kvm_age_page(gfn, level, slot, young);
1935         return young;
1936 }
1937 
1938 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1939                               struct kvm_memory_slot *slot, gfn_t gfn,
1940                               int level, unsigned long data)
1941 {
1942         u64 *sptep;
1943         struct rmap_iterator iter;
1944 
1945         for_each_rmap_spte(rmap_head, &iter, sptep)
1946                 if (is_accessed_spte(*sptep))
1947                         return 1;
1948         return 0;
1949 }
1950 
1951 #define RMAP_RECYCLE_THRESHOLD 1000
1952 
1953 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1954 {
1955         struct kvm_rmap_head *rmap_head;
1956         struct kvm_mmu_page *sp;
1957 
1958         sp = page_header(__pa(spte));
1959 
1960         rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1961 
1962         kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1963         kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1964                         KVM_PAGES_PER_HPAGE(sp->role.level));
1965 }
1966 
1967 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1968 {
1969         return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1970 }
1971 
1972 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1973 {
1974         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1975 }
1976 
1977 #ifdef MMU_DEBUG
1978 static int is_empty_shadow_page(u64 *spt)
1979 {
1980         u64 *pos;
1981         u64 *end;
1982 
1983         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1984                 if (is_shadow_present_pte(*pos)) {
1985                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1986                                pos, *pos);
1987                         return 0;
1988                 }
1989         return 1;
1990 }
1991 #endif
1992 
1993 /*
1994  * This value is the sum of all of the kvm instances's
1995  * kvm->arch.n_used_mmu_pages values.  We need a global,
1996  * aggregate version in order to make the slab shrinker
1997  * faster
1998  */
1999 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
2000 {
2001         kvm->arch.n_used_mmu_pages += nr;
2002         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2003 }
2004 
2005 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2006 {
2007         MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2008         hlist_del(&sp->hash_link);
2009         list_del(&sp->link);
2010         free_page((unsigned long)sp->spt);
2011         if (!sp->role.direct)
2012                 free_page((unsigned long)sp->gfns);
2013         kmem_cache_free(mmu_page_header_cache, sp);
2014 }
2015 
2016 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2017 {
2018         return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2019 }
2020 
2021 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2022                                     struct kvm_mmu_page *sp, u64 *parent_pte)
2023 {
2024         if (!parent_pte)
2025                 return;
2026 
2027         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2028 }
2029 
2030 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2031                                        u64 *parent_pte)
2032 {
2033         __pte_list_remove(parent_pte, &sp->parent_ptes);
2034 }
2035 
2036 static void drop_parent_pte(struct kvm_mmu_page *sp,
2037                             u64 *parent_pte)
2038 {
2039         mmu_page_remove_parent_pte(sp, parent_pte);
2040         mmu_spte_clear_no_track(parent_pte);
2041 }
2042 
2043 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2044 {
2045         struct kvm_mmu_page *sp;
2046 
2047         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2048         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2049         if (!direct)
2050                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2051         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2052 
2053         /*
2054          * The active_mmu_pages list is the FIFO list, do not move the
2055          * page until it is zapped. kvm_zap_obsolete_pages depends on
2056          * this feature. See the comments in kvm_zap_obsolete_pages().
2057          */
2058         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2059         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2060         return sp;
2061 }
2062 
2063 static void mark_unsync(u64 *spte);
2064 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2065 {
2066         u64 *sptep;
2067         struct rmap_iterator iter;
2068 
2069         for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2070                 mark_unsync(sptep);
2071         }
2072 }
2073 
2074 static void mark_unsync(u64 *spte)
2075 {
2076         struct kvm_mmu_page *sp;
2077         unsigned int index;
2078 
2079         sp = page_header(__pa(spte));
2080         index = spte - sp->spt;
2081         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2082                 return;
2083         if (sp->unsync_children++)
2084                 return;
2085         kvm_mmu_mark_parents_unsync(sp);
2086 }
2087 
2088 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2089                                struct kvm_mmu_page *sp)
2090 {
2091         return 0;
2092 }
2093 
2094 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2095 {
2096 }
2097 
2098 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2099                                  struct kvm_mmu_page *sp, u64 *spte,
2100                                  const void *pte)
2101 {
2102         WARN_ON(1);
2103 }
2104 
2105 #define KVM_PAGE_ARRAY_NR 16
2106 
2107 struct kvm_mmu_pages {
2108         struct mmu_page_and_offset {
2109                 struct kvm_mmu_page *sp;
2110                 unsigned int idx;
2111         } page[KVM_PAGE_ARRAY_NR];
2112         unsigned int nr;
2113 };
2114 
2115 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2116                          int idx)
2117 {
2118         int i;
2119 
2120         if (sp->unsync)
2121                 for (i=0; i < pvec->nr; i++)
2122                         if (pvec->page[i].sp == sp)
2123                                 return 0;
2124 
2125         pvec->page[pvec->nr].sp = sp;
2126         pvec->page[pvec->nr].idx = idx;
2127         pvec->nr++;
2128         return (pvec->nr == KVM_PAGE_ARRAY_NR);
2129 }
2130 
2131 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2132 {
2133         --sp->unsync_children;
2134         WARN_ON((int)sp->unsync_children < 0);
2135         __clear_bit(idx, sp->unsync_child_bitmap);
2136 }
2137 
2138 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2139                            struct kvm_mmu_pages *pvec)
2140 {
2141         int i, ret, nr_unsync_leaf = 0;
2142 
2143         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2144                 struct kvm_mmu_page *child;
2145                 u64 ent = sp->spt[i];
2146 
2147                 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2148                         clear_unsync_child_bit(sp, i);
2149                         continue;
2150                 }
2151 
2152                 child = page_header(ent & PT64_BASE_ADDR_MASK);
2153 
2154                 if (child->unsync_children) {
2155                         if (mmu_pages_add(pvec, child, i))
2156                                 return -ENOSPC;
2157 
2158                         ret = __mmu_unsync_walk(child, pvec);
2159                         if (!ret) {
2160                                 clear_unsync_child_bit(sp, i);
2161                                 continue;
2162                         } else if (ret > 0) {
2163                                 nr_unsync_leaf += ret;
2164                         } else
2165                                 return ret;
2166                 } else if (child->unsync) {
2167                         nr_unsync_leaf++;
2168                         if (mmu_pages_add(pvec, child, i))
2169                                 return -ENOSPC;
2170                 } else
2171                         clear_unsync_child_bit(sp, i);
2172         }
2173 
2174         return nr_unsync_leaf;
2175 }
2176 
2177 #define INVALID_INDEX (-1)
2178 
2179 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2180                            struct kvm_mmu_pages *pvec)
2181 {
2182         pvec->nr = 0;
2183         if (!sp->unsync_children)
2184                 return 0;
2185 
2186         mmu_pages_add(pvec, sp, INVALID_INDEX);
2187         return __mmu_unsync_walk(sp, pvec);
2188 }
2189 
2190 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2191 {
2192         WARN_ON(!sp->unsync);
2193         trace_kvm_mmu_sync_page(sp);
2194         sp->unsync = 0;
2195         --kvm->stat.mmu_unsync;
2196 }
2197 
2198 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2199                                     struct list_head *invalid_list);
2200 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2201                                     struct list_head *invalid_list);
2202 
2203 /*
2204  * NOTE: we should pay more attention on the zapped-obsolete page
2205  * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2206  * since it has been deleted from active_mmu_pages but still can be found
2207  * at hast list.
2208  *
2209  * for_each_valid_sp() has skipped that kind of pages.
2210  */
2211 #define for_each_valid_sp(_kvm, _sp, _gfn)                              \
2212         hlist_for_each_entry(_sp,                                       \
2213           &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2214                 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) {    \
2215                 } else
2216 
2217 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn)                 \
2218         for_each_valid_sp(_kvm, _sp, _gfn)                              \
2219                 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2220 
2221 /* @sp->gfn should be write-protected at the call site */
2222 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2223                             struct list_head *invalid_list)
2224 {
2225         if (sp->role.cr4_pae != !!is_pae(vcpu)
2226             || vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2227                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2228                 return false;
2229         }
2230 
2231         return true;
2232 }
2233 
2234 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2235                                  struct list_head *invalid_list,
2236                                  bool remote_flush, bool local_flush)
2237 {
2238         if (!list_empty(invalid_list)) {
2239                 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2240                 return;
2241         }
2242 
2243         if (remote_flush)
2244                 kvm_flush_remote_tlbs(vcpu->kvm);
2245         else if (local_flush)
2246                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2247 }
2248 
2249 #ifdef CONFIG_KVM_MMU_AUDIT
2250 #include "mmu_audit.c"
2251 #else
2252 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2253 static void mmu_audit_disable(void) { }
2254 #endif
2255 
2256 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2257 {
2258         return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2259 }
2260 
2261 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2262                          struct list_head *invalid_list)
2263 {
2264         kvm_unlink_unsync_page(vcpu->kvm, sp);
2265         return __kvm_sync_page(vcpu, sp, invalid_list);
2266 }
2267 
2268 /* @gfn should be write-protected at the call site */
2269 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2270                            struct list_head *invalid_list)
2271 {
2272         struct kvm_mmu_page *s;
2273         bool ret = false;
2274 
2275         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2276                 if (!s->unsync)
2277                         continue;
2278 
2279                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2280                 ret |= kvm_sync_page(vcpu, s, invalid_list);
2281         }
2282 
2283         return ret;
2284 }
2285 
2286 struct mmu_page_path {
2287         struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2288         unsigned int idx[PT64_ROOT_MAX_LEVEL];
2289 };
2290 
2291 #define for_each_sp(pvec, sp, parents, i)                       \
2292                 for (i = mmu_pages_first(&pvec, &parents);      \
2293                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
2294                         i = mmu_pages_next(&pvec, &parents, i))
2295 
2296 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2297                           struct mmu_page_path *parents,
2298                           int i)
2299 {
2300         int n;
2301 
2302         for (n = i+1; n < pvec->nr; n++) {
2303                 struct kvm_mmu_page *sp = pvec->page[n].sp;
2304                 unsigned idx = pvec->page[n].idx;
2305                 int level = sp->role.level;
2306 
2307                 parents->idx[level-1] = idx;
2308                 if (level == PT_PAGE_TABLE_LEVEL)
2309                         break;
2310 
2311                 parents->parent[level-2] = sp;
2312         }
2313 
2314         return n;
2315 }
2316 
2317 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2318                            struct mmu_page_path *parents)
2319 {
2320         struct kvm_mmu_page *sp;
2321         int level;
2322 
2323         if (pvec->nr == 0)
2324                 return 0;
2325 
2326         WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2327 
2328         sp = pvec->page[0].sp;
2329         level = sp->role.level;
2330         WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2331 
2332         parents->parent[level-2] = sp;
2333 
2334         /* Also set up a sentinel.  Further entries in pvec are all
2335          * children of sp, so this element is never overwritten.
2336          */
2337         parents->parent[level-1] = NULL;
2338         return mmu_pages_next(pvec, parents, 0);
2339 }
2340 
2341 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2342 {
2343         struct kvm_mmu_page *sp;
2344         unsigned int level = 0;
2345 
2346         do {
2347                 unsigned int idx = parents->idx[level];
2348                 sp = parents->parent[level];
2349                 if (!sp)
2350                         return;
2351 
2352                 WARN_ON(idx == INVALID_INDEX);
2353                 clear_unsync_child_bit(sp, idx);
2354                 level++;
2355         } while (!sp->unsync_children);
2356 }
2357 
2358 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2359                               struct kvm_mmu_page *parent)
2360 {
2361         int i;
2362         struct kvm_mmu_page *sp;
2363         struct mmu_page_path parents;
2364         struct kvm_mmu_pages pages;
2365         LIST_HEAD(invalid_list);
2366         bool flush = false;
2367 
2368         while (mmu_unsync_walk(parent, &pages)) {
2369                 bool protected = false;
2370 
2371                 for_each_sp(pages, sp, parents, i)
2372                         protected |= rmap_write_protect(vcpu, sp->gfn);
2373 
2374                 if (protected) {
2375                         kvm_flush_remote_tlbs(vcpu->kvm);
2376                         flush = false;
2377                 }
2378 
2379                 for_each_sp(pages, sp, parents, i) {
2380                         flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2381                         mmu_pages_clear_parents(&parents);
2382                 }
2383                 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2384                         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2385                         cond_resched_lock(&vcpu->kvm->mmu_lock);
2386                         flush = false;
2387                 }
2388         }
2389 
2390         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2391 }
2392 
2393 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2394 {
2395         atomic_set(&sp->write_flooding_count,  0);
2396 }
2397 
2398 static void clear_sp_write_flooding_count(u64 *spte)
2399 {
2400         struct kvm_mmu_page *sp =  page_header(__pa(spte));
2401 
2402         __clear_sp_write_flooding_count(sp);
2403 }
2404 
2405 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2406                                              gfn_t gfn,
2407                                              gva_t gaddr,
2408                                              unsigned level,
2409                                              int direct,
2410                                              unsigned access)
2411 {
2412         union kvm_mmu_page_role role;
2413         unsigned quadrant;
2414         struct kvm_mmu_page *sp;
2415         bool need_sync = false;
2416         bool flush = false;
2417         int collisions = 0;
2418         LIST_HEAD(invalid_list);
2419 
2420         role = vcpu->arch.mmu->mmu_role.base;
2421         role.level = level;
2422         role.direct = direct;
2423         if (role.direct)
2424                 role.cr4_pae = 0;
2425         role.access = access;
2426         if (!vcpu->arch.mmu->direct_map
2427             && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2428                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2429                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2430                 role.quadrant = quadrant;
2431         }
2432         for_each_valid_sp(vcpu->kvm, sp, gfn) {
2433                 if (sp->gfn != gfn) {
2434                         collisions++;
2435                         continue;
2436                 }
2437 
2438                 if (!need_sync && sp->unsync)
2439                         need_sync = true;
2440 
2441                 if (sp->role.word != role.word)
2442                         continue;
2443 
2444                 if (sp->unsync) {
2445                         /* The page is good, but __kvm_sync_page might still end
2446                          * up zapping it.  If so, break in order to rebuild it.
2447                          */
2448                         if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2449                                 break;
2450 
2451                         WARN_ON(!list_empty(&invalid_list));
2452                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2453                 }
2454 
2455                 if (sp->unsync_children)
2456                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2457 
2458                 __clear_sp_write_flooding_count(sp);
2459                 trace_kvm_mmu_get_page(sp, false);
2460                 goto out;
2461         }
2462 
2463         ++vcpu->kvm->stat.mmu_cache_miss;
2464 
2465         sp = kvm_mmu_alloc_page(vcpu, direct);
2466 
2467         sp->gfn = gfn;
2468         sp->role = role;
2469         hlist_add_head(&sp->hash_link,
2470                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2471         if (!direct) {
2472                 /*
2473                  * we should do write protection before syncing pages
2474                  * otherwise the content of the synced shadow page may
2475                  * be inconsistent with guest page table.
2476                  */
2477                 account_shadowed(vcpu->kvm, sp);
2478                 if (level == PT_PAGE_TABLE_LEVEL &&
2479                       rmap_write_protect(vcpu, gfn))
2480                         kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2481 
2482                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2483                         flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2484         }
2485         sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2486         clear_page(sp->spt);
2487         trace_kvm_mmu_get_page(sp, true);
2488 
2489         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2490 out:
2491         if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2492                 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2493         return sp;
2494 }
2495 
2496 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2497                                         struct kvm_vcpu *vcpu, hpa_t root,
2498                                         u64 addr)
2499 {
2500         iterator->addr = addr;
2501         iterator->shadow_addr = root;
2502         iterator->level = vcpu->arch.mmu->shadow_root_level;
2503 
2504         if (iterator->level == PT64_ROOT_4LEVEL &&
2505             vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2506             !vcpu->arch.mmu->direct_map)
2507                 --iterator->level;
2508 
2509         if (iterator->level == PT32E_ROOT_LEVEL) {
2510                 /*
2511                  * prev_root is currently only used for 64-bit hosts. So only
2512                  * the active root_hpa is valid here.
2513                  */
2514                 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2515 
2516                 iterator->shadow_addr
2517                         = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2518                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2519                 --iterator->level;
2520                 if (!iterator->shadow_addr)
2521                         iterator->level = 0;
2522         }
2523 }
2524 
2525 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2526                              struct kvm_vcpu *vcpu, u64 addr)
2527 {
2528         shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2529                                     addr);
2530 }
2531 
2532 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2533 {
2534         if (iterator->level < PT_PAGE_TABLE_LEVEL)
2535                 return false;
2536 
2537         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2538         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2539         return true;
2540 }
2541 
2542 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2543                                u64 spte)
2544 {
2545         if (is_last_spte(spte, iterator->level)) {
2546                 iterator->level = 0;
2547                 return;
2548         }
2549 
2550         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2551         --iterator->level;
2552 }
2553 
2554 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2555 {
2556         __shadow_walk_next(iterator, *iterator->sptep);
2557 }
2558 
2559 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2560                              struct kvm_mmu_page *sp)
2561 {
2562         u64 spte;
2563 
2564         BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2565 
2566         spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2567                shadow_user_mask | shadow_x_mask | shadow_me_mask;
2568 
2569         if (sp_ad_disabled(sp))
2570                 spte |= shadow_acc_track_value;
2571         else
2572                 spte |= shadow_accessed_mask;
2573 
2574         mmu_spte_set(sptep, spte);
2575 
2576         mmu_page_add_parent_pte(vcpu, sp, sptep);
2577 
2578         if (sp->unsync_children || sp->unsync)
2579                 mark_unsync(sptep);
2580 }
2581 
2582 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2583                                    unsigned direct_access)
2584 {
2585         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2586                 struct kvm_mmu_page *child;
2587 
2588                 /*
2589                  * For the direct sp, if the guest pte's dirty bit
2590                  * changed form clean to dirty, it will corrupt the
2591                  * sp's access: allow writable in the read-only sp,
2592                  * so we should update the spte at this point to get
2593                  * a new sp with the correct access.
2594                  */
2595                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2596                 if (child->role.access == direct_access)
2597                         return;
2598 
2599                 drop_parent_pte(child, sptep);
2600                 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2601         }
2602 }
2603 
2604 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2605                              u64 *spte)
2606 {
2607         u64 pte;
2608         struct kvm_mmu_page *child;
2609 
2610         pte = *spte;
2611         if (is_shadow_present_pte(pte)) {
2612                 if (is_last_spte(pte, sp->role.level)) {
2613                         drop_spte(kvm, spte);
2614                         if (is_large_pte(pte))
2615                                 --kvm->stat.lpages;
2616                 } else {
2617                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2618                         drop_parent_pte(child, spte);
2619                 }
2620                 return true;
2621         }
2622 
2623         if (is_mmio_spte(pte))
2624                 mmu_spte_clear_no_track(spte);
2625 
2626         return false;
2627 }
2628 
2629 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2630                                          struct kvm_mmu_page *sp)
2631 {
2632         unsigned i;
2633 
2634         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2635                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2636 }
2637 
2638 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2639 {
2640         u64 *sptep;
2641         struct rmap_iterator iter;
2642 
2643         while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2644                 drop_parent_pte(sp, sptep);
2645 }
2646 
2647 static int mmu_zap_unsync_children(struct kvm *kvm,
2648                                    struct kvm_mmu_page *parent,
2649                                    struct list_head *invalid_list)
2650 {
2651         int i, zapped = 0;
2652         struct mmu_page_path parents;
2653         struct kvm_mmu_pages pages;
2654 
2655         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2656                 return 0;
2657 
2658         while (mmu_unsync_walk(parent, &pages)) {
2659                 struct kvm_mmu_page *sp;
2660 
2661                 for_each_sp(pages, sp, parents, i) {
2662                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2663                         mmu_pages_clear_parents(&parents);
2664                         zapped++;
2665                 }
2666         }
2667 
2668         return zapped;
2669 }
2670 
2671 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2672                                     struct list_head *invalid_list)
2673 {
2674         int ret;
2675 
2676         trace_kvm_mmu_prepare_zap_page(sp);
2677         ++kvm->stat.mmu_shadow_zapped;
2678         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2679         kvm_mmu_page_unlink_children(kvm, sp);
2680         kvm_mmu_unlink_parents(kvm, sp);
2681 
2682         if (!sp->role.invalid && !sp->role.direct)
2683                 unaccount_shadowed(kvm, sp);
2684 
2685         if (sp->unsync)
2686                 kvm_unlink_unsync_page(kvm, sp);
2687         if (!sp->root_count) {
2688                 /* Count self */
2689                 ret++;
2690                 list_move(&sp->link, invalid_list);
2691                 kvm_mod_used_mmu_pages(kvm, -1);
2692         } else {
2693                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2694 
2695                 /*
2696                  * The obsolete pages can not be used on any vcpus.
2697                  * See the comments in kvm_mmu_invalidate_zap_all_pages().
2698                  */
2699                 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2700                         kvm_reload_remote_mmus(kvm);
2701         }
2702 
2703         sp->role.invalid = 1;
2704         return ret;
2705 }
2706 
2707 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2708                                     struct list_head *invalid_list)
2709 {
2710         struct kvm_mmu_page *sp, *nsp;
2711 
2712         if (list_empty(invalid_list))
2713                 return;
2714 
2715         /*
2716          * We need to make sure everyone sees our modifications to
2717          * the page tables and see changes to vcpu->mode here. The barrier
2718          * in the kvm_flush_remote_tlbs() achieves this. This pairs
2719          * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2720          *
2721          * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2722          * guest mode and/or lockless shadow page table walks.
2723          */
2724         kvm_flush_remote_tlbs(kvm);
2725 
2726         list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2727                 WARN_ON(!sp->role.invalid || sp->root_count);
2728                 kvm_mmu_free_page(sp);
2729         }
2730 }
2731 
2732 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2733                                         struct list_head *invalid_list)
2734 {
2735         struct kvm_mmu_page *sp;
2736 
2737         if (list_empty(&kvm->arch.active_mmu_pages))
2738                 return false;
2739 
2740         sp = list_last_entry(&kvm->arch.active_mmu_pages,
2741                              struct kvm_mmu_page, link);
2742         return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2743 }
2744 
2745 /*
2746  * Changing the number of mmu pages allocated to the vm
2747  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2748  */
2749 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2750 {
2751         LIST_HEAD(invalid_list);
2752 
2753         spin_lock(&kvm->mmu_lock);
2754 
2755         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2756                 /* Need to free some mmu pages to achieve the goal. */
2757                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2758                         if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2759                                 break;
2760 
2761                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2762                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2763         }
2764 
2765         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2766 
2767         spin_unlock(&kvm->mmu_lock);
2768 }
2769 
2770 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2771 {
2772         struct kvm_mmu_page *sp;
2773         LIST_HEAD(invalid_list);
2774         int r;
2775 
2776         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2777         r = 0;
2778         spin_lock(&kvm->mmu_lock);
2779         for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2780                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2781                          sp->role.word);
2782                 r = 1;
2783                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2784         }
2785         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2786         spin_unlock(&kvm->mmu_lock);
2787 
2788         return r;
2789 }
2790 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2791 
2792 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2793 {
2794         trace_kvm_mmu_unsync_page(sp);
2795         ++vcpu->kvm->stat.mmu_unsync;
2796         sp->unsync = 1;
2797 
2798         kvm_mmu_mark_parents_unsync(sp);
2799 }
2800 
2801 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2802                                    bool can_unsync)
2803 {
2804         struct kvm_mmu_page *sp;
2805 
2806         if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2807                 return true;
2808 
2809         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2810                 if (!can_unsync)
2811                         return true;
2812 
2813                 if (sp->unsync)
2814                         continue;
2815 
2816                 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2817                 kvm_unsync_page(vcpu, sp);
2818         }
2819 
2820         /*
2821          * We need to ensure that the marking of unsync pages is visible
2822          * before the SPTE is updated to allow writes because
2823          * kvm_mmu_sync_roots() checks the unsync flags without holding
2824          * the MMU lock and so can race with this. If the SPTE was updated
2825          * before the page had been marked as unsync-ed, something like the
2826          * following could happen:
2827          *
2828          * CPU 1                    CPU 2
2829          * ---------------------------------------------------------------------
2830          * 1.2 Host updates SPTE
2831          *     to be writable
2832          *                      2.1 Guest writes a GPTE for GVA X.
2833          *                          (GPTE being in the guest page table shadowed
2834          *                           by the SP from CPU 1.)
2835          *                          This reads SPTE during the page table walk.
2836          *                          Since SPTE.W is read as 1, there is no
2837          *                          fault.
2838          *
2839          *                      2.2 Guest issues TLB flush.
2840          *                          That causes a VM Exit.
2841          *
2842          *                      2.3 kvm_mmu_sync_pages() reads sp->unsync.
2843          *                          Since it is false, so it just returns.
2844          *
2845          *                      2.4 Guest accesses GVA X.
2846          *                          Since the mapping in the SP was not updated,
2847          *                          so the old mapping for GVA X incorrectly
2848          *                          gets used.
2849          * 1.1 Host marks SP
2850          *     as unsync
2851          *     (sp->unsync = true)
2852          *
2853          * The write barrier below ensures that 1.1 happens before 1.2 and thus
2854          * the situation in 2.4 does not arise. The implicit barrier in 2.2
2855          * pairs with this write barrier.
2856          */
2857         smp_wmb();
2858 
2859         return false;
2860 }
2861 
2862 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2863 {
2864         if (pfn_valid(pfn))
2865                 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2866                         /*
2867                          * Some reserved pages, such as those from NVDIMM
2868                          * DAX devices, are not for MMIO, and can be mapped
2869                          * with cached memory type for better performance.
2870                          * However, the above check misconceives those pages
2871                          * as MMIO, and results in KVM mapping them with UC
2872                          * memory type, which would hurt the performance.
2873                          * Therefore, we check the host memory type in addition
2874                          * and only treat UC/UC-/WC pages as MMIO.
2875                          */
2876                         (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2877 
2878         return true;
2879 }
2880 
2881 /* Bits which may be returned by set_spte() */
2882 #define SET_SPTE_WRITE_PROTECTED_PT     BIT(0)
2883 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH  BIT(1)
2884 
2885 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2886                     unsigned pte_access, int level,
2887                     gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2888                     bool can_unsync, bool host_writable)
2889 {
2890         u64 spte = 0;
2891         int ret = 0;
2892         struct kvm_mmu_page *sp;
2893 
2894         if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2895                 return 0;
2896 
2897         sp = page_header(__pa(sptep));
2898         if (sp_ad_disabled(sp))
2899                 spte |= shadow_acc_track_value;
2900 
2901         /*
2902          * For the EPT case, shadow_present_mask is 0 if hardware
2903          * supports exec-only page table entries.  In that case,
2904          * ACC_USER_MASK and shadow_user_mask are used to represent
2905          * read access.  See FNAME(gpte_access) in paging_tmpl.h.
2906          */
2907         spte |= shadow_present_mask;
2908         if (!speculative)
2909                 spte |= spte_shadow_accessed_mask(spte);
2910 
2911         if (pte_access & ACC_EXEC_MASK)
2912                 spte |= shadow_x_mask;
2913         else
2914                 spte |= shadow_nx_mask;
2915 
2916         if (pte_access & ACC_USER_MASK)
2917                 spte |= shadow_user_mask;
2918 
2919         if (level > PT_PAGE_TABLE_LEVEL)
2920                 spte |= PT_PAGE_SIZE_MASK;
2921         if (tdp_enabled)
2922                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2923                         kvm_is_mmio_pfn(pfn));
2924 
2925         if (host_writable)
2926                 spte |= SPTE_HOST_WRITEABLE;
2927         else
2928                 pte_access &= ~ACC_WRITE_MASK;
2929 
2930         if (!kvm_is_mmio_pfn(pfn))
2931                 spte |= shadow_me_mask;
2932 
2933         spte |= (u64)pfn << PAGE_SHIFT;
2934 
2935         if (pte_access & ACC_WRITE_MASK) {
2936 
2937                 /*
2938                  * Other vcpu creates new sp in the window between
2939                  * mapping_level() and acquiring mmu-lock. We can
2940                  * allow guest to retry the access, the mapping can
2941                  * be fixed if guest refault.
2942                  */
2943                 if (level > PT_PAGE_TABLE_LEVEL &&
2944                     mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2945                         goto done;
2946 
2947                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2948 
2949                 /*
2950                  * Optimization: for pte sync, if spte was writable the hash
2951                  * lookup is unnecessary (and expensive). Write protection
2952                  * is responsibility of mmu_get_page / kvm_sync_page.
2953                  * Same reasoning can be applied to dirty page accounting.
2954                  */
2955                 if (!can_unsync && is_writable_pte(*sptep))
2956                         goto set_pte;
2957 
2958                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2959                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2960                                  __func__, gfn);
2961                         ret |= SET_SPTE_WRITE_PROTECTED_PT;
2962                         pte_access &= ~ACC_WRITE_MASK;
2963                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2964                 }
2965         }
2966 
2967         if (pte_access & ACC_WRITE_MASK) {
2968                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2969                 spte |= spte_shadow_dirty_mask(spte);
2970         }
2971 
2972         if (speculative)
2973                 spte = mark_spte_for_access_track(spte);
2974 
2975 set_pte:
2976         if (mmu_spte_update(sptep, spte))
2977                 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2978 done:
2979         return ret;
2980 }
2981 
2982 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2983                         int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2984                         bool speculative, bool host_writable)
2985 {
2986         int was_rmapped = 0;
2987         int rmap_count;
2988         int set_spte_ret;
2989         int ret = RET_PF_RETRY;
2990         bool flush = false;
2991 
2992         pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2993                  *sptep, write_fault, gfn);
2994 
2995         if (is_shadow_present_pte(*sptep)) {
2996                 /*
2997                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2998                  * the parent of the now unreachable PTE.
2999                  */
3000                 if (level > PT_PAGE_TABLE_LEVEL &&
3001                     !is_large_pte(*sptep)) {
3002                         struct kvm_mmu_page *child;
3003                         u64 pte = *sptep;
3004 
3005                         child = page_header(pte & PT64_BASE_ADDR_MASK);
3006                         drop_parent_pte(child, sptep);
3007                         flush = true;
3008                 } else if (pfn != spte_to_pfn(*sptep)) {
3009                         pgprintk("hfn old %llx new %llx\n",
3010                                  spte_to_pfn(*sptep), pfn);
3011                         drop_spte(vcpu->kvm, sptep);
3012                         flush = true;
3013                 } else
3014                         was_rmapped = 1;
3015         }
3016 
3017         set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3018                                 speculative, true, host_writable);
3019         if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3020                 if (write_fault)
3021                         ret = RET_PF_EMULATE;
3022                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3023         }
3024 
3025         if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3026                 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3027                                 KVM_PAGES_PER_HPAGE(level));
3028 
3029         if (unlikely(is_mmio_spte(*sptep)))
3030                 ret = RET_PF_EMULATE;
3031 
3032         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3033         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
3034                  is_large_pte(*sptep)? "2MB" : "4kB",
3035                  *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
3036                  *sptep, sptep);
3037         if (!was_rmapped && is_large_pte(*sptep))
3038                 ++vcpu->kvm->stat.lpages;
3039 
3040         if (is_shadow_present_pte(*sptep)) {
3041                 if (!was_rmapped) {
3042                         rmap_count = rmap_add(vcpu, sptep, gfn);
3043                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3044                                 rmap_recycle(vcpu, sptep, gfn);
3045                 }
3046         }
3047 
3048         kvm_release_pfn_clean(pfn);
3049 
3050         return ret;
3051 }
3052 
3053 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3054                                      bool no_dirty_log)
3055 {
3056         struct kvm_memory_slot *slot;
3057 
3058         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3059         if (!slot)
3060                 return KVM_PFN_ERR_FAULT;
3061 
3062         return gfn_to_pfn_memslot_atomic(slot, gfn);
3063 }
3064 
3065 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3066                                     struct kvm_mmu_page *sp,
3067                                     u64 *start, u64 *end)
3068 {
3069         struct page *pages[PTE_PREFETCH_NUM];
3070         struct kvm_memory_slot *slot;
3071         unsigned access = sp->role.access;
3072         int i, ret;
3073         gfn_t gfn;
3074 
3075         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3076         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3077         if (!slot)
3078                 return -1;
3079 
3080         ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3081         if (ret <= 0)
3082                 return -1;
3083 
3084         for (i = 0; i < ret; i++, gfn++, start++)
3085                 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3086                              page_to_pfn(pages[i]), true, true);
3087 
3088         return 0;
3089 }
3090 
3091 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3092                                   struct kvm_mmu_page *sp, u64 *sptep)
3093 {
3094         u64 *spte, *start = NULL;
3095         int i;
3096 
3097         WARN_ON(!sp->role.direct);
3098 
3099         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3100         spte = sp->spt + i;
3101 
3102         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3103                 if (is_shadow_present_pte(*spte) || spte == sptep) {
3104                         if (!start)
3105                                 continue;
3106                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3107                                 break;
3108                         start = NULL;
3109                 } else if (!start)
3110                         start = spte;
3111         }
3112 }
3113 
3114 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3115 {
3116         struct kvm_mmu_page *sp;
3117 
3118         sp = page_header(__pa(sptep));
3119 
3120         /*
3121          * Without accessed bits, there's no way to distinguish between
3122          * actually accessed translations and prefetched, so disable pte
3123          * prefetch if accessed bits aren't available.
3124          */
3125         if (sp_ad_disabled(sp))
3126                 return;
3127 
3128         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3129                 return;
3130 
3131         __direct_pte_prefetch(vcpu, sp, sptep);
3132 }
3133 
3134 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
3135                         int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
3136 {
3137         struct kvm_shadow_walk_iterator iterator;
3138         struct kvm_mmu_page *sp;
3139         int emulate = 0;
3140         gfn_t pseudo_gfn;
3141 
3142         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3143                 return 0;
3144 
3145         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
3146                 if (iterator.level == level) {
3147                         emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
3148                                                write, level, gfn, pfn, prefault,
3149                                                map_writable);
3150                         direct_pte_prefetch(vcpu, iterator.sptep);
3151                         ++vcpu->stat.pf_fixed;
3152                         break;
3153                 }
3154 
3155                 drop_large_spte(vcpu, iterator.sptep);
3156                 if (!is_shadow_present_pte(*iterator.sptep)) {
3157                         u64 base_addr = iterator.addr;
3158 
3159                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
3160                         pseudo_gfn = base_addr >> PAGE_SHIFT;
3161                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
3162                                               iterator.level - 1, 1, ACC_ALL);
3163 
3164                         link_shadow_page(vcpu, iterator.sptep, sp);
3165                 }
3166         }
3167         return emulate;
3168 }
3169 
3170 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3171 {
3172         send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3173 }
3174 
3175 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3176 {
3177         /*
3178          * Do not cache the mmio info caused by writing the readonly gfn
3179          * into the spte otherwise read access on readonly gfn also can
3180          * caused mmio page fault and treat it as mmio access.
3181          */
3182         if (pfn == KVM_PFN_ERR_RO_FAULT)
3183                 return RET_PF_EMULATE;
3184 
3185         if (pfn == KVM_PFN_ERR_HWPOISON) {
3186                 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3187                 return RET_PF_RETRY;
3188         }
3189 
3190         return -EFAULT;
3191 }
3192 
3193 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3194                                         gfn_t *gfnp, kvm_pfn_t *pfnp,
3195                                         int *levelp)
3196 {
3197         kvm_pfn_t pfn = *pfnp;
3198         gfn_t gfn = *gfnp;
3199         int level = *levelp;
3200 
3201         /*
3202          * Check if it's a transparent hugepage. If this would be an
3203          * hugetlbfs page, level wouldn't be set to
3204          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3205          * here.
3206          */
3207         if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3208             level == PT_PAGE_TABLE_LEVEL &&
3209             PageTransCompoundMap(pfn_to_page(pfn)) &&
3210             !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3211                 unsigned long mask;
3212                 /*
3213                  * mmu_notifier_retry was successful and we hold the
3214                  * mmu_lock here, so the pmd can't become splitting
3215                  * from under us, and in turn
3216                  * __split_huge_page_refcount() can't run from under
3217                  * us and we can safely transfer the refcount from
3218                  * PG_tail to PG_head as we switch the pfn to tail to
3219                  * head.
3220                  */
3221                 *levelp = level = PT_DIRECTORY_LEVEL;
3222                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3223                 VM_BUG_ON((gfn & mask) != (pfn & mask));
3224                 if (pfn & mask) {
3225                         gfn &= ~mask;
3226                         *gfnp = gfn;
3227                         kvm_release_pfn_clean(pfn);
3228                         pfn &= ~mask;
3229                         kvm_get_pfn(pfn);
3230                         *pfnp = pfn;
3231                 }
3232         }
3233 }
3234 
3235 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3236                                 kvm_pfn_t pfn, unsigned access, int *ret_val)
3237 {
3238         /* The pfn is invalid, report the error! */
3239         if (unlikely(is_error_pfn(pfn))) {
3240                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3241                 return true;
3242         }
3243 
3244         if (unlikely(is_noslot_pfn(pfn)))
3245                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3246 
3247         return false;
3248 }
3249 
3250 static bool page_fault_can_be_fast(u32 error_code)
3251 {
3252         /*
3253          * Do not fix the mmio spte with invalid generation number which
3254          * need to be updated by slow page fault path.
3255          */
3256         if (unlikely(error_code & PFERR_RSVD_MASK))
3257                 return false;
3258 
3259         /* See if the page fault is due to an NX violation */
3260         if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3261                       == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3262                 return false;
3263 
3264         /*
3265          * #PF can be fast if:
3266          * 1. The shadow page table entry is not present, which could mean that
3267          *    the fault is potentially caused by access tracking (if enabled).
3268          * 2. The shadow page table entry is present and the fault
3269          *    is caused by write-protect, that means we just need change the W
3270          *    bit of the spte which can be done out of mmu-lock.
3271          *
3272          * However, if access tracking is disabled we know that a non-present
3273          * page must be a genuine page fault where we have to create a new SPTE.
3274          * So, if access tracking is disabled, we return true only for write
3275          * accesses to a present page.
3276          */
3277 
3278         return shadow_acc_track_mask != 0 ||
3279                ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3280                 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3281 }
3282 
3283 /*
3284  * Returns true if the SPTE was fixed successfully. Otherwise,
3285  * someone else modified the SPTE from its original value.
3286  */
3287 static bool
3288 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3289                         u64 *sptep, u64 old_spte, u64 new_spte)
3290 {
3291         gfn_t gfn;
3292 
3293         WARN_ON(!sp->role.direct);
3294 
3295         /*
3296          * Theoretically we could also set dirty bit (and flush TLB) here in
3297          * order to eliminate unnecessary PML logging. See comments in
3298          * set_spte. But fast_page_fault is very unlikely to happen with PML
3299          * enabled, so we do not do this. This might result in the same GPA
3300          * to be logged in PML buffer again when the write really happens, and
3301          * eventually to be called by mark_page_dirty twice. But it's also no
3302          * harm. This also avoids the TLB flush needed after setting dirty bit
3303          * so non-PML cases won't be impacted.
3304          *
3305          * Compare with set_spte where instead shadow_dirty_mask is set.
3306          */
3307         if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3308                 return false;
3309 
3310         if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3311                 /*
3312                  * The gfn of direct spte is stable since it is
3313                  * calculated by sp->gfn.
3314                  */
3315                 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3316                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3317         }
3318 
3319         return true;
3320 }
3321 
3322 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3323 {
3324         if (fault_err_code & PFERR_FETCH_MASK)
3325                 return is_executable_pte(spte);
3326 
3327         if (fault_err_code & PFERR_WRITE_MASK)
3328                 return is_writable_pte(spte);
3329 
3330         /* Fault was on Read access */
3331         return spte & PT_PRESENT_MASK;
3332 }
3333 
3334 /*
3335  * Return value:
3336  * - true: let the vcpu to access on the same address again.
3337  * - false: let the real page fault path to fix it.
3338  */
3339 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3340                             u32 error_code)
3341 {
3342         struct kvm_shadow_walk_iterator iterator;
3343         struct kvm_mmu_page *sp;
3344         bool fault_handled = false;
3345         u64 spte = 0ull;
3346         uint retry_count = 0;
3347 
3348         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3349                 return false;
3350 
3351         if (!page_fault_can_be_fast(error_code))
3352                 return false;
3353 
3354         walk_shadow_page_lockless_begin(vcpu);
3355 
3356         do {
3357                 u64 new_spte;
3358 
3359                 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3360                         if (!is_shadow_present_pte(spte) ||
3361                             iterator.level < level)
3362                                 break;
3363 
3364                 sp = page_header(__pa(iterator.sptep));
3365                 if (!is_last_spte(spte, sp->role.level))
3366                         break;
3367 
3368                 /*
3369                  * Check whether the memory access that caused the fault would
3370                  * still cause it if it were to be performed right now. If not,
3371                  * then this is a spurious fault caused by TLB lazily flushed,
3372                  * or some other CPU has already fixed the PTE after the
3373                  * current CPU took the fault.
3374                  *
3375                  * Need not check the access of upper level table entries since
3376                  * they are always ACC_ALL.
3377                  */
3378                 if (is_access_allowed(error_code, spte)) {
3379                         fault_handled = true;
3380                         break;
3381                 }
3382 
3383                 new_spte = spte;
3384 
3385                 if (is_access_track_spte(spte))
3386                         new_spte = restore_acc_track_spte(new_spte);
3387 
3388                 /*
3389                  * Currently, to simplify the code, write-protection can
3390                  * be removed in the fast path only if the SPTE was
3391                  * write-protected for dirty-logging or access tracking.
3392                  */
3393                 if ((error_code & PFERR_WRITE_MASK) &&
3394                     spte_can_locklessly_be_made_writable(spte))
3395                 {
3396                         new_spte |= PT_WRITABLE_MASK;
3397 
3398                         /*
3399                          * Do not fix write-permission on the large spte.  Since
3400                          * we only dirty the first page into the dirty-bitmap in
3401                          * fast_pf_fix_direct_spte(), other pages are missed
3402                          * if its slot has dirty logging enabled.
3403                          *
3404                          * Instead, we let the slow page fault path create a
3405                          * normal spte to fix the access.
3406                          *
3407                          * See the comments in kvm_arch_commit_memory_region().
3408                          */
3409                         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3410                                 break;
3411                 }
3412 
3413                 /* Verify that the fault can be handled in the fast path */
3414                 if (new_spte == spte ||
3415                     !is_access_allowed(error_code, new_spte))
3416                         break;
3417 
3418                 /*
3419                  * Currently, fast page fault only works for direct mapping
3420                  * since the gfn is not stable for indirect shadow page. See
3421                  * Documentation/virtual/kvm/locking.txt to get more detail.
3422                  */
3423                 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3424                                                         iterator.sptep, spte,
3425                                                         new_spte);
3426                 if (fault_handled)
3427                         break;
3428 
3429                 if (++retry_count > 4) {
3430                         printk_once(KERN_WARNING
3431                                 "kvm: Fast #PF retrying more than 4 times.\n");
3432                         break;
3433                 }
3434 
3435         } while (true);
3436 
3437         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3438                               spte, fault_handled);
3439         walk_shadow_page_lockless_end(vcpu);
3440 
3441         return fault_handled;
3442 }
3443 
3444 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3445                          gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3446 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3447 
3448 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3449                          gfn_t gfn, bool prefault)
3450 {
3451         int r;
3452         int level;
3453         bool force_pt_level = false;
3454         kvm_pfn_t pfn;
3455         unsigned long mmu_seq;
3456         bool map_writable, write = error_code & PFERR_WRITE_MASK;
3457 
3458         level = mapping_level(vcpu, gfn, &force_pt_level);
3459         if (likely(!force_pt_level)) {
3460                 /*
3461                  * This path builds a PAE pagetable - so we can map
3462                  * 2mb pages at maximum. Therefore check if the level
3463                  * is larger than that.
3464                  */
3465                 if (level > PT_DIRECTORY_LEVEL)
3466                         level = PT_DIRECTORY_LEVEL;
3467 
3468                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3469         }
3470 
3471         if (fast_page_fault(vcpu, v, level, error_code))
3472                 return RET_PF_RETRY;
3473 
3474         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3475         smp_rmb();
3476 
3477         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3478                 return RET_PF_RETRY;
3479 
3480         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3481                 return r;
3482 
3483         spin_lock(&vcpu->kvm->mmu_lock);
3484         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3485                 goto out_unlock;
3486         if (make_mmu_pages_available(vcpu) < 0)
3487                 goto out_unlock;
3488         if (likely(!force_pt_level))
3489                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3490         r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3491         spin_unlock(&vcpu->kvm->mmu_lock);
3492 
3493         return r;
3494 
3495 out_unlock:
3496         spin_unlock(&vcpu->kvm->mmu_lock);
3497         kvm_release_pfn_clean(pfn);
3498         return RET_PF_RETRY;
3499 }
3500 
3501 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3502                                struct list_head *invalid_list)
3503 {
3504         struct kvm_mmu_page *sp;
3505 
3506         if (!VALID_PAGE(*root_hpa))
3507                 return;
3508 
3509         sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3510         --sp->root_count;
3511         if (!sp->root_count && sp->role.invalid)
3512                 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3513 
3514         *root_hpa = INVALID_PAGE;
3515 }
3516 
3517 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3518 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3519                         ulong roots_to_free)
3520 {
3521         int i;
3522         LIST_HEAD(invalid_list);
3523         bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3524 
3525         BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3526 
3527         /* Before acquiring the MMU lock, see if we need to do any real work. */
3528         if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3529                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3530                         if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3531                             VALID_PAGE(mmu->prev_roots[i].hpa))
3532                                 break;
3533 
3534                 if (i == KVM_MMU_NUM_PREV_ROOTS)
3535                         return;
3536         }
3537 
3538         spin_lock(&vcpu->kvm->mmu_lock);
3539 
3540         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3541                 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3542                         mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3543                                            &invalid_list);
3544 
3545         if (free_active_root) {
3546                 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3547                     (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3548                         mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3549                                            &invalid_list);
3550                 } else {
3551                         for (i = 0; i < 4; ++i)
3552                                 if (mmu->pae_root[i] != 0)
3553                                         mmu_free_root_page(vcpu->kvm,
3554                                                            &mmu->pae_root[i],
3555                                                            &invalid_list);
3556                         mmu->root_hpa = INVALID_PAGE;
3557                 }
3558                 mmu->root_cr3 = 0;
3559         }
3560 
3561         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3562         spin_unlock(&vcpu->kvm->mmu_lock);
3563 }
3564 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3565 
3566 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3567 {
3568         int ret = 0;
3569 
3570         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3571                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3572                 ret = 1;
3573         }
3574 
3575         return ret;
3576 }
3577 
3578 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3579 {
3580         struct kvm_mmu_page *sp;
3581         unsigned i;
3582 
3583         if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3584                 spin_lock(&vcpu->kvm->mmu_lock);
3585                 if(make_mmu_pages_available(vcpu) < 0) {
3586                         spin_unlock(&vcpu->kvm->mmu_lock);
3587                         return -ENOSPC;
3588                 }
3589                 sp = kvm_mmu_get_page(vcpu, 0, 0,
3590                                 vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
3591                 ++sp->root_count;
3592                 spin_unlock(&vcpu->kvm->mmu_lock);
3593                 vcpu->arch.mmu->root_hpa = __pa(sp->spt);
3594         } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) {
3595                 for (i = 0; i < 4; ++i) {
3596                         hpa_t root = vcpu->arch.mmu->pae_root[i];
3597 
3598                         MMU_WARN_ON(VALID_PAGE(root));
3599                         spin_lock(&vcpu->kvm->mmu_lock);
3600                         if (make_mmu_pages_available(vcpu) < 0) {
3601                                 spin_unlock(&vcpu->kvm->mmu_lock);
3602                                 return -ENOSPC;
3603                         }
3604                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3605                                         i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3606                         root = __pa(sp->spt);
3607                         ++sp->root_count;
3608                         spin_unlock(&vcpu->kvm->mmu_lock);
3609                         vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3610                 }
3611                 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3612         } else
3613                 BUG();
3614         vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3615 
3616         return 0;
3617 }
3618 
3619 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3620 {
3621         struct kvm_mmu_page *sp;
3622         u64 pdptr, pm_mask;
3623         gfn_t root_gfn, root_cr3;
3624         int i;
3625 
3626         root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3627         root_gfn = root_cr3 >> PAGE_SHIFT;
3628 
3629         if (mmu_check_root(vcpu, root_gfn))
3630                 return 1;
3631 
3632         /*
3633          * Do we shadow a long mode page table? If so we need to
3634          * write-protect the guests page table root.
3635          */
3636         if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3637                 hpa_t root = vcpu->arch.mmu->root_hpa;
3638 
3639                 MMU_WARN_ON(VALID_PAGE(root));
3640 
3641                 spin_lock(&vcpu->kvm->mmu_lock);
3642                 if (make_mmu_pages_available(vcpu) < 0) {
3643                         spin_unlock(&vcpu->kvm->mmu_lock);
3644                         return -ENOSPC;
3645                 }
3646                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3647                                 vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
3648                 root = __pa(sp->spt);
3649                 ++sp->root_count;
3650                 spin_unlock(&vcpu->kvm->mmu_lock);
3651                 vcpu->arch.mmu->root_hpa = root;
3652                 goto set_root_cr3;
3653         }
3654 
3655         /*
3656          * We shadow a 32 bit page table. This may be a legacy 2-level
3657          * or a PAE 3-level page table. In either case we need to be aware that
3658          * the shadow page table may be a PAE or a long mode page table.
3659          */
3660         pm_mask = PT_PRESENT_MASK;
3661         if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3662                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3663 
3664         for (i = 0; i < 4; ++i) {
3665                 hpa_t root = vcpu->arch.mmu->pae_root[i];
3666 
3667                 MMU_WARN_ON(VALID_PAGE(root));
3668                 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3669                         pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3670                         if (!(pdptr & PT_PRESENT_MASK)) {
3671                                 vcpu->arch.mmu->pae_root[i] = 0;
3672                                 continue;
3673                         }
3674                         root_gfn = pdptr >> PAGE_SHIFT;
3675                         if (mmu_check_root(vcpu, root_gfn))
3676                                 return 1;
3677                 }
3678                 spin_lock(&vcpu->kvm->mmu_lock);
3679                 if (make_mmu_pages_available(vcpu) < 0) {
3680                         spin_unlock(&vcpu->kvm->mmu_lock);
3681                         return -ENOSPC;
3682                 }
3683                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3684                                       0, ACC_ALL);
3685                 root = __pa(sp->spt);
3686                 ++sp->root_count;
3687                 spin_unlock(&vcpu->kvm->mmu_lock);
3688 
3689                 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3690         }
3691         vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3692 
3693         /*
3694          * If we shadow a 32 bit page table with a long mode page
3695          * table we enter this path.
3696          */
3697         if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3698                 if (vcpu->arch.mmu->lm_root == NULL) {
3699                         /*
3700                          * The additional page necessary for this is only
3701                          * allocated on demand.
3702                          */
3703 
3704                         u64 *lm_root;
3705 
3706                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3707                         if (lm_root == NULL)
3708                                 return 1;
3709 
3710                         lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3711 
3712                         vcpu->arch.mmu->lm_root = lm_root;
3713                 }
3714 
3715                 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3716         }
3717 
3718 set_root_cr3:
3719         vcpu->arch.mmu->root_cr3 = root_cr3;
3720 
3721         return 0;
3722 }
3723 
3724 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3725 {
3726         if (vcpu->arch.mmu->direct_map)
3727                 return mmu_alloc_direct_roots(vcpu);
3728         else
3729                 return mmu_alloc_shadow_roots(vcpu);
3730 }
3731 
3732 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3733 {
3734         int i;
3735         struct kvm_mmu_page *sp;
3736 
3737         if (vcpu->arch.mmu->direct_map)
3738                 return;
3739 
3740         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3741                 return;
3742 
3743         vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3744 
3745         if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3746                 hpa_t root = vcpu->arch.mmu->root_hpa;
3747                 sp = page_header(root);
3748 
3749                 /*
3750                  * Even if another CPU was marking the SP as unsync-ed
3751                  * simultaneously, any guest page table changes are not
3752                  * guaranteed to be visible anyway until this VCPU issues a TLB
3753                  * flush strictly after those changes are made. We only need to
3754                  * ensure that the other CPU sets these flags before any actual
3755                  * changes to the page tables are made. The comments in
3756                  * mmu_need_write_protect() describe what could go wrong if this
3757                  * requirement isn't satisfied.
3758                  */
3759                 if (!smp_load_acquire(&sp->unsync) &&
3760                     !smp_load_acquire(&sp->unsync_children))
3761                         return;
3762 
3763                 spin_lock(&vcpu->kvm->mmu_lock);
3764                 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3765 
3766                 mmu_sync_children(vcpu, sp);
3767 
3768                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3769                 spin_unlock(&vcpu->kvm->mmu_lock);
3770                 return;
3771         }
3772 
3773         spin_lock(&vcpu->kvm->mmu_lock);
3774         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3775 
3776         for (i = 0; i < 4; ++i) {
3777                 hpa_t root = vcpu->arch.mmu->pae_root[i];
3778 
3779                 if (root && VALID_PAGE(root)) {
3780                         root &= PT64_BASE_ADDR_MASK;
3781                         sp = page_header(root);
3782                         mmu_sync_children(vcpu, sp);
3783                 }
3784         }
3785 
3786         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3787         spin_unlock(&vcpu->kvm->mmu_lock);
3788 }
3789 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3790 
3791 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3792                                   u32 access, struct x86_exception *exception)
3793 {
3794         if (exception)
3795                 exception->error_code = 0;
3796         return vaddr;
3797 }
3798 
3799 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3800                                          u32 access,
3801                                          struct x86_exception *exception)
3802 {
3803         if (exception)
3804                 exception->error_code = 0;
3805         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3806 }
3807 
3808 static bool
3809 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3810 {
3811         int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3812 
3813         return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3814                 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3815 }
3816 
3817 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3818 {
3819         return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3820 }
3821 
3822 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3823 {
3824         return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3825 }
3826 
3827 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3828 {
3829         /*
3830          * A nested guest cannot use the MMIO cache if it is using nested
3831          * page tables, because cr2 is a nGPA while the cache stores GPAs.
3832          */
3833         if (mmu_is_nested(vcpu))
3834                 return false;
3835 
3836         if (direct)
3837                 return vcpu_match_mmio_gpa(vcpu, addr);
3838 
3839         return vcpu_match_mmio_gva(vcpu, addr);
3840 }
3841 
3842 /* return true if reserved bit is detected on spte. */
3843 static bool
3844 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3845 {
3846         struct kvm_shadow_walk_iterator iterator;
3847         u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3848         int root, leaf;
3849         bool reserved = false;
3850 
3851         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3852                 goto exit;
3853 
3854         walk_shadow_page_lockless_begin(vcpu);
3855 
3856         for (shadow_walk_init(&iterator, vcpu, addr),
3857                  leaf = root = iterator.level;
3858              shadow_walk_okay(&iterator);
3859              __shadow_walk_next(&iterator, spte)) {
3860                 spte = mmu_spte_get_lockless(iterator.sptep);
3861 
3862                 sptes[leaf - 1] = spte;
3863                 leaf--;
3864 
3865                 if (!is_shadow_present_pte(spte))
3866                         break;
3867 
3868                 reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte,
3869                                                     iterator.level);
3870         }
3871 
3872         walk_shadow_page_lockless_end(vcpu);
3873 
3874         if (reserved) {
3875                 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3876                        __func__, addr);
3877                 while (root > leaf) {
3878                         pr_err("------ spte 0x%llx level %d.\n",
3879                                sptes[root - 1], root);
3880                         root--;
3881                 }
3882         }
3883 exit:
3884         *sptep = spte;
3885         return reserved;
3886 }
3887 
3888 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3889 {
3890         u64 spte;
3891         bool reserved;
3892 
3893         if (mmio_info_in_cache(vcpu, addr, direct))
3894                 return RET_PF_EMULATE;
3895 
3896         reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3897         if (WARN_ON(reserved))
3898                 return -EINVAL;
3899 
3900         if (is_mmio_spte(spte)) {
3901                 gfn_t gfn = get_mmio_spte_gfn(spte);
3902                 unsigned access = get_mmio_spte_access(spte);
3903 
3904                 if (!check_mmio_spte(vcpu, spte))
3905                         return RET_PF_INVALID;
3906 
3907                 if (direct)
3908                         addr = 0;
3909 
3910                 trace_handle_mmio_page_fault(addr, gfn, access);
3911                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3912                 return RET_PF_EMULATE;
3913         }
3914 
3915         /*
3916          * If the page table is zapped by other cpus, let CPU fault again on
3917          * the address.
3918          */
3919         return RET_PF_RETRY;
3920 }
3921 
3922 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3923                                          u32 error_code, gfn_t gfn)
3924 {
3925         if (unlikely(error_code & PFERR_RSVD_MASK))
3926                 return false;
3927 
3928         if (!(error_code & PFERR_PRESENT_MASK) ||
3929               !(error_code & PFERR_WRITE_MASK))
3930                 return false;
3931 
3932         /*
3933          * guest is writing the page which is write tracked which can
3934          * not be fixed by page fault handler.
3935          */
3936         if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3937                 return true;
3938 
3939         return false;
3940 }
3941 
3942 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3943 {
3944         struct kvm_shadow_walk_iterator iterator;
3945         u64 spte;
3946 
3947         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3948                 return;
3949 
3950         walk_shadow_page_lockless_begin(vcpu);
3951         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3952                 clear_sp_write_flooding_count(iterator.sptep);
3953                 if (!is_shadow_present_pte(spte))
3954                         break;
3955         }
3956         walk_shadow_page_lockless_end(vcpu);
3957 }
3958 
3959 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3960                                 u32 error_code, bool prefault)
3961 {
3962         gfn_t gfn = gva >> PAGE_SHIFT;
3963         int r;
3964 
3965         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3966 
3967         if (page_fault_handle_page_track(vcpu, error_code, gfn))
3968                 return RET_PF_EMULATE;
3969 
3970         r = mmu_topup_memory_caches(vcpu);
3971         if (r)
3972                 return r;
3973 
3974         MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
3975 
3976 
3977         return nonpaging_map(vcpu, gva & PAGE_MASK,
3978                              error_code, gfn, prefault);
3979 }
3980 
3981 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3982 {
3983         struct kvm_arch_async_pf arch;
3984 
3985         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3986         arch.gfn = gfn;
3987         arch.direct_map = vcpu->arch.mmu->direct_map;
3988         arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3989 
3990         return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3991 }
3992 
3993 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3994 {
3995         if (unlikely(!lapic_in_kernel(vcpu) ||
3996                      kvm_event_needs_reinjection(vcpu) ||
3997                      vcpu->arch.exception.pending))
3998                 return false;
3999 
4000         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
4001                 return false;
4002 
4003         return kvm_x86_ops->interrupt_allowed(vcpu);
4004 }
4005 
4006 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4007                          gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
4008 {
4009         struct kvm_memory_slot *slot;
4010         bool async;
4011 
4012         /*
4013          * Don't expose private memslots to L2.
4014          */
4015         if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
4016                 *pfn = KVM_PFN_NOSLOT;
4017                 return false;
4018         }
4019 
4020         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4021         async = false;
4022         *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4023         if (!async)
4024                 return false; /* *pfn has correct page already */
4025 
4026         if (!prefault && kvm_can_do_async_pf(vcpu)) {
4027                 trace_kvm_try_async_get_page(gva, gfn);
4028                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4029                         trace_kvm_async_pf_doublefault(gva, gfn);
4030                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4031                         return true;
4032                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
4033                         return true;
4034         }
4035 
4036         *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4037         return false;
4038 }
4039 
4040 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4041                                 u64 fault_address, char *insn, int insn_len)
4042 {
4043         int r = 1;
4044 
4045         vcpu->arch.l1tf_flush_l1d = true;
4046         switch (vcpu->arch.apf.host_apf_reason) {
4047         default:
4048                 trace_kvm_page_fault(fault_address, error_code);
4049 
4050                 if (kvm_event_needs_reinjection(vcpu))
4051                         kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4052                 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4053                                 insn_len);
4054                 break;
4055         case KVM_PV_REASON_PAGE_NOT_PRESENT:
4056                 vcpu->arch.apf.host_apf_reason = 0;
4057                 local_irq_disable();
4058                 kvm_async_pf_task_wait(fault_address, 0);
4059                 local_irq_enable();
4060                 break;
4061         case KVM_PV_REASON_PAGE_READY:
4062                 vcpu->arch.apf.host_apf_reason = 0;
4063                 local_irq_disable();
4064                 kvm_async_pf_task_wake(fault_address);
4065                 local_irq_enable();
4066                 break;
4067         }
4068         return r;
4069 }
4070 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4071 
4072 static bool
4073 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
4074 {
4075         int page_num = KVM_PAGES_PER_HPAGE(level);
4076 
4077         gfn &= ~(page_num - 1);
4078 
4079         return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
4080 }
4081 
4082 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
4083                           bool prefault)
4084 {
4085         kvm_pfn_t pfn;
4086         int r;
4087         int level;
4088         bool force_pt_level;
4089         gfn_t gfn = gpa >> PAGE_SHIFT;
4090         unsigned long mmu_seq;
4091         int write = error_code & PFERR_WRITE_MASK;
4092         bool map_writable;
4093 
4094         MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4095 
4096         if (page_fault_handle_page_track(vcpu, error_code, gfn))
4097                 return RET_PF_EMULATE;
4098 
4099         r = mmu_topup_memory_caches(vcpu);
4100         if (r)
4101                 return r;
4102 
4103         force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
4104                                                            PT_DIRECTORY_LEVEL);
4105         level = mapping_level(vcpu, gfn, &force_pt_level);
4106         if (likely(!force_pt_level)) {
4107                 if (level > PT_DIRECTORY_LEVEL &&
4108                     !check_hugepage_cache_consistency(vcpu, gfn, level))
4109                         level = PT_DIRECTORY_LEVEL;
4110                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4111         }
4112 
4113         if (fast_page_fault(vcpu, gpa, level, error_code))
4114                 return RET_PF_RETRY;
4115 
4116         mmu_seq = vcpu->kvm->mmu_notifier_seq;
4117         smp_rmb();
4118 
4119         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4120                 return RET_PF_RETRY;
4121 
4122         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4123                 return r;
4124 
4125         spin_lock(&vcpu->kvm->mmu_lock);
4126         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4127                 goto out_unlock;
4128         if (make_mmu_pages_available(vcpu) < 0)
4129                 goto out_unlock;
4130         if (likely(!force_pt_level))
4131                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
4132         r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
4133         spin_unlock(&vcpu->kvm->mmu_lock);
4134 
4135         return r;
4136 
4137 out_unlock:
4138         spin_unlock(&vcpu->kvm->mmu_lock);
4139         kvm_release_pfn_clean(pfn);
4140         return RET_PF_RETRY;
4141 }
4142 
4143 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4144                                    struct kvm_mmu *context)
4145 {
4146         context->page_fault = nonpaging_page_fault;
4147         context->gva_to_gpa = nonpaging_gva_to_gpa;
4148         context->sync_page = nonpaging_sync_page;
4149         context->invlpg = nonpaging_invlpg;
4150         context->update_pte = nonpaging_update_pte;
4151         context->root_level = 0;
4152         context->shadow_root_level = PT32E_ROOT_LEVEL;
4153         context->direct_map = true;
4154         context->nx = false;
4155 }
4156 
4157 /*
4158  * Find out if a previously cached root matching the new CR3/role is available.
4159  * The current root is also inserted into the cache.
4160  * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4161  * returned.
4162  * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4163  * false is returned. This root should now be freed by the caller.
4164  */
4165 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4166                                   union kvm_mmu_page_role new_role)
4167 {
4168         uint i;
4169         struct kvm_mmu_root_info root;
4170         struct kvm_mmu *mmu = vcpu->arch.mmu;
4171 
4172         root.cr3 = mmu->root_cr3;
4173         root.hpa = mmu->root_hpa;
4174 
4175         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4176                 swap(root, mmu->prev_roots[i]);
4177 
4178                 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4179                     page_header(root.hpa) != NULL &&
4180                     new_role.word == page_header(root.hpa)->role.word)
4181                         break;
4182         }
4183 
4184         mmu->root_hpa = root.hpa;
4185         mmu->root_cr3 = root.cr3;
4186 
4187         return i < KVM_MMU_NUM_PREV_ROOTS;
4188 }
4189 
4190 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4191                             union kvm_mmu_page_role new_role,
4192                             bool skip_tlb_flush)
4193 {
4194         struct kvm_mmu *mmu = vcpu->arch.mmu;
4195 
4196         /*
4197          * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4198          * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4199          * later if necessary.
4200          */
4201         if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4202             mmu->root_level >= PT64_ROOT_4LEVEL) {
4203                 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4204                         return false;
4205 
4206                 if (cached_root_available(vcpu, new_cr3, new_role)) {
4207                         /*
4208                          * It is possible that the cached previous root page is
4209                          * obsolete because of a change in the MMU
4210                          * generation number. However, that is accompanied by
4211                          * KVM_REQ_MMU_RELOAD, which will free the root that we
4212                          * have set here and allocate a new one.
4213                          */
4214 
4215                         kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4216                         if (!skip_tlb_flush) {
4217                                 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4218                                 kvm_x86_ops->tlb_flush(vcpu, true);
4219                         }
4220 
4221                         /*
4222                          * The last MMIO access's GVA and GPA are cached in the
4223                          * VCPU. When switching to a new CR3, that GVA->GPA
4224                          * mapping may no longer be valid. So clear any cached
4225                          * MMIO info even when we don't need to sync the shadow
4226                          * page tables.
4227                          */
4228                         vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4229 
4230                         __clear_sp_write_flooding_count(
4231                                 page_header(mmu->root_hpa));
4232 
4233                         return true;
4234                 }
4235         }
4236 
4237         return false;
4238 }
4239 
4240 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4241                               union kvm_mmu_page_role new_role,
4242                               bool skip_tlb_flush)
4243 {
4244         if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4245                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu,
4246                                    KVM_MMU_ROOT_CURRENT);
4247 }
4248 
4249 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4250 {
4251         __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4252                           skip_tlb_flush);
4253 }
4254 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4255 
4256 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4257 {
4258         return kvm_read_cr3(vcpu);
4259 }
4260 
4261 static void inject_page_fault(struct kvm_vcpu *vcpu,
4262                               struct x86_exception *fault)
4263 {
4264         vcpu->arch.mmu->inject_page_fault(vcpu, fault);
4265 }
4266 
4267 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4268                            unsigned access, int *nr_present)
4269 {
4270         if (unlikely(is_mmio_spte(*sptep))) {
4271                 if (gfn != get_mmio_spte_gfn(*sptep)) {
4272                         mmu_spte_clear_no_track(sptep);
4273                         return true;
4274                 }
4275 
4276                 (*nr_present)++;
4277                 mark_mmio_spte(vcpu, sptep, gfn, access);
4278                 return true;
4279         }
4280 
4281         return false;
4282 }
4283 
4284 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4285                                 unsigned level, unsigned gpte)
4286 {
4287         /*
4288          * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4289          * If it is clear, there are no large pages at this level, so clear
4290          * PT_PAGE_SIZE_MASK in gpte if that is the case.
4291          */
4292         gpte &= level - mmu->last_nonleaf_level;
4293 
4294         /*
4295          * PT_PAGE_TABLE_LEVEL always terminates.  The RHS has bit 7 set
4296          * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4297          * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4298          */
4299         gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4300 
4301         return gpte & PT_PAGE_SIZE_MASK;
4302 }
4303 
4304 #define PTTYPE_EPT 18 /* arbitrary */
4305 #define PTTYPE PTTYPE_EPT
4306 #include "paging_tmpl.h"
4307 #undef PTTYPE
4308 
4309 #define PTTYPE 64
4310 #include "paging_tmpl.h"
4311 #undef PTTYPE
4312 
4313 #define PTTYPE 32
4314 #include "paging_tmpl.h"
4315 #undef PTTYPE
4316 
4317 static void
4318 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4319                         struct rsvd_bits_validate *rsvd_check,
4320                         int maxphyaddr, int level, bool nx, bool gbpages,
4321                         bool pse, bool amd)
4322 {
4323         u64 exb_bit_rsvd = 0;
4324         u64 gbpages_bit_rsvd = 0;
4325         u64 nonleaf_bit8_rsvd = 0;
4326 
4327         rsvd_check->bad_mt_xwr = 0;
4328 
4329         if (!nx)
4330                 exb_bit_rsvd = rsvd_bits(63, 63);
4331         if (!gbpages)
4332                 gbpages_bit_rsvd = rsvd_bits(7, 7);
4333 
4334         /*
4335          * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4336          * leaf entries) on AMD CPUs only.
4337          */
4338         if (amd)
4339                 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4340 
4341         switch (level) {
4342         case PT32_ROOT_LEVEL:
4343                 /* no rsvd bits for 2 level 4K page table entries */
4344                 rsvd_check->rsvd_bits_mask[0][1] = 0;
4345                 rsvd_check->rsvd_bits_mask[0][0] = 0;
4346                 rsvd_check->rsvd_bits_mask[1][0] =
4347                         rsvd_check->rsvd_bits_mask[0][0];
4348 
4349                 if (!pse) {
4350                         rsvd_check->rsvd_bits_mask[1][1] = 0;
4351                         break;
4352                 }
4353 
4354                 if (is_cpuid_PSE36())
4355                         /* 36bits PSE 4MB page */
4356                         rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4357                 else
4358                         /* 32 bits PSE 4MB page */
4359                         rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4360                 break;
4361         case PT32E_ROOT_LEVEL:
4362                 rsvd_check->rsvd_bits_mask[0][2] =
4363                         rsvd_bits(maxphyaddr, 63) |
4364                         rsvd_bits(5, 8) | rsvd_bits(1, 2);      /* PDPTE */
4365                 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4366                         rsvd_bits(maxphyaddr, 62);      /* PDE */
4367                 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4368                         rsvd_bits(maxphyaddr, 62);      /* PTE */
4369                 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4370                         rsvd_bits(maxphyaddr, 62) |
4371                         rsvd_bits(13, 20);              /* large page */
4372                 rsvd_check->rsvd_bits_mask[1][0] =
4373                         rsvd_check->rsvd_bits_mask[0][0];
4374                 break;
4375         case PT64_ROOT_5LEVEL:
4376                 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4377                         nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4378                         rsvd_bits(maxphyaddr, 51);
4379                 rsvd_check->rsvd_bits_mask[1][4] =
4380                         rsvd_check->rsvd_bits_mask[0][4];
4381                 /* fall through */
4382         case PT64_ROOT_4LEVEL:
4383                 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4384                         nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4385                         rsvd_bits(maxphyaddr, 51);
4386                 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4387                         nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4388                         rsvd_bits(maxphyaddr, 51);
4389                 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4390                         rsvd_bits(maxphyaddr, 51);
4391                 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4392                         rsvd_bits(maxphyaddr, 51);
4393                 rsvd_check->rsvd_bits_mask[1][3] =
4394                         rsvd_check->rsvd_bits_mask[0][3];
4395                 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4396                         gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4397                         rsvd_bits(13, 29);
4398                 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4399                         rsvd_bits(maxphyaddr, 51) |
4400                         rsvd_bits(13, 20);              /* large page */
4401                 rsvd_check->rsvd_bits_mask[1][0] =
4402                         rsvd_check->rsvd_bits_mask[0][0];
4403                 break;
4404         }
4405 }
4406 
4407 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4408                                   struct kvm_mmu *context)
4409 {
4410         __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4411                                 cpuid_maxphyaddr(vcpu), context->root_level,
4412                                 context->nx,
4413                                 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4414                                 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4415 }
4416 
4417 static void
4418 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4419                             int maxphyaddr, bool execonly)
4420 {
4421         u64 bad_mt_xwr;
4422 
4423         rsvd_check->rsvd_bits_mask[0][4] =
4424                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4425         rsvd_check->rsvd_bits_mask[0][3] =
4426                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4427         rsvd_check->rsvd_bits_mask[0][2] =
4428                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4429         rsvd_check->rsvd_bits_mask[0][1] =
4430                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4431         rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4432 
4433         /* large page */
4434         rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4435         rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4436         rsvd_check->rsvd_bits_mask[1][2] =
4437                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4438         rsvd_check->rsvd_bits_mask[1][1] =
4439                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4440         rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4441 
4442         bad_mt_xwr = 0xFFull << (2 * 8);        /* bits 3..5 must not be 2 */
4443         bad_mt_xwr |= 0xFFull << (3 * 8);       /* bits 3..5 must not be 3 */
4444         bad_mt_xwr |= 0xFFull << (7 * 8);       /* bits 3..5 must not be 7 */
4445         bad_mt_xwr |= REPEAT_BYTE(1ull << 2);   /* bits 0..2 must not be 010 */
4446         bad_mt_xwr |= REPEAT_BYTE(1ull << 6);   /* bits 0..2 must not be 110 */
4447         if (!execonly) {
4448                 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4449                 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4450         }
4451         rsvd_check->bad_mt_xwr = bad_mt_xwr;
4452 }
4453 
4454 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4455                 struct kvm_mmu *context, bool execonly)
4456 {
4457         __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4458                                     cpuid_maxphyaddr(vcpu), execonly);
4459 }
4460 
4461 /*
4462  * the page table on host is the shadow page table for the page
4463  * table in guest or amd nested guest, its mmu features completely
4464  * follow the features in guest.
4465  */
4466 void
4467 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4468 {
4469         bool uses_nx = context->nx ||
4470                 context->mmu_role.base.smep_andnot_wp;
4471         struct rsvd_bits_validate *shadow_zero_check;
4472         int i;
4473 
4474         /*
4475          * Passing "true" to the last argument is okay; it adds a check
4476          * on bit 8 of the SPTEs which KVM doesn't use anyway.
4477          */
4478         shadow_zero_check = &context->shadow_zero_check;
4479         __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4480                                 boot_cpu_data.x86_phys_bits,
4481                                 context->shadow_root_level, uses_nx,
4482                                 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4483                                 is_pse(vcpu), true);
4484 
4485         if (!shadow_me_mask)
4486                 return;
4487 
4488         for (i = context->shadow_root_level; --i >= 0;) {
4489                 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4490                 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4491         }
4492 
4493 }
4494 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4495 
4496 static inline bool boot_cpu_is_amd(void)
4497 {
4498         WARN_ON_ONCE(!tdp_enabled);
4499         return shadow_x_mask == 0;
4500 }
4501 
4502 /*
4503  * the direct page table on host, use as much mmu features as
4504  * possible, however, kvm currently does not do execution-protection.
4505  */
4506 static void
4507 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4508                                 struct kvm_mmu *context)
4509 {
4510         struct rsvd_bits_validate *shadow_zero_check;
4511         int i;
4512 
4513         shadow_zero_check = &context->shadow_zero_check;
4514 
4515         if (boot_cpu_is_amd())
4516                 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4517                                         boot_cpu_data.x86_phys_bits,
4518                                         context->shadow_root_level, false,
4519                                         boot_cpu_has(X86_FEATURE_GBPAGES),
4520                                         true, true);
4521         else
4522                 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4523                                             boot_cpu_data.x86_phys_bits,
4524                                             false);
4525 
4526         if (!shadow_me_mask)
4527                 return;
4528 
4529         for (i = context->shadow_root_level; --i >= 0;) {
4530                 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4531                 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4532         }
4533 }
4534 
4535 /*
4536  * as the comments in reset_shadow_zero_bits_mask() except it
4537  * is the shadow page table for intel nested guest.
4538  */
4539 static void
4540 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4541                                 struct kvm_mmu *context, bool execonly)
4542 {
4543         __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4544                                     boot_cpu_data.x86_phys_bits, execonly);
4545 }
4546 
4547 #define BYTE_MASK(access) \
4548         ((1 & (access) ? 2 : 0) | \
4549          (2 & (access) ? 4 : 0) | \
4550          (3 & (access) ? 8 : 0) | \
4551          (4 & (access) ? 16 : 0) | \
4552          (5 & (access) ? 32 : 0) | \
4553          (6 & (access) ? 64 : 0) | \
4554          (7 & (access) ? 128 : 0))
4555 
4556 
4557 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4558                                       struct kvm_mmu *mmu, bool ept)
4559 {
4560         unsigned byte;
4561 
4562         const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4563         const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4564         const u8 u = BYTE_MASK(ACC_USER_MASK);
4565 
4566         bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4567         bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4568         bool cr0_wp = is_write_protection(vcpu);
4569 
4570         for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4571                 unsigned pfec = byte << 1;
4572 
4573                 /*
4574                  * Each "*f" variable has a 1 bit for each UWX value
4575                  * that causes a fault with the given PFEC.
4576                  */
4577 
4578                 /* Faults from writes to non-writable pages */
4579                 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4580                 /* Faults from user mode accesses to supervisor pages */
4581                 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4582                 /* Faults from fetches of non-executable pages*/
4583                 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4584                 /* Faults from kernel mode fetches of user pages */
4585                 u8 smepf = 0;
4586                 /* Faults from kernel mode accesses of user pages */
4587                 u8 smapf = 0;
4588 
4589                 if (!ept) {
4590                         /* Faults from kernel mode accesses to user pages */
4591                         u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4592 
4593                         /* Not really needed: !nx will cause pte.nx to fault */
4594                         if (!mmu->nx)
4595                                 ff = 0;
4596 
4597                         /* Allow supervisor writes if !cr0.wp */
4598                         if (!cr0_wp)
4599                                 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4600 
4601                         /* Disallow supervisor fetches of user code if cr4.smep */
4602                         if (cr4_smep)
4603                                 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4604 
4605                         /*
4606                          * SMAP:kernel-mode data accesses from user-mode
4607                          * mappings should fault. A fault is considered
4608                          * as a SMAP violation if all of the following
4609                          * conditions are true:
4610                          *   - X86_CR4_SMAP is set in CR4
4611                          *   - A user page is accessed
4612                          *   - The access is not a fetch
4613                          *   - Page fault in kernel mode
4614                          *   - if CPL = 3 or X86_EFLAGS_AC is clear
4615                          *
4616                          * Here, we cover the first three conditions.
4617                          * The fourth is computed dynamically in permission_fault();
4618                          * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4619                          * *not* subject to SMAP restrictions.
4620                          */
4621                         if (cr4_smap)
4622                                 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4623                 }
4624 
4625                 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4626         }
4627 }
4628 
4629 /*
4630 * PKU is an additional mechanism by which the paging controls access to
4631 * user-mode addresses based on the value in the PKRU register.  Protection
4632 * key violations are reported through a bit in the page fault error code.
4633 * Unlike other bits of the error code, the PK bit is not known at the
4634 * call site of e.g. gva_to_gpa; it must be computed directly in
4635 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4636 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4637 *
4638 * In particular the following conditions come from the error code, the
4639 * page tables and the machine state:
4640 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4641 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4642 * - PK is always zero if U=0 in the page tables
4643 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4644 *
4645 * The PKRU bitmask caches the result of these four conditions.  The error
4646 * code (minus the P bit) and the page table's U bit form an index into the
4647 * PKRU bitmask.  Two bits of the PKRU bitmask are then extracted and ANDed
4648 * with the two bits of the PKRU register corresponding to the protection key.
4649 * For the first three conditions above the bits will be 00, thus masking
4650 * away both AD and WD.  For all reads or if the last condition holds, WD
4651 * only will be masked away.
4652 */
4653 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4654                                 bool ept)
4655 {
4656         unsigned bit;
4657         bool wp;
4658 
4659         if (ept) {
4660                 mmu->pkru_mask = 0;
4661                 return;
4662         }
4663 
4664         /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4665         if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4666                 mmu->pkru_mask = 0;
4667                 return;
4668         }
4669 
4670         wp = is_write_protection(vcpu);
4671 
4672         for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4673                 unsigned pfec, pkey_bits;
4674                 bool check_pkey, check_write, ff, uf, wf, pte_user;
4675 
4676                 pfec = bit << 1;
4677                 ff = pfec & PFERR_FETCH_MASK;
4678                 uf = pfec & PFERR_USER_MASK;
4679                 wf = pfec & PFERR_WRITE_MASK;
4680 
4681                 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4682                 pte_user = pfec & PFERR_RSVD_MASK;
4683 
4684                 /*
4685                  * Only need to check the access which is not an
4686                  * instruction fetch and is to a user page.
4687                  */
4688                 check_pkey = (!ff && pte_user);
4689                 /*
4690                  * write access is controlled by PKRU if it is a
4691                  * user access or CR0.WP = 1.
4692                  */
4693                 check_write = check_pkey && wf && (uf || wp);
4694 
4695                 /* PKRU.AD stops both read and write access. */
4696                 pkey_bits = !!check_pkey;
4697                 /* PKRU.WD stops write access. */
4698                 pkey_bits |= (!!check_write) << 1;
4699 
4700                 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4701         }
4702 }
4703 
4704 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4705 {
4706         unsigned root_level = mmu->root_level;
4707 
4708         mmu->last_nonleaf_level = root_level;
4709         if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4710                 mmu->last_nonleaf_level++;
4711 }
4712 
4713 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4714                                          struct kvm_mmu *context,
4715                                          int level)
4716 {
4717         context->nx = is_nx(vcpu);
4718         context->root_level = level;
4719 
4720         reset_rsvds_bits_mask(vcpu, context);
4721         update_permission_bitmask(vcpu, context, false);
4722         update_pkru_bitmask(vcpu, context, false);
4723         update_last_nonleaf_level(vcpu, context);
4724 
4725         MMU_WARN_ON(!is_pae(vcpu));
4726         context->page_fault = paging64_page_fault;
4727         context->gva_to_gpa = paging64_gva_to_gpa;
4728         context->sync_page = paging64_sync_page;
4729         context->invlpg = paging64_invlpg;
4730         context->update_pte = paging64_update_pte;
4731         context->shadow_root_level = level;
4732         context->direct_map = false;
4733 }
4734 
4735 static void paging64_init_context(struct kvm_vcpu *vcpu,
4736                                   struct kvm_mmu *context)
4737 {
4738         int root_level = is_la57_mode(vcpu) ?
4739                          PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4740 
4741         paging64_init_context_common(vcpu, context, root_level);
4742 }
4743 
4744 static void paging32_init_context(struct kvm_vcpu *vcpu,
4745                                   struct kvm_mmu *context)
4746 {
4747         context->nx = false;
4748         context->root_level = PT32_ROOT_LEVEL;
4749 
4750         reset_rsvds_bits_mask(vcpu, context);
4751         update_permission_bitmask(vcpu, context, false);
4752         update_pkru_bitmask(vcpu, context, false);
4753         update_last_nonleaf_level(vcpu, context);
4754 
4755         context->page_fault = paging32_page_fault;
4756         context->gva_to_gpa = paging32_gva_to_gpa;
4757         context->sync_page = paging32_sync_page;
4758         context->invlpg = paging32_invlpg;
4759         context->update_pte = paging32_update_pte;
4760         context->shadow_root_level = PT32E_ROOT_LEVEL;
4761         context->direct_map = false;
4762 }
4763 
4764 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4765                                    struct kvm_mmu *context)
4766 {
4767         paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4768 }
4769 
4770 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4771 {
4772         union kvm_mmu_extended_role ext = {0};
4773 
4774         ext.cr0_pg = !!is_paging(vcpu);
4775         ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4776         ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4777         ext.cr4_pse = !!is_pse(vcpu);
4778         ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4779         ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4780         ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4781 
4782         ext.valid = 1;
4783 
4784         return ext;
4785 }
4786 
4787 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4788                                                    bool base_only)
4789 {
4790         union kvm_mmu_role role = {0};
4791 
4792         role.base.access = ACC_ALL;
4793         role.base.nxe = !!is_nx(vcpu);
4794         role.base.cr4_pae = !!is_pae(vcpu);
4795         role.base.cr0_wp = is_write_protection(vcpu);
4796         role.base.smm = is_smm(vcpu);
4797         role.base.guest_mode = is_guest_mode(vcpu);
4798 
4799         if (base_only)
4800                 return role;
4801 
4802         role.ext = kvm_calc_mmu_role_ext(vcpu);
4803 
4804         return role;
4805 }
4806 
4807 static union kvm_mmu_role
4808 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4809 {
4810         union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4811 
4812         role.base.ad_disabled = (shadow_accessed_mask == 0);
4813         role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
4814         role.base.direct = true;
4815 
4816         return role;
4817 }
4818 
4819 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4820 {
4821         struct kvm_mmu *context = vcpu->arch.mmu;
4822         union kvm_mmu_role new_role =
4823                 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4824 
4825         new_role.base.word &= mmu_base_role_mask.word;
4826         if (new_role.as_u64 == context->mmu_role.as_u64)
4827                 return;
4828 
4829         context->mmu_role.as_u64 = new_role.as_u64;
4830         context->page_fault = tdp_page_fault;
4831         context->sync_page = nonpaging_sync_page;
4832         context->invlpg = nonpaging_invlpg;
4833         context->update_pte = nonpaging_update_pte;
4834         context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4835         context->direct_map = true;
4836         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4837         context->get_cr3 = get_cr3;
4838         context->get_pdptr = kvm_pdptr_read;
4839         context->inject_page_fault = kvm_inject_page_fault;
4840 
4841         if (!is_paging(vcpu)) {
4842                 context->nx = false;
4843                 context->gva_to_gpa = nonpaging_gva_to_gpa;
4844                 context->root_level = 0;
4845         } else if (is_long_mode(vcpu)) {
4846                 context->nx = is_nx(vcpu);
4847                 context->root_level = is_la57_mode(vcpu) ?
4848                                 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4849                 reset_rsvds_bits_mask(vcpu, context);
4850                 context->gva_to_gpa = paging64_gva_to_gpa;
4851         } else if (is_pae(vcpu)) {
4852                 context->nx = is_nx(vcpu);
4853                 context->root_level = PT32E_ROOT_LEVEL;
4854                 reset_rsvds_bits_mask(vcpu, context);
4855                 context->gva_to_gpa = paging64_gva_to_gpa;
4856         } else {
4857                 context->nx = false;
4858                 context->root_level = PT32_ROOT_LEVEL;
4859                 reset_rsvds_bits_mask(vcpu, context);
4860                 context->gva_to_gpa = paging32_gva_to_gpa;
4861         }
4862 
4863         update_permission_bitmask(vcpu, context, false);
4864         update_pkru_bitmask(vcpu, context, false);
4865         update_last_nonleaf_level(vcpu, context);
4866         reset_tdp_shadow_zero_bits_mask(vcpu, context);
4867 }
4868 
4869 static union kvm_mmu_role
4870 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4871 {
4872         union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4873 
4874         role.base.smep_andnot_wp = role.ext.cr4_smep &&
4875                 !is_write_protection(vcpu);
4876         role.base.smap_andnot_wp = role.ext.cr4_smap &&
4877                 !is_write_protection(vcpu);
4878         role.base.direct = !is_paging(vcpu);
4879 
4880         if (!is_long_mode(vcpu))
4881                 role.base.level = PT32E_ROOT_LEVEL;
4882         else if (is_la57_mode(vcpu))
4883                 role.base.level = PT64_ROOT_5LEVEL;
4884         else
4885                 role.base.level = PT64_ROOT_4LEVEL;
4886 
4887         return role;
4888 }
4889 
4890 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4891 {
4892         struct kvm_mmu *context = vcpu->arch.mmu;
4893         union kvm_mmu_role new_role =
4894                 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4895 
4896         new_role.base.word &= mmu_base_role_mask.word;
4897         if (new_role.as_u64 == context->mmu_role.as_u64)
4898                 return;
4899 
4900         if (!is_paging(vcpu))
4901                 nonpaging_init_context(vcpu, context);
4902         else if (is_long_mode(vcpu))
4903                 paging64_init_context(vcpu, context);
4904         else if (is_pae(vcpu))
4905                 paging32E_init_context(vcpu, context);
4906         else
4907                 paging32_init_context(vcpu, context);
4908 
4909         context->mmu_role.as_u64 = new_role.as_u64;
4910         reset_shadow_zero_bits_mask(vcpu, context);
4911 }
4912 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4913 
4914 static union kvm_mmu_role
4915 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4916                                    bool execonly)
4917 {
4918         union kvm_mmu_role role = {0};
4919         union kvm_mmu_page_role root_base = vcpu->arch.root_mmu.mmu_role.base;
4920 
4921         /* Legacy paging and SMM flags are inherited from root_mmu */
4922         role.base.smm = root_base.smm;
4923         role.base.nxe = root_base.nxe;
4924         role.base.cr0_wp = root_base.cr0_wp;
4925         role.base.smep_andnot_wp = root_base.smep_andnot_wp;
4926         role.base.smap_andnot_wp = root_base.smap_andnot_wp;
4927 
4928         role.base.level = PT64_ROOT_4LEVEL;
4929         role.base.direct = false;
4930         role.base.ad_disabled = !accessed_dirty;
4931         role.base.guest_mode = true;
4932         role.base.access = ACC_ALL;
4933 
4934         role.ext = kvm_calc_mmu_role_ext(vcpu);
4935         role.ext.execonly = execonly;
4936 
4937         return role;
4938 }
4939 
4940 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4941                              bool accessed_dirty, gpa_t new_eptp)
4942 {
4943         struct kvm_mmu *context = vcpu->arch.mmu;
4944         union kvm_mmu_role new_role =
4945                 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4946                                                    execonly);
4947 
4948         __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false);
4949 
4950         new_role.base.word &= mmu_base_role_mask.word;
4951         if (new_role.as_u64 == context->mmu_role.as_u64)
4952                 return;
4953 
4954         context->shadow_root_level = PT64_ROOT_4LEVEL;
4955 
4956         context->nx = true;
4957         context->ept_ad = accessed_dirty;
4958         context->page_fault = ept_page_fault;
4959         context->gva_to_gpa = ept_gva_to_gpa;
4960         context->sync_page = ept_sync_page;
4961         context->invlpg = ept_invlpg;
4962         context->update_pte = ept_update_pte;
4963         context->root_level = PT64_ROOT_4LEVEL;
4964         context->direct_map = false;
4965         context->mmu_role.as_u64 = new_role.as_u64;
4966 
4967         update_permission_bitmask(vcpu, context, true);
4968         update_pkru_bitmask(vcpu, context, true);
4969         update_last_nonleaf_level(vcpu, context);
4970         reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4971         reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4972 }
4973 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4974 
4975 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4976 {
4977         struct kvm_mmu *context = vcpu->arch.mmu;
4978 
4979         kvm_init_shadow_mmu(vcpu);
4980         context->set_cr3           = kvm_x86_ops->set_cr3;
4981         context->get_cr3           = get_cr3;
4982         context->get_pdptr         = kvm_pdptr_read;
4983         context->inject_page_fault = kvm_inject_page_fault;
4984 }
4985 
4986 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4987 {
4988         union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4989         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4990 
4991         new_role.base.word &= mmu_base_role_mask.word;
4992         if (new_role.as_u64 == g_context->mmu_role.as_u64)
4993                 return;
4994 
4995         g_context->mmu_role.as_u64 = new_role.as_u64;
4996         g_context->get_cr3           = get_cr3;
4997         g_context->get_pdptr         = kvm_pdptr_read;
4998         g_context->inject_page_fault = kvm_inject_page_fault;
4999 
5000         /*
5001          * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5002          * L1's nested page tables (e.g. EPT12). The nested translation
5003          * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5004          * L2's page tables as the first level of translation and L1's
5005          * nested page tables as the second level of translation. Basically
5006          * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5007          */
5008         if (!is_paging(vcpu)) {
5009                 g_context->nx = false;
5010                 g_context->root_level = 0;
5011                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5012         } else if (is_long_mode(vcpu)) {
5013                 g_context->nx = is_nx(vcpu);
5014                 g_context->root_level = is_la57_mode(vcpu) ?
5015                                         PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5016                 reset_rsvds_bits_mask(vcpu, g_context);
5017                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5018         } else if (is_pae(vcpu)) {
5019                 g_context->nx = is_nx(vcpu);
5020                 g_context->root_level = PT32E_ROOT_LEVEL;
5021                 reset_rsvds_bits_mask(vcpu, g_context);
5022                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5023         } else {
5024                 g_context->nx = false;
5025                 g_context->root_level = PT32_ROOT_LEVEL;
5026                 reset_rsvds_bits_mask(vcpu, g_context);
5027                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5028         }
5029 
5030         update_permission_bitmask(vcpu, g_context, false);
5031         update_pkru_bitmask(vcpu, g_context, false);
5032         update_last_nonleaf_level(vcpu, g_context);
5033 }
5034 
5035 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5036 {
5037         if (reset_roots) {
5038                 uint i;
5039 
5040                 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5041 
5042                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5043                         vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5044         }
5045 
5046         if (mmu_is_nested(vcpu))
5047                 init_kvm_nested_mmu(vcpu);
5048         else if (tdp_enabled)
5049                 init_kvm_tdp_mmu(vcpu);
5050         else
5051                 init_kvm_softmmu(vcpu);
5052 }
5053 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5054 
5055 static union kvm_mmu_page_role
5056 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5057 {
5058         union kvm_mmu_role role;
5059 
5060         if (tdp_enabled)
5061                 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5062         else
5063                 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5064 
5065         return role.base;
5066 }
5067 
5068 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5069 {
5070         kvm_mmu_unload(vcpu);
5071         kvm_init_mmu(vcpu, true);
5072 }
5073 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5074 
5075 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5076 {
5077         int r;
5078 
5079         r = mmu_topup_memory_caches(vcpu);
5080         if (r)
5081                 goto out;
5082         r = mmu_alloc_roots(vcpu);
5083         kvm_mmu_sync_roots(vcpu);
5084         if (r)
5085                 goto out;
5086         kvm_mmu_load_cr3(vcpu);
5087         kvm_x86_ops->tlb_flush(vcpu, true);
5088 out:
5089         return r;
5090 }
5091 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5092 
5093 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5094 {
5095         kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5096         WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5097         kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5098         WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5099 }
5100 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5101 
5102 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5103                                   struct kvm_mmu_page *sp, u64 *spte,
5104                                   const void *new)
5105 {
5106         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
5107                 ++vcpu->kvm->stat.mmu_pde_zapped;
5108                 return;
5109         }
5110 
5111         ++vcpu->kvm->stat.mmu_pte_updated;
5112         vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5113 }
5114 
5115 static bool need_remote_flush(u64 old, u64 new)
5116 {
5117         if (!is_shadow_present_pte(old))
5118                 return false;
5119         if (!is_shadow_present_pte(new))
5120                 return true;
5121         if ((old ^ new) & PT64_BASE_ADDR_MASK)
5122                 return true;
5123         old ^= shadow_nx_mask;
5124         new ^= shadow_nx_mask;
5125         return (old & ~new & PT64_PERM_MASK) != 0;
5126 }
5127 
5128 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5129                                     int *bytes)
5130 {
5131         u64 gentry = 0;
5132         int r;
5133 
5134         /*
5135          * Assume that the pte write on a page table of the same type
5136          * as the current vcpu paging mode since we update the sptes only
5137          * when they have the same mode.
5138          */
5139         if (is_pae(vcpu) && *bytes == 4) {
5140                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5141                 *gpa &= ~(gpa_t)7;
5142                 *bytes = 8;
5143         }
5144 
5145         if (*bytes == 4 || *bytes == 8) {
5146                 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5147                 if (r)
5148                         gentry = 0;
5149         }
5150 
5151         return gentry;
5152 }
5153 
5154 /*
5155  * If we're seeing too many writes to a page, it may no longer be a page table,
5156  * or we may be forking, in which case it is better to unmap the page.
5157  */
5158 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5159 {
5160         /*
5161          * Skip write-flooding detected for the sp whose level is 1, because
5162          * it can become unsync, then the guest page is not write-protected.
5163          */
5164         if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5165                 return false;
5166 
5167         atomic_inc(&sp->write_flooding_count);
5168         return atomic_read(&sp->write_flooding_count) >= 3;
5169 }
5170 
5171 /*
5172  * Misaligned accesses are too much trouble to fix up; also, they usually
5173  * indicate a page is not used as a page table.
5174  */
5175 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5176                                     int bytes)
5177 {
5178         unsigned offset, pte_size, misaligned;
5179 
5180         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5181                  gpa, bytes, sp->role.word);
5182 
5183         offset = offset_in_page(gpa);
5184         pte_size = sp->role.cr4_pae ? 8 : 4;
5185 
5186         /*
5187          * Sometimes, the OS only writes the last one bytes to update status
5188          * bits, for example, in linux, andb instruction is used in clear_bit().
5189          */
5190         if (!(offset & (pte_size - 1)) && bytes == 1)
5191                 return false;
5192 
5193         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5194         misaligned |= bytes < 4;
5195 
5196         return misaligned;
5197 }
5198 
5199 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5200 {
5201         unsigned page_offset, quadrant;
5202         u64 *spte;
5203         int level;
5204 
5205         page_offset = offset_in_page(gpa);
5206         level = sp->role.level;
5207         *nspte = 1;
5208         if (!sp->role.cr4_pae) {
5209                 page_offset <<= 1;      /* 32->64 */
5210                 /*
5211                  * A 32-bit pde maps 4MB while the shadow pdes map
5212                  * only 2MB.  So we need to double the offset again
5213                  * and zap two pdes instead of one.
5214                  */
5215                 if (level == PT32_ROOT_LEVEL) {
5216                         page_offset &= ~7; /* kill rounding error */
5217                         page_offset <<= 1;
5218                         *nspte = 2;
5219                 }
5220                 quadrant = page_offset >> PAGE_SHIFT;
5221                 page_offset &= ~PAGE_MASK;
5222                 if (quadrant != sp->role.quadrant)
5223                         return NULL;
5224         }
5225 
5226         spte = &sp->spt[page_offset / sizeof(*spte)];
5227         return spte;
5228 }
5229 
5230 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5231                               const u8 *new, int bytes,
5232                               struct kvm_page_track_notifier_node *node)
5233 {
5234         gfn_t gfn = gpa >> PAGE_SHIFT;
5235         struct kvm_mmu_page *sp;
5236         LIST_HEAD(invalid_list);
5237         u64 entry, gentry, *spte;
5238         int npte;
5239         bool remote_flush, local_flush;
5240 
5241         /*
5242          * If we don't have indirect shadow pages, it means no page is
5243          * write-protected, so we can exit simply.
5244          */
5245         if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5246                 return;
5247 
5248         remote_flush = local_flush = false;
5249 
5250         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5251 
5252         /*
5253          * No need to care whether allocation memory is successful
5254          * or not since pte prefetch is skiped if it does not have
5255          * enough objects in the cache.
5256          */
5257         mmu_topup_memory_caches(vcpu);
5258 
5259         spin_lock(&vcpu->kvm->mmu_lock);
5260 
5261         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5262 
5263         ++vcpu->kvm->stat.mmu_pte_write;
5264         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5265 
5266         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5267                 if (detect_write_misaligned(sp, gpa, bytes) ||
5268                       detect_write_flooding(sp)) {
5269                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5270                         ++vcpu->kvm->stat.mmu_flooded;
5271                         continue;
5272                 }
5273 
5274                 spte = get_written_sptes(sp, gpa, &npte);
5275                 if (!spte)
5276                         continue;
5277 
5278                 local_flush = true;
5279                 while (npte--) {
5280                         u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5281 
5282                         entry = *spte;
5283                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
5284                         if (gentry &&
5285                               !((sp->role.word ^ base_role)
5286                               & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5287                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5288                         if (need_remote_flush(entry, *spte))
5289                                 remote_flush = true;
5290                         ++spte;
5291                 }
5292         }
5293         kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5294         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5295         spin_unlock(&vcpu->kvm->mmu_lock);
5296 }
5297 
5298 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5299 {
5300         gpa_t gpa;
5301         int r;
5302 
5303         if (vcpu->arch.mmu->direct_map)
5304                 return 0;
5305 
5306         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5307 
5308         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5309 
5310         return r;
5311 }
5312 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5313 
5314 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
5315 {
5316         LIST_HEAD(invalid_list);
5317 
5318         if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
5319                 return 0;
5320 
5321         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
5322                 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
5323                         break;
5324 
5325                 ++vcpu->kvm->stat.mmu_recycled;
5326         }
5327         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
5328 
5329         if (!kvm_mmu_available_pages(vcpu->kvm))
5330                 return -ENOSPC;
5331         return 0;
5332 }
5333 
5334 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
5335                        void *insn, int insn_len)
5336 {
5337         int r, emulation_type = 0;
5338         enum emulation_result er;
5339         bool direct = vcpu->arch.mmu->direct_map;
5340 
5341         /* With shadow page tables, fault_address contains a GVA or nGPA.  */
5342         if (vcpu->arch.mmu->direct_map) {
5343                 vcpu->arch.gpa_available = true;
5344                 vcpu->arch.gpa_val = cr2;
5345         }
5346 
5347         r = RET_PF_INVALID;
5348         if (unlikely(error_code & PFERR_RSVD_MASK)) {
5349                 r = handle_mmio_page_fault(vcpu, cr2, direct);
5350                 if (r == RET_PF_EMULATE)
5351                         goto emulate;
5352         }
5353 
5354         if (r == RET_PF_INVALID) {
5355                 r = vcpu->arch.mmu->page_fault(vcpu, cr2,
5356                                                lower_32_bits(error_code),
5357                                                false);
5358                 WARN_ON(r == RET_PF_INVALID);
5359         }
5360 
5361         if (r == RET_PF_RETRY)
5362                 return 1;
5363         if (r < 0)
5364                 return r;
5365 
5366         /*
5367          * Before emulating the instruction, check if the error code
5368          * was due to a RO violation while translating the guest page.
5369          * This can occur when using nested virtualization with nested
5370          * paging in both guests. If true, we simply unprotect the page
5371          * and resume the guest.
5372          */
5373         if (vcpu->arch.mmu->direct_map &&
5374             (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5375                 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
5376                 return 1;
5377         }
5378 
5379         /*
5380          * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5381          * optimistically try to just unprotect the page and let the processor
5382          * re-execute the instruction that caused the page fault.  Do not allow
5383          * retrying MMIO emulation, as it's not only pointless but could also
5384          * cause us to enter an infinite loop because the processor will keep
5385          * faulting on the non-existent MMIO address.  Retrying an instruction
5386          * from a nested guest is also pointless and dangerous as we are only
5387          * explicitly shadowing L1's page tables, i.e. unprotecting something
5388          * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5389          */
5390         if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
5391                 emulation_type = EMULTYPE_ALLOW_RETRY;
5392 emulate:
5393         /*
5394          * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5395          * This can happen if a guest gets a page-fault on data access but the HW
5396          * table walker is not able to read the instruction page (e.g instruction
5397          * page is not present in memory). In those cases we simply restart the
5398          * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5399          */
5400         if (unlikely(insn && !insn_len)) {
5401                 if (!kvm_x86_ops->need_emulation_on_page_fault(vcpu))
5402                         return 1;
5403         }
5404 
5405         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
5406 
5407         switch (er) {
5408         case EMULATE_DONE:
5409                 return 1;
5410         case EMULATE_USER_EXIT:
5411                 ++vcpu->stat.mmio_exits;
5412                 /* fall through */
5413         case EMULATE_FAIL:
5414                 return 0;
5415         default:
5416                 BUG();
5417         }
5418 }
5419 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5420 
5421 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5422 {
5423         struct kvm_mmu *mmu = vcpu->arch.mmu;
5424         int i;
5425 
5426         /* INVLPG on a * non-canonical address is a NOP according to the SDM.  */
5427         if (is_noncanonical_address(gva, vcpu))
5428                 return;
5429 
5430         mmu->invlpg(vcpu, gva, mmu->root_hpa);
5431 
5432         /*
5433          * INVLPG is required to invalidate any global mappings for the VA,
5434          * irrespective of PCID. Since it would take us roughly similar amount
5435          * of work to determine whether any of the prev_root mappings of the VA
5436          * is marked global, or to just sync it blindly, so we might as well
5437          * just always sync it.
5438          *
5439          * Mappings not reachable via the current cr3 or the prev_roots will be
5440          * synced when switching to that cr3, so nothing needs to be done here
5441          * for them.
5442          */
5443         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5444                 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5445                         mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5446 
5447         kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5448         ++vcpu->stat.invlpg;
5449 }
5450 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5451 
5452 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5453 {
5454         struct kvm_mmu *mmu = vcpu->arch.mmu;
5455         bool tlb_flush = false;
5456         uint i;
5457 
5458         if (pcid == kvm_get_active_pcid(vcpu)) {
5459                 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5460                 tlb_flush = true;
5461         }
5462 
5463         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5464                 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5465                     pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5466                         mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5467                         tlb_flush = true;
5468                 }
5469         }
5470 
5471         if (tlb_flush)
5472                 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5473 
5474         ++vcpu->stat.invlpg;
5475 
5476         /*
5477          * Mappings not reachable via the current cr3 or the prev_roots will be
5478          * synced when switching to that cr3, so nothing needs to be done here
5479          * for them.
5480          */
5481 }
5482 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5483 
5484 void kvm_enable_tdp(void)
5485 {
5486         tdp_enabled = true;
5487 }
5488 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5489 
5490 void kvm_disable_tdp(void)
5491 {
5492         tdp_enabled = false;
5493 }
5494 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5495 
5496 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5497 {
5498         free_page((unsigned long)vcpu->arch.mmu->pae_root);
5499         free_page((unsigned long)vcpu->arch.mmu->lm_root);
5500 }
5501 
5502 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5503 {
5504         struct page *page;
5505         int i;
5506 
5507         if (tdp_enabled)
5508                 return 0;
5509 
5510         /*
5511          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5512          * Therefore we need to allocate shadow page tables in the first
5513          * 4GB of memory, which happens to fit the DMA32 zone.
5514          */
5515         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
5516         if (!page)
5517                 return -ENOMEM;
5518 
5519         vcpu->arch.mmu->pae_root = page_address(page);
5520         for (i = 0; i < 4; ++i)
5521                 vcpu->arch.mmu->pae_root[i] = INVALID_PAGE;
5522 
5523         return 0;
5524 }
5525 
5526 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5527 {
5528         uint i;
5529 
5530         vcpu->arch.mmu = &vcpu->arch.root_mmu;
5531         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5532 
5533         vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5534         vcpu->arch.root_mmu.root_cr3 = 0;
5535         vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5536         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5537                 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5538 
5539         vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5540         vcpu->arch.guest_mmu.root_cr3 = 0;
5541         vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5542         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5543                 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5544 
5545         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5546         return alloc_mmu_pages(vcpu);
5547 }
5548 
5549 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5550                         struct kvm_memory_slot *slot,
5551                         struct kvm_page_track_notifier_node *node)
5552 {
5553         kvm_mmu_invalidate_zap_all_pages(kvm);
5554 }
5555 
5556 void kvm_mmu_init_vm(struct kvm *kvm)
5557 {
5558         struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5559 
5560         node->track_write = kvm_mmu_pte_write;
5561         node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5562         kvm_page_track_register_notifier(kvm, node);
5563 }
5564 
5565 void kvm_mmu_uninit_vm(struct kvm *kvm)
5566 {
5567         struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5568 
5569         kvm_page_track_unregister_notifier(kvm, node);
5570 }
5571 
5572 /* The return value indicates if tlb flush on all vcpus is needed. */
5573 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5574 
5575 /* The caller should hold mmu-lock before calling this function. */
5576 static __always_inline bool
5577 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5578                         slot_level_handler fn, int start_level, int end_level,
5579                         gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5580 {
5581         struct slot_rmap_walk_iterator iterator;
5582         bool flush = false;
5583 
5584         for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5585                         end_gfn, &iterator) {
5586                 if (iterator.rmap)
5587                         flush |= fn(kvm, iterator.rmap);
5588 
5589                 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5590                         if (flush && lock_flush_tlb) {
5591                                 kvm_flush_remote_tlbs(kvm);
5592                                 flush = false;
5593                         }
5594                         cond_resched_lock(&kvm->mmu_lock);
5595                 }
5596         }
5597 
5598         if (flush && lock_flush_tlb) {
5599                 kvm_flush_remote_tlbs(kvm);
5600                 flush = false;
5601         }
5602 
5603         return flush;
5604 }
5605 
5606 static __always_inline bool
5607 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5608                   slot_level_handler fn, int start_level, int end_level,
5609                   bool lock_flush_tlb)
5610 {
5611         return slot_handle_level_range(kvm, memslot, fn, start_level,
5612                         end_level, memslot->base_gfn,
5613                         memslot->base_gfn + memslot->npages - 1,
5614                         lock_flush_tlb);
5615 }
5616 
5617 static __always_inline bool
5618 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5619                       slot_level_handler fn, bool lock_flush_tlb)
5620 {
5621         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5622                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5623 }
5624 
5625 static __always_inline bool
5626 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5627                         slot_level_handler fn, bool lock_flush_tlb)
5628 {
5629         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5630                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5631 }
5632 
5633 static __always_inline bool
5634 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5635                  slot_level_handler fn, bool lock_flush_tlb)
5636 {
5637         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5638                                  PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5639 }
5640 
5641 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5642 {
5643         struct kvm_memslots *slots;
5644         struct kvm_memory_slot *memslot;
5645         int i;
5646 
5647         spin_lock(&kvm->mmu_lock);
5648         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5649                 slots = __kvm_memslots(kvm, i);
5650                 kvm_for_each_memslot(memslot, slots) {
5651                         gfn_t start, end;
5652 
5653                         start = max(gfn_start, memslot->base_gfn);
5654                         end = min(gfn_end, memslot->base_gfn + memslot->npages);
5655                         if (start >= end)
5656                                 continue;
5657 
5658                         slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5659                                                 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5660                                                 start, end - 1, true);
5661                 }
5662         }
5663 
5664         spin_unlock(&kvm->mmu_lock);
5665 }
5666 
5667 static bool slot_rmap_write_protect(struct kvm *kvm,
5668                                     struct kvm_rmap_head *rmap_head)
5669 {
5670         return __rmap_write_protect(kvm, rmap_head, false);
5671 }
5672 
5673 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5674                                       struct kvm_memory_slot *memslot)
5675 {
5676         bool flush;
5677 
5678         spin_lock(&kvm->mmu_lock);
5679         flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5680                                       false);
5681         spin_unlock(&kvm->mmu_lock);
5682 
5683         /*
5684          * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5685          * which do tlb flush out of mmu-lock should be serialized by
5686          * kvm->slots_lock otherwise tlb flush would be missed.
5687          */
5688         lockdep_assert_held(&kvm->slots_lock);
5689 
5690         /*
5691          * We can flush all the TLBs out of the mmu lock without TLB
5692          * corruption since we just change the spte from writable to
5693          * readonly so that we only need to care the case of changing
5694          * spte from present to present (changing the spte from present
5695          * to nonpresent will flush all the TLBs immediately), in other
5696          * words, the only case we care is mmu_spte_update() where we
5697          * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5698          * instead of PT_WRITABLE_MASK, that means it does not depend
5699          * on PT_WRITABLE_MASK anymore.
5700          */
5701         if (flush)
5702                 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5703                         memslot->npages);
5704 }
5705 
5706 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5707                                          struct kvm_rmap_head *rmap_head)
5708 {
5709         u64 *sptep;
5710         struct rmap_iterator iter;
5711         int need_tlb_flush = 0;
5712         kvm_pfn_t pfn;
5713         struct kvm_mmu_page *sp;
5714 
5715 restart:
5716         for_each_rmap_spte(rmap_head, &iter, sptep) {
5717                 sp = page_header(__pa(sptep));
5718                 pfn = spte_to_pfn(*sptep);
5719 
5720                 /*
5721                  * We cannot do huge page mapping for indirect shadow pages,
5722                  * which are found on the last rmap (level = 1) when not using
5723                  * tdp; such shadow pages are synced with the page table in
5724                  * the guest, and the guest page table is using 4K page size
5725                  * mapping if the indirect sp has level = 1.
5726                  */
5727                 if (sp->role.direct &&
5728                         !kvm_is_reserved_pfn(pfn) &&
5729                         PageTransCompoundMap(pfn_to_page(pfn))) {
5730                         pte_list_remove(rmap_head, sptep);
5731 
5732                         if (kvm_available_flush_tlb_with_range())
5733                                 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5734                                         KVM_PAGES_PER_HPAGE(sp->role.level));
5735                         else
5736                                 need_tlb_flush = 1;
5737 
5738                         goto restart;
5739                 }
5740         }
5741 
5742         return need_tlb_flush;
5743 }
5744 
5745 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5746                                    const struct kvm_memory_slot *memslot)
5747 {
5748         /* FIXME: const-ify all uses of struct kvm_memory_slot.  */
5749         spin_lock(&kvm->mmu_lock);
5750         slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5751                          kvm_mmu_zap_collapsible_spte, true);
5752         spin_unlock(&kvm->mmu_lock);
5753 }
5754 
5755 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5756                                    struct kvm_memory_slot *memslot)
5757 {
5758         bool flush;
5759 
5760         spin_lock(&kvm->mmu_lock);
5761         flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5762         spin_unlock(&kvm->mmu_lock);
5763 
5764         lockdep_assert_held(&kvm->slots_lock);
5765 
5766         /*
5767          * It's also safe to flush TLBs out of mmu lock here as currently this
5768          * function is only used for dirty logging, in which case flushing TLB
5769          * out of mmu lock also guarantees no dirty pages will be lost in
5770          * dirty_bitmap.
5771          */
5772         if (flush)
5773                 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5774                                 memslot->npages);
5775 }
5776 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5777 
5778 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5779                                         struct kvm_memory_slot *memslot)
5780 {
5781         bool flush;
5782 
5783         spin_lock(&kvm->mmu_lock);
5784         flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5785                                         false);
5786         spin_unlock(&kvm->mmu_lock);
5787 
5788         /* see kvm_mmu_slot_remove_write_access */
5789         lockdep_assert_held(&kvm->slots_lock);
5790 
5791         if (flush)
5792                 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5793                                 memslot->npages);
5794 }
5795 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5796 
5797 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5798                             struct kvm_memory_slot *memslot)
5799 {
5800         bool flush;
5801 
5802         spin_lock(&kvm->mmu_lock);
5803         flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5804         spin_unlock(&kvm->mmu_lock);
5805 
5806         lockdep_assert_held(&kvm->slots_lock);
5807 
5808         /* see kvm_mmu_slot_leaf_clear_dirty */
5809         if (flush)
5810                 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5811                                 memslot->npages);
5812 }
5813 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5814 
5815 #define BATCH_ZAP_PAGES 10
5816 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5817 {
5818         struct kvm_mmu_page *sp, *node;
5819         int batch = 0;
5820 
5821 restart:
5822         list_for_each_entry_safe_reverse(sp, node,
5823               &kvm->arch.active_mmu_pages, link) {
5824                 int ret;
5825 
5826                 /*
5827                  * No obsolete page exists before new created page since
5828                  * active_mmu_pages is the FIFO list.
5829                  */
5830                 if (!is_obsolete_sp(kvm, sp))
5831                         break;
5832 
5833                 /*
5834                  * Since we are reversely walking the list and the invalid
5835                  * list will be moved to the head, skip the invalid page
5836                  * can help us to avoid the infinity list walking.
5837                  */
5838                 if (sp->role.invalid)
5839                         continue;
5840 
5841                 /*
5842                  * Need not flush tlb since we only zap the sp with invalid
5843                  * generation number.
5844                  */
5845                 if (batch >= BATCH_ZAP_PAGES &&
5846                       cond_resched_lock(&kvm->mmu_lock)) {
5847                         batch = 0;
5848                         goto restart;
5849                 }
5850 
5851                 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5852                                 &kvm->arch.zapped_obsolete_pages);
5853                 batch += ret;
5854 
5855                 if (ret)
5856                         goto restart;
5857         }
5858 
5859         /*
5860          * Should flush tlb before free page tables since lockless-walking
5861          * may use the pages.
5862          */
5863         kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5864 }
5865 
5866 /*
5867  * Fast invalidate all shadow pages and use lock-break technique
5868  * to zap obsolete pages.
5869  *
5870  * It's required when memslot is being deleted or VM is being
5871  * destroyed, in these cases, we should ensure that KVM MMU does
5872  * not use any resource of the being-deleted slot or all slots
5873  * after calling the function.
5874  */
5875 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5876 {
5877         spin_lock(&kvm->mmu_lock);
5878         trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5879         kvm->arch.mmu_valid_gen++;
5880 
5881         /*
5882          * Notify all vcpus to reload its shadow page table
5883          * and flush TLB. Then all vcpus will switch to new
5884          * shadow page table with the new mmu_valid_gen.
5885          *
5886          * Note: we should do this under the protection of
5887          * mmu-lock, otherwise, vcpu would purge shadow page
5888          * but miss tlb flush.
5889          */
5890         kvm_reload_remote_mmus(kvm);
5891 
5892         kvm_zap_obsolete_pages(kvm);
5893         spin_unlock(&kvm->mmu_lock);
5894 }
5895 
5896 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5897 {
5898         return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5899 }
5900 
5901 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5902 {
5903         gen &= MMIO_GEN_MASK;
5904 
5905         /*
5906          * Shift to eliminate the "update in-progress" flag, which isn't
5907          * included in the spte's generation number.
5908          */
5909         gen >>= 1;
5910 
5911         /*
5912          * Generation numbers are incremented in multiples of the number of
5913          * address spaces in order to provide unique generations across all
5914          * address spaces.  Strip what is effectively the address space
5915          * modifier prior to checking for a wrap of the MMIO generation so
5916          * that a wrap in any address space is detected.
5917          */
5918         gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5919 
5920         /*
5921          * The very rare case: if the MMIO generation number has wrapped,
5922          * zap all shadow pages.
5923          */
5924         if (unlikely(gen == 0)) {
5925                 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5926                 kvm_mmu_invalidate_zap_all_pages(kvm);
5927         }
5928 }
5929 
5930 static unsigned long
5931 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5932 {
5933         struct kvm *kvm;
5934         int nr_to_scan = sc->nr_to_scan;
5935         unsigned long freed = 0;
5936 
5937         spin_lock(&kvm_lock);
5938 
5939         list_for_each_entry(kvm, &vm_list, vm_list) {
5940                 int idx;
5941                 LIST_HEAD(invalid_list);
5942 
5943                 /*
5944                  * Never scan more than sc->nr_to_scan VM instances.
5945                  * Will not hit this condition practically since we do not try
5946                  * to shrink more than one VM and it is very unlikely to see
5947                  * !n_used_mmu_pages so many times.
5948                  */
5949                 if (!nr_to_scan--)
5950                         break;
5951                 /*
5952                  * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5953                  * here. We may skip a VM instance errorneosly, but we do not
5954                  * want to shrink a VM that only started to populate its MMU
5955                  * anyway.
5956                  */
5957                 if (!kvm->arch.n_used_mmu_pages &&
5958                       !kvm_has_zapped_obsolete_pages(kvm))
5959                         continue;
5960 
5961                 idx = srcu_read_lock(&kvm->srcu);
5962                 spin_lock(&kvm->mmu_lock);
5963 
5964                 if (kvm_has_zapped_obsolete_pages(kvm)) {
5965                         kvm_mmu_commit_zap_page(kvm,
5966                               &kvm->arch.zapped_obsolete_pages);
5967                         goto unlock;
5968                 }
5969 
5970                 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5971                         freed++;
5972                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5973 
5974 unlock:
5975                 spin_unlock(&kvm->mmu_lock);
5976                 srcu_read_unlock(&kvm->srcu, idx);
5977 
5978                 /*
5979                  * unfair on small ones
5980                  * per-vm shrinkers cry out
5981                  * sadness comes quickly
5982                  */
5983                 list_move_tail(&kvm->vm_list, &vm_list);
5984                 break;
5985         }
5986 
5987         spin_unlock(&kvm_lock);
5988         return freed;
5989 }
5990 
5991 static unsigned long
5992 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5993 {
5994         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5995 }
5996 
5997 static struct shrinker mmu_shrinker = {
5998         .count_objects = mmu_shrink_count,
5999         .scan_objects = mmu_shrink_scan,
6000         .seeks = DEFAULT_SEEKS * 10,
6001 };
6002 
6003 static void mmu_destroy_caches(void)
6004 {
6005         kmem_cache_destroy(pte_list_desc_cache);
6006         kmem_cache_destroy(mmu_page_header_cache);
6007 }
6008 
6009 int kvm_mmu_module_init(void)
6010 {
6011         int ret = -ENOMEM;
6012 
6013         /*
6014          * MMU roles use union aliasing which is, generally speaking, an
6015          * undefined behavior. However, we supposedly know how compilers behave
6016          * and the current status quo is unlikely to change. Guardians below are
6017          * supposed to let us know if the assumption becomes false.
6018          */
6019         BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6020         BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6021         BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6022 
6023         kvm_mmu_reset_all_pte_masks();
6024 
6025         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6026                                             sizeof(struct pte_list_desc),
6027                                             0, SLAB_ACCOUNT, NULL);
6028         if (!pte_list_desc_cache)
6029                 goto out;
6030 
6031         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6032                                                   sizeof(struct kvm_mmu_page),
6033                                                   0, SLAB_ACCOUNT, NULL);
6034         if (!mmu_page_header_cache)
6035                 goto out;
6036 
6037         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6038                 goto out;
6039 
6040         ret = register_shrinker(&mmu_shrinker);
6041         if (ret)
6042                 goto out;
6043 
6044         return 0;
6045 
6046 out:
6047         mmu_destroy_caches();
6048         return ret;
6049 }
6050 
6051 /*
6052  * Calculate mmu pages needed for kvm.
6053  */
6054 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
6055 {
6056         unsigned int nr_mmu_pages;
6057         unsigned int  nr_pages = 0;
6058         struct kvm_memslots *slots;
6059         struct kvm_memory_slot *memslot;
6060         int i;
6061 
6062         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6063                 slots = __kvm_memslots(kvm, i);
6064 
6065                 kvm_for_each_memslot(memslot, slots)
6066                         nr_pages += memslot->npages;
6067         }
6068 
6069         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6070         nr_mmu_pages = max(nr_mmu_pages,
6071                            (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
6072 
6073         return nr_mmu_pages;
6074 }
6075 
6076 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6077 {
6078         kvm_mmu_unload(vcpu);
6079         free_mmu_pages(vcpu);
6080         mmu_free_memory_caches(vcpu);
6081 }
6082 
6083 void kvm_mmu_module_exit(void)
6084 {
6085         mmu_destroy_caches();
6086         percpu_counter_destroy(&kvm_total_used_mmu_pages);
6087         unregister_shrinker(&mmu_shrinker);
6088         mmu_audit_disable();
6089 }
6090 

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