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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/svm.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * AMD SVM support
  5  *
  6  * Copyright (C) 2006 Qumranet, Inc.
  7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  8  *
  9  * Authors:
 10  *   Yaniv Kamay  <yaniv@qumranet.com>
 11  *   Avi Kivity   <avi@qumranet.com>
 12  *
 13  * This work is licensed under the terms of the GNU GPL, version 2.  See
 14  * the COPYING file in the top-level directory.
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) "SVM: " fmt
 19 
 20 #include <linux/kvm_host.h>
 21 
 22 #include "irq.h"
 23 #include "mmu.h"
 24 #include "kvm_cache_regs.h"
 25 #include "x86.h"
 26 #include "cpuid.h"
 27 #include "pmu.h"
 28 
 29 #include <linux/module.h>
 30 #include <linux/mod_devicetable.h>
 31 #include <linux/kernel.h>
 32 #include <linux/vmalloc.h>
 33 #include <linux/highmem.h>
 34 #include <linux/sched.h>
 35 #include <linux/trace_events.h>
 36 #include <linux/slab.h>
 37 #include <linux/amd-iommu.h>
 38 #include <linux/hashtable.h>
 39 #include <linux/frame.h>
 40 #include <linux/psp-sev.h>
 41 #include <linux/file.h>
 42 #include <linux/pagemap.h>
 43 #include <linux/swap.h>
 44 
 45 #include <asm/apic.h>
 46 #include <asm/perf_event.h>
 47 #include <asm/tlbflush.h>
 48 #include <asm/desc.h>
 49 #include <asm/debugreg.h>
 50 #include <asm/kvm_para.h>
 51 #include <asm/irq_remapping.h>
 52 #include <asm/nospec-branch.h>
 53 
 54 #include <asm/virtext.h>
 55 #include "trace.h"
 56 
 57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 58 
 59 MODULE_AUTHOR("Qumranet");
 60 MODULE_LICENSE("GPL");
 61 
 62 static const struct x86_cpu_id svm_cpu_id[] = {
 63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
 64         {}
 65 };
 66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
 67 
 68 #define IOPM_ALLOC_ORDER 2
 69 #define MSRPM_ALLOC_ORDER 1
 70 
 71 #define SEG_TYPE_LDT 2
 72 #define SEG_TYPE_BUSY_TSS16 3
 73 
 74 #define SVM_FEATURE_NPT            (1 <<  0)
 75 #define SVM_FEATURE_LBRV           (1 <<  1)
 76 #define SVM_FEATURE_SVML           (1 <<  2)
 77 #define SVM_FEATURE_NRIP           (1 <<  3)
 78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
 79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
 80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
 81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
 82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
 83 
 84 #define SVM_AVIC_DOORBELL       0xc001011b
 85 
 86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 89 
 90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
 91 
 92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
 93 #define TSC_RATIO_MIN           0x0000000000000001ULL
 94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
 95 
 96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
 97 
 98 /*
 99  * 0xff is broadcast, so the max index allowed for physical APIC ID
100  * table is 0xfe.  APIC IDs above 0xff are reserved.
101  */
102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
103 
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
107 
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS               8
110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
111 
112 #define AVIC_VM_ID_BITS                 24
113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
115 
116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117                                                 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
120 
121 static bool erratum_383_found __read_mostly;
122 
123 static const u32 host_save_user_msrs[] = {
124 #ifdef CONFIG_X86_64
125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
126         MSR_FS_BASE,
127 #endif
128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
129         MSR_TSC_AUX,
130 };
131 
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
133 
134 struct kvm_sev_info {
135         bool active;            /* SEV enabled guest */
136         unsigned int asid;      /* ASID used for this guest */
137         unsigned int handle;    /* SEV firmware handle */
138         int fd;                 /* SEV device fd */
139         unsigned long pages_locked; /* Number of pages locked */
140         struct list_head regions_list;  /* List of registered regions */
141 };
142 
143 struct kvm_svm {
144         struct kvm kvm;
145 
146         /* Struct members for AVIC */
147         u32 avic_vm_id;
148         u32 ldr_mode;
149         struct page *avic_logical_id_table_page;
150         struct page *avic_physical_id_table_page;
151         struct hlist_node hnode;
152 
153         struct kvm_sev_info sev_info;
154 };
155 
156 struct kvm_vcpu;
157 
158 struct nested_state {
159         struct vmcb *hsave;
160         u64 hsave_msr;
161         u64 vm_cr_msr;
162         u64 vmcb;
163 
164         /* These are the merged vectors */
165         u32 *msrpm;
166 
167         /* gpa pointers to the real vectors */
168         u64 vmcb_msrpm;
169         u64 vmcb_iopm;
170 
171         /* A VMEXIT is required but not yet emulated */
172         bool exit_required;
173 
174         /* cache for intercepts of the guest */
175         u32 intercept_cr;
176         u32 intercept_dr;
177         u32 intercept_exceptions;
178         u64 intercept;
179 
180         /* Nested Paging related state */
181         u64 nested_cr3;
182 };
183 
184 #define MSRPM_OFFSETS   16
185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
186 
187 /*
188  * Set osvw_len to higher value when updated Revision Guides
189  * are published and we know what the new status bits are
190  */
191 static uint64_t osvw_len = 4, osvw_status;
192 
193 struct vcpu_svm {
194         struct kvm_vcpu vcpu;
195         struct vmcb *vmcb;
196         unsigned long vmcb_pa;
197         struct svm_cpu_data *svm_data;
198         uint64_t asid_generation;
199         uint64_t sysenter_esp;
200         uint64_t sysenter_eip;
201         uint64_t tsc_aux;
202 
203         u64 msr_decfg;
204 
205         u64 next_rip;
206 
207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
208         struct {
209                 u16 fs;
210                 u16 gs;
211                 u16 ldt;
212                 u64 gs_base;
213         } host;
214 
215         u64 spec_ctrl;
216 
217         u32 *msrpm;
218 
219         ulong nmi_iret_rip;
220 
221         struct nested_state nested;
222 
223         bool nmi_singlestep;
224         u64 nmi_singlestep_guest_rflags;
225 
226         unsigned int3_injected;
227         unsigned long int3_rip;
228 
229         /* cached guest cpuid flags for faster access */
230         bool nrips_enabled      : 1;
231 
232         u32 ldr_reg;
233         struct page *avic_backing_page;
234         u64 *avic_physical_id_cache;
235         bool avic_is_running;
236 
237         /*
238          * Per-vcpu list of struct amd_svm_iommu_ir:
239          * This is used mainly to store interrupt remapping information used
240          * when update the vcpu affinity. This avoids the need to scan for
241          * IRTE and try to match ga_tag in the IOMMU driver.
242          */
243         struct list_head ir_list;
244         spinlock_t ir_list_lock;
245 
246         /* which host CPU was used for running this vcpu */
247         unsigned int last_cpu;
248 };
249 
250 /*
251  * This is a wrapper of struct amd_iommu_ir_data.
252  */
253 struct amd_svm_iommu_ir {
254         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
255         void *data;             /* Storing pointer to struct amd_ir_data */
256 };
257 
258 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
259 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
260 
261 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
262 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
263 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
264 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
265 
266 static DEFINE_PER_CPU(u64, current_tsc_ratio);
267 #define TSC_RATIO_DEFAULT       0x0100000000ULL
268 
269 #define MSR_INVALID                     0xffffffffU
270 
271 static const struct svm_direct_access_msrs {
272         u32 index;   /* Index of the MSR */
273         bool always; /* True if intercept is always on */
274 } direct_access_msrs[] = {
275         { .index = MSR_STAR,                            .always = true  },
276         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
277 #ifdef CONFIG_X86_64
278         { .index = MSR_GS_BASE,                         .always = true  },
279         { .index = MSR_FS_BASE,                         .always = true  },
280         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
281         { .index = MSR_LSTAR,                           .always = true  },
282         { .index = MSR_CSTAR,                           .always = true  },
283         { .index = MSR_SYSCALL_MASK,                    .always = true  },
284 #endif
285         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
286         { .index = MSR_IA32_PRED_CMD,                   .always = false },
287         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
288         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
289         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
290         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
291         { .index = MSR_INVALID,                         .always = false },
292 };
293 
294 /* enable NPT for AMD64 and X86 with PAE */
295 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
296 static bool npt_enabled = true;
297 #else
298 static bool npt_enabled;
299 #endif
300 
301 /*
302  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
303  * pause_filter_count: On processors that support Pause filtering(indicated
304  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
305  *      count value. On VMRUN this value is loaded into an internal counter.
306  *      Each time a pause instruction is executed, this counter is decremented
307  *      until it reaches zero at which time a #VMEXIT is generated if pause
308  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
309  *      Intercept Filtering for more details.
310  *      This also indicate if ple logic enabled.
311  *
312  * pause_filter_thresh: In addition, some processor families support advanced
313  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
314  *      the amount of time a guest is allowed to execute in a pause loop.
315  *      In this mode, a 16-bit pause filter threshold field is added in the
316  *      VMCB. The threshold value is a cycle count that is used to reset the
317  *      pause counter. As with simple pause filtering, VMRUN loads the pause
318  *      count value from VMCB into an internal counter. Then, on each pause
319  *      instruction the hardware checks the elapsed number of cycles since
320  *      the most recent pause instruction against the pause filter threshold.
321  *      If the elapsed cycle count is greater than the pause filter threshold,
322  *      then the internal pause count is reloaded from the VMCB and execution
323  *      continues. If the elapsed cycle count is less than the pause filter
324  *      threshold, then the internal pause count is decremented. If the count
325  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
326  *      triggered. If advanced pause filtering is supported and pause filter
327  *      threshold field is set to zero, the filter will operate in the simpler,
328  *      count only mode.
329  */
330 
331 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
332 module_param(pause_filter_thresh, ushort, 0444);
333 
334 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
335 module_param(pause_filter_count, ushort, 0444);
336 
337 /* Default doubles per-vcpu window every exit. */
338 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
339 module_param(pause_filter_count_grow, ushort, 0444);
340 
341 /* Default resets per-vcpu window every exit to pause_filter_count. */
342 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
343 module_param(pause_filter_count_shrink, ushort, 0444);
344 
345 /* Default is to compute the maximum so we can never overflow. */
346 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
347 module_param(pause_filter_count_max, ushort, 0444);
348 
349 /* allow nested paging (virtualized MMU) for all guests */
350 static int npt = true;
351 module_param(npt, int, S_IRUGO);
352 
353 /* allow nested virtualization in KVM/SVM */
354 static int nested = true;
355 module_param(nested, int, S_IRUGO);
356 
357 /* enable / disable AVIC */
358 static int avic;
359 #ifdef CONFIG_X86_LOCAL_APIC
360 module_param(avic, int, S_IRUGO);
361 #endif
362 
363 /* enable/disable Virtual VMLOAD VMSAVE */
364 static int vls = true;
365 module_param(vls, int, 0444);
366 
367 /* enable/disable Virtual GIF */
368 static int vgif = true;
369 module_param(vgif, int, 0444);
370 
371 /* enable/disable SEV support */
372 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
373 module_param(sev, int, 0444);
374 
375 static u8 rsm_ins_bytes[] = "\x0f\xaa";
376 
377 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
378 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
379 static void svm_complete_interrupts(struct vcpu_svm *svm);
380 
381 static int nested_svm_exit_handled(struct vcpu_svm *svm);
382 static int nested_svm_intercept(struct vcpu_svm *svm);
383 static int nested_svm_vmexit(struct vcpu_svm *svm);
384 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
385                                       bool has_error_code, u32 error_code);
386 
387 enum {
388         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
389                             pause filter count */
390         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
391         VMCB_ASID,       /* ASID */
392         VMCB_INTR,       /* int_ctl, int_vector */
393         VMCB_NPT,        /* npt_en, nCR3, gPAT */
394         VMCB_CR,         /* CR0, CR3, CR4, EFER */
395         VMCB_DR,         /* DR6, DR7 */
396         VMCB_DT,         /* GDT, IDT */
397         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
398         VMCB_CR2,        /* CR2 only */
399         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
400         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
401                           * AVIC PHYSICAL_TABLE pointer,
402                           * AVIC LOGICAL_TABLE pointer
403                           */
404         VMCB_DIRTY_MAX,
405 };
406 
407 /* TPR and CR2 are always written before VMRUN */
408 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
409 
410 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
411 
412 static unsigned int max_sev_asid;
413 static unsigned int min_sev_asid;
414 static unsigned long *sev_asid_bitmap;
415 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
416 
417 struct enc_region {
418         struct list_head list;
419         unsigned long npages;
420         struct page **pages;
421         unsigned long uaddr;
422         unsigned long size;
423 };
424 
425 
426 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
427 {
428         return container_of(kvm, struct kvm_svm, kvm);
429 }
430 
431 static inline bool svm_sev_enabled(void)
432 {
433         return max_sev_asid;
434 }
435 
436 static inline bool sev_guest(struct kvm *kvm)
437 {
438         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
439 
440         return sev->active;
441 }
442 
443 static inline int sev_get_asid(struct kvm *kvm)
444 {
445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
446 
447         return sev->asid;
448 }
449 
450 static inline void mark_all_dirty(struct vmcb *vmcb)
451 {
452         vmcb->control.clean = 0;
453 }
454 
455 static inline void mark_all_clean(struct vmcb *vmcb)
456 {
457         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
458                                & ~VMCB_ALWAYS_DIRTY_MASK;
459 }
460 
461 static inline void mark_dirty(struct vmcb *vmcb, int bit)
462 {
463         vmcb->control.clean &= ~(1 << bit);
464 }
465 
466 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
467 {
468         return container_of(vcpu, struct vcpu_svm, vcpu);
469 }
470 
471 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
472 {
473         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
474         mark_dirty(svm->vmcb, VMCB_AVIC);
475 }
476 
477 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
478 {
479         struct vcpu_svm *svm = to_svm(vcpu);
480         u64 *entry = svm->avic_physical_id_cache;
481 
482         if (!entry)
483                 return false;
484 
485         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
486 }
487 
488 static void recalc_intercepts(struct vcpu_svm *svm)
489 {
490         struct vmcb_control_area *c, *h;
491         struct nested_state *g;
492 
493         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
494 
495         if (!is_guest_mode(&svm->vcpu))
496                 return;
497 
498         c = &svm->vmcb->control;
499         h = &svm->nested.hsave->control;
500         g = &svm->nested;
501 
502         c->intercept_cr = h->intercept_cr | g->intercept_cr;
503         c->intercept_dr = h->intercept_dr | g->intercept_dr;
504         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
505         c->intercept = h->intercept | g->intercept;
506 }
507 
508 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
509 {
510         if (is_guest_mode(&svm->vcpu))
511                 return svm->nested.hsave;
512         else
513                 return svm->vmcb;
514 }
515 
516 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
517 {
518         struct vmcb *vmcb = get_host_vmcb(svm);
519 
520         vmcb->control.intercept_cr |= (1U << bit);
521 
522         recalc_intercepts(svm);
523 }
524 
525 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
526 {
527         struct vmcb *vmcb = get_host_vmcb(svm);
528 
529         vmcb->control.intercept_cr &= ~(1U << bit);
530 
531         recalc_intercepts(svm);
532 }
533 
534 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
535 {
536         struct vmcb *vmcb = get_host_vmcb(svm);
537 
538         return vmcb->control.intercept_cr & (1U << bit);
539 }
540 
541 static inline void set_dr_intercepts(struct vcpu_svm *svm)
542 {
543         struct vmcb *vmcb = get_host_vmcb(svm);
544 
545         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
546                 | (1 << INTERCEPT_DR1_READ)
547                 | (1 << INTERCEPT_DR2_READ)
548                 | (1 << INTERCEPT_DR3_READ)
549                 | (1 << INTERCEPT_DR4_READ)
550                 | (1 << INTERCEPT_DR5_READ)
551                 | (1 << INTERCEPT_DR6_READ)
552                 | (1 << INTERCEPT_DR7_READ)
553                 | (1 << INTERCEPT_DR0_WRITE)
554                 | (1 << INTERCEPT_DR1_WRITE)
555                 | (1 << INTERCEPT_DR2_WRITE)
556                 | (1 << INTERCEPT_DR3_WRITE)
557                 | (1 << INTERCEPT_DR4_WRITE)
558                 | (1 << INTERCEPT_DR5_WRITE)
559                 | (1 << INTERCEPT_DR6_WRITE)
560                 | (1 << INTERCEPT_DR7_WRITE);
561 
562         recalc_intercepts(svm);
563 }
564 
565 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
566 {
567         struct vmcb *vmcb = get_host_vmcb(svm);
568 
569         vmcb->control.intercept_dr = 0;
570 
571         recalc_intercepts(svm);
572 }
573 
574 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
575 {
576         struct vmcb *vmcb = get_host_vmcb(svm);
577 
578         vmcb->control.intercept_exceptions |= (1U << bit);
579 
580         recalc_intercepts(svm);
581 }
582 
583 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
584 {
585         struct vmcb *vmcb = get_host_vmcb(svm);
586 
587         vmcb->control.intercept_exceptions &= ~(1U << bit);
588 
589         recalc_intercepts(svm);
590 }
591 
592 static inline void set_intercept(struct vcpu_svm *svm, int bit)
593 {
594         struct vmcb *vmcb = get_host_vmcb(svm);
595 
596         vmcb->control.intercept |= (1ULL << bit);
597 
598         recalc_intercepts(svm);
599 }
600 
601 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
602 {
603         struct vmcb *vmcb = get_host_vmcb(svm);
604 
605         vmcb->control.intercept &= ~(1ULL << bit);
606 
607         recalc_intercepts(svm);
608 }
609 
610 static inline bool vgif_enabled(struct vcpu_svm *svm)
611 {
612         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
613 }
614 
615 static inline void enable_gif(struct vcpu_svm *svm)
616 {
617         if (vgif_enabled(svm))
618                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
619         else
620                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
621 }
622 
623 static inline void disable_gif(struct vcpu_svm *svm)
624 {
625         if (vgif_enabled(svm))
626                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
627         else
628                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
629 }
630 
631 static inline bool gif_set(struct vcpu_svm *svm)
632 {
633         if (vgif_enabled(svm))
634                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
635         else
636                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
637 }
638 
639 static unsigned long iopm_base;
640 
641 struct kvm_ldttss_desc {
642         u16 limit0;
643         u16 base0;
644         unsigned base1:8, type:5, dpl:2, p:1;
645         unsigned limit1:4, zero0:3, g:1, base2:8;
646         u32 base3;
647         u32 zero1;
648 } __attribute__((packed));
649 
650 struct svm_cpu_data {
651         int cpu;
652 
653         u64 asid_generation;
654         u32 max_asid;
655         u32 next_asid;
656         u32 min_asid;
657         struct kvm_ldttss_desc *tss_desc;
658 
659         struct page *save_area;
660         struct vmcb *current_vmcb;
661 
662         /* index = sev_asid, value = vmcb pointer */
663         struct vmcb **sev_vmcbs;
664 };
665 
666 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
667 
668 struct svm_init_data {
669         int cpu;
670         int r;
671 };
672 
673 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
674 
675 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
676 #define MSRS_RANGE_SIZE 2048
677 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
678 
679 static u32 svm_msrpm_offset(u32 msr)
680 {
681         u32 offset;
682         int i;
683 
684         for (i = 0; i < NUM_MSR_MAPS; i++) {
685                 if (msr < msrpm_ranges[i] ||
686                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
687                         continue;
688 
689                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
690                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
691 
692                 /* Now we have the u8 offset - but need the u32 offset */
693                 return offset / 4;
694         }
695 
696         /* MSR not in any range */
697         return MSR_INVALID;
698 }
699 
700 #define MAX_INST_SIZE 15
701 
702 static inline void clgi(void)
703 {
704         asm volatile (__ex(SVM_CLGI));
705 }
706 
707 static inline void stgi(void)
708 {
709         asm volatile (__ex(SVM_STGI));
710 }
711 
712 static inline void invlpga(unsigned long addr, u32 asid)
713 {
714         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
715 }
716 
717 static int get_npt_level(struct kvm_vcpu *vcpu)
718 {
719 #ifdef CONFIG_X86_64
720         return PT64_ROOT_4LEVEL;
721 #else
722         return PT32E_ROOT_LEVEL;
723 #endif
724 }
725 
726 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
727 {
728         vcpu->arch.efer = efer;
729         if (!npt_enabled && !(efer & EFER_LMA))
730                 efer &= ~EFER_LME;
731 
732         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
733         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
734 }
735 
736 static int is_external_interrupt(u32 info)
737 {
738         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
739         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
740 }
741 
742 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
743 {
744         struct vcpu_svm *svm = to_svm(vcpu);
745         u32 ret = 0;
746 
747         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
748                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
749         return ret;
750 }
751 
752 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
753 {
754         struct vcpu_svm *svm = to_svm(vcpu);
755 
756         if (mask == 0)
757                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
758         else
759                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
760 
761 }
762 
763 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
764 {
765         struct vcpu_svm *svm = to_svm(vcpu);
766 
767         if (svm->vmcb->control.next_rip != 0) {
768                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
769                 svm->next_rip = svm->vmcb->control.next_rip;
770         }
771 
772         if (!svm->next_rip) {
773                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
774                                 EMULATE_DONE)
775                         printk(KERN_DEBUG "%s: NOP\n", __func__);
776                 return;
777         }
778         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
779                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
780                        __func__, kvm_rip_read(vcpu), svm->next_rip);
781 
782         kvm_rip_write(vcpu, svm->next_rip);
783         svm_set_interrupt_shadow(vcpu, 0);
784 }
785 
786 static void svm_queue_exception(struct kvm_vcpu *vcpu)
787 {
788         struct vcpu_svm *svm = to_svm(vcpu);
789         unsigned nr = vcpu->arch.exception.nr;
790         bool has_error_code = vcpu->arch.exception.has_error_code;
791         bool reinject = vcpu->arch.exception.injected;
792         u32 error_code = vcpu->arch.exception.error_code;
793 
794         /*
795          * If we are within a nested VM we'd better #VMEXIT and let the guest
796          * handle the exception
797          */
798         if (!reinject &&
799             nested_svm_check_exception(svm, nr, has_error_code, error_code))
800                 return;
801 
802         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
803                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
804 
805                 /*
806                  * For guest debugging where we have to reinject #BP if some
807                  * INT3 is guest-owned:
808                  * Emulate nRIP by moving RIP forward. Will fail if injection
809                  * raises a fault that is not intercepted. Still better than
810                  * failing in all cases.
811                  */
812                 skip_emulated_instruction(&svm->vcpu);
813                 rip = kvm_rip_read(&svm->vcpu);
814                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
815                 svm->int3_injected = rip - old_rip;
816         }
817 
818         svm->vmcb->control.event_inj = nr
819                 | SVM_EVTINJ_VALID
820                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
821                 | SVM_EVTINJ_TYPE_EXEPT;
822         svm->vmcb->control.event_inj_err = error_code;
823 }
824 
825 static void svm_init_erratum_383(void)
826 {
827         u32 low, high;
828         int err;
829         u64 val;
830 
831         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
832                 return;
833 
834         /* Use _safe variants to not break nested virtualization */
835         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
836         if (err)
837                 return;
838 
839         val |= (1ULL << 47);
840 
841         low  = lower_32_bits(val);
842         high = upper_32_bits(val);
843 
844         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
845 
846         erratum_383_found = true;
847 }
848 
849 static void svm_init_osvw(struct kvm_vcpu *vcpu)
850 {
851         /*
852          * Guests should see errata 400 and 415 as fixed (assuming that
853          * HLT and IO instructions are intercepted).
854          */
855         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
856         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
857 
858         /*
859          * By increasing VCPU's osvw.length to 3 we are telling the guest that
860          * all osvw.status bits inside that length, including bit 0 (which is
861          * reserved for erratum 298), are valid. However, if host processor's
862          * osvw_len is 0 then osvw_status[0] carries no information. We need to
863          * be conservative here and therefore we tell the guest that erratum 298
864          * is present (because we really don't know).
865          */
866         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
867                 vcpu->arch.osvw.status |= 1;
868 }
869 
870 static int has_svm(void)
871 {
872         const char *msg;
873 
874         if (!cpu_has_svm(&msg)) {
875                 printk(KERN_INFO "has_svm: %s\n", msg);
876                 return 0;
877         }
878 
879         return 1;
880 }
881 
882 static void svm_hardware_disable(void)
883 {
884         /* Make sure we clean up behind us */
885         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
886                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
887 
888         cpu_svm_disable();
889 
890         amd_pmu_disable_virt();
891 }
892 
893 static int svm_hardware_enable(void)
894 {
895 
896         struct svm_cpu_data *sd;
897         uint64_t efer;
898         struct desc_struct *gdt;
899         int me = raw_smp_processor_id();
900 
901         rdmsrl(MSR_EFER, efer);
902         if (efer & EFER_SVME)
903                 return -EBUSY;
904 
905         if (!has_svm()) {
906                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
907                 return -EINVAL;
908         }
909         sd = per_cpu(svm_data, me);
910         if (!sd) {
911                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
912                 return -EINVAL;
913         }
914 
915         sd->asid_generation = 1;
916         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
917         sd->next_asid = sd->max_asid + 1;
918         sd->min_asid = max_sev_asid + 1;
919 
920         gdt = get_current_gdt_rw();
921         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
922 
923         wrmsrl(MSR_EFER, efer | EFER_SVME);
924 
925         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
926 
927         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
928                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
929                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
930         }
931 
932 
933         /*
934          * Get OSVW bits.
935          *
936          * Note that it is possible to have a system with mixed processor
937          * revisions and therefore different OSVW bits. If bits are not the same
938          * on different processors then choose the worst case (i.e. if erratum
939          * is present on one processor and not on another then assume that the
940          * erratum is present everywhere).
941          */
942         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
943                 uint64_t len, status = 0;
944                 int err;
945 
946                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
947                 if (!err)
948                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
949                                                       &err);
950 
951                 if (err)
952                         osvw_status = osvw_len = 0;
953                 else {
954                         if (len < osvw_len)
955                                 osvw_len = len;
956                         osvw_status |= status;
957                         osvw_status &= (1ULL << osvw_len) - 1;
958                 }
959         } else
960                 osvw_status = osvw_len = 0;
961 
962         svm_init_erratum_383();
963 
964         amd_pmu_enable_virt();
965 
966         return 0;
967 }
968 
969 static void svm_cpu_uninit(int cpu)
970 {
971         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
972 
973         if (!sd)
974                 return;
975 
976         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
977         kfree(sd->sev_vmcbs);
978         __free_page(sd->save_area);
979         kfree(sd);
980 }
981 
982 static int svm_cpu_init(int cpu)
983 {
984         struct svm_cpu_data *sd;
985         int r;
986 
987         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
988         if (!sd)
989                 return -ENOMEM;
990         sd->cpu = cpu;
991         r = -ENOMEM;
992         sd->save_area = alloc_page(GFP_KERNEL);
993         if (!sd->save_area)
994                 goto err_1;
995 
996         if (svm_sev_enabled()) {
997                 r = -ENOMEM;
998                 sd->sev_vmcbs = kmalloc((max_sev_asid + 1) * sizeof(void *), GFP_KERNEL);
999                 if (!sd->sev_vmcbs)
1000                         goto err_1;
1001         }
1002 
1003         per_cpu(svm_data, cpu) = sd;
1004 
1005         return 0;
1006 
1007 err_1:
1008         kfree(sd);
1009         return r;
1010 
1011 }
1012 
1013 static bool valid_msr_intercept(u32 index)
1014 {
1015         int i;
1016 
1017         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1018                 if (direct_access_msrs[i].index == index)
1019                         return true;
1020 
1021         return false;
1022 }
1023 
1024 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1025 {
1026         u8 bit_write;
1027         unsigned long tmp;
1028         u32 offset;
1029         u32 *msrpm;
1030 
1031         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1032                                       to_svm(vcpu)->msrpm;
1033 
1034         offset    = svm_msrpm_offset(msr);
1035         bit_write = 2 * (msr & 0x0f) + 1;
1036         tmp       = msrpm[offset];
1037 
1038         BUG_ON(offset == MSR_INVALID);
1039 
1040         return !!test_bit(bit_write,  &tmp);
1041 }
1042 
1043 static void set_msr_interception(u32 *msrpm, unsigned msr,
1044                                  int read, int write)
1045 {
1046         u8 bit_read, bit_write;
1047         unsigned long tmp;
1048         u32 offset;
1049 
1050         /*
1051          * If this warning triggers extend the direct_access_msrs list at the
1052          * beginning of the file
1053          */
1054         WARN_ON(!valid_msr_intercept(msr));
1055 
1056         offset    = svm_msrpm_offset(msr);
1057         bit_read  = 2 * (msr & 0x0f);
1058         bit_write = 2 * (msr & 0x0f) + 1;
1059         tmp       = msrpm[offset];
1060 
1061         BUG_ON(offset == MSR_INVALID);
1062 
1063         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1064         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1065 
1066         msrpm[offset] = tmp;
1067 }
1068 
1069 static void svm_vcpu_init_msrpm(u32 *msrpm)
1070 {
1071         int i;
1072 
1073         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1074 
1075         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1076                 if (!direct_access_msrs[i].always)
1077                         continue;
1078 
1079                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1080         }
1081 }
1082 
1083 static void add_msr_offset(u32 offset)
1084 {
1085         int i;
1086 
1087         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1088 
1089                 /* Offset already in list? */
1090                 if (msrpm_offsets[i] == offset)
1091                         return;
1092 
1093                 /* Slot used by another offset? */
1094                 if (msrpm_offsets[i] != MSR_INVALID)
1095                         continue;
1096 
1097                 /* Add offset to list */
1098                 msrpm_offsets[i] = offset;
1099 
1100                 return;
1101         }
1102 
1103         /*
1104          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1105          * increase MSRPM_OFFSETS in this case.
1106          */
1107         BUG();
1108 }
1109 
1110 static void init_msrpm_offsets(void)
1111 {
1112         int i;
1113 
1114         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1115 
1116         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1117                 u32 offset;
1118 
1119                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1120                 BUG_ON(offset == MSR_INVALID);
1121 
1122                 add_msr_offset(offset);
1123         }
1124 }
1125 
1126 static void svm_enable_lbrv(struct vcpu_svm *svm)
1127 {
1128         u32 *msrpm = svm->msrpm;
1129 
1130         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1131         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1132         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1133         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1134         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1135 }
1136 
1137 static void svm_disable_lbrv(struct vcpu_svm *svm)
1138 {
1139         u32 *msrpm = svm->msrpm;
1140 
1141         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1142         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1143         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1144         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1145         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1146 }
1147 
1148 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1149 {
1150         svm->nmi_singlestep = false;
1151 
1152         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1153                 /* Clear our flags if they were not set by the guest */
1154                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1155                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1156                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1157                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1158         }
1159 }
1160 
1161 /* Note:
1162  * This hash table is used to map VM_ID to a struct kvm_svm,
1163  * when handling AMD IOMMU GALOG notification to schedule in
1164  * a particular vCPU.
1165  */
1166 #define SVM_VM_DATA_HASH_BITS   8
1167 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1168 static u32 next_vm_id = 0;
1169 static bool next_vm_id_wrapped = 0;
1170 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1171 
1172 /* Note:
1173  * This function is called from IOMMU driver to notify
1174  * SVM to schedule in a particular vCPU of a particular VM.
1175  */
1176 static int avic_ga_log_notifier(u32 ga_tag)
1177 {
1178         unsigned long flags;
1179         struct kvm_svm *kvm_svm;
1180         struct kvm_vcpu *vcpu = NULL;
1181         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1182         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1183 
1184         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1185 
1186         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1187         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1188                 if (kvm_svm->avic_vm_id != vm_id)
1189                         continue;
1190                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1191                 break;
1192         }
1193         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1194 
1195         /* Note:
1196          * At this point, the IOMMU should have already set the pending
1197          * bit in the vAPIC backing page. So, we just need to schedule
1198          * in the vcpu.
1199          */
1200         if (vcpu)
1201                 kvm_vcpu_wake_up(vcpu);
1202 
1203         return 0;
1204 }
1205 
1206 static __init int sev_hardware_setup(void)
1207 {
1208         struct sev_user_data_status *status;
1209         int rc;
1210 
1211         /* Maximum number of encrypted guests supported simultaneously */
1212         max_sev_asid = cpuid_ecx(0x8000001F);
1213 
1214         if (!max_sev_asid)
1215                 return 1;
1216 
1217         /* Minimum ASID value that should be used for SEV guest */
1218         min_sev_asid = cpuid_edx(0x8000001F);
1219 
1220         /* Initialize SEV ASID bitmap */
1221         sev_asid_bitmap = kcalloc(BITS_TO_LONGS(max_sev_asid),
1222                                 sizeof(unsigned long), GFP_KERNEL);
1223         if (!sev_asid_bitmap)
1224                 return 1;
1225 
1226         status = kmalloc(sizeof(*status), GFP_KERNEL);
1227         if (!status)
1228                 return 1;
1229 
1230         /*
1231          * Check SEV platform status.
1232          *
1233          * PLATFORM_STATUS can be called in any state, if we failed to query
1234          * the PLATFORM status then either PSP firmware does not support SEV
1235          * feature or SEV firmware is dead.
1236          */
1237         rc = sev_platform_status(status, NULL);
1238         if (rc)
1239                 goto err;
1240 
1241         pr_info("SEV supported\n");
1242 
1243 err:
1244         kfree(status);
1245         return rc;
1246 }
1247 
1248 static void grow_ple_window(struct kvm_vcpu *vcpu)
1249 {
1250         struct vcpu_svm *svm = to_svm(vcpu);
1251         struct vmcb_control_area *control = &svm->vmcb->control;
1252         int old = control->pause_filter_count;
1253 
1254         control->pause_filter_count = __grow_ple_window(old,
1255                                                         pause_filter_count,
1256                                                         pause_filter_count_grow,
1257                                                         pause_filter_count_max);
1258 
1259         if (control->pause_filter_count != old)
1260                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1261 
1262         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1263                                   control->pause_filter_count, old);
1264 }
1265 
1266 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1267 {
1268         struct vcpu_svm *svm = to_svm(vcpu);
1269         struct vmcb_control_area *control = &svm->vmcb->control;
1270         int old = control->pause_filter_count;
1271 
1272         control->pause_filter_count =
1273                                 __shrink_ple_window(old,
1274                                                     pause_filter_count,
1275                                                     pause_filter_count_shrink,
1276                                                     pause_filter_count);
1277         if (control->pause_filter_count != old)
1278                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1279 
1280         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1281                                     control->pause_filter_count, old);
1282 }
1283 
1284 static __init int svm_hardware_setup(void)
1285 {
1286         int cpu;
1287         struct page *iopm_pages;
1288         void *iopm_va;
1289         int r;
1290 
1291         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1292 
1293         if (!iopm_pages)
1294                 return -ENOMEM;
1295 
1296         iopm_va = page_address(iopm_pages);
1297         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1298         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1299 
1300         init_msrpm_offsets();
1301 
1302         if (boot_cpu_has(X86_FEATURE_NX))
1303                 kvm_enable_efer_bits(EFER_NX);
1304 
1305         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1306                 kvm_enable_efer_bits(EFER_FFXSR);
1307 
1308         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1309                 kvm_has_tsc_control = true;
1310                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1311                 kvm_tsc_scaling_ratio_frac_bits = 32;
1312         }
1313 
1314         /* Check for pause filtering support */
1315         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1316                 pause_filter_count = 0;
1317                 pause_filter_thresh = 0;
1318         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1319                 pause_filter_thresh = 0;
1320         }
1321 
1322         if (nested) {
1323                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1324                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1325         }
1326 
1327         if (sev) {
1328                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1329                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1330                         r = sev_hardware_setup();
1331                         if (r)
1332                                 sev = false;
1333                 } else {
1334                         sev = false;
1335                 }
1336         }
1337 
1338         for_each_possible_cpu(cpu) {
1339                 r = svm_cpu_init(cpu);
1340                 if (r)
1341                         goto err;
1342         }
1343 
1344         if (!boot_cpu_has(X86_FEATURE_NPT))
1345                 npt_enabled = false;
1346 
1347         if (npt_enabled && !npt) {
1348                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1349                 npt_enabled = false;
1350         }
1351 
1352         if (npt_enabled) {
1353                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1354                 kvm_enable_tdp();
1355         } else
1356                 kvm_disable_tdp();
1357 
1358         if (avic) {
1359                 if (!npt_enabled ||
1360                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1361                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1362                         avic = false;
1363                 } else {
1364                         pr_info("AVIC enabled\n");
1365 
1366                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1367                 }
1368         }
1369 
1370         if (vls) {
1371                 if (!npt_enabled ||
1372                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1373                     !IS_ENABLED(CONFIG_X86_64)) {
1374                         vls = false;
1375                 } else {
1376                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1377                 }
1378         }
1379 
1380         if (vgif) {
1381                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1382                         vgif = false;
1383                 else
1384                         pr_info("Virtual GIF supported\n");
1385         }
1386 
1387         return 0;
1388 
1389 err:
1390         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1391         iopm_base = 0;
1392         return r;
1393 }
1394 
1395 static __exit void svm_hardware_unsetup(void)
1396 {
1397         int cpu;
1398 
1399         if (svm_sev_enabled())
1400                 kfree(sev_asid_bitmap);
1401 
1402         for_each_possible_cpu(cpu)
1403                 svm_cpu_uninit(cpu);
1404 
1405         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1406         iopm_base = 0;
1407 }
1408 
1409 static void init_seg(struct vmcb_seg *seg)
1410 {
1411         seg->selector = 0;
1412         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1413                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1414         seg->limit = 0xffff;
1415         seg->base = 0;
1416 }
1417 
1418 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1419 {
1420         seg->selector = 0;
1421         seg->attrib = SVM_SELECTOR_P_MASK | type;
1422         seg->limit = 0xffff;
1423         seg->base = 0;
1424 }
1425 
1426 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1427 {
1428         struct vcpu_svm *svm = to_svm(vcpu);
1429 
1430         if (is_guest_mode(vcpu))
1431                 return svm->nested.hsave->control.tsc_offset;
1432 
1433         return vcpu->arch.tsc_offset;
1434 }
1435 
1436 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1437 {
1438         struct vcpu_svm *svm = to_svm(vcpu);
1439         u64 g_tsc_offset = 0;
1440 
1441         if (is_guest_mode(vcpu)) {
1442                 /* Write L1's TSC offset.  */
1443                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1444                                svm->nested.hsave->control.tsc_offset;
1445                 svm->nested.hsave->control.tsc_offset = offset;
1446         } else
1447                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1448                                            svm->vmcb->control.tsc_offset,
1449                                            offset);
1450 
1451         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1452 
1453         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1454 }
1455 
1456 static void avic_init_vmcb(struct vcpu_svm *svm)
1457 {
1458         struct vmcb *vmcb = svm->vmcb;
1459         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1460         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1461         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1462         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1463 
1464         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1465         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1466         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1467         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1468         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1469 }
1470 
1471 static void init_vmcb(struct vcpu_svm *svm)
1472 {
1473         struct vmcb_control_area *control = &svm->vmcb->control;
1474         struct vmcb_save_area *save = &svm->vmcb->save;
1475 
1476         svm->vcpu.arch.hflags = 0;
1477 
1478         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1479         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1480         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1481         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1482         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1483         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1484         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1485                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1486 
1487         set_dr_intercepts(svm);
1488 
1489         set_exception_intercept(svm, PF_VECTOR);
1490         set_exception_intercept(svm, UD_VECTOR);
1491         set_exception_intercept(svm, MC_VECTOR);
1492         set_exception_intercept(svm, AC_VECTOR);
1493         set_exception_intercept(svm, DB_VECTOR);
1494         /*
1495          * Guest access to VMware backdoor ports could legitimately
1496          * trigger #GP because of TSS I/O permission bitmap.
1497          * We intercept those #GP and allow access to them anyway
1498          * as VMware does.
1499          */
1500         if (enable_vmware_backdoor)
1501                 set_exception_intercept(svm, GP_VECTOR);
1502 
1503         set_intercept(svm, INTERCEPT_INTR);
1504         set_intercept(svm, INTERCEPT_NMI);
1505         set_intercept(svm, INTERCEPT_SMI);
1506         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1507         set_intercept(svm, INTERCEPT_RDPMC);
1508         set_intercept(svm, INTERCEPT_CPUID);
1509         set_intercept(svm, INTERCEPT_INVD);
1510         set_intercept(svm, INTERCEPT_INVLPG);
1511         set_intercept(svm, INTERCEPT_INVLPGA);
1512         set_intercept(svm, INTERCEPT_IOIO_PROT);
1513         set_intercept(svm, INTERCEPT_MSR_PROT);
1514         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1515         set_intercept(svm, INTERCEPT_SHUTDOWN);
1516         set_intercept(svm, INTERCEPT_VMRUN);
1517         set_intercept(svm, INTERCEPT_VMMCALL);
1518         set_intercept(svm, INTERCEPT_VMLOAD);
1519         set_intercept(svm, INTERCEPT_VMSAVE);
1520         set_intercept(svm, INTERCEPT_STGI);
1521         set_intercept(svm, INTERCEPT_CLGI);
1522         set_intercept(svm, INTERCEPT_SKINIT);
1523         set_intercept(svm, INTERCEPT_WBINVD);
1524         set_intercept(svm, INTERCEPT_XSETBV);
1525         set_intercept(svm, INTERCEPT_RSM);
1526 
1527         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1528                 set_intercept(svm, INTERCEPT_MONITOR);
1529                 set_intercept(svm, INTERCEPT_MWAIT);
1530         }
1531 
1532         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1533                 set_intercept(svm, INTERCEPT_HLT);
1534 
1535         control->iopm_base_pa = __sme_set(iopm_base);
1536         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1537         control->int_ctl = V_INTR_MASKING_MASK;
1538 
1539         init_seg(&save->es);
1540         init_seg(&save->ss);
1541         init_seg(&save->ds);
1542         init_seg(&save->fs);
1543         init_seg(&save->gs);
1544 
1545         save->cs.selector = 0xf000;
1546         save->cs.base = 0xffff0000;
1547         /* Executable/Readable Code Segment */
1548         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1549                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1550         save->cs.limit = 0xffff;
1551 
1552         save->gdtr.limit = 0xffff;
1553         save->idtr.limit = 0xffff;
1554 
1555         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1556         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1557 
1558         svm_set_efer(&svm->vcpu, 0);
1559         save->dr6 = 0xffff0ff0;
1560         kvm_set_rflags(&svm->vcpu, 2);
1561         save->rip = 0x0000fff0;
1562         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1563 
1564         /*
1565          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1566          * It also updates the guest-visible cr0 value.
1567          */
1568         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1569         kvm_mmu_reset_context(&svm->vcpu);
1570 
1571         save->cr4 = X86_CR4_PAE;
1572         /* rdx = ?? */
1573 
1574         if (npt_enabled) {
1575                 /* Setup VMCB for Nested Paging */
1576                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1577                 clr_intercept(svm, INTERCEPT_INVLPG);
1578                 clr_exception_intercept(svm, PF_VECTOR);
1579                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1580                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1581                 save->g_pat = svm->vcpu.arch.pat;
1582                 save->cr3 = 0;
1583                 save->cr4 = 0;
1584         }
1585         svm->asid_generation = 0;
1586 
1587         svm->nested.vmcb = 0;
1588         svm->vcpu.arch.hflags = 0;
1589 
1590         if (pause_filter_count) {
1591                 control->pause_filter_count = pause_filter_count;
1592                 if (pause_filter_thresh)
1593                         control->pause_filter_thresh = pause_filter_thresh;
1594                 set_intercept(svm, INTERCEPT_PAUSE);
1595         } else {
1596                 clr_intercept(svm, INTERCEPT_PAUSE);
1597         }
1598 
1599         if (kvm_vcpu_apicv_active(&svm->vcpu))
1600                 avic_init_vmcb(svm);
1601 
1602         /*
1603          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1604          * in VMCB and clear intercepts to avoid #VMEXIT.
1605          */
1606         if (vls) {
1607                 clr_intercept(svm, INTERCEPT_VMLOAD);
1608                 clr_intercept(svm, INTERCEPT_VMSAVE);
1609                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1610         }
1611 
1612         if (vgif) {
1613                 clr_intercept(svm, INTERCEPT_STGI);
1614                 clr_intercept(svm, INTERCEPT_CLGI);
1615                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1616         }
1617 
1618         if (sev_guest(svm->vcpu.kvm)) {
1619                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1620                 clr_exception_intercept(svm, UD_VECTOR);
1621         }
1622 
1623         mark_all_dirty(svm->vmcb);
1624 
1625         enable_gif(svm);
1626 
1627 }
1628 
1629 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1630                                        unsigned int index)
1631 {
1632         u64 *avic_physical_id_table;
1633         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1634 
1635         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1636                 return NULL;
1637 
1638         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1639 
1640         return &avic_physical_id_table[index];
1641 }
1642 
1643 /**
1644  * Note:
1645  * AVIC hardware walks the nested page table to check permissions,
1646  * but does not use the SPA address specified in the leaf page
1647  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1648  * field of the VMCB. Therefore, we set up the
1649  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1650  */
1651 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1652 {
1653         struct kvm *kvm = vcpu->kvm;
1654         int ret;
1655 
1656         if (kvm->arch.apic_access_page_done)
1657                 return 0;
1658 
1659         ret = x86_set_memory_region(kvm,
1660                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1661                                     APIC_DEFAULT_PHYS_BASE,
1662                                     PAGE_SIZE);
1663         if (ret)
1664                 return ret;
1665 
1666         kvm->arch.apic_access_page_done = true;
1667         return 0;
1668 }
1669 
1670 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1671 {
1672         int ret;
1673         u64 *entry, new_entry;
1674         int id = vcpu->vcpu_id;
1675         struct vcpu_svm *svm = to_svm(vcpu);
1676 
1677         ret = avic_init_access_page(vcpu);
1678         if (ret)
1679                 return ret;
1680 
1681         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1682                 return -EINVAL;
1683 
1684         if (!svm->vcpu.arch.apic->regs)
1685                 return -EINVAL;
1686 
1687         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1688 
1689         /* Setting AVIC backing page address in the phy APIC ID table */
1690         entry = avic_get_physical_id_entry(vcpu, id);
1691         if (!entry)
1692                 return -EINVAL;
1693 
1694         new_entry = READ_ONCE(*entry);
1695         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1696                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1697                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1698         WRITE_ONCE(*entry, new_entry);
1699 
1700         svm->avic_physical_id_cache = entry;
1701 
1702         return 0;
1703 }
1704 
1705 static void __sev_asid_free(int asid)
1706 {
1707         struct svm_cpu_data *sd;
1708         int cpu, pos;
1709 
1710         pos = asid - 1;
1711         clear_bit(pos, sev_asid_bitmap);
1712 
1713         for_each_possible_cpu(cpu) {
1714                 sd = per_cpu(svm_data, cpu);
1715                 sd->sev_vmcbs[pos] = NULL;
1716         }
1717 }
1718 
1719 static void sev_asid_free(struct kvm *kvm)
1720 {
1721         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1722 
1723         __sev_asid_free(sev->asid);
1724 }
1725 
1726 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1727 {
1728         struct sev_data_decommission *decommission;
1729         struct sev_data_deactivate *data;
1730 
1731         if (!handle)
1732                 return;
1733 
1734         data = kzalloc(sizeof(*data), GFP_KERNEL);
1735         if (!data)
1736                 return;
1737 
1738         /* deactivate handle */
1739         data->handle = handle;
1740         sev_guest_deactivate(data, NULL);
1741 
1742         wbinvd_on_all_cpus();
1743         sev_guest_df_flush(NULL);
1744         kfree(data);
1745 
1746         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1747         if (!decommission)
1748                 return;
1749 
1750         /* decommission handle */
1751         decommission->handle = handle;
1752         sev_guest_decommission(decommission, NULL);
1753 
1754         kfree(decommission);
1755 }
1756 
1757 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1758                                     unsigned long ulen, unsigned long *n,
1759                                     int write)
1760 {
1761         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1762         unsigned long npages, npinned, size;
1763         unsigned long locked, lock_limit;
1764         struct page **pages;
1765         int first, last;
1766 
1767         /* Calculate number of pages. */
1768         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1769         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1770         npages = (last - first + 1);
1771 
1772         locked = sev->pages_locked + npages;
1773         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1774         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1775                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1776                 return NULL;
1777         }
1778 
1779         /* Avoid using vmalloc for smaller buffers. */
1780         size = npages * sizeof(struct page *);
1781         if (size > PAGE_SIZE)
1782                 pages = vmalloc(size);
1783         else
1784                 pages = kmalloc(size, GFP_KERNEL);
1785 
1786         if (!pages)
1787                 return NULL;
1788 
1789         /* Pin the user virtual address. */
1790         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1791         if (npinned != npages) {
1792                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1793                 goto err;
1794         }
1795 
1796         *n = npages;
1797         sev->pages_locked = locked;
1798 
1799         return pages;
1800 
1801 err:
1802         if (npinned > 0)
1803                 release_pages(pages, npinned);
1804 
1805         kvfree(pages);
1806         return NULL;
1807 }
1808 
1809 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1810                              unsigned long npages)
1811 {
1812         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1813 
1814         release_pages(pages, npages);
1815         kvfree(pages);
1816         sev->pages_locked -= npages;
1817 }
1818 
1819 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1820 {
1821         uint8_t *page_virtual;
1822         unsigned long i;
1823 
1824         if (npages == 0 || pages == NULL)
1825                 return;
1826 
1827         for (i = 0; i < npages; i++) {
1828                 page_virtual = kmap_atomic(pages[i]);
1829                 clflush_cache_range(page_virtual, PAGE_SIZE);
1830                 kunmap_atomic(page_virtual);
1831         }
1832 }
1833 
1834 static void __unregister_enc_region_locked(struct kvm *kvm,
1835                                            struct enc_region *region)
1836 {
1837         /*
1838          * The guest may change the memory encryption attribute from C=0 -> C=1
1839          * or vice versa for this memory range. Lets make sure caches are
1840          * flushed to ensure that guest data gets written into memory with
1841          * correct C-bit.
1842          */
1843         sev_clflush_pages(region->pages, region->npages);
1844 
1845         sev_unpin_memory(kvm, region->pages, region->npages);
1846         list_del(&region->list);
1847         kfree(region);
1848 }
1849 
1850 static struct kvm *svm_vm_alloc(void)
1851 {
1852         struct kvm_svm *kvm_svm = kzalloc(sizeof(struct kvm_svm), GFP_KERNEL);
1853         return &kvm_svm->kvm;
1854 }
1855 
1856 static void svm_vm_free(struct kvm *kvm)
1857 {
1858         kfree(to_kvm_svm(kvm));
1859 }
1860 
1861 static void sev_vm_destroy(struct kvm *kvm)
1862 {
1863         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1864         struct list_head *head = &sev->regions_list;
1865         struct list_head *pos, *q;
1866 
1867         if (!sev_guest(kvm))
1868                 return;
1869 
1870         mutex_lock(&kvm->lock);
1871 
1872         /*
1873          * if userspace was terminated before unregistering the memory regions
1874          * then lets unpin all the registered memory.
1875          */
1876         if (!list_empty(head)) {
1877                 list_for_each_safe(pos, q, head) {
1878                         __unregister_enc_region_locked(kvm,
1879                                 list_entry(pos, struct enc_region, list));
1880                 }
1881         }
1882 
1883         mutex_unlock(&kvm->lock);
1884 
1885         sev_unbind_asid(kvm, sev->handle);
1886         sev_asid_free(kvm);
1887 }
1888 
1889 static void avic_vm_destroy(struct kvm *kvm)
1890 {
1891         unsigned long flags;
1892         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1893 
1894         if (!avic)
1895                 return;
1896 
1897         if (kvm_svm->avic_logical_id_table_page)
1898                 __free_page(kvm_svm->avic_logical_id_table_page);
1899         if (kvm_svm->avic_physical_id_table_page)
1900                 __free_page(kvm_svm->avic_physical_id_table_page);
1901 
1902         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1903         hash_del(&kvm_svm->hnode);
1904         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1905 }
1906 
1907 static void svm_vm_destroy(struct kvm *kvm)
1908 {
1909         avic_vm_destroy(kvm);
1910         sev_vm_destroy(kvm);
1911 }
1912 
1913 static int avic_vm_init(struct kvm *kvm)
1914 {
1915         unsigned long flags;
1916         int err = -ENOMEM;
1917         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1918         struct kvm_svm *k2;
1919         struct page *p_page;
1920         struct page *l_page;
1921         u32 vm_id;
1922 
1923         if (!avic)
1924                 return 0;
1925 
1926         /* Allocating physical APIC ID table (4KB) */
1927         p_page = alloc_page(GFP_KERNEL);
1928         if (!p_page)
1929                 goto free_avic;
1930 
1931         kvm_svm->avic_physical_id_table_page = p_page;
1932         clear_page(page_address(p_page));
1933 
1934         /* Allocating logical APIC ID table (4KB) */
1935         l_page = alloc_page(GFP_KERNEL);
1936         if (!l_page)
1937                 goto free_avic;
1938 
1939         kvm_svm->avic_logical_id_table_page = l_page;
1940         clear_page(page_address(l_page));
1941 
1942         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1943  again:
1944         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1945         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1946                 next_vm_id_wrapped = 1;
1947                 goto again;
1948         }
1949         /* Is it still in use? Only possible if wrapped at least once */
1950         if (next_vm_id_wrapped) {
1951                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1952                         if (k2->avic_vm_id == vm_id)
1953                                 goto again;
1954                 }
1955         }
1956         kvm_svm->avic_vm_id = vm_id;
1957         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1958         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1959 
1960         return 0;
1961 
1962 free_avic:
1963         avic_vm_destroy(kvm);
1964         return err;
1965 }
1966 
1967 static inline int
1968 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1969 {
1970         int ret = 0;
1971         unsigned long flags;
1972         struct amd_svm_iommu_ir *ir;
1973         struct vcpu_svm *svm = to_svm(vcpu);
1974 
1975         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1976                 return 0;
1977 
1978         /*
1979          * Here, we go through the per-vcpu ir_list to update all existing
1980          * interrupt remapping table entry targeting this vcpu.
1981          */
1982         spin_lock_irqsave(&svm->ir_list_lock, flags);
1983 
1984         if (list_empty(&svm->ir_list))
1985                 goto out;
1986 
1987         list_for_each_entry(ir, &svm->ir_list, node) {
1988                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1989                 if (ret)
1990                         break;
1991         }
1992 out:
1993         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1994         return ret;
1995 }
1996 
1997 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1998 {
1999         u64 entry;
2000         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2001         int h_physical_id = kvm_cpu_get_apicid(cpu);
2002         struct vcpu_svm *svm = to_svm(vcpu);
2003 
2004         if (!kvm_vcpu_apicv_active(vcpu))
2005                 return;
2006 
2007         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2008                 return;
2009 
2010         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2011         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2012 
2013         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2014         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2015 
2016         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2017         if (svm->avic_is_running)
2018                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2019 
2020         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2021         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2022                                         svm->avic_is_running);
2023 }
2024 
2025 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2026 {
2027         u64 entry;
2028         struct vcpu_svm *svm = to_svm(vcpu);
2029 
2030         if (!kvm_vcpu_apicv_active(vcpu))
2031                 return;
2032 
2033         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2034         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2035                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2036 
2037         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2038         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2039 }
2040 
2041 /**
2042  * This function is called during VCPU halt/unhalt.
2043  */
2044 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2045 {
2046         struct vcpu_svm *svm = to_svm(vcpu);
2047 
2048         svm->avic_is_running = is_run;
2049         if (is_run)
2050                 avic_vcpu_load(vcpu, vcpu->cpu);
2051         else
2052                 avic_vcpu_put(vcpu);
2053 }
2054 
2055 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2056 {
2057         struct vcpu_svm *svm = to_svm(vcpu);
2058         u32 dummy;
2059         u32 eax = 1;
2060 
2061         vcpu->arch.microcode_version = 0x01000065;
2062         svm->spec_ctrl = 0;
2063 
2064         if (!init_event) {
2065                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2066                                            MSR_IA32_APICBASE_ENABLE;
2067                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2068                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2069         }
2070         init_vmcb(svm);
2071 
2072         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2073         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2074 
2075         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2076                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2077 }
2078 
2079 static int avic_init_vcpu(struct vcpu_svm *svm)
2080 {
2081         int ret;
2082 
2083         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2084                 return 0;
2085 
2086         ret = avic_init_backing_page(&svm->vcpu);
2087         if (ret)
2088                 return ret;
2089 
2090         INIT_LIST_HEAD(&svm->ir_list);
2091         spin_lock_init(&svm->ir_list_lock);
2092 
2093         return ret;
2094 }
2095 
2096 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2097 {
2098         struct vcpu_svm *svm;
2099         struct page *page;
2100         struct page *msrpm_pages;
2101         struct page *hsave_page;
2102         struct page *nested_msrpm_pages;
2103         int err;
2104 
2105         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2106         if (!svm) {
2107                 err = -ENOMEM;
2108                 goto out;
2109         }
2110 
2111         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2112         if (err)
2113                 goto free_svm;
2114 
2115         err = -ENOMEM;
2116         page = alloc_page(GFP_KERNEL);
2117         if (!page)
2118                 goto uninit;
2119 
2120         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2121         if (!msrpm_pages)
2122                 goto free_page1;
2123 
2124         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2125         if (!nested_msrpm_pages)
2126                 goto free_page2;
2127 
2128         hsave_page = alloc_page(GFP_KERNEL);
2129         if (!hsave_page)
2130                 goto free_page3;
2131 
2132         err = avic_init_vcpu(svm);
2133         if (err)
2134                 goto free_page4;
2135 
2136         /* We initialize this flag to true to make sure that the is_running
2137          * bit would be set the first time the vcpu is loaded.
2138          */
2139         svm->avic_is_running = true;
2140 
2141         svm->nested.hsave = page_address(hsave_page);
2142 
2143         svm->msrpm = page_address(msrpm_pages);
2144         svm_vcpu_init_msrpm(svm->msrpm);
2145 
2146         svm->nested.msrpm = page_address(nested_msrpm_pages);
2147         svm_vcpu_init_msrpm(svm->nested.msrpm);
2148 
2149         svm->vmcb = page_address(page);
2150         clear_page(svm->vmcb);
2151         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2152         svm->asid_generation = 0;
2153         init_vmcb(svm);
2154 
2155         svm_init_osvw(&svm->vcpu);
2156 
2157         return &svm->vcpu;
2158 
2159 free_page4:
2160         __free_page(hsave_page);
2161 free_page3:
2162         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2163 free_page2:
2164         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2165 free_page1:
2166         __free_page(page);
2167 uninit:
2168         kvm_vcpu_uninit(&svm->vcpu);
2169 free_svm:
2170         kmem_cache_free(kvm_vcpu_cache, svm);
2171 out:
2172         return ERR_PTR(err);
2173 }
2174 
2175 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2176 {
2177         struct vcpu_svm *svm = to_svm(vcpu);
2178 
2179         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2180         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2181         __free_page(virt_to_page(svm->nested.hsave));
2182         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2183         kvm_vcpu_uninit(vcpu);
2184         kmem_cache_free(kvm_vcpu_cache, svm);
2185         /*
2186          * The vmcb page can be recycled, causing a false negative in
2187          * svm_vcpu_load(). So do a full IBPB now.
2188          */
2189         indirect_branch_prediction_barrier();
2190 }
2191 
2192 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2193 {
2194         struct vcpu_svm *svm = to_svm(vcpu);
2195         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2196         int i;
2197 
2198         if (unlikely(cpu != vcpu->cpu)) {
2199                 svm->asid_generation = 0;
2200                 mark_all_dirty(svm->vmcb);
2201         }
2202 
2203 #ifdef CONFIG_X86_64
2204         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2205 #endif
2206         savesegment(fs, svm->host.fs);
2207         savesegment(gs, svm->host.gs);
2208         svm->host.ldt = kvm_read_ldt();
2209 
2210         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2211                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2212 
2213         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2214                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2215                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2216                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2217                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2218                 }
2219         }
2220         /* This assumes that the kernel never uses MSR_TSC_AUX */
2221         if (static_cpu_has(X86_FEATURE_RDTSCP))
2222                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2223 
2224         if (sd->current_vmcb != svm->vmcb) {
2225                 sd->current_vmcb = svm->vmcb;
2226                 indirect_branch_prediction_barrier();
2227         }
2228         avic_vcpu_load(vcpu, cpu);
2229 }
2230 
2231 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2232 {
2233         struct vcpu_svm *svm = to_svm(vcpu);
2234         int i;
2235 
2236         avic_vcpu_put(vcpu);
2237 
2238         ++vcpu->stat.host_state_reload;
2239         kvm_load_ldt(svm->host.ldt);
2240 #ifdef CONFIG_X86_64
2241         loadsegment(fs, svm->host.fs);
2242         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2243         load_gs_index(svm->host.gs);
2244 #else
2245 #ifdef CONFIG_X86_32_LAZY_GS
2246         loadsegment(gs, svm->host.gs);
2247 #endif
2248 #endif
2249         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2250                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2251 }
2252 
2253 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2254 {
2255         avic_set_running(vcpu, false);
2256 }
2257 
2258 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2259 {
2260         avic_set_running(vcpu, true);
2261 }
2262 
2263 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2264 {
2265         struct vcpu_svm *svm = to_svm(vcpu);
2266         unsigned long rflags = svm->vmcb->save.rflags;
2267 
2268         if (svm->nmi_singlestep) {
2269                 /* Hide our flags if they were not set by the guest */
2270                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2271                         rflags &= ~X86_EFLAGS_TF;
2272                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2273                         rflags &= ~X86_EFLAGS_RF;
2274         }
2275         return rflags;
2276 }
2277 
2278 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2279 {
2280         if (to_svm(vcpu)->nmi_singlestep)
2281                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2282 
2283        /*
2284         * Any change of EFLAGS.VM is accompanied by a reload of SS
2285         * (caused by either a task switch or an inter-privilege IRET),
2286         * so we do not need to update the CPL here.
2287         */
2288         to_svm(vcpu)->vmcb->save.rflags = rflags;
2289 }
2290 
2291 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2292 {
2293         switch (reg) {
2294         case VCPU_EXREG_PDPTR:
2295                 BUG_ON(!npt_enabled);
2296                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2297                 break;
2298         default:
2299                 BUG();
2300         }
2301 }
2302 
2303 static void svm_set_vintr(struct vcpu_svm *svm)
2304 {
2305         set_intercept(svm, INTERCEPT_VINTR);
2306 }
2307 
2308 static void svm_clear_vintr(struct vcpu_svm *svm)
2309 {
2310         clr_intercept(svm, INTERCEPT_VINTR);
2311 }
2312 
2313 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2314 {
2315         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2316 
2317         switch (seg) {
2318         case VCPU_SREG_CS: return &save->cs;
2319         case VCPU_SREG_DS: return &save->ds;
2320         case VCPU_SREG_ES: return &save->es;
2321         case VCPU_SREG_FS: return &save->fs;
2322         case VCPU_SREG_GS: return &save->gs;
2323         case VCPU_SREG_SS: return &save->ss;
2324         case VCPU_SREG_TR: return &save->tr;
2325         case VCPU_SREG_LDTR: return &save->ldtr;
2326         }
2327         BUG();
2328         return NULL;
2329 }
2330 
2331 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2332 {
2333         struct vmcb_seg *s = svm_seg(vcpu, seg);
2334 
2335         return s->base;
2336 }
2337 
2338 static void svm_get_segment(struct kvm_vcpu *vcpu,
2339                             struct kvm_segment *var, int seg)
2340 {
2341         struct vmcb_seg *s = svm_seg(vcpu, seg);
2342 
2343         var->base = s->base;
2344         var->limit = s->limit;
2345         var->selector = s->selector;
2346         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2347         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2348         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2349         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2350         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2351         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2352         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2353 
2354         /*
2355          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2356          * However, the SVM spec states that the G bit is not observed by the
2357          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2358          * So let's synthesize a legal G bit for all segments, this helps
2359          * running KVM nested. It also helps cross-vendor migration, because
2360          * Intel's vmentry has a check on the 'G' bit.
2361          */
2362         var->g = s->limit > 0xfffff;
2363 
2364         /*
2365          * AMD's VMCB does not have an explicit unusable field, so emulate it
2366          * for cross vendor migration purposes by "not present"
2367          */
2368         var->unusable = !var->present;
2369 
2370         switch (seg) {
2371         case VCPU_SREG_TR:
2372                 /*
2373                  * Work around a bug where the busy flag in the tr selector
2374                  * isn't exposed
2375                  */
2376                 var->type |= 0x2;
2377                 break;
2378         case VCPU_SREG_DS:
2379         case VCPU_SREG_ES:
2380         case VCPU_SREG_FS:
2381         case VCPU_SREG_GS:
2382                 /*
2383                  * The accessed bit must always be set in the segment
2384                  * descriptor cache, although it can be cleared in the
2385                  * descriptor, the cached bit always remains at 1. Since
2386                  * Intel has a check on this, set it here to support
2387                  * cross-vendor migration.
2388                  */
2389                 if (!var->unusable)
2390                         var->type |= 0x1;
2391                 break;
2392         case VCPU_SREG_SS:
2393                 /*
2394                  * On AMD CPUs sometimes the DB bit in the segment
2395                  * descriptor is left as 1, although the whole segment has
2396                  * been made unusable. Clear it here to pass an Intel VMX
2397                  * entry check when cross vendor migrating.
2398                  */
2399                 if (var->unusable)
2400                         var->db = 0;
2401                 /* This is symmetric with svm_set_segment() */
2402                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2403                 break;
2404         }
2405 }
2406 
2407 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2408 {
2409         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2410 
2411         return save->cpl;
2412 }
2413 
2414 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2415 {
2416         struct vcpu_svm *svm = to_svm(vcpu);
2417 
2418         dt->size = svm->vmcb->save.idtr.limit;
2419         dt->address = svm->vmcb->save.idtr.base;
2420 }
2421 
2422 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2423 {
2424         struct vcpu_svm *svm = to_svm(vcpu);
2425 
2426         svm->vmcb->save.idtr.limit = dt->size;
2427         svm->vmcb->save.idtr.base = dt->address ;
2428         mark_dirty(svm->vmcb, VMCB_DT);
2429 }
2430 
2431 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2432 {
2433         struct vcpu_svm *svm = to_svm(vcpu);
2434 
2435         dt->size = svm->vmcb->save.gdtr.limit;
2436         dt->address = svm->vmcb->save.gdtr.base;
2437 }
2438 
2439 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2440 {
2441         struct vcpu_svm *svm = to_svm(vcpu);
2442 
2443         svm->vmcb->save.gdtr.limit = dt->size;
2444         svm->vmcb->save.gdtr.base = dt->address ;
2445         mark_dirty(svm->vmcb, VMCB_DT);
2446 }
2447 
2448 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2449 {
2450 }
2451 
2452 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2453 {
2454 }
2455 
2456 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2457 {
2458 }
2459 
2460 static void update_cr0_intercept(struct vcpu_svm *svm)
2461 {
2462         ulong gcr0 = svm->vcpu.arch.cr0;
2463         u64 *hcr0 = &svm->vmcb->save.cr0;
2464 
2465         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2466                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2467 
2468         mark_dirty(svm->vmcb, VMCB_CR);
2469 
2470         if (gcr0 == *hcr0) {
2471                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2472                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2473         } else {
2474                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2475                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2476         }
2477 }
2478 
2479 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2480 {
2481         struct vcpu_svm *svm = to_svm(vcpu);
2482 
2483 #ifdef CONFIG_X86_64
2484         if (vcpu->arch.efer & EFER_LME) {
2485                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2486                         vcpu->arch.efer |= EFER_LMA;
2487                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2488                 }
2489 
2490                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2491                         vcpu->arch.efer &= ~EFER_LMA;
2492                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2493                 }
2494         }
2495 #endif
2496         vcpu->arch.cr0 = cr0;
2497 
2498         if (!npt_enabled)
2499                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2500 
2501         /*
2502          * re-enable caching here because the QEMU bios
2503          * does not do it - this results in some delay at
2504          * reboot
2505          */
2506         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2507                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2508         svm->vmcb->save.cr0 = cr0;
2509         mark_dirty(svm->vmcb, VMCB_CR);
2510         update_cr0_intercept(svm);
2511 }
2512 
2513 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2514 {
2515         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2516         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2517 
2518         if (cr4 & X86_CR4_VMXE)
2519                 return 1;
2520 
2521         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2522                 svm_flush_tlb(vcpu, true);
2523 
2524         vcpu->arch.cr4 = cr4;
2525         if (!npt_enabled)
2526                 cr4 |= X86_CR4_PAE;
2527         cr4 |= host_cr4_mce;
2528         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2529         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2530         return 0;
2531 }
2532 
2533 static void svm_set_segment(struct kvm_vcpu *vcpu,
2534                             struct kvm_segment *var, int seg)
2535 {
2536         struct vcpu_svm *svm = to_svm(vcpu);
2537         struct vmcb_seg *s = svm_seg(vcpu, seg);
2538 
2539         s->base = var->base;
2540         s->limit = var->limit;
2541         s->selector = var->selector;
2542         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2543         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2544         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2545         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2546         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2547         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2548         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2549         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2550 
2551         /*
2552          * This is always accurate, except if SYSRET returned to a segment
2553          * with SS.DPL != 3.  Intel does not have this quirk, and always
2554          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2555          * would entail passing the CPL to userspace and back.
2556          */
2557         if (seg == VCPU_SREG_SS)
2558                 /* This is symmetric with svm_get_segment() */
2559                 svm->vmcb->save.cpl = (var->dpl & 3);
2560 
2561         mark_dirty(svm->vmcb, VMCB_SEG);
2562 }
2563 
2564 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2565 {
2566         struct vcpu_svm *svm = to_svm(vcpu);
2567 
2568         clr_exception_intercept(svm, BP_VECTOR);
2569 
2570         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2571                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2572                         set_exception_intercept(svm, BP_VECTOR);
2573         } else
2574                 vcpu->guest_debug = 0;
2575 }
2576 
2577 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2578 {
2579         if (sd->next_asid > sd->max_asid) {
2580                 ++sd->asid_generation;
2581                 sd->next_asid = sd->min_asid;
2582                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2583         }
2584 
2585         svm->asid_generation = sd->asid_generation;
2586         svm->vmcb->control.asid = sd->next_asid++;
2587 
2588         mark_dirty(svm->vmcb, VMCB_ASID);
2589 }
2590 
2591 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2592 {
2593         return to_svm(vcpu)->vmcb->save.dr6;
2594 }
2595 
2596 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2597 {
2598         struct vcpu_svm *svm = to_svm(vcpu);
2599 
2600         svm->vmcb->save.dr6 = value;
2601         mark_dirty(svm->vmcb, VMCB_DR);
2602 }
2603 
2604 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2605 {
2606         struct vcpu_svm *svm = to_svm(vcpu);
2607 
2608         get_debugreg(vcpu->arch.db[0], 0);
2609         get_debugreg(vcpu->arch.db[1], 1);
2610         get_debugreg(vcpu->arch.db[2], 2);
2611         get_debugreg(vcpu->arch.db[3], 3);
2612         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2613         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2614 
2615         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2616         set_dr_intercepts(svm);
2617 }
2618 
2619 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2620 {
2621         struct vcpu_svm *svm = to_svm(vcpu);
2622 
2623         svm->vmcb->save.dr7 = value;
2624         mark_dirty(svm->vmcb, VMCB_DR);
2625 }
2626 
2627 static int pf_interception(struct vcpu_svm *svm)
2628 {
2629         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2630         u64 error_code = svm->vmcb->control.exit_info_1;
2631 
2632         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2633                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2634                         svm->vmcb->control.insn_bytes : NULL,
2635                         svm->vmcb->control.insn_len);
2636 }
2637 
2638 static int npf_interception(struct vcpu_svm *svm)
2639 {
2640         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2641         u64 error_code = svm->vmcb->control.exit_info_1;
2642 
2643         trace_kvm_page_fault(fault_address, error_code);
2644         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2645                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2646                         svm->vmcb->control.insn_bytes : NULL,
2647                         svm->vmcb->control.insn_len);
2648 }
2649 
2650 static int db_interception(struct vcpu_svm *svm)
2651 {
2652         struct kvm_run *kvm_run = svm->vcpu.run;
2653 
2654         if (!(svm->vcpu.guest_debug &
2655               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2656                 !svm->nmi_singlestep) {
2657                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2658                 return 1;
2659         }
2660 
2661         if (svm->nmi_singlestep) {
2662                 disable_nmi_singlestep(svm);
2663         }
2664 
2665         if (svm->vcpu.guest_debug &
2666             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2667                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2668                 kvm_run->debug.arch.pc =
2669                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2670                 kvm_run->debug.arch.exception = DB_VECTOR;
2671                 return 0;
2672         }
2673 
2674         return 1;
2675 }
2676 
2677 static int bp_interception(struct vcpu_svm *svm)
2678 {
2679         struct kvm_run *kvm_run = svm->vcpu.run;
2680 
2681         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2682         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2683         kvm_run->debug.arch.exception = BP_VECTOR;
2684         return 0;
2685 }
2686 
2687 static int ud_interception(struct vcpu_svm *svm)
2688 {
2689         return handle_ud(&svm->vcpu);
2690 }
2691 
2692 static int ac_interception(struct vcpu_svm *svm)
2693 {
2694         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2695         return 1;
2696 }
2697 
2698 static int gp_interception(struct vcpu_svm *svm)
2699 {
2700         struct kvm_vcpu *vcpu = &svm->vcpu;
2701         u32 error_code = svm->vmcb->control.exit_info_1;
2702         int er;
2703 
2704         WARN_ON_ONCE(!enable_vmware_backdoor);
2705 
2706         er = emulate_instruction(vcpu,
2707                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2708         if (er == EMULATE_USER_EXIT)
2709                 return 0;
2710         else if (er != EMULATE_DONE)
2711                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2712         return 1;
2713 }
2714 
2715 static bool is_erratum_383(void)
2716 {
2717         int err, i;
2718         u64 value;
2719 
2720         if (!erratum_383_found)
2721                 return false;
2722 
2723         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2724         if (err)
2725                 return false;
2726 
2727         /* Bit 62 may or may not be set for this mce */
2728         value &= ~(1ULL << 62);
2729 
2730         if (value != 0xb600000000010015ULL)
2731                 return false;
2732 
2733         /* Clear MCi_STATUS registers */
2734         for (i = 0; i < 6; ++i)
2735                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2736 
2737         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2738         if (!err) {
2739                 u32 low, high;
2740 
2741                 value &= ~(1ULL << 2);
2742                 low    = lower_32_bits(value);
2743                 high   = upper_32_bits(value);
2744 
2745                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2746         }
2747 
2748         /* Flush tlb to evict multi-match entries */
2749         __flush_tlb_all();
2750 
2751         return true;
2752 }
2753 
2754 static void svm_handle_mce(struct vcpu_svm *svm)
2755 {
2756         if (is_erratum_383()) {
2757                 /*
2758                  * Erratum 383 triggered. Guest state is corrupt so kill the
2759                  * guest.
2760                  */
2761                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2762 
2763                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2764 
2765                 return;
2766         }
2767 
2768         /*
2769          * On an #MC intercept the MCE handler is not called automatically in
2770          * the host. So do it by hand here.
2771          */
2772         asm volatile (
2773                 "int $0x12\n");
2774         /* not sure if we ever come back to this point */
2775 
2776         return;
2777 }
2778 
2779 static int mc_interception(struct vcpu_svm *svm)
2780 {
2781         return 1;
2782 }
2783 
2784 static int shutdown_interception(struct vcpu_svm *svm)
2785 {
2786         struct kvm_run *kvm_run = svm->vcpu.run;
2787 
2788         /*
2789          * VMCB is undefined after a SHUTDOWN intercept
2790          * so reinitialize it.
2791          */
2792         clear_page(svm->vmcb);
2793         init_vmcb(svm);
2794 
2795         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2796         return 0;
2797 }
2798 
2799 static int io_interception(struct vcpu_svm *svm)
2800 {
2801         struct kvm_vcpu *vcpu = &svm->vcpu;
2802         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2803         int size, in, string;
2804         unsigned port;
2805 
2806         ++svm->vcpu.stat.io_exits;
2807         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2808         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2809         if (string)
2810                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2811 
2812         port = io_info >> 16;
2813         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2814         svm->next_rip = svm->vmcb->control.exit_info_2;
2815 
2816         return kvm_fast_pio(&svm->vcpu, size, port, in);
2817 }
2818 
2819 static int nmi_interception(struct vcpu_svm *svm)
2820 {
2821         return 1;
2822 }
2823 
2824 static int intr_interception(struct vcpu_svm *svm)
2825 {
2826         ++svm->vcpu.stat.irq_exits;
2827         return 1;
2828 }
2829 
2830 static int nop_on_interception(struct vcpu_svm *svm)
2831 {
2832         return 1;
2833 }
2834 
2835 static int halt_interception(struct vcpu_svm *svm)
2836 {
2837         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2838         return kvm_emulate_halt(&svm->vcpu);
2839 }
2840 
2841 static int vmmcall_interception(struct vcpu_svm *svm)
2842 {
2843         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2844         return kvm_emulate_hypercall(&svm->vcpu);
2845 }
2846 
2847 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2848 {
2849         struct vcpu_svm *svm = to_svm(vcpu);
2850 
2851         return svm->nested.nested_cr3;
2852 }
2853 
2854 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2855 {
2856         struct vcpu_svm *svm = to_svm(vcpu);
2857         u64 cr3 = svm->nested.nested_cr3;
2858         u64 pdpte;
2859         int ret;
2860 
2861         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2862                                        offset_in_page(cr3) + index * 8, 8);
2863         if (ret)
2864                 return 0;
2865         return pdpte;
2866 }
2867 
2868 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2869                                    unsigned long root)
2870 {
2871         struct vcpu_svm *svm = to_svm(vcpu);
2872 
2873         svm->vmcb->control.nested_cr3 = __sme_set(root);
2874         mark_dirty(svm->vmcb, VMCB_NPT);
2875         svm_flush_tlb(vcpu, true);
2876 }
2877 
2878 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2879                                        struct x86_exception *fault)
2880 {
2881         struct vcpu_svm *svm = to_svm(vcpu);
2882 
2883         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2884                 /*
2885                  * TODO: track the cause of the nested page fault, and
2886                  * correctly fill in the high bits of exit_info_1.
2887                  */
2888                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2889                 svm->vmcb->control.exit_code_hi = 0;
2890                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2891                 svm->vmcb->control.exit_info_2 = fault->address;
2892         }
2893 
2894         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2895         svm->vmcb->control.exit_info_1 |= fault->error_code;
2896 
2897         /*
2898          * The present bit is always zero for page structure faults on real
2899          * hardware.
2900          */
2901         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2902                 svm->vmcb->control.exit_info_1 &= ~1;
2903 
2904         nested_svm_vmexit(svm);
2905 }
2906 
2907 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2908 {
2909         WARN_ON(mmu_is_nested(vcpu));
2910         kvm_init_shadow_mmu(vcpu);
2911         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2912         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2913         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2914         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2915         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2916         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2917         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2918 }
2919 
2920 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2921 {
2922         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2923 }
2924 
2925 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2926 {
2927         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2928             !is_paging(&svm->vcpu)) {
2929                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2930                 return 1;
2931         }
2932 
2933         if (svm->vmcb->save.cpl) {
2934                 kvm_inject_gp(&svm->vcpu, 0);
2935                 return 1;
2936         }
2937 
2938         return 0;
2939 }
2940 
2941 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2942                                       bool has_error_code, u32 error_code)
2943 {
2944         int vmexit;
2945 
2946         if (!is_guest_mode(&svm->vcpu))
2947                 return 0;
2948 
2949         vmexit = nested_svm_intercept(svm);
2950         if (vmexit != NESTED_EXIT_DONE)
2951                 return 0;
2952 
2953         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2954         svm->vmcb->control.exit_code_hi = 0;
2955         svm->vmcb->control.exit_info_1 = error_code;
2956 
2957         /*
2958          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2959          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2960          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2961          * written only when inject_pending_event runs (DR6 would written here
2962          * too).  This should be conditional on a new capability---if the
2963          * capability is disabled, kvm_multiple_exception would write the
2964          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2965          */
2966         if (svm->vcpu.arch.exception.nested_apf)
2967                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2968         else
2969                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2970 
2971         svm->nested.exit_required = true;
2972         return vmexit;
2973 }
2974 
2975 /* This function returns true if it is save to enable the irq window */
2976 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2977 {
2978         if (!is_guest_mode(&svm->vcpu))
2979                 return true;
2980 
2981         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2982                 return true;
2983 
2984         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2985                 return false;
2986 
2987         /*
2988          * if vmexit was already requested (by intercepted exception
2989          * for instance) do not overwrite it with "external interrupt"
2990          * vmexit.
2991          */
2992         if (svm->nested.exit_required)
2993                 return false;
2994 
2995         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2996         svm->vmcb->control.exit_info_1 = 0;
2997         svm->vmcb->control.exit_info_2 = 0;
2998 
2999         if (svm->nested.intercept & 1ULL) {
3000                 /*
3001                  * The #vmexit can't be emulated here directly because this
3002                  * code path runs with irqs and preemption disabled. A
3003                  * #vmexit emulation might sleep. Only signal request for
3004                  * the #vmexit here.
3005                  */
3006                 svm->nested.exit_required = true;
3007                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3008                 return false;
3009         }
3010 
3011         return true;
3012 }
3013 
3014 /* This function returns true if it is save to enable the nmi window */
3015 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3016 {
3017         if (!is_guest_mode(&svm->vcpu))
3018                 return true;
3019 
3020         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3021                 return true;
3022 
3023         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3024         svm->nested.exit_required = true;
3025 
3026         return false;
3027 }
3028 
3029 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3030 {
3031         struct page *page;
3032 
3033         might_sleep();
3034 
3035         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3036         if (is_error_page(page))
3037                 goto error;
3038 
3039         *_page = page;
3040 
3041         return kmap(page);
3042 
3043 error:
3044         kvm_inject_gp(&svm->vcpu, 0);
3045 
3046         return NULL;
3047 }
3048 
3049 static void nested_svm_unmap(struct page *page)
3050 {
3051         kunmap(page);
3052         kvm_release_page_dirty(page);
3053 }
3054 
3055 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3056 {
3057         unsigned port, size, iopm_len;
3058         u16 val, mask;
3059         u8 start_bit;
3060         u64 gpa;
3061 
3062         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3063                 return NESTED_EXIT_HOST;
3064 
3065         port = svm->vmcb->control.exit_info_1 >> 16;
3066         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3067                 SVM_IOIO_SIZE_SHIFT;
3068         gpa  = svm->nested.vmcb_iopm + (port / 8);
3069         start_bit = port % 8;
3070         iopm_len = (start_bit + size > 8) ? 2 : 1;
3071         mask = (0xf >> (4 - size)) << start_bit;
3072         val = 0;
3073 
3074         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3075                 return NESTED_EXIT_DONE;
3076 
3077         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3078 }
3079 
3080 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3081 {
3082         u32 offset, msr, value;
3083         int write, mask;
3084 
3085         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3086                 return NESTED_EXIT_HOST;
3087 
3088         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3089         offset = svm_msrpm_offset(msr);
3090         write  = svm->vmcb->control.exit_info_1 & 1;
3091         mask   = 1 << ((2 * (msr & 0xf)) + write);
3092 
3093         if (offset == MSR_INVALID)
3094                 return NESTED_EXIT_DONE;
3095 
3096         /* Offset is in 32 bit units but need in 8 bit units */
3097         offset *= 4;
3098 
3099         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3100                 return NESTED_EXIT_DONE;
3101 
3102         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3103 }
3104 
3105 /* DB exceptions for our internal use must not cause vmexit */
3106 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3107 {
3108         unsigned long dr6;
3109 
3110         /* if we're not singlestepping, it's not ours */
3111         if (!svm->nmi_singlestep)
3112                 return NESTED_EXIT_DONE;
3113 
3114         /* if it's not a singlestep exception, it's not ours */
3115         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3116                 return NESTED_EXIT_DONE;
3117         if (!(dr6 & DR6_BS))
3118                 return NESTED_EXIT_DONE;
3119 
3120         /* if the guest is singlestepping, it should get the vmexit */
3121         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3122                 disable_nmi_singlestep(svm);
3123                 return NESTED_EXIT_DONE;
3124         }
3125 
3126         /* it's ours, the nested hypervisor must not see this one */
3127         return NESTED_EXIT_HOST;
3128 }
3129 
3130 static int nested_svm_exit_special(struct vcpu_svm *svm)
3131 {
3132         u32 exit_code = svm->vmcb->control.exit_code;
3133 
3134         switch (exit_code) {
3135         case SVM_EXIT_INTR:
3136         case SVM_EXIT_NMI:
3137         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3138                 return NESTED_EXIT_HOST;
3139         case SVM_EXIT_NPF:
3140                 /* For now we are always handling NPFs when using them */
3141                 if (npt_enabled)
3142                         return NESTED_EXIT_HOST;
3143                 break;
3144         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3145                 /* When we're shadowing, trap PFs, but not async PF */
3146                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3147                         return NESTED_EXIT_HOST;
3148                 break;
3149         default:
3150                 break;
3151         }
3152 
3153         return NESTED_EXIT_CONTINUE;
3154 }
3155 
3156 /*
3157  * If this function returns true, this #vmexit was already handled
3158  */
3159 static int nested_svm_intercept(struct vcpu_svm *svm)
3160 {
3161         u32 exit_code = svm->vmcb->control.exit_code;
3162         int vmexit = NESTED_EXIT_HOST;
3163 
3164         switch (exit_code) {
3165         case SVM_EXIT_MSR:
3166                 vmexit = nested_svm_exit_handled_msr(svm);
3167                 break;
3168         case SVM_EXIT_IOIO:
3169                 vmexit = nested_svm_intercept_ioio(svm);
3170                 break;
3171         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3172                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3173                 if (svm->nested.intercept_cr & bit)
3174                         vmexit = NESTED_EXIT_DONE;
3175                 break;
3176         }
3177         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3178                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3179                 if (svm->nested.intercept_dr & bit)
3180                         vmexit = NESTED_EXIT_DONE;
3181                 break;
3182         }
3183         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3184                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3185                 if (svm->nested.intercept_exceptions & excp_bits) {
3186                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3187                                 vmexit = nested_svm_intercept_db(svm);
3188                         else
3189                                 vmexit = NESTED_EXIT_DONE;
3190                 }
3191                 /* async page fault always cause vmexit */
3192                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3193                          svm->vcpu.arch.exception.nested_apf != 0)
3194                         vmexit = NESTED_EXIT_DONE;
3195                 break;
3196         }
3197         case SVM_EXIT_ERR: {
3198                 vmexit = NESTED_EXIT_DONE;
3199                 break;
3200         }
3201         default: {
3202                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3203                 if (svm->nested.intercept & exit_bits)
3204                         vmexit = NESTED_EXIT_DONE;
3205         }
3206         }
3207 
3208         return vmexit;
3209 }
3210 
3211 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3212 {
3213         int vmexit;
3214 
3215         vmexit = nested_svm_intercept(svm);
3216 
3217         if (vmexit == NESTED_EXIT_DONE)
3218                 nested_svm_vmexit(svm);
3219 
3220         return vmexit;
3221 }
3222 
3223 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3224 {
3225         struct vmcb_control_area *dst  = &dst_vmcb->control;
3226         struct vmcb_control_area *from = &from_vmcb->control;
3227 
3228         dst->intercept_cr         = from->intercept_cr;
3229         dst->intercept_dr         = from->intercept_dr;
3230         dst->intercept_exceptions = from->intercept_exceptions;
3231         dst->intercept            = from->intercept;
3232         dst->iopm_base_pa         = from->iopm_base_pa;
3233         dst->msrpm_base_pa        = from->msrpm_base_pa;
3234         dst->tsc_offset           = from->tsc_offset;
3235         dst->asid                 = from->asid;
3236         dst->tlb_ctl              = from->tlb_ctl;
3237         dst->int_ctl              = from->int_ctl;
3238         dst->int_vector           = from->int_vector;
3239         dst->int_state            = from->int_state;
3240         dst->exit_code            = from->exit_code;
3241         dst->exit_code_hi         = from->exit_code_hi;
3242         dst->exit_info_1          = from->exit_info_1;
3243         dst->exit_info_2          = from->exit_info_2;
3244         dst->exit_int_info        = from->exit_int_info;
3245         dst->exit_int_info_err    = from->exit_int_info_err;
3246         dst->nested_ctl           = from->nested_ctl;
3247         dst->event_inj            = from->event_inj;
3248         dst->event_inj_err        = from->event_inj_err;
3249         dst->nested_cr3           = from->nested_cr3;
3250         dst->virt_ext              = from->virt_ext;
3251 }
3252 
3253 static int nested_svm_vmexit(struct vcpu_svm *svm)
3254 {
3255         struct vmcb *nested_vmcb;
3256         struct vmcb *hsave = svm->nested.hsave;
3257         struct vmcb *vmcb = svm->vmcb;
3258         struct page *page;
3259 
3260         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3261                                        vmcb->control.exit_info_1,
3262                                        vmcb->control.exit_info_2,
3263                                        vmcb->control.exit_int_info,
3264                                        vmcb->control.exit_int_info_err,
3265                                        KVM_ISA_SVM);
3266 
3267         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3268         if (!nested_vmcb)
3269                 return 1;
3270 
3271         /* Exit Guest-Mode */
3272         leave_guest_mode(&svm->vcpu);
3273         svm->nested.vmcb = 0;
3274 
3275         /* Give the current vmcb to the guest */
3276         disable_gif(svm);
3277 
3278         nested_vmcb->save.es     = vmcb->save.es;
3279         nested_vmcb->save.cs     = vmcb->save.cs;
3280         nested_vmcb->save.ss     = vmcb->save.ss;
3281         nested_vmcb->save.ds     = vmcb->save.ds;
3282         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3283         nested_vmcb->save.idtr   = vmcb->save.idtr;
3284         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3285         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3286         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3287         nested_vmcb->save.cr2    = vmcb->save.cr2;
3288         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3289         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3290         nested_vmcb->save.rip    = vmcb->save.rip;
3291         nested_vmcb->save.rsp    = vmcb->save.rsp;
3292         nested_vmcb->save.rax    = vmcb->save.rax;
3293         nested_vmcb->save.dr7    = vmcb->save.dr7;
3294         nested_vmcb->save.dr6    = vmcb->save.dr6;
3295         nested_vmcb->save.cpl    = vmcb->save.cpl;
3296 
3297         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3298         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3299         nested_vmcb->control.int_state         = vmcb->control.int_state;
3300         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3301         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3302         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3303         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3304         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3305         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3306 
3307         if (svm->nrips_enabled)
3308                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3309 
3310         /*
3311          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3312          * to make sure that we do not lose injected events. So check event_inj
3313          * here and copy it to exit_int_info if it is valid.
3314          * Exit_int_info and event_inj can't be both valid because the case
3315          * below only happens on a VMRUN instruction intercept which has
3316          * no valid exit_int_info set.
3317          */
3318         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3319                 struct vmcb_control_area *nc = &nested_vmcb->control;
3320 
3321                 nc->exit_int_info     = vmcb->control.event_inj;
3322                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3323         }
3324 
3325         nested_vmcb->control.tlb_ctl           = 0;
3326         nested_vmcb->control.event_inj         = 0;
3327         nested_vmcb->control.event_inj_err     = 0;
3328 
3329         /* We always set V_INTR_MASKING and remember the old value in hflags */
3330         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3331                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3332 
3333         /* Restore the original control entries */
3334         copy_vmcb_control_area(vmcb, hsave);
3335 
3336         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3337         kvm_clear_exception_queue(&svm->vcpu);
3338         kvm_clear_interrupt_queue(&svm->vcpu);
3339 
3340         svm->nested.nested_cr3 = 0;
3341 
3342         /* Restore selected save entries */
3343         svm->vmcb->save.es = hsave->save.es;
3344         svm->vmcb->save.cs = hsave->save.cs;
3345         svm->vmcb->save.ss = hsave->save.ss;
3346         svm->vmcb->save.ds = hsave->save.ds;
3347         svm->vmcb->save.gdtr = hsave->save.gdtr;
3348         svm->vmcb->save.idtr = hsave->save.idtr;
3349         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3350         svm_set_efer(&svm->vcpu, hsave->save.efer);
3351         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3352         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3353         if (npt_enabled) {
3354                 svm->vmcb->save.cr3 = hsave->save.cr3;
3355                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3356         } else {
3357                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3358         }
3359         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3360         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3361         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3362         svm->vmcb->save.dr7 = 0;
3363         svm->vmcb->save.cpl = 0;
3364         svm->vmcb->control.exit_int_info = 0;
3365 
3366         mark_all_dirty(svm->vmcb);
3367 
3368         nested_svm_unmap(page);
3369 
3370         nested_svm_uninit_mmu_context(&svm->vcpu);
3371         kvm_mmu_reset_context(&svm->vcpu);
3372         kvm_mmu_load(&svm->vcpu);
3373 
3374         return 0;
3375 }
3376 
3377 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3378 {
3379         /*
3380          * This function merges the msr permission bitmaps of kvm and the
3381          * nested vmcb. It is optimized in that it only merges the parts where
3382          * the kvm msr permission bitmap may contain zero bits
3383          */
3384         int i;
3385 
3386         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3387                 return true;
3388 
3389         for (i = 0; i < MSRPM_OFFSETS; i++) {
3390                 u32 value, p;
3391                 u64 offset;
3392 
3393                 if (msrpm_offsets[i] == 0xffffffff)
3394                         break;
3395 
3396                 p      = msrpm_offsets[i];
3397                 offset = svm->nested.vmcb_msrpm + (p * 4);
3398 
3399                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3400                         return false;
3401 
3402                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3403         }
3404 
3405         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3406 
3407         return true;
3408 }
3409 
3410 static bool nested_vmcb_checks(struct vmcb *vmcb)
3411 {
3412         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3413                 return false;
3414 
3415         if (vmcb->control.asid == 0)
3416                 return false;
3417 
3418         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3419             !npt_enabled)
3420                 return false;
3421 
3422         return true;
3423 }
3424 
3425 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3426                                  struct vmcb *nested_vmcb, struct page *page)
3427 {
3428         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3429                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3430         else
3431                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3432 
3433         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3434                 kvm_mmu_unload(&svm->vcpu);
3435                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3436                 nested_svm_init_mmu_context(&svm->vcpu);
3437         }
3438 
3439         /* Load the nested guest state */
3440         svm->vmcb->save.es = nested_vmcb->save.es;
3441         svm->vmcb->save.cs = nested_vmcb->save.cs;
3442         svm->vmcb->save.ss = nested_vmcb->save.ss;
3443         svm->vmcb->save.ds = nested_vmcb->save.ds;
3444         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3445         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3446         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3447         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3448         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3449         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3450         if (npt_enabled) {
3451                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3452                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3453         } else
3454                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3455 
3456         /* Guest paging mode is active - reset mmu */
3457         kvm_mmu_reset_context(&svm->vcpu);
3458 
3459         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3460         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3461         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3462         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3463 
3464         /* In case we don't even reach vcpu_run, the fields are not updated */
3465         svm->vmcb->save.rax = nested_vmcb->save.rax;
3466         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3467         svm->vmcb->save.rip = nested_vmcb->save.rip;
3468         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3469         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3470         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3471 
3472         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3473         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3474 
3475         /* cache intercepts */
3476         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3477         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3478         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3479         svm->nested.intercept            = nested_vmcb->control.intercept;
3480 
3481         svm_flush_tlb(&svm->vcpu, true);
3482         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3483         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3484                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3485         else
3486                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3487 
3488         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3489                 /* We only want the cr8 intercept bits of the guest */
3490                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3491                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3492         }
3493 
3494         /* We don't want to see VMMCALLs from a nested guest */
3495         clr_intercept(svm, INTERCEPT_VMMCALL);
3496 
3497         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3498         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3499 
3500         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3501         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3502         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3503         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3504         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3505 
3506         nested_svm_unmap(page);
3507 
3508         /* Enter Guest-Mode */
3509         enter_guest_mode(&svm->vcpu);
3510 
3511         /*
3512          * Merge guest and host intercepts - must be called  with vcpu in
3513          * guest-mode to take affect here
3514          */
3515         recalc_intercepts(svm);
3516 
3517         svm->nested.vmcb = vmcb_gpa;
3518 
3519         enable_gif(svm);
3520 
3521         mark_all_dirty(svm->vmcb);
3522 }
3523 
3524 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3525 {
3526         struct vmcb *nested_vmcb;
3527         struct vmcb *hsave = svm->nested.hsave;
3528         struct vmcb *vmcb = svm->vmcb;
3529         struct page *page;
3530         u64 vmcb_gpa;
3531 
3532         vmcb_gpa = svm->vmcb->save.rax;
3533 
3534         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3535         if (!nested_vmcb)
3536                 return false;
3537 
3538         if (!nested_vmcb_checks(nested_vmcb)) {
3539                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3540                 nested_vmcb->control.exit_code_hi = 0;
3541                 nested_vmcb->control.exit_info_1  = 0;
3542                 nested_vmcb->control.exit_info_2  = 0;
3543 
3544                 nested_svm_unmap(page);
3545 
3546                 return false;
3547         }
3548 
3549         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3550                                nested_vmcb->save.rip,
3551                                nested_vmcb->control.int_ctl,
3552                                nested_vmcb->control.event_inj,
3553                                nested_vmcb->control.nested_ctl);
3554 
3555         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3556                                     nested_vmcb->control.intercept_cr >> 16,
3557                                     nested_vmcb->control.intercept_exceptions,
3558                                     nested_vmcb->control.intercept);
3559 
3560         /* Clear internal status */
3561         kvm_clear_exception_queue(&svm->vcpu);
3562         kvm_clear_interrupt_queue(&svm->vcpu);
3563 
3564         /*
3565          * Save the old vmcb, so we don't need to pick what we save, but can
3566          * restore everything when a VMEXIT occurs
3567          */
3568         hsave->save.es     = vmcb->save.es;
3569         hsave->save.cs     = vmcb->save.cs;
3570         hsave->save.ss     = vmcb->save.ss;
3571         hsave->save.ds     = vmcb->save.ds;
3572         hsave->save.gdtr   = vmcb->save.gdtr;
3573         hsave->save.idtr   = vmcb->save.idtr;
3574         hsave->save.efer   = svm->vcpu.arch.efer;
3575         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3576         hsave->save.cr4    = svm->vcpu.arch.cr4;
3577         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3578         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3579         hsave->save.rsp    = vmcb->save.rsp;
3580         hsave->save.rax    = vmcb->save.rax;
3581         if (npt_enabled)
3582                 hsave->save.cr3    = vmcb->save.cr3;
3583         else
3584                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3585 
3586         copy_vmcb_control_area(hsave, vmcb);
3587 
3588         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3589 
3590         return true;
3591 }
3592 
3593 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3594 {
3595         to_vmcb->save.fs = from_vmcb->save.fs;
3596         to_vmcb->save.gs = from_vmcb->save.gs;
3597         to_vmcb->save.tr = from_vmcb->save.tr;
3598         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3599         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3600         to_vmcb->save.star = from_vmcb->save.star;
3601         to_vmcb->save.lstar = from_vmcb->save.lstar;
3602         to_vmcb->save.cstar = from_vmcb->save.cstar;
3603         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3604         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3605         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3606         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3607 }
3608 
3609 static int vmload_interception(struct vcpu_svm *svm)
3610 {
3611         struct vmcb *nested_vmcb;
3612         struct page *page;
3613         int ret;
3614 
3615         if (nested_svm_check_permissions(svm))
3616                 return 1;
3617 
3618         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3619         if (!nested_vmcb)
3620                 return 1;
3621 
3622         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3623         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3624 
3625         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3626         nested_svm_unmap(page);
3627 
3628         return ret;
3629 }
3630 
3631 static int vmsave_interception(struct vcpu_svm *svm)
3632 {
3633         struct vmcb *nested_vmcb;
3634         struct page *page;
3635         int ret;
3636 
3637         if (nested_svm_check_permissions(svm))
3638                 return 1;
3639 
3640         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3641         if (!nested_vmcb)
3642                 return 1;
3643 
3644         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3645         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3646 
3647         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3648         nested_svm_unmap(page);
3649 
3650         return ret;
3651 }
3652 
3653 static int vmrun_interception(struct vcpu_svm *svm)
3654 {
3655         if (nested_svm_check_permissions(svm))
3656                 return 1;
3657 
3658         /* Save rip after vmrun instruction */
3659         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3660 
3661         if (!nested_svm_vmrun(svm))
3662                 return 1;
3663 
3664         if (!nested_svm_vmrun_msrpm(svm))
3665                 goto failed;
3666 
3667         return 1;
3668 
3669 failed:
3670 
3671         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3672         svm->vmcb->control.exit_code_hi = 0;
3673         svm->vmcb->control.exit_info_1  = 0;
3674         svm->vmcb->control.exit_info_2  = 0;
3675 
3676         nested_svm_vmexit(svm);
3677 
3678         return 1;
3679 }
3680 
3681 static int stgi_interception(struct vcpu_svm *svm)
3682 {
3683         int ret;
3684 
3685         if (nested_svm_check_permissions(svm))
3686                 return 1;
3687 
3688         /*
3689          * If VGIF is enabled, the STGI intercept is only added to
3690          * detect the opening of the SMI/NMI window; remove it now.
3691          */
3692         if (vgif_enabled(svm))
3693                 clr_intercept(svm, INTERCEPT_STGI);
3694 
3695         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3696         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3697         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3698 
3699         enable_gif(svm);
3700 
3701         return ret;
3702 }
3703 
3704 static int clgi_interception(struct vcpu_svm *svm)
3705 {
3706         int ret;
3707 
3708         if (nested_svm_check_permissions(svm))
3709                 return 1;
3710 
3711         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3712         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3713 
3714         disable_gif(svm);
3715 
3716         /* After a CLGI no interrupts should come */
3717         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3718                 svm_clear_vintr(svm);
3719                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3720                 mark_dirty(svm->vmcb, VMCB_INTR);
3721         }
3722 
3723         return ret;
3724 }
3725 
3726 static int invlpga_interception(struct vcpu_svm *svm)
3727 {
3728         struct kvm_vcpu *vcpu = &svm->vcpu;
3729 
3730         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3731                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3732 
3733         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3734         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3735 
3736         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3737         return kvm_skip_emulated_instruction(&svm->vcpu);
3738 }
3739 
3740 static int skinit_interception(struct vcpu_svm *svm)
3741 {
3742         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3743 
3744         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3745         return 1;
3746 }
3747 
3748 static int wbinvd_interception(struct vcpu_svm *svm)
3749 {
3750         return kvm_emulate_wbinvd(&svm->vcpu);
3751 }
3752 
3753 static int xsetbv_interception(struct vcpu_svm *svm)
3754 {
3755         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3756         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3757 
3758         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3759                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3760                 return kvm_skip_emulated_instruction(&svm->vcpu);
3761         }
3762 
3763         return 1;
3764 }
3765 
3766 static int task_switch_interception(struct vcpu_svm *svm)
3767 {
3768         u16 tss_selector;
3769         int reason;
3770         int int_type = svm->vmcb->control.exit_int_info &
3771                 SVM_EXITINTINFO_TYPE_MASK;
3772         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3773         uint32_t type =
3774                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3775         uint32_t idt_v =
3776                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3777         bool has_error_code = false;
3778         u32 error_code = 0;
3779 
3780         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3781 
3782         if (svm->vmcb->control.exit_info_2 &
3783             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3784                 reason = TASK_SWITCH_IRET;
3785         else if (svm->vmcb->control.exit_info_2 &
3786                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3787                 reason = TASK_SWITCH_JMP;
3788         else if (idt_v)
3789                 reason = TASK_SWITCH_GATE;
3790         else
3791                 reason = TASK_SWITCH_CALL;
3792 
3793         if (reason == TASK_SWITCH_GATE) {
3794                 switch (type) {
3795                 case SVM_EXITINTINFO_TYPE_NMI:
3796                         svm->vcpu.arch.nmi_injected = false;
3797                         break;
3798                 case SVM_EXITINTINFO_TYPE_EXEPT:
3799                         if (svm->vmcb->control.exit_info_2 &
3800                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3801                                 has_error_code = true;
3802                                 error_code =
3803                                         (u32)svm->vmcb->control.exit_info_2;
3804                         }
3805                         kvm_clear_exception_queue(&svm->vcpu);
3806                         break;
3807                 case SVM_EXITINTINFO_TYPE_INTR:
3808                         kvm_clear_interrupt_queue(&svm->vcpu);
3809                         break;
3810                 default:
3811                         break;
3812                 }
3813         }
3814 
3815         if (reason != TASK_SWITCH_GATE ||
3816             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3817             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3818              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3819                 skip_emulated_instruction(&svm->vcpu);
3820 
3821         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3822                 int_vec = -1;
3823 
3824         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3825                                 has_error_code, error_code) == EMULATE_FAIL) {
3826                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3827                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3828                 svm->vcpu.run->internal.ndata = 0;
3829                 return 0;
3830         }
3831         return 1;
3832 }
3833 
3834 static int cpuid_interception(struct vcpu_svm *svm)
3835 {
3836         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3837         return kvm_emulate_cpuid(&svm->vcpu);
3838 }
3839 
3840 static int iret_interception(struct vcpu_svm *svm)
3841 {
3842         ++svm->vcpu.stat.nmi_window_exits;
3843         clr_intercept(svm, INTERCEPT_IRET);
3844         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3845         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3846         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3847         return 1;
3848 }
3849 
3850 static int invlpg_interception(struct vcpu_svm *svm)
3851 {
3852         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3853                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3854 
3855         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3856         return kvm_skip_emulated_instruction(&svm->vcpu);
3857 }
3858 
3859 static int emulate_on_interception(struct vcpu_svm *svm)
3860 {
3861         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3862 }
3863 
3864 static int rsm_interception(struct vcpu_svm *svm)
3865 {
3866         return x86_emulate_instruction(&svm->vcpu, 0, 0,
3867                                        rsm_ins_bytes, 2) == EMULATE_DONE;
3868 }
3869 
3870 static int rdpmc_interception(struct vcpu_svm *svm)
3871 {
3872         int err;
3873 
3874         if (!static_cpu_has(X86_FEATURE_NRIPS))
3875                 return emulate_on_interception(svm);
3876 
3877         err = kvm_rdpmc(&svm->vcpu);
3878         return kvm_complete_insn_gp(&svm->vcpu, err);
3879 }
3880 
3881 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3882                                             unsigned long val)
3883 {
3884         unsigned long cr0 = svm->vcpu.arch.cr0;
3885         bool ret = false;
3886         u64 intercept;
3887 
3888         intercept = svm->nested.intercept;
3889 
3890         if (!is_guest_mode(&svm->vcpu) ||
3891             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3892                 return false;
3893 
3894         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3895         val &= ~SVM_CR0_SELECTIVE_MASK;
3896 
3897         if (cr0 ^ val) {
3898                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3899                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3900         }
3901 
3902         return ret;
3903 }
3904 
3905 #define CR_VALID (1ULL << 63)
3906 
3907 static int cr_interception(struct vcpu_svm *svm)
3908 {
3909         int reg, cr;
3910         unsigned long val;
3911         int err;
3912 
3913         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3914                 return emulate_on_interception(svm);
3915 
3916         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3917                 return emulate_on_interception(svm);
3918 
3919         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3920         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3921                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3922         else
3923                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3924 
3925         err = 0;
3926         if (cr >= 16) { /* mov to cr */
3927                 cr -= 16;
3928                 val = kvm_register_read(&svm->vcpu, reg);
3929                 switch (cr) {
3930                 case 0:
3931                         if (!check_selective_cr0_intercepted(svm, val))
3932                                 err = kvm_set_cr0(&svm->vcpu, val);
3933                         else
3934                                 return 1;
3935 
3936                         break;
3937                 case 3:
3938                         err = kvm_set_cr3(&svm->vcpu, val);
3939                         break;
3940                 case 4:
3941                         err = kvm_set_cr4(&svm->vcpu, val);
3942                         break;
3943                 case 8:
3944                         err = kvm_set_cr8(&svm->vcpu, val);
3945                         break;
3946                 default:
3947                         WARN(1, "unhandled write to CR%d", cr);
3948                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3949                         return 1;
3950                 }
3951         } else { /* mov from cr */
3952                 switch (cr) {
3953                 case 0:
3954                         val = kvm_read_cr0(&svm->vcpu);
3955                         break;
3956                 case 2:
3957                         val = svm->vcpu.arch.cr2;
3958                         break;
3959                 case 3:
3960                         val = kvm_read_cr3(&svm->vcpu);
3961                         break;
3962                 case 4:
3963                         val = kvm_read_cr4(&svm->vcpu);
3964                         break;
3965                 case 8:
3966                         val = kvm_get_cr8(&svm->vcpu);
3967                         break;
3968                 default:
3969                         WARN(1, "unhandled read from CR%d", cr);
3970                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3971                         return 1;
3972                 }
3973                 kvm_register_write(&svm->vcpu, reg, val);
3974         }
3975         return kvm_complete_insn_gp(&svm->vcpu, err);
3976 }
3977 
3978 static int dr_interception(struct vcpu_svm *svm)
3979 {
3980         int reg, dr;
3981         unsigned long val;
3982 
3983         if (svm->vcpu.guest_debug == 0) {
3984                 /*
3985                  * No more DR vmexits; force a reload of the debug registers
3986                  * and reenter on this instruction.  The next vmexit will
3987                  * retrieve the full state of the debug registers.
3988                  */
3989                 clr_dr_intercepts(svm);
3990                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3991                 return 1;
3992         }
3993 
3994         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3995                 return emulate_on_interception(svm);
3996 
3997         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3998         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3999 
4000         if (dr >= 16) { /* mov to DRn */
4001                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4002                         return 1;
4003                 val = kvm_register_read(&svm->vcpu, reg);
4004                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4005         } else {
4006                 if (!kvm_require_dr(&svm->vcpu, dr))
4007                         return 1;
4008                 kvm_get_dr(&svm->vcpu, dr, &val);
4009                 kvm_register_write(&svm->vcpu, reg, val);
4010         }
4011 
4012         return kvm_skip_emulated_instruction(&svm->vcpu);
4013 }
4014 
4015 static int cr8_write_interception(struct vcpu_svm *svm)
4016 {
4017         struct kvm_run *kvm_run = svm->vcpu.run;
4018         int r;
4019 
4020         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4021         /* instruction emulation calls kvm_set_cr8() */
4022         r = cr_interception(svm);
4023         if (lapic_in_kernel(&svm->vcpu))
4024                 return r;
4025         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4026                 return r;
4027         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4028         return 0;
4029 }
4030 
4031 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4032 {
4033         msr->data = 0;
4034 
4035         switch (msr->index) {
4036         case MSR_F10H_DECFG:
4037                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4038                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4039                 break;
4040         default:
4041                 return 1;
4042         }
4043 
4044         return 0;
4045 }
4046 
4047 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4048 {
4049         struct vcpu_svm *svm = to_svm(vcpu);
4050 
4051         switch (msr_info->index) {
4052         case MSR_STAR:
4053                 msr_info->data = svm->vmcb->save.star;
4054                 break;
4055 #ifdef CONFIG_X86_64
4056         case MSR_LSTAR:
4057                 msr_info->data = svm->vmcb->save.lstar;
4058                 break;
4059         case MSR_CSTAR:
4060                 msr_info->data = svm->vmcb->save.cstar;
4061                 break;
4062         case MSR_KERNEL_GS_BASE:
4063                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4064                 break;
4065         case MSR_SYSCALL_MASK:
4066                 msr_info->data = svm->vmcb->save.sfmask;
4067                 break;
4068 #endif
4069         case MSR_IA32_SYSENTER_CS:
4070                 msr_info->data = svm->vmcb->save.sysenter_cs;
4071                 break;
4072         case MSR_IA32_SYSENTER_EIP:
4073                 msr_info->data = svm->sysenter_eip;
4074                 break;
4075         case MSR_IA32_SYSENTER_ESP:
4076                 msr_info->data = svm->sysenter_esp;
4077                 break;
4078         case MSR_TSC_AUX:
4079                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4080                         return 1;
4081                 msr_info->data = svm->tsc_aux;
4082                 break;
4083         /*
4084          * Nobody will change the following 5 values in the VMCB so we can
4085          * safely return them on rdmsr. They will always be 0 until LBRV is
4086          * implemented.
4087          */
4088         case MSR_IA32_DEBUGCTLMSR:
4089                 msr_info->data = svm->vmcb->save.dbgctl;
4090                 break;
4091         case MSR_IA32_LASTBRANCHFROMIP:
4092                 msr_info->data = svm->vmcb->save.br_from;
4093                 break;
4094         case MSR_IA32_LASTBRANCHTOIP:
4095                 msr_info->data = svm->vmcb->save.br_to;
4096                 break;
4097         case MSR_IA32_LASTINTFROMIP:
4098                 msr_info->data = svm->vmcb->save.last_excp_from;
4099                 break;
4100         case MSR_IA32_LASTINTTOIP:
4101                 msr_info->data = svm->vmcb->save.last_excp_to;
4102                 break;
4103         case MSR_VM_HSAVE_PA:
4104                 msr_info->data = svm->nested.hsave_msr;
4105                 break;
4106         case MSR_VM_CR:
4107                 msr_info->data = svm->nested.vm_cr_msr;
4108                 break;
4109         case MSR_IA32_SPEC_CTRL:
4110                 if (!msr_info->host_initiated &&
4111                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS))
4112                         return 1;
4113 
4114                 msr_info->data = svm->spec_ctrl;
4115                 break;
4116         case MSR_F15H_IC_CFG: {
4117 
4118                 int family, model;
4119 
4120                 family = guest_cpuid_family(vcpu);
4121                 model  = guest_cpuid_model(vcpu);
4122 
4123                 if (family < 0 || model < 0)
4124                         return kvm_get_msr_common(vcpu, msr_info);
4125 
4126                 msr_info->data = 0;
4127 
4128                 if (family == 0x15 &&
4129                     (model >= 0x2 && model < 0x20))
4130                         msr_info->data = 0x1E;
4131                 }
4132                 break;
4133         case MSR_F10H_DECFG:
4134                 msr_info->data = svm->msr_decfg;
4135                 break;
4136         default:
4137                 return kvm_get_msr_common(vcpu, msr_info);
4138         }
4139         return 0;
4140 }
4141 
4142 static int rdmsr_interception(struct vcpu_svm *svm)
4143 {
4144         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4145         struct msr_data msr_info;
4146 
4147         msr_info.index = ecx;
4148         msr_info.host_initiated = false;
4149         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4150                 trace_kvm_msr_read_ex(ecx);
4151                 kvm_inject_gp(&svm->vcpu, 0);
4152                 return 1;
4153         } else {
4154                 trace_kvm_msr_read(ecx, msr_info.data);
4155 
4156                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4157                                    msr_info.data & 0xffffffff);
4158                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4159                                    msr_info.data >> 32);
4160                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4161                 return kvm_skip_emulated_instruction(&svm->vcpu);
4162         }
4163 }
4164 
4165 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4166 {
4167         struct vcpu_svm *svm = to_svm(vcpu);
4168         int svm_dis, chg_mask;
4169 
4170         if (data & ~SVM_VM_CR_VALID_MASK)
4171                 return 1;
4172 
4173         chg_mask = SVM_VM_CR_VALID_MASK;
4174 
4175         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4176                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4177 
4178         svm->nested.vm_cr_msr &= ~chg_mask;
4179         svm->nested.vm_cr_msr |= (data & chg_mask);
4180 
4181         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4182 
4183         /* check for svm_disable while efer.svme is set */
4184         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4185                 return 1;
4186 
4187         return 0;
4188 }
4189 
4190 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4191 {
4192         struct vcpu_svm *svm = to_svm(vcpu);
4193 
4194         u32 ecx = msr->index;
4195         u64 data = msr->data;
4196         switch (ecx) {
4197         case MSR_IA32_CR_PAT:
4198                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4199                         return 1;
4200                 vcpu->arch.pat = data;
4201                 svm->vmcb->save.g_pat = data;
4202                 mark_dirty(svm->vmcb, VMCB_NPT);
4203                 break;
4204         case MSR_IA32_SPEC_CTRL:
4205                 if (!msr->host_initiated &&
4206                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS))
4207                         return 1;
4208 
4209                 /* The STIBP bit doesn't fault even if it's not advertised */
4210                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
4211                         return 1;
4212 
4213                 svm->spec_ctrl = data;
4214 
4215                 if (!data)
4216                         break;
4217 
4218                 /*
4219                  * For non-nested:
4220                  * When it's written (to non-zero) for the first time, pass
4221                  * it through.
4222                  *
4223                  * For nested:
4224                  * The handling of the MSR bitmap for L2 guests is done in
4225                  * nested_svm_vmrun_msrpm.
4226                  * We update the L1 MSR bit as well since it will end up
4227                  * touching the MSR anyway now.
4228                  */
4229                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4230                 break;
4231         case MSR_IA32_PRED_CMD:
4232                 if (!msr->host_initiated &&
4233                     !guest_cpuid_has(vcpu, X86_FEATURE_IBPB))
4234                         return 1;
4235 
4236                 if (data & ~PRED_CMD_IBPB)
4237                         return 1;
4238 
4239                 if (!data)
4240                         break;
4241 
4242                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4243                 if (is_guest_mode(vcpu))
4244                         break;
4245                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4246                 break;
4247         case MSR_STAR:
4248                 svm->vmcb->save.star = data;
4249                 break;
4250 #ifdef CONFIG_X86_64
4251         case MSR_LSTAR:
4252                 svm->vmcb->save.lstar = data;
4253                 break;
4254         case MSR_CSTAR:
4255                 svm->vmcb->save.cstar = data;
4256                 break;
4257         case MSR_KERNEL_GS_BASE:
4258                 svm->vmcb->save.kernel_gs_base = data;
4259                 break;
4260         case MSR_SYSCALL_MASK:
4261                 svm->vmcb->save.sfmask = data;
4262                 break;
4263 #endif
4264         case MSR_IA32_SYSENTER_CS:
4265                 svm->vmcb->save.sysenter_cs = data;
4266                 break;
4267         case MSR_IA32_SYSENTER_EIP:
4268                 svm->sysenter_eip = data;
4269                 svm->vmcb->save.sysenter_eip = data;
4270                 break;
4271         case MSR_IA32_SYSENTER_ESP:
4272                 svm->sysenter_esp = data;
4273                 svm->vmcb->save.sysenter_esp = data;
4274                 break;
4275         case MSR_TSC_AUX:
4276                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4277                         return 1;
4278 
4279                 /*
4280                  * This is rare, so we update the MSR here instead of using
4281                  * direct_access_msrs.  Doing that would require a rdmsr in
4282                  * svm_vcpu_put.
4283                  */
4284                 svm->tsc_aux = data;
4285                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4286                 break;
4287         case MSR_IA32_DEBUGCTLMSR:
4288                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4289                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4290                                     __func__, data);
4291                         break;
4292                 }
4293                 if (data & DEBUGCTL_RESERVED_BITS)
4294                         return 1;
4295 
4296                 svm->vmcb->save.dbgctl = data;
4297                 mark_dirty(svm->vmcb, VMCB_LBR);
4298                 if (data & (1ULL<<0))
4299                         svm_enable_lbrv(svm);
4300                 else
4301                         svm_disable_lbrv(svm);
4302                 break;
4303         case MSR_VM_HSAVE_PA:
4304                 svm->nested.hsave_msr = data;
4305                 break;
4306         case MSR_VM_CR:
4307                 return svm_set_vm_cr(vcpu, data);
4308         case MSR_VM_IGNNE:
4309                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4310                 break;
4311         case MSR_F10H_DECFG: {
4312                 struct kvm_msr_entry msr_entry;
4313 
4314                 msr_entry.index = msr->index;
4315                 if (svm_get_msr_feature(&msr_entry))
4316                         return 1;
4317 
4318                 /* Check the supported bits */
4319                 if (data & ~msr_entry.data)
4320                         return 1;
4321 
4322                 /* Don't allow the guest to change a bit, #GP */
4323                 if (!msr->host_initiated && (data ^ msr_entry.data))
4324                         return 1;
4325 
4326                 svm->msr_decfg = data;
4327                 break;
4328         }
4329         case MSR_IA32_APICBASE:
4330                 if (kvm_vcpu_apicv_active(vcpu))
4331                         avic_update_vapic_bar(to_svm(vcpu), data);
4332                 /* Follow through */
4333         default:
4334                 return kvm_set_msr_common(vcpu, msr);
4335         }
4336         return 0;
4337 }
4338 
4339 static int wrmsr_interception(struct vcpu_svm *svm)
4340 {
4341         struct msr_data msr;
4342         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4343         u64 data = kvm_read_edx_eax(&svm->vcpu);
4344 
4345         msr.data = data;
4346         msr.index = ecx;
4347         msr.host_initiated = false;
4348 
4349         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4350         if (kvm_set_msr(&svm->vcpu, &msr)) {
4351                 trace_kvm_msr_write_ex(ecx, data);
4352                 kvm_inject_gp(&svm->vcpu, 0);
4353                 return 1;
4354         } else {
4355                 trace_kvm_msr_write(ecx, data);
4356                 return kvm_skip_emulated_instruction(&svm->vcpu);
4357         }
4358 }
4359 
4360 static int msr_interception(struct vcpu_svm *svm)
4361 {
4362         if (svm->vmcb->control.exit_info_1)
4363                 return wrmsr_interception(svm);
4364         else
4365                 return rdmsr_interception(svm);
4366 }
4367 
4368 static int interrupt_window_interception(struct vcpu_svm *svm)
4369 {
4370         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4371         svm_clear_vintr(svm);
4372         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4373         mark_dirty(svm->vmcb, VMCB_INTR);
4374         ++svm->vcpu.stat.irq_window_exits;
4375         return 1;
4376 }
4377 
4378 static int pause_interception(struct vcpu_svm *svm)
4379 {
4380         struct kvm_vcpu *vcpu = &svm->vcpu;
4381         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4382 
4383         if (pause_filter_thresh)
4384                 grow_ple_window(vcpu);
4385 
4386         kvm_vcpu_on_spin(vcpu, in_kernel);
4387         return 1;
4388 }
4389 
4390 static int nop_interception(struct vcpu_svm *svm)
4391 {
4392         return kvm_skip_emulated_instruction(&(svm->vcpu));
4393 }
4394 
4395 static int monitor_interception(struct vcpu_svm *svm)
4396 {
4397         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4398         return nop_interception(svm);
4399 }
4400 
4401 static int mwait_interception(struct vcpu_svm *svm)
4402 {
4403         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4404         return nop_interception(svm);
4405 }
4406 
4407 enum avic_ipi_failure_cause {
4408         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4409         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4410         AVIC_IPI_FAILURE_INVALID_TARGET,
4411         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4412 };
4413 
4414 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4415 {
4416         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4417         u32 icrl = svm->vmcb->control.exit_info_1;
4418         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4419         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4420         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4421 
4422         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4423 
4424         switch (id) {
4425         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4426                 /*
4427                  * AVIC hardware handles the generation of
4428                  * IPIs when the specified Message Type is Fixed
4429                  * (also known as fixed delivery mode) and
4430                  * the Trigger Mode is edge-triggered. The hardware
4431                  * also supports self and broadcast delivery modes
4432                  * specified via the Destination Shorthand(DSH)
4433                  * field of the ICRL. Logical and physical APIC ID
4434                  * formats are supported. All other IPI types cause
4435                  * a #VMEXIT, which needs to emulated.
4436                  */
4437                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4438                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4439                 break;
4440         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4441                 int i;
4442                 struct kvm_vcpu *vcpu;
4443                 struct kvm *kvm = svm->vcpu.kvm;
4444                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4445 
4446                 /*
4447                  * At this point, we expect that the AVIC HW has already
4448                  * set the appropriate IRR bits on the valid target
4449                  * vcpus. So, we just need to kick the appropriate vcpu.
4450                  */
4451                 kvm_for_each_vcpu(i, vcpu, kvm) {
4452                         bool m = kvm_apic_match_dest(vcpu, apic,
4453                                                      icrl & KVM_APIC_SHORT_MASK,
4454                                                      GET_APIC_DEST_FIELD(icrh),
4455                                                      icrl & KVM_APIC_DEST_MASK);
4456 
4457                         if (m && !avic_vcpu_is_running(vcpu))
4458                                 kvm_vcpu_wake_up(vcpu);
4459                 }
4460                 break;
4461         }
4462         case AVIC_IPI_FAILURE_INVALID_TARGET:
4463                 break;
4464         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4465                 WARN_ONCE(1, "Invalid backing page\n");
4466                 break;
4467         default:
4468                 pr_err("Unknown IPI interception\n");
4469         }
4470 
4471         return 1;
4472 }
4473 
4474 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4475 {
4476         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4477         int index;
4478         u32 *logical_apic_id_table;
4479         int dlid = GET_APIC_LOGICAL_ID(ldr);
4480 
4481         if (!dlid)
4482                 return NULL;
4483 
4484         if (flat) { /* flat */
4485                 index = ffs(dlid) - 1;
4486                 if (index > 7)
4487                         return NULL;
4488         } else { /* cluster */
4489                 int cluster = (dlid & 0xf0) >> 4;
4490                 int apic = ffs(dlid & 0x0f) - 1;
4491 
4492                 if ((apic < 0) || (apic > 7) ||
4493                     (cluster >= 0xf))
4494                         return NULL;
4495                 index = (cluster << 2) + apic;
4496         }
4497 
4498         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4499 
4500         return &logical_apic_id_table[index];
4501 }
4502 
4503 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4504                           bool valid)
4505 {
4506         bool flat;
4507         u32 *entry, new_entry;
4508 
4509         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4510         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4511         if (!entry)
4512                 return -EINVAL;
4513 
4514         new_entry = READ_ONCE(*entry);
4515         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4516         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4517         if (valid)
4518                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4519         else
4520                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4521         WRITE_ONCE(*entry, new_entry);
4522 
4523         return 0;
4524 }
4525 
4526 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4527 {
4528         int ret;
4529         struct vcpu_svm *svm = to_svm(vcpu);
4530         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4531 
4532         if (!ldr)
4533                 return 1;
4534 
4535         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4536         if (ret && svm->ldr_reg) {
4537                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4538                 svm->ldr_reg = 0;
4539         } else {
4540                 svm->ldr_reg = ldr;
4541         }
4542         return ret;
4543 }
4544 
4545 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4546 {
4547         u64 *old, *new;
4548         struct vcpu_svm *svm = to_svm(vcpu);
4549         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4550         u32 id = (apic_id_reg >> 24) & 0xff;
4551 
4552         if (vcpu->vcpu_id == id)
4553                 return 0;
4554 
4555         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4556         new = avic_get_physical_id_entry(vcpu, id);
4557         if (!new || !old)
4558                 return 1;
4559 
4560         /* We need to move physical_id_entry to new offset */
4561         *new = *old;
4562         *old = 0ULL;
4563         to_svm(vcpu)->avic_physical_id_cache = new;
4564 
4565         /*
4566          * Also update the guest physical APIC ID in the logical
4567          * APIC ID table entry if already setup the LDR.
4568          */
4569         if (svm->ldr_reg)
4570                 avic_handle_ldr_update(vcpu);
4571 
4572         return 0;
4573 }
4574 
4575 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4576 {
4577         struct vcpu_svm *svm = to_svm(vcpu);
4578         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4579         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4580         u32 mod = (dfr >> 28) & 0xf;
4581 
4582         /*
4583          * We assume that all local APICs are using the same type.
4584          * If this changes, we need to flush the AVIC logical
4585          * APID id table.
4586          */
4587         if (kvm_svm->ldr_mode == mod)
4588                 return 0;
4589 
4590         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4591         kvm_svm->ldr_mode = mod;
4592 
4593         if (svm->ldr_reg)
4594                 avic_handle_ldr_update(vcpu);
4595         return 0;
4596 }
4597 
4598 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4599 {
4600         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4601         u32 offset = svm->vmcb->control.exit_info_1 &
4602                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4603 
4604         switch (offset) {
4605         case APIC_ID:
4606                 if (avic_handle_apic_id_update(&svm->vcpu))
4607                         return 0;
4608                 break;
4609         case APIC_LDR:
4610                 if (avic_handle_ldr_update(&svm->vcpu))
4611                         return 0;
4612                 break;
4613         case APIC_DFR:
4614                 avic_handle_dfr_update(&svm->vcpu);
4615                 break;
4616         default:
4617                 break;
4618         }
4619 
4620         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4621 
4622         return 1;
4623 }
4624 
4625 static bool is_avic_unaccelerated_access_trap(u32 offset)
4626 {
4627         bool ret = false;
4628 
4629         switch (offset) {
4630         case APIC_ID:
4631         case APIC_EOI:
4632         case APIC_RRR:
4633         case APIC_LDR:
4634         case APIC_DFR:
4635         case APIC_SPIV:
4636         case APIC_ESR:
4637         case APIC_ICR:
4638         case APIC_LVTT:
4639         case APIC_LVTTHMR:
4640         case APIC_LVTPC:
4641         case APIC_LVT0:
4642         case APIC_LVT1:
4643         case APIC_LVTERR:
4644         case APIC_TMICT:
4645         case APIC_TDCR:
4646                 ret = true;
4647                 break;
4648         default:
4649                 break;
4650         }
4651         return ret;
4652 }
4653 
4654 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4655 {
4656         int ret = 0;
4657         u32 offset = svm->vmcb->control.exit_info_1 &
4658                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4659         u32 vector = svm->vmcb->control.exit_info_2 &
4660                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4661         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4662                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4663         bool trap = is_avic_unaccelerated_access_trap(offset);
4664 
4665         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4666                                             trap, write, vector);
4667         if (trap) {
4668                 /* Handling Trap */
4669                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4670                 ret = avic_unaccel_trap_write(svm);
4671         } else {
4672                 /* Handling Fault */
4673                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4674         }
4675 
4676         return ret;
4677 }
4678 
4679 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4680         [SVM_EXIT_READ_CR0]                     = cr_interception,
4681         [SVM_EXIT_READ_CR3]                     = cr_interception,
4682         [SVM_EXIT_READ_CR4]                     = cr_interception,
4683         [SVM_EXIT_READ_CR8]                     = cr_interception,
4684         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4685         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4686         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4687         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4688         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4689         [SVM_EXIT_READ_DR0]                     = dr_interception,
4690         [SVM_EXIT_READ_DR1]                     = dr_interception,
4691         [SVM_EXIT_READ_DR2]                     = dr_interception,
4692         [SVM_EXIT_READ_DR3]                     = dr_interception,
4693         [SVM_EXIT_READ_DR4]                     = dr_interception,
4694         [SVM_EXIT_READ_DR5]                     = dr_interception,
4695         [SVM_EXIT_READ_DR6]                     = dr_interception,
4696         [SVM_EXIT_READ_DR7]                     = dr_interception,
4697         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4698         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4699         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4700         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4701         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4702         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4703         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4704         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4705         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4706         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4707         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4708         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4709         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4710         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4711         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4712         [SVM_EXIT_INTR]                         = intr_interception,
4713         [SVM_EXIT_NMI]                          = nmi_interception,
4714         [SVM_EXIT_SMI]                          = nop_on_interception,
4715         [SVM_EXIT_INIT]                         = nop_on_interception,
4716         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4717         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4718         [SVM_EXIT_CPUID]                        = cpuid_interception,
4719         [SVM_EXIT_IRET]                         = iret_interception,
4720         [SVM_EXIT_INVD]                         = emulate_on_interception,
4721         [SVM_EXIT_PAUSE]                        = pause_interception,
4722         [SVM_EXIT_HLT]                          = halt_interception,
4723         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4724         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4725         [SVM_EXIT_IOIO]                         = io_interception,
4726         [SVM_EXIT_MSR]                          = msr_interception,
4727         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4728         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4729         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4730         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4731         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4732         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4733         [SVM_EXIT_STGI]                         = stgi_interception,
4734         [SVM_EXIT_CLGI]                         = clgi_interception,
4735         [SVM_EXIT_SKINIT]                       = skinit_interception,
4736         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4737         [SVM_EXIT_MONITOR]                      = monitor_interception,
4738         [SVM_EXIT_MWAIT]                        = mwait_interception,
4739         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4740         [SVM_EXIT_NPF]                          = npf_interception,
4741         [SVM_EXIT_RSM]                          = rsm_interception,
4742         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4743         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4744 };
4745 
4746 static void dump_vmcb(struct kvm_vcpu *vcpu)
4747 {
4748         struct vcpu_svm *svm = to_svm(vcpu);
4749         struct vmcb_control_area *control = &svm->vmcb->control;
4750         struct vmcb_save_area *save = &svm->vmcb->save;
4751 
4752         pr_err("VMCB Control Area:\n");
4753         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4754         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4755         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4756         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4757         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4758         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4759         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4760         pr_err("%-20s%d\n", "pause filter threshold:",
4761                control->pause_filter_thresh);
4762         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4763         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4764         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4765         pr_err("%-20s%d\n", "asid:", control->asid);
4766         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4767         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4768         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4769         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4770         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4771         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4772         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4773         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4774         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4775         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4776         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4777         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4778         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4779         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4780         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4781         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4782         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4783         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4784         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4785         pr_err("VMCB State Save Area:\n");
4786         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4787                "es:",
4788                save->es.selector, save->es.attrib,
4789                save->es.limit, save->es.base);
4790         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4791                "cs:",
4792                save->cs.selector, save->cs.attrib,
4793                save->cs.limit, save->cs.base);
4794         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4795                "ss:",
4796                save->ss.selector, save->ss.attrib,
4797                save->ss.limit, save->ss.base);
4798         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4799                "ds:",
4800                save->ds.selector, save->ds.attrib,
4801                save->ds.limit, save->ds.base);
4802         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4803                "fs:",
4804                save->fs.selector, save->fs.attrib,
4805                save->fs.limit, save->fs.base);
4806         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4807                "gs:",
4808                save->gs.selector, save->gs.attrib,
4809                save->gs.limit, save->gs.base);
4810         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4811                "gdtr:",
4812                save->gdtr.selector, save->gdtr.attrib,
4813                save->gdtr.limit, save->gdtr.base);
4814         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4815                "ldtr:",
4816                save->ldtr.selector, save->ldtr.attrib,
4817                save->ldtr.limit, save->ldtr.base);
4818         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4819                "idtr:",
4820                save->idtr.selector, save->idtr.attrib,
4821                save->idtr.limit, save->idtr.base);
4822         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4823                "tr:",
4824                save->tr.selector, save->tr.attrib,
4825                save->tr.limit, save->tr.base);
4826         pr_err("cpl:            %d                efer:         %016llx\n",
4827                 save->cpl, save->efer);
4828         pr_err("%-15s %016llx %-13s %016llx\n",
4829                "cr0:", save->cr0, "cr2:", save->cr2);
4830         pr_err("%-15s %016llx %-13s %016llx\n",
4831                "cr3:", save->cr3, "cr4:", save->cr4);
4832         pr_err("%-15s %016llx %-13s %016llx\n",
4833                "dr6:", save->dr6, "dr7:", save->dr7);
4834         pr_err("%-15s %016llx %-13s %016llx\n",
4835                "rip:", save->rip, "rflags:", save->rflags);
4836         pr_err("%-15s %016llx %-13s %016llx\n",
4837                "rsp:", save->rsp, "rax:", save->rax);
4838         pr_err("%-15s %016llx %-13s %016llx\n",
4839                "star:", save->star, "lstar:", save->lstar);
4840         pr_err("%-15s %016llx %-13s %016llx\n",
4841                "cstar:", save->cstar, "sfmask:", save->sfmask);
4842         pr_err("%-15s %016llx %-13s %016llx\n",
4843                "kernel_gs_base:", save->kernel_gs_base,
4844                "sysenter_cs:", save->sysenter_cs);
4845         pr_err("%-15s %016llx %-13s %016llx\n",
4846                "sysenter_esp:", save->sysenter_esp,
4847                "sysenter_eip:", save->sysenter_eip);
4848         pr_err("%-15s %016llx %-13s %016llx\n",
4849                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4850         pr_err("%-15s %016llx %-13s %016llx\n",
4851                "br_from:", save->br_from, "br_to:", save->br_to);
4852         pr_err("%-15s %016llx %-13s %016llx\n",
4853                "excp_from:", save->last_excp_from,
4854                "excp_to:", save->last_excp_to);
4855 }
4856 
4857 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4858 {
4859         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4860 
4861         *info1 = control->exit_info_1;
4862         *info2 = control->exit_info_2;
4863 }
4864 
4865 static int handle_exit(struct kvm_vcpu *vcpu)
4866 {
4867         struct vcpu_svm *svm = to_svm(vcpu);
4868         struct kvm_run *kvm_run = vcpu->run;
4869         u32 exit_code = svm->vmcb->control.exit_code;
4870 
4871         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4872 
4873         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4874                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4875         if (npt_enabled)
4876                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4877 
4878         if (unlikely(svm->nested.exit_required)) {
4879                 nested_svm_vmexit(svm);
4880                 svm->nested.exit_required = false;
4881 
4882                 return 1;
4883         }
4884 
4885         if (is_guest_mode(vcpu)) {
4886                 int vmexit;
4887 
4888                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4889                                         svm->vmcb->control.exit_info_1,
4890                                         svm->vmcb->control.exit_info_2,
4891                                         svm->vmcb->control.exit_int_info,
4892                                         svm->vmcb->control.exit_int_info_err,
4893                                         KVM_ISA_SVM);
4894 
4895                 vmexit = nested_svm_exit_special(svm);
4896 
4897                 if (vmexit == NESTED_EXIT_CONTINUE)
4898                         vmexit = nested_svm_exit_handled(svm);
4899 
4900                 if (vmexit == NESTED_EXIT_DONE)
4901                         return 1;
4902         }
4903 
4904         svm_complete_interrupts(svm);
4905 
4906         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4907                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4908                 kvm_run->fail_entry.hardware_entry_failure_reason
4909                         = svm->vmcb->control.exit_code;
4910                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4911                 dump_vmcb(vcpu);
4912                 return 0;
4913         }
4914 
4915         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4916             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4917             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4918             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4919                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4920                        "exit_code 0x%x\n",
4921                        __func__, svm->vmcb->control.exit_int_info,
4922                        exit_code);
4923 
4924         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4925             || !svm_exit_handlers[exit_code]) {
4926                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4927                 kvm_queue_exception(vcpu, UD_VECTOR);
4928                 return 1;
4929         }
4930 
4931         return svm_exit_handlers[exit_code](svm);
4932 }
4933 
4934 static void reload_tss(struct kvm_vcpu *vcpu)
4935 {
4936         int cpu = raw_smp_processor_id();
4937 
4938         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4939         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4940         load_TR_desc();
4941 }
4942 
4943 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4944 {
4945         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4946         int asid = sev_get_asid(svm->vcpu.kvm);
4947 
4948         /* Assign the asid allocated with this SEV guest */
4949         svm->vmcb->control.asid = asid;
4950 
4951         /*
4952          * Flush guest TLB:
4953          *
4954          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4955          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4956          */
4957         if (sd->sev_vmcbs[asid] == svm->vmcb &&
4958             svm->last_cpu == cpu)
4959                 return;
4960 
4961         svm->last_cpu = cpu;
4962         sd->sev_vmcbs[asid] = svm->vmcb;
4963         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4964         mark_dirty(svm->vmcb, VMCB_ASID);
4965 }
4966 
4967 static void pre_svm_run(struct vcpu_svm *svm)
4968 {
4969         int cpu = raw_smp_processor_id();
4970 
4971         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4972 
4973         if (sev_guest(svm->vcpu.kvm))
4974                 return pre_sev_run(svm, cpu);
4975 
4976         /* FIXME: handle wraparound of asid_generation */
4977         if (svm->asid_generation != sd->asid_generation)
4978                 new_asid(svm, sd);
4979 }
4980 
4981 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4982 {
4983         struct vcpu_svm *svm = to_svm(vcpu);
4984 
4985         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4986         vcpu->arch.hflags |= HF_NMI_MASK;
4987         set_intercept(svm, INTERCEPT_IRET);
4988         ++vcpu->stat.nmi_injections;
4989 }
4990 
4991 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4992 {
4993         struct vmcb_control_area *control;
4994 
4995         /* The following fields are ignored when AVIC is enabled */
4996         control = &svm->vmcb->control;
4997         control->int_vector = irq;
4998         control->int_ctl &= ~V_INTR_PRIO_MASK;
4999         control->int_ctl |= V_IRQ_MASK |
5000                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5001         mark_dirty(svm->vmcb, VMCB_INTR);
5002 }
5003 
5004 static void svm_set_irq(struct kvm_vcpu *vcpu)
5005 {
5006         struct vcpu_svm *svm = to_svm(vcpu);
5007 
5008         BUG_ON(!(gif_set(svm)));
5009 
5010         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5011         ++vcpu->stat.irq_injections;
5012 
5013         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5014                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5015 }
5016 
5017 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5018 {
5019         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5020 }
5021 
5022 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5023 {
5024         struct vcpu_svm *svm = to_svm(vcpu);
5025 
5026         if (svm_nested_virtualize_tpr(vcpu) ||
5027             kvm_vcpu_apicv_active(vcpu))
5028                 return;
5029 
5030         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5031 
5032         if (irr == -1)
5033                 return;
5034 
5035         if (tpr >= irr)
5036                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5037 }
5038 
5039 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
5040 {
5041         return;
5042 }
5043 
5044 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5045 {
5046         return avic && irqchip_split(vcpu->kvm);
5047 }
5048 
5049 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5050 {
5051 }
5052 
5053 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5054 {
5055 }
5056 
5057 /* Note: Currently only used by Hyper-V. */
5058 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5059 {
5060         struct vcpu_svm *svm = to_svm(vcpu);
5061         struct vmcb *vmcb = svm->vmcb;
5062 
5063         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5064                 return;
5065 
5066         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5067         mark_dirty(vmcb, VMCB_INTR);
5068 }
5069 
5070 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5071 {
5072         return;
5073 }
5074 
5075 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5076 {
5077         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5078         smp_mb__after_atomic();
5079 
5080         if (avic_vcpu_is_running(vcpu))
5081                 wrmsrl(SVM_AVIC_DOORBELL,
5082                        kvm_cpu_get_apicid(vcpu->cpu));
5083         else
5084                 kvm_vcpu_wake_up(vcpu);
5085 }
5086 
5087 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5088 {
5089         unsigned long flags;
5090         struct amd_svm_iommu_ir *cur;
5091 
5092         spin_lock_irqsave(&svm->ir_list_lock, flags);
5093         list_for_each_entry(cur, &svm->ir_list, node) {
5094                 if (cur->data != pi->ir_data)
5095                         continue;
5096                 list_del(&cur->node);
5097                 kfree(cur);
5098                 break;
5099         }
5100         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5101 }
5102 
5103 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5104 {
5105         int ret = 0;
5106         unsigned long flags;
5107         struct amd_svm_iommu_ir *ir;
5108 
5109         /**
5110          * In some cases, the existing irte is updaed and re-set,
5111          * so we need to check here if it's already been * added
5112          * to the ir_list.
5113          */
5114         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5115                 struct kvm *kvm = svm->vcpu.kvm;
5116                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5117                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5118                 struct vcpu_svm *prev_svm;
5119 
5120                 if (!prev_vcpu) {
5121                         ret = -EINVAL;
5122                         goto out;
5123                 }
5124 
5125                 prev_svm = to_svm(prev_vcpu);
5126                 svm_ir_list_del(prev_svm, pi);
5127         }
5128 
5129         /**
5130          * Allocating new amd_iommu_pi_data, which will get
5131          * add to the per-vcpu ir_list.
5132          */
5133         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5134         if (!ir) {
5135                 ret = -ENOMEM;
5136                 goto out;
5137         }
5138         ir->data = pi->ir_data;
5139 
5140         spin_lock_irqsave(&svm->ir_list_lock, flags);
5141         list_add(&ir->node, &svm->ir_list);
5142         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5143 out:
5144         return ret;
5145 }
5146 
5147 /**
5148  * Note:
5149  * The HW cannot support posting multicast/broadcast
5150  * interrupts to a vCPU. So, we still use legacy interrupt
5151  * remapping for these kind of interrupts.
5152  *
5153  * For lowest-priority interrupts, we only support
5154  * those with single CPU as the destination, e.g. user
5155  * configures the interrupts via /proc/irq or uses
5156  * irqbalance to make the interrupts single-CPU.
5157  */
5158 static int
5159 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5160                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5161 {
5162         struct kvm_lapic_irq irq;
5163         struct kvm_vcpu *vcpu = NULL;
5164 
5165         kvm_set_msi_irq(kvm, e, &irq);
5166 
5167         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5168                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5169                          __func__, irq.vector);
5170                 return -1;
5171         }
5172 
5173         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5174                  irq.vector);
5175         *svm = to_svm(vcpu);
5176         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5177         vcpu_info->vector = irq.vector;
5178 
5179         return 0;
5180 }
5181 
5182 /*
5183  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5184  *
5185  * @kvm: kvm
5186  * @host_irq: host irq of the interrupt
5187  * @guest_irq: gsi of the interrupt
5188  * @set: set or unset PI
5189  * returns 0 on success, < 0 on failure
5190  */
5191 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5192                               uint32_t guest_irq, bool set)
5193 {
5194         struct kvm_kernel_irq_routing_entry *e;
5195         struct kvm_irq_routing_table *irq_rt;
5196         int idx, ret = -EINVAL;
5197 
5198         if (!kvm_arch_has_assigned_device(kvm) ||
5199             !irq_remapping_cap(IRQ_POSTING_CAP))
5200                 return 0;
5201 
5202         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5203                  __func__, host_irq, guest_irq, set);
5204 
5205         idx = srcu_read_lock(&kvm->irq_srcu);
5206         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5207         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5208 
5209         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5210                 struct vcpu_data vcpu_info;
5211                 struct vcpu_svm *svm = NULL;
5212 
5213                 if (e->type != KVM_IRQ_ROUTING_MSI)
5214                         continue;
5215 
5216                 /**
5217                  * Here, we setup with legacy mode in the following cases:
5218                  * 1. When cannot target interrupt to a specific vcpu.
5219                  * 2. Unsetting posted interrupt.
5220                  * 3. APIC virtialization is disabled for the vcpu.
5221                  */
5222                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5223                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5224                         struct amd_iommu_pi_data pi;
5225 
5226                         /* Try to enable guest_mode in IRTE */
5227                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5228                                             AVIC_HPA_MASK);
5229                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5230                                                      svm->vcpu.vcpu_id);
5231                         pi.is_guest_mode = true;
5232                         pi.vcpu_data = &vcpu_info;
5233                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5234 
5235                         /**
5236                          * Here, we successfully setting up vcpu affinity in
5237                          * IOMMU guest mode. Now, we need to store the posted
5238                          * interrupt information in a per-vcpu ir_list so that
5239                          * we can reference to them directly when we update vcpu
5240                          * scheduling information in IOMMU irte.
5241                          */
5242                         if (!ret && pi.is_guest_mode)
5243                                 svm_ir_list_add(svm, &pi);
5244                 } else {
5245                         /* Use legacy mode in IRTE */
5246                         struct amd_iommu_pi_data pi;
5247 
5248                         /**
5249                          * Here, pi is used to:
5250                          * - Tell IOMMU to use legacy mode for this interrupt.
5251                          * - Retrieve ga_tag of prior interrupt remapping data.
5252                          */
5253                         pi.is_guest_mode = false;
5254                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5255 
5256                         /**
5257                          * Check if the posted interrupt was previously
5258                          * setup with the guest_mode by checking if the ga_tag
5259                          * was cached. If so, we need to clean up the per-vcpu
5260                          * ir_list.
5261                          */
5262                         if (!ret && pi.prev_ga_tag) {
5263                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5264                                 struct kvm_vcpu *vcpu;
5265 
5266                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5267                                 if (vcpu)
5268                                         svm_ir_list_del(to_svm(vcpu), &pi);
5269                         }
5270                 }
5271 
5272                 if (!ret && svm) {
5273                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5274                                                  e->gsi, vcpu_info.vector,
5275                                                  vcpu_info.pi_desc_addr, set);
5276                 }
5277 
5278                 if (ret < 0) {
5279                         pr_err("%s: failed to update PI IRTE\n", __func__);
5280                         goto out;
5281                 }
5282         }
5283 
5284         ret = 0;
5285 out:
5286         srcu_read_unlock(&kvm->irq_srcu, idx);
5287         return ret;
5288 }
5289 
5290 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5291 {
5292         struct vcpu_svm *svm = to_svm(vcpu);
5293         struct vmcb *vmcb = svm->vmcb;
5294         int ret;
5295         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5296               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5297         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5298 
5299         return ret;
5300 }
5301 
5302 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5303 {
5304         struct vcpu_svm *svm = to_svm(vcpu);
5305 
5306         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5307 }
5308 
5309 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5310 {
5311         struct vcpu_svm *svm = to_svm(vcpu);
5312 
5313         if (masked) {
5314                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5315                 set_intercept(svm, INTERCEPT_IRET);
5316         } else {
5317                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5318                 clr_intercept(svm, INTERCEPT_IRET);
5319         }
5320 }
5321 
5322 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5323 {
5324         struct vcpu_svm *svm = to_svm(vcpu);
5325         struct vmcb *vmcb = svm->vmcb;
5326         int ret;
5327 
5328         if (!gif_set(svm) ||
5329              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5330                 return 0;
5331 
5332         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5333 
5334         if (is_guest_mode(vcpu))
5335                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5336 
5337         return ret;
5338 }
5339 
5340 static void enable_irq_window(struct kvm_vcpu *vcpu)
5341 {
5342         struct vcpu_svm *svm = to_svm(vcpu);
5343 
5344         if (kvm_vcpu_apicv_active(vcpu))
5345                 return;
5346 
5347         /*
5348          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5349          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5350          * get that intercept, this function will be called again though and
5351          * we'll get the vintr intercept. However, if the vGIF feature is
5352          * enabled, the STGI interception will not occur. Enable the irq
5353          * window under the assumption that the hardware will set the GIF.
5354          */
5355         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5356                 svm_set_vintr(svm);
5357                 svm_inject_irq(svm, 0x0);
5358         }
5359 }
5360 
5361 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5362 {
5363         struct vcpu_svm *svm = to_svm(vcpu);
5364 
5365         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5366             == HF_NMI_MASK)
5367                 return; /* IRET will cause a vm exit */
5368 
5369         if (!gif_set(svm)) {
5370                 if (vgif_enabled(svm))
5371                         set_intercept(svm, INTERCEPT_STGI);
5372                 return; /* STGI will cause a vm exit */
5373         }
5374 
5375         if (svm->nested.exit_required)
5376                 return; /* we're not going to run the guest yet */
5377 
5378         /*
5379          * Something prevents NMI from been injected. Single step over possible
5380          * problem (IRET or exception injection or interrupt shadow)
5381          */
5382         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5383         svm->nmi_singlestep = true;
5384         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5385 }
5386 
5387 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5388 {
5389         return 0;
5390 }
5391 
5392 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5393 {
5394         return 0;
5395 }
5396 
5397 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5398 {
5399         struct vcpu_svm *svm = to_svm(vcpu);
5400 
5401         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5402                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5403         else
5404                 svm->asid_generation--;
5405 }
5406 
5407 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5408 {
5409 }
5410 
5411 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5412 {
5413         struct vcpu_svm *svm = to_svm(vcpu);
5414 
5415         if (svm_nested_virtualize_tpr(vcpu))
5416                 return;
5417 
5418         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5419                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5420                 kvm_set_cr8(vcpu, cr8);
5421         }
5422 }
5423 
5424 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5425 {
5426         struct vcpu_svm *svm = to_svm(vcpu);
5427         u64 cr8;
5428 
5429         if (svm_nested_virtualize_tpr(vcpu) ||
5430             kvm_vcpu_apicv_active(vcpu))
5431                 return;
5432 
5433         cr8 = kvm_get_cr8(vcpu);
5434         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5435         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5436 }
5437 
5438 static void svm_complete_interrupts(struct vcpu_svm *svm)
5439 {
5440         u8 vector;
5441         int type;
5442         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5443         unsigned int3_injected = svm->int3_injected;
5444 
5445         svm->int3_injected = 0;
5446 
5447         /*
5448          * If we've made progress since setting HF_IRET_MASK, we've
5449          * executed an IRET and can allow NMI injection.
5450          */
5451         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5452             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5453                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5454                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5455         }
5456 
5457         svm->vcpu.arch.nmi_injected = false;
5458         kvm_clear_exception_queue(&svm->vcpu);
5459         kvm_clear_interrupt_queue(&svm->vcpu);
5460 
5461         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5462                 return;
5463 
5464         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5465 
5466         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5467         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5468 
5469         switch (type) {
5470         case SVM_EXITINTINFO_TYPE_NMI:
5471                 svm->vcpu.arch.nmi_injected = true;
5472                 break;
5473         case SVM_EXITINTINFO_TYPE_EXEPT:
5474                 /*
5475                  * In case of software exceptions, do not reinject the vector,
5476                  * but re-execute the instruction instead. Rewind RIP first
5477                  * if we emulated INT3 before.
5478                  */
5479                 if (kvm_exception_is_soft(vector)) {
5480                         if (vector == BP_VECTOR && int3_injected &&
5481                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5482                                 kvm_rip_write(&svm->vcpu,
5483                                               kvm_rip_read(&svm->vcpu) -
5484                                               int3_injected);
5485                         break;
5486                 }
5487                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5488                         u32 err = svm->vmcb->control.exit_int_info_err;
5489                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5490 
5491                 } else
5492                         kvm_requeue_exception(&svm->vcpu, vector);
5493                 break;
5494         case SVM_EXITINTINFO_TYPE_INTR:
5495                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5496                 break;
5497         default:
5498                 break;
5499         }
5500 }
5501 
5502 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5503 {
5504         struct vcpu_svm *svm = to_svm(vcpu);
5505         struct vmcb_control_area *control = &svm->vmcb->control;
5506 
5507         control->exit_int_info = control->event_inj;
5508         control->exit_int_info_err = control->event_inj_err;
5509         control->event_inj = 0;
5510         svm_complete_interrupts(svm);
5511 }
5512 
5513 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5514 {
5515         struct vcpu_svm *svm = to_svm(vcpu);
5516 
5517         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5518         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5519         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5520 
5521         /*
5522          * A vmexit emulation is required before the vcpu can be executed
5523          * again.
5524          */
5525         if (unlikely(svm->nested.exit_required))
5526                 return;
5527 
5528         /*
5529          * Disable singlestep if we're injecting an interrupt/exception.
5530          * We don't want our modified rflags to be pushed on the stack where
5531          * we might not be able to easily reset them if we disabled NMI
5532          * singlestep later.
5533          */
5534         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5535                 /*
5536                  * Event injection happens before external interrupts cause a
5537                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5538                  * is enough to force an immediate vmexit.
5539                  */
5540                 disable_nmi_singlestep(svm);
5541                 smp_send_reschedule(vcpu->cpu);
5542         }
5543 
5544         pre_svm_run(svm);
5545 
5546         sync_lapic_to_cr8(vcpu);
5547 
5548         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5549 
5550         clgi();
5551 
5552         local_irq_enable();
5553 
5554         /*
5555          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5556          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5557          * is no need to worry about the conditional branch over the wrmsr
5558          * being speculatively taken.
5559          */
5560         if (svm->spec_ctrl)
5561                 native_wrmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
5562 
5563         asm volatile (
5564                 "push %%" _ASM_BP "; \n\t"
5565                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5566                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5567                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5568                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5569                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5570                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5571 #ifdef CONFIG_X86_64
5572                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5573                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5574                 "mov %c[r10](%[svm]), %%r10 \n\t"
5575                 "mov %c[r11](%[svm]), %%r11 \n\t"
5576                 "mov %c[r12](%[svm]), %%r12 \n\t"
5577                 "mov %c[r13](%[svm]), %%r13 \n\t"
5578                 "mov %c[r14](%[svm]), %%r14 \n\t"
5579                 "mov %c[r15](%[svm]), %%r15 \n\t"
5580 #endif
5581 
5582                 /* Enter guest mode */
5583                 "push %%" _ASM_AX " \n\t"
5584                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5585                 __ex(SVM_VMLOAD) "\n\t"
5586                 __ex(SVM_VMRUN) "\n\t"
5587                 __ex(SVM_VMSAVE) "\n\t"
5588                 "pop %%" _ASM_AX " \n\t"
5589 
5590                 /* Save guest registers, load host registers */
5591                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5592                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5593                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5594                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5595                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5596                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5597 #ifdef CONFIG_X86_64
5598                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5599                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5600                 "mov %%r10, %c[r10](%[svm]) \n\t"
5601                 "mov %%r11, %c[r11](%[svm]) \n\t"
5602                 "mov %%r12, %c[r12](%[svm]) \n\t"
5603                 "mov %%r13, %c[r13](%[svm]) \n\t"
5604                 "mov %%r14, %c[r14](%[svm]) \n\t"
5605                 "mov %%r15, %c[r15](%[svm]) \n\t"
5606 #endif
5607                 /*
5608                 * Clear host registers marked as clobbered to prevent
5609                 * speculative use.
5610                 */
5611                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5612                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5613                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5614                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5615                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5616 #ifdef CONFIG_X86_64
5617                 "xor %%r8, %%r8 \n\t"
5618                 "xor %%r9, %%r9 \n\t"
5619                 "xor %%r10, %%r10 \n\t"
5620                 "xor %%r11, %%r11 \n\t"
5621                 "xor %%r12, %%r12 \n\t"
5622                 "xor %%r13, %%r13 \n\t"
5623                 "xor %%r14, %%r14 \n\t"
5624                 "xor %%r15, %%r15 \n\t"
5625 #endif
5626                 "pop %%" _ASM_BP
5627                 :
5628                 : [svm]"a"(svm),
5629                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5630                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5631                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5632                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5633                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5634                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5635                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5636 #ifdef CONFIG_X86_64
5637                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5638                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5639                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5640                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5641                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5642                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5643                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5644                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5645 #endif
5646                 : "cc", "memory"
5647 #ifdef CONFIG_X86_64
5648                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5649                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5650 #else
5651                 , "ebx", "ecx", "edx", "esi", "edi"
5652 #endif
5653                 );
5654 
5655         /*
5656          * We do not use IBRS in the kernel. If this vCPU has used the
5657          * SPEC_CTRL MSR it may have left it on; save the value and
5658          * turn it off. This is much more efficient than blindly adding
5659          * it to the atomic save/restore list. Especially as the former
5660          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5661          *
5662          * For non-nested case:
5663          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5664          * save it.
5665          *
5666          * For nested case:
5667          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5668          * save it.
5669          */
5670         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5671                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5672 
5673         if (svm->spec_ctrl)
5674                 native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
5675 
5676         /* Eliminate branch target predictions from guest mode */
5677         vmexit_fill_RSB();
5678 
5679 #ifdef CONFIG_X86_64
5680         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5681 #else
5682         loadsegment(fs, svm->host.fs);
5683 #ifndef CONFIG_X86_32_LAZY_GS
5684         loadsegment(gs, svm->host.gs);
5685 #endif
5686 #endif
5687 
5688         reload_tss(vcpu);
5689 
5690         local_irq_disable();
5691 
5692         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5693         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5694         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5695         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5696 
5697         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5698                 kvm_before_interrupt(&svm->vcpu);
5699 
5700         stgi();
5701 
5702         /* Any pending NMI will happen here */
5703 
5704         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5705                 kvm_after_interrupt(&svm->vcpu);
5706 
5707         sync_cr8_to_lapic(vcpu);
5708 
5709         svm->next_rip = 0;
5710 
5711         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5712 
5713         /* if exit due to PF check for async PF */
5714         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5715                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5716 
5717         if (npt_enabled) {
5718                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5719                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5720         }
5721 
5722         /*
5723          * We need to handle MC intercepts here before the vcpu has a chance to
5724          * change the physical cpu
5725          */
5726         if (unlikely(svm->vmcb->control.exit_code ==
5727                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5728                 svm_handle_mce(svm);
5729 
5730         mark_all_clean(svm->vmcb);
5731 }
5732 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5733 
5734 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5735 {
5736         struct vcpu_svm *svm = to_svm(vcpu);
5737 
5738         svm->vmcb->save.cr3 = __sme_set(root);
5739         mark_dirty(svm->vmcb, VMCB_CR);
5740         svm_flush_tlb(vcpu, true);
5741 }
5742 
5743 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5744 {
5745         struct vcpu_svm *svm = to_svm(vcpu);
5746 
5747         svm->vmcb->control.nested_cr3 = __sme_set(root);
5748         mark_dirty(svm->vmcb, VMCB_NPT);
5749 
5750         /* Also sync guest cr3 here in case we live migrate */
5751         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5752         mark_dirty(svm->vmcb, VMCB_CR);
5753 
5754         svm_flush_tlb(vcpu, true);
5755 }
5756 
5757 static int is_disabled(void)
5758 {
5759         u64 vm_cr;
5760 
5761         rdmsrl(MSR_VM_CR, vm_cr);
5762         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5763                 return 1;
5764 
5765         return 0;
5766 }
5767 
5768 static void
5769 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5770 {
5771         /*
5772          * Patch in the VMMCALL instruction:
5773          */
5774         hypercall[0] = 0x0f;
5775         hypercall[1] = 0x01;
5776         hypercall[2] = 0xd9;
5777 }
5778 
5779 static void svm_check_processor_compat(void *rtn)
5780 {
5781         *(int *)rtn = 0;
5782 }
5783 
5784 static bool svm_cpu_has_accelerated_tpr(void)
5785 {
5786         return false;
5787 }
5788 
5789 static bool svm_has_high_real_mode_segbase(void)
5790 {
5791         return true;
5792 }
5793 
5794 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5795 {
5796         return 0;
5797 }
5798 
5799 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5800 {
5801         struct vcpu_svm *svm = to_svm(vcpu);
5802 
5803         /* Update nrips enabled cache */
5804         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5805 
5806         if (!kvm_vcpu_apicv_active(vcpu))
5807                 return;
5808 
5809         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5810 }
5811 
5812 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5813 {
5814         switch (func) {
5815         case 0x1:
5816                 if (avic)
5817                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5818                 break;
5819         case 0x80000001:
5820                 if (nested)
5821                         entry->ecx |= (1 << 2); /* Set SVM bit */
5822                 break;
5823         case 0x8000000A:
5824                 entry->eax = 1; /* SVM revision 1 */
5825                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5826                                    ASID emulation to nested SVM */
5827                 entry->ecx = 0; /* Reserved */
5828                 entry->edx = 0; /* Per default do not support any
5829                                    additional features */
5830 
5831                 /* Support next_rip if host supports it */
5832                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5833                         entry->edx |= SVM_FEATURE_NRIP;
5834 
5835                 /* Support NPT for the guest if enabled */
5836                 if (npt_enabled)
5837                         entry->edx |= SVM_FEATURE_NPT;
5838 
5839                 break;
5840         case 0x8000001F:
5841                 /* Support memory encryption cpuid if host supports it */
5842                 if (boot_cpu_has(X86_FEATURE_SEV))
5843                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5844                                 &entry->ecx, &entry->edx);
5845 
5846         }
5847 }
5848 
5849 static int svm_get_lpage_level(void)
5850 {
5851         return PT_PDPE_LEVEL;
5852 }
5853 
5854 static bool svm_rdtscp_supported(void)
5855 {
5856         return boot_cpu_has(X86_FEATURE_RDTSCP);
5857 }
5858 
5859 static bool svm_invpcid_supported(void)
5860 {
5861         return false;
5862 }
5863 
5864 static bool svm_mpx_supported(void)
5865 {
5866         return false;
5867 }
5868 
5869 static bool svm_xsaves_supported(void)
5870 {
5871         return false;
5872 }
5873 
5874 static bool svm_umip_emulated(void)
5875 {
5876         return false;
5877 }
5878 
5879 static bool svm_has_wbinvd_exit(void)
5880 {
5881         return true;
5882 }
5883 
5884 #define PRE_EX(exit)  { .exit_code = (exit), \
5885                         .stage = X86_ICPT_PRE_EXCEPT, }
5886 #define POST_EX(exit) { .exit_code = (exit), \
5887                         .stage = X86_ICPT_POST_EXCEPT, }
5888 #define POST_MEM(exit) { .exit_code = (exit), \
5889                         .stage = X86_ICPT_POST_MEMACCESS, }
5890 
5891 static const struct __x86_intercept {
5892         u32 exit_code;
5893         enum x86_intercept_stage stage;
5894 } x86_intercept_map[] = {
5895         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5896         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5897         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5898         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5899         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5900         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5901         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5902         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5903         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5904         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5905         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5906         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5907         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5908         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5909         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5910         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5911         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5912         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5913         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5914         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5915         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5916         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5917         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5918         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5919         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5920         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5921         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5922         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5923         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5924         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5925         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5926         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5927         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5928         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5929         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5930         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5931         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5932         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5933         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5934         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5935         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5936         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5937         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5938         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5939         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5940         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5941 };
5942 
5943 #undef PRE_EX
5944 #undef POST_EX
5945 #undef POST_MEM
5946 
5947 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5948                                struct x86_instruction_info *info,
5949                                enum x86_intercept_stage stage)
5950 {
5951         struct vcpu_svm *svm = to_svm(vcpu);
5952         int vmexit, ret = X86EMUL_CONTINUE;
5953         struct __x86_intercept icpt_info;
5954         struct vmcb *vmcb = svm->vmcb;
5955 
5956         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5957                 goto out;
5958 
5959         icpt_info = x86_intercept_map[info->intercept];
5960 
5961         if (stage != icpt_info.stage)
5962                 goto out;
5963 
5964         switch (icpt_info.exit_code) {
5965         case SVM_EXIT_READ_CR0:
5966                 if (info->intercept == x86_intercept_cr_read)
5967                         icpt_info.exit_code += info->modrm_reg;
5968                 break;
5969         case SVM_EXIT_WRITE_CR0: {
5970                 unsigned long cr0, val;
5971                 u64 intercept;
5972 
5973                 if (info->intercept == x86_intercept_cr_write)
5974                         icpt_info.exit_code += info->modrm_reg;
5975 
5976                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5977                     info->intercept == x86_intercept_clts)
5978                         break;
5979 
5980                 intercept = svm->nested.intercept;
5981 
5982                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5983                         break;
5984 
5985                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5986                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5987 
5988                 if (info->intercept == x86_intercept_lmsw) {
5989                         cr0 &= 0xfUL;
5990                         val &= 0xfUL;
5991                         /* lmsw can't clear PE - catch this here */
5992                         if (cr0 & X86_CR0_PE)
5993                                 val |= X86_CR0_PE;
5994                 }
5995 
5996                 if (cr0 ^ val)
5997                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5998 
5999                 break;
6000         }
6001         case SVM_EXIT_READ_DR0:
6002         case SVM_EXIT_WRITE_DR0:
6003                 icpt_info.exit_code += info->modrm_reg;
6004                 break;
6005         case SVM_EXIT_MSR:
6006                 if (info->intercept == x86_intercept_wrmsr)
6007                         vmcb->control.exit_info_1 = 1;
6008                 else
6009                         vmcb->control.exit_info_1 = 0;
6010                 break;
6011         case SVM_EXIT_PAUSE:
6012                 /*
6013                  * We get this for NOP only, but pause
6014                  * is rep not, check this here
6015                  */
6016                 if (info->rep_prefix != REPE_PREFIX)
6017                         goto out;
6018                 break;
6019         case SVM_EXIT_IOIO: {
6020                 u64 exit_info;
6021                 u32 bytes;
6022 
6023                 if (info->intercept == x86_intercept_in ||
6024                     info->intercept == x86_intercept_ins) {
6025                         exit_info = ((info->src_val & 0xffff) << 16) |
6026                                 SVM_IOIO_TYPE_MASK;
6027                         bytes = info->dst_bytes;
6028                 } else {
6029                         exit_info = (info->dst_val & 0xffff) << 16;
6030                         bytes = info->src_bytes;
6031                 }
6032 
6033                 if (info->intercept == x86_intercept_outs ||
6034                     info->intercept == x86_intercept_ins)
6035                         exit_info |= SVM_IOIO_STR_MASK;
6036 
6037                 if (info->rep_prefix)
6038                         exit_info |= SVM_IOIO_REP_MASK;
6039 
6040                 bytes = min(bytes, 4u);
6041 
6042                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6043 
6044                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6045 
6046                 vmcb->control.exit_info_1 = exit_info;
6047                 vmcb->control.exit_info_2 = info->next_rip;
6048 
6049                 break;
6050         }
6051         default:
6052                 break;
6053         }
6054 
6055         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6056         if (static_cpu_has(X86_FEATURE_NRIPS))
6057                 vmcb->control.next_rip  = info->next_rip;
6058         vmcb->control.exit_code = icpt_info.exit_code;
6059         vmexit = nested_svm_exit_handled(svm);
6060 
6061         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6062                                            : X86EMUL_CONTINUE;
6063 
6064 out:
6065         return ret;
6066 }
6067 
6068 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6069 {
6070         local_irq_enable();
6071         /*
6072          * We must have an instruction with interrupts enabled, so
6073          * the timer interrupt isn't delayed by the interrupt shadow.
6074          */
6075         asm("nop");
6076         local_irq_disable();
6077 }
6078 
6079 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6080 {
6081         if (pause_filter_thresh)
6082                 shrink_ple_window(vcpu);
6083 }
6084 
6085 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6086 {
6087         if (avic_handle_apic_id_update(vcpu) != 0)
6088                 return;
6089         if (avic_handle_dfr_update(vcpu) != 0)
6090                 return;
6091         avic_handle_ldr_update(vcpu);
6092 }
6093 
6094 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6095 {
6096         /* [63:9] are reserved. */
6097         vcpu->arch.mcg_cap &= 0x1ff;
6098 }
6099 
6100 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6101 {
6102         struct vcpu_svm *svm = to_svm(vcpu);
6103 
6104         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6105         if (!gif_set(svm))
6106                 return 0;
6107 
6108         if (is_guest_mode(&svm->vcpu) &&
6109             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6110                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6111                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6112                 svm->nested.exit_required = true;
6113                 return 0;
6114         }
6115 
6116         return 1;
6117 }
6118 
6119 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6120 {
6121         struct vcpu_svm *svm = to_svm(vcpu);
6122         int ret;
6123 
6124         if (is_guest_mode(vcpu)) {
6125                 /* FED8h - SVM Guest */
6126                 put_smstate(u64, smstate, 0x7ed8, 1);
6127                 /* FEE0h - SVM Guest VMCB Physical Address */
6128                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6129 
6130                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6131                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6132                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6133 
6134                 ret = nested_svm_vmexit(svm);
6135                 if (ret)
6136                         return ret;
6137         }
6138         return 0;
6139 }
6140 
6141 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6142 {
6143         struct vcpu_svm *svm = to_svm(vcpu);
6144         struct vmcb *nested_vmcb;
6145         struct page *page;
6146         struct {
6147                 u64 guest;
6148                 u64 vmcb;
6149         } svm_state_save;
6150         int ret;
6151 
6152         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6153                                   sizeof(svm_state_save));
6154         if (ret)
6155                 return ret;
6156 
6157         if (svm_state_save.guest) {
6158                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6159                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6160                 if (nested_vmcb)
6161                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6162                 else
6163                         ret = 1;
6164                 vcpu->arch.hflags |= HF_SMM_MASK;
6165         }
6166         return ret;
6167 }
6168 
6169 static int enable_smi_window(struct kvm_vcpu *vcpu)
6170 {
6171         struct vcpu_svm *svm = to_svm(vcpu);
6172 
6173         if (!gif_set(svm)) {
6174                 if (vgif_enabled(svm))
6175                         set_intercept(svm, INTERCEPT_STGI);
6176                 /* STGI will cause a vm exit */
6177                 return 1;
6178         }
6179         return 0;
6180 }
6181 
6182 static int sev_asid_new(void)
6183 {
6184         int pos;
6185 
6186         /*
6187          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6188          */
6189         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6190         if (pos >= max_sev_asid)
6191                 return -EBUSY;
6192 
6193         set_bit(pos, sev_asid_bitmap);
6194         return pos + 1;
6195 }
6196 
6197 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6198 {
6199         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6200         int asid, ret;
6201 
6202         ret = -EBUSY;
6203         asid = sev_asid_new();
6204         if (asid < 0)
6205                 return ret;
6206 
6207         ret = sev_platform_init(&argp->error);
6208         if (ret)
6209                 goto e_free;
6210 
6211         sev->active = true;
6212         sev->asid = asid;
6213         INIT_LIST_HEAD(&sev->regions_list);
6214 
6215         return 0;
6216 
6217 e_free:
6218         __sev_asid_free(asid);
6219         return ret;
6220 }
6221 
6222 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6223 {
6224         struct sev_data_activate *data;
6225         int asid = sev_get_asid(kvm);
6226         int ret;
6227 
6228         wbinvd_on_all_cpus();
6229 
6230         ret = sev_guest_df_flush(error);
6231         if (ret)
6232                 return ret;
6233 
6234         data = kzalloc(sizeof(*data), GFP_KERNEL);
6235         if (!data)
6236                 return -ENOMEM;
6237 
6238         /* activate ASID on the given handle */
6239         data->handle = handle;
6240         data->asid   = asid;
6241         ret = sev_guest_activate(data, error);
6242         kfree(data);
6243 
6244         return ret;
6245 }
6246 
6247 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6248 {
6249         struct fd f;
6250         int ret;
6251 
6252         f = fdget(fd);
6253         if (!f.file)
6254                 return -EBADF;
6255 
6256         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6257 
6258         fdput(f);
6259         return ret;
6260 }
6261 
6262 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6263 {
6264         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6265 
6266         return __sev_issue_cmd(sev->fd, id, data, error);
6267 }
6268 
6269 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6270 {
6271         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6272         struct sev_data_launch_start *start;
6273         struct kvm_sev_launch_start params;
6274         void *dh_blob, *session_blob;
6275         int *error = &argp->error;
6276         int ret;
6277 
6278         if (!sev_guest(kvm))
6279                 return -ENOTTY;
6280 
6281         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6282                 return -EFAULT;
6283 
6284         start = kzalloc(sizeof(*start), GFP_KERNEL);
6285         if (!start)
6286                 return -ENOMEM;
6287 
6288         dh_blob = NULL;
6289         if (params.dh_uaddr) {
6290                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6291                 if (IS_ERR(dh_blob)) {
6292                         ret = PTR_ERR(dh_blob);
6293                         goto e_free;
6294                 }
6295 
6296                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6297                 start->dh_cert_len = params.dh_len;
6298         }
6299 
6300         session_blob = NULL;
6301         if (params.session_uaddr) {
6302                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6303                 if (IS_ERR(session_blob)) {
6304                         ret = PTR_ERR(session_blob);
6305                         goto e_free_dh;
6306                 }
6307 
6308                 start->session_address = __sme_set(__pa(session_blob));
6309                 start->session_len = params.session_len;
6310         }
6311 
6312         start->handle = params.handle;
6313         start->policy = params.policy;
6314 
6315         /* create memory encryption context */
6316         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6317         if (ret)
6318                 goto e_free_session;
6319 
6320         /* Bind ASID to this guest */
6321         ret = sev_bind_asid(kvm, start->handle, error);
6322         if (ret)
6323                 goto e_free_session;
6324 
6325         /* return handle to userspace */
6326         params.handle = start->handle;
6327         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6328                 sev_unbind_asid(kvm, start->handle);
6329                 ret = -EFAULT;
6330                 goto e_free_session;
6331         }
6332 
6333         sev->handle = start->handle;
6334         sev->fd = argp->sev_fd;
6335 
6336 e_free_session:
6337         kfree(session_blob);
6338 e_free_dh:
6339         kfree(dh_blob);
6340 e_free:
6341         kfree(start);
6342         return ret;
6343 }
6344 
6345 static int get_num_contig_pages(int idx, struct page **inpages,
6346                                 unsigned long npages)
6347 {
6348         unsigned long paddr, next_paddr;
6349         int i = idx + 1, pages = 1;
6350 
6351         /* find the number of contiguous pages starting from idx */
6352         paddr = __sme_page_pa(inpages[idx]);
6353         while (i < npages) {
6354                 next_paddr = __sme_page_pa(inpages[i++]);
6355                 if ((paddr + PAGE_SIZE) == next_paddr) {
6356                         pages++;
6357                         paddr = next_paddr;
6358                         continue;
6359                 }
6360                 break;
6361         }
6362 
6363         return pages;
6364 }
6365 
6366 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6367 {
6368         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6369         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6370         struct kvm_sev_launch_update_data params;
6371         struct sev_data_launch_update_data *data;
6372         struct page **inpages;
6373         int i, ret, pages;
6374 
6375         if (!sev_guest(kvm))
6376                 return -ENOTTY;
6377 
6378         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6379                 return -EFAULT;
6380 
6381         data = kzalloc(sizeof(*data), GFP_KERNEL);
6382         if (!data)
6383                 return -ENOMEM;
6384 
6385         vaddr = params.uaddr;
6386         size = params.len;
6387         vaddr_end = vaddr + size;
6388 
6389         /* Lock the user memory. */
6390         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6391         if (!inpages) {
6392                 ret = -ENOMEM;
6393                 goto e_free;
6394         }
6395 
6396         /*
6397          * The LAUNCH_UPDATE command will perform in-place encryption of the
6398          * memory content (i.e it will write the same memory region with C=1).
6399          * It's possible that the cache may contain the data with C=0, i.e.,
6400          * unencrypted so invalidate it first.
6401          */
6402         sev_clflush_pages(inpages, npages);
6403 
6404         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6405                 int offset, len;
6406 
6407                 /*
6408                  * If the user buffer is not page-aligned, calculate the offset
6409                  * within the page.
6410                  */
6411                 offset = vaddr & (PAGE_SIZE - 1);
6412 
6413                 /* Calculate the number of pages that can be encrypted in one go. */
6414                 pages = get_num_contig_pages(i, inpages, npages);
6415 
6416                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6417 
6418                 data->handle = sev->handle;
6419                 data->len = len;
6420                 data->address = __sme_page_pa(inpages[i]) + offset;
6421                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6422                 if (ret)
6423                         goto e_unpin;
6424 
6425                 size -= len;
6426                 next_vaddr = vaddr + len;
6427         }
6428 
6429 e_unpin:
6430         /* content of memory is updated, mark pages dirty */
6431         for (i = 0; i < npages; i++) {
6432                 set_page_dirty_lock(inpages[i]);
6433                 mark_page_accessed(inpages[i]);
6434         }
6435         /* unlock the user pages */
6436         sev_unpin_memory(kvm, inpages, npages);
6437 e_free:
6438         kfree(data);
6439         return ret;
6440 }
6441 
6442 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6443 {
6444         void __user *measure = (void __user *)(uintptr_t)argp->data;
6445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6446         struct sev_data_launch_measure *data;
6447         struct kvm_sev_launch_measure params;
6448         void __user *p = NULL;
6449         void *blob = NULL;
6450         int ret;
6451 
6452         if (!sev_guest(kvm))
6453                 return -ENOTTY;
6454 
6455         if (copy_from_user(&params, measure, sizeof(params)))
6456                 return -EFAULT;
6457 
6458         data = kzalloc(sizeof(*data), GFP_KERNEL);
6459         if (!data)
6460                 return -ENOMEM;
6461 
6462         /* User wants to query the blob length */
6463         if (!params.len)
6464                 goto cmd;
6465 
6466         p = (void __user *)(uintptr_t)params.uaddr;
6467         if (p) {
6468                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6469                         ret = -EINVAL;
6470                         goto e_free;
6471                 }
6472 
6473                 ret = -ENOMEM;
6474                 blob = kmalloc(params.len, GFP_KERNEL);
6475                 if (!blob)
6476                         goto e_free;
6477 
6478                 data->address = __psp_pa(blob);
6479                 data->len = params.len;
6480         }
6481 
6482 cmd:
6483         data->handle = sev->handle;
6484         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6485 
6486         /*
6487          * If we query the session length, FW responded with expected data.
6488          */
6489         if (!params.len)
6490                 goto done;
6491 
6492         if (ret)
6493                 goto e_free_blob;
6494 
6495         if (blob) {
6496                 if (copy_to_user(p, blob, params.len))
6497                         ret = -EFAULT;
6498         }
6499 
6500 done:
6501         params.len = data->len;
6502         if (copy_to_user(measure, &params, sizeof(params)))
6503                 ret = -EFAULT;
6504 e_free_blob:
6505         kfree(blob);
6506 e_free:
6507         kfree(data);
6508         return ret;
6509 }
6510 
6511 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6512 {
6513         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6514         struct sev_data_launch_finish *data;
6515         int ret;
6516 
6517         if (!sev_guest(kvm))
6518                 return -ENOTTY;
6519 
6520         data = kzalloc(sizeof(*data), GFP_KERNEL);
6521         if (!data)
6522                 return -ENOMEM;
6523 
6524         data->handle = sev->handle;
6525         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6526 
6527         kfree(data);
6528         return ret;
6529 }
6530 
6531 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6532 {
6533         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6534         struct kvm_sev_guest_status params;
6535         struct sev_data_guest_status *data;
6536         int ret;
6537 
6538         if (!sev_guest(kvm))
6539                 return -ENOTTY;
6540 
6541         data = kzalloc(sizeof(*data), GFP_KERNEL);
6542         if (!data)
6543                 return -ENOMEM;
6544 
6545         data->handle = sev->handle;
6546         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6547         if (ret)
6548                 goto e_free;
6549 
6550         params.policy = data->policy;
6551         params.state = data->state;
6552         params.handle = data->handle;
6553 
6554         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6555                 ret = -EFAULT;
6556 e_free:
6557         kfree(data);
6558         return ret;
6559 }
6560 
6561 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6562                                unsigned long dst, int size,
6563                                int *error, bool enc)
6564 {
6565         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6566         struct sev_data_dbg *data;
6567         int ret;
6568 
6569         data = kzalloc(sizeof(*data), GFP_KERNEL);
6570         if (!data)
6571                 return -ENOMEM;
6572 
6573         data->handle = sev->handle;
6574         data->dst_addr = dst;
6575         data->src_addr = src;
6576         data->len = size;
6577 
6578         ret = sev_issue_cmd(kvm,
6579                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6580                             data, error);
6581         kfree(data);
6582         return ret;
6583 }
6584 
6585 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6586                              unsigned long dst_paddr, int sz, int *err)
6587 {
6588         int offset;
6589 
6590         /*
6591          * Its safe to read more than we are asked, caller should ensure that
6592          * destination has enough space.
6593          */
6594         src_paddr = round_down(src_paddr, 16);
6595         offset = src_paddr & 15;
6596         sz = round_up(sz + offset, 16);
6597 
6598         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6599 }
6600 
6601 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6602                                   unsigned long __user dst_uaddr,
6603                                   unsigned long dst_paddr,
6604                                   int size, int *err)
6605 {
6606         struct page *tpage = NULL;
6607         int ret, offset;
6608 
6609         /* if inputs are not 16-byte then use intermediate buffer */
6610         if (!IS_ALIGNED(dst_paddr, 16) ||
6611             !IS_ALIGNED(paddr,     16) ||
6612             !IS_ALIGNED(size,      16)) {
6613                 tpage = (void *)alloc_page(GFP_KERNEL);
6614                 if (!tpage)
6615                         return -ENOMEM;
6616 
6617                 dst_paddr = __sme_page_pa(tpage);
6618         }
6619 
6620         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6621         if (ret)
6622                 goto e_free;
6623 
6624         if (tpage) {
6625                 offset = paddr & 15;
6626                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6627                                  page_address(tpage) + offset, size))
6628                         ret = -EFAULT;
6629         }
6630 
6631 e_free:
6632         if (tpage)
6633                 __free_page(tpage);
6634 
6635         return ret;
6636 }
6637 
6638 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6639                                   unsigned long __user vaddr,
6640                                   unsigned long dst_paddr,
6641                                   unsigned long __user dst_vaddr,
6642                                   int size, int *error)
6643 {
6644         struct page *src_tpage = NULL;
6645         struct page *dst_tpage = NULL;
6646         int ret, len = size;
6647 
6648         /* If source buffer is not aligned then use an intermediate buffer */
6649         if (!IS_ALIGNED(vaddr, 16)) {
6650                 src_tpage = alloc_page(GFP_KERNEL);
6651                 if (!src_tpage)
6652                         return -ENOMEM;
6653 
6654                 if (copy_from_user(page_address(src_tpage),
6655                                 (void __user *)(uintptr_t)vaddr, size)) {
6656                         __free_page(src_tpage);
6657                         return -EFAULT;
6658                 }
6659 
6660                 paddr = __sme_page_pa(src_tpage);
6661         }
6662 
6663         /*
6664          *  If destination buffer or length is not aligned then do read-modify-write:
6665          *   - decrypt destination in an intermediate buffer
6666          *   - copy the source buffer in an intermediate buffer
6667          *   - use the intermediate buffer as source buffer
6668          */
6669         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6670                 int dst_offset;
6671 
6672                 dst_tpage = alloc_page(GFP_KERNEL);
6673                 if (!dst_tpage) {
6674                         ret = -ENOMEM;
6675                         goto e_free;
6676                 }
6677 
6678                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6679                                         __sme_page_pa(dst_tpage), size, error);
6680                 if (ret)
6681                         goto e_free;
6682 
6683                 /*
6684                  *  If source is kernel buffer then use memcpy() otherwise
6685                  *  copy_from_user().
6686                  */
6687                 dst_offset = dst_paddr & 15;
6688 
6689                 if (src_tpage)
6690                         memcpy(page_address(dst_tpage) + dst_offset,
6691                                page_address(src_tpage), size);
6692                 else {
6693                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6694                                            (void __user *)(uintptr_t)vaddr, size)) {
6695                                 ret = -EFAULT;
6696                                 goto e_free;
6697                         }
6698                 }
6699 
6700                 paddr = __sme_page_pa(dst_tpage);
6701                 dst_paddr = round_down(dst_paddr, 16);
6702                 len = round_up(size, 16);
6703         }
6704 
6705         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6706 
6707 e_free:
6708         if (src_tpage)
6709                 __free_page(src_tpage);
6710         if (dst_tpage)
6711                 __free_page(dst_tpage);
6712         return ret;
6713 }
6714 
6715 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6716 {
6717         unsigned long vaddr, vaddr_end, next_vaddr;
6718         unsigned long dst_vaddr, dst_vaddr_end;
6719         struct page **src_p, **dst_p;
6720         struct kvm_sev_dbg debug;
6721         unsigned long n;
6722         int ret, size;
6723 
6724         if (!sev_guest(kvm))
6725                 return -ENOTTY;
6726 
6727         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6728                 return -EFAULT;
6729 
6730         vaddr = debug.src_uaddr;
6731         size = debug.len;
6732         vaddr_end = vaddr + size;
6733         dst_vaddr = debug.dst_uaddr;
6734         dst_vaddr_end = dst_vaddr + size;
6735 
6736         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6737                 int len, s_off, d_off;
6738 
6739                 /* lock userspace source and destination page */
6740                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6741                 if (!src_p)
6742                         return -EFAULT;
6743 
6744                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6745                 if (!dst_p) {
6746                         sev_unpin_memory(kvm, src_p, n);
6747                         return -EFAULT;
6748                 }
6749 
6750                 /*
6751                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6752                  * memory content (i.e it will write the same memory region with C=1).
6753                  * It's possible that the cache may contain the data with C=0, i.e.,
6754                  * unencrypted so invalidate it first.
6755                  */
6756                 sev_clflush_pages(src_p, 1);
6757                 sev_clflush_pages(dst_p, 1);
6758 
6759                 /*
6760                  * Since user buffer may not be page aligned, calculate the
6761                  * offset within the page.
6762                  */
6763                 s_off = vaddr & ~PAGE_MASK;
6764                 d_off = dst_vaddr & ~PAGE_MASK;
6765                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6766 
6767                 if (dec)
6768                         ret = __sev_dbg_decrypt_user(kvm,
6769                                                      __sme_page_pa(src_p[0]) + s_off,
6770                                                      dst_vaddr,
6771                                                      __sme_page_pa(dst_p[0]) + d_off,
6772                                                      len, &argp->error);
6773                 else
6774                         ret = __sev_dbg_encrypt_user(kvm,
6775                                                      __sme_page_pa(src_p[0]) + s_off,
6776                                                      vaddr,
6777                                                      __sme_page_pa(dst_p[0]) + d_off,
6778                                                      dst_vaddr,
6779                                                      len, &argp->error);
6780 
6781                 sev_unpin_memory(kvm, src_p, 1);
6782                 sev_unpin_memory(kvm, dst_p, 1);
6783 
6784                 if (ret)
6785                         goto err;
6786 
6787                 next_vaddr = vaddr + len;
6788                 dst_vaddr = dst_vaddr + len;
6789                 size -= len;
6790         }
6791 err:
6792         return ret;
6793 }
6794 
6795 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6796 {
6797         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6798         struct sev_data_launch_secret *data;
6799         struct kvm_sev_launch_secret params;
6800         struct page **pages;
6801         void *blob, *hdr;
6802         unsigned long n;
6803         int ret, offset;
6804 
6805         if (!sev_guest(kvm))
6806                 return -ENOTTY;
6807 
6808         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6809                 return -EFAULT;
6810 
6811         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6812         if (!pages)
6813                 return -ENOMEM;
6814 
6815         /*
6816          * The secret must be copied into contiguous memory region, lets verify
6817          * that userspace memory pages are contiguous before we issue command.
6818          */
6819         if (get_num_contig_pages(0, pages, n) != n) {
6820                 ret = -EINVAL;
6821                 goto e_unpin_memory;
6822         }
6823 
6824         ret = -ENOMEM;
6825         data = kzalloc(sizeof(*data), GFP_KERNEL);
6826         if (!data)
6827                 goto e_unpin_memory;
6828 
6829         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6830         data->guest_address = __sme_page_pa(pages[0]) + offset;
6831         data->guest_len = params.guest_len;
6832 
6833         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6834         if (IS_ERR(blob)) {
6835                 ret = PTR_ERR(blob);
6836                 goto e_free;
6837         }
6838 
6839         data->trans_address = __psp_pa(blob);
6840         data->trans_len = params.trans_len;
6841 
6842         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6843         if (IS_ERR(hdr)) {
6844                 ret = PTR_ERR(hdr);
6845                 goto e_free_blob;
6846         }
6847         data->hdr_address = __psp_pa(hdr);
6848         data->hdr_len = params.hdr_len;
6849 
6850         data->handle = sev->handle;
6851         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6852 
6853         kfree(hdr);
6854 
6855 e_free_blob:
6856         kfree(blob);
6857 e_free:
6858         kfree(data);
6859 e_unpin_memory:
6860         sev_unpin_memory(kvm, pages, n);
6861         return ret;
6862 }
6863 
6864 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6865 {
6866         struct kvm_sev_cmd sev_cmd;
6867         int r;
6868 
6869         if (!svm_sev_enabled())
6870                 return -ENOTTY;
6871 
6872         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6873                 return -EFAULT;
6874 
6875         mutex_lock(&kvm->lock);
6876 
6877         switch (sev_cmd.id) {
6878         case KVM_SEV_INIT:
6879                 r = sev_guest_init(kvm, &sev_cmd);
6880                 break;
6881         case KVM_SEV_LAUNCH_START:
6882                 r = sev_launch_start(kvm, &sev_cmd);
6883                 break;
6884         case KVM_SEV_LAUNCH_UPDATE_DATA:
6885                 r = sev_launch_update_data(kvm, &sev_cmd);
6886                 break;
6887         case KVM_SEV_LAUNCH_MEASURE:
6888                 r = sev_launch_measure(kvm, &sev_cmd);
6889                 break;
6890         case KVM_SEV_LAUNCH_FINISH:
6891                 r = sev_launch_finish(kvm, &sev_cmd);
6892                 break;
6893         case KVM_SEV_GUEST_STATUS:
6894                 r = sev_guest_status(kvm, &sev_cmd);
6895                 break;
6896         case KVM_SEV_DBG_DECRYPT:
6897                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6898                 break;
6899         case KVM_SEV_DBG_ENCRYPT:
6900                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6901                 break;
6902         case KVM_SEV_LAUNCH_SECRET:
6903                 r = sev_launch_secret(kvm, &sev_cmd);
6904                 break;
6905         default:
6906                 r = -EINVAL;
6907                 goto out;
6908         }
6909 
6910         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6911                 r = -EFAULT;
6912 
6913 out:
6914         mutex_unlock(&kvm->lock);
6915         return r;
6916 }
6917 
6918 static int svm_register_enc_region(struct kvm *kvm,
6919                                    struct kvm_enc_region *range)
6920 {
6921         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6922         struct enc_region *region;
6923         int ret = 0;
6924 
6925         if (!sev_guest(kvm))
6926                 return -ENOTTY;
6927 
6928         region = kzalloc(sizeof(*region), GFP_KERNEL);
6929         if (!region)
6930                 return -ENOMEM;
6931 
6932         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6933         if (!region->pages) {
6934                 ret = -ENOMEM;
6935                 goto e_free;
6936         }
6937 
6938         /*
6939          * The guest may change the memory encryption attribute from C=0 -> C=1
6940          * or vice versa for this memory range. Lets make sure caches are
6941          * flushed to ensure that guest data gets written into memory with
6942          * correct C-bit.
6943          */
6944         sev_clflush_pages(region->pages, region->npages);
6945 
6946         region->uaddr = range->addr;
6947         region->size = range->size;
6948 
6949         mutex_lock(&kvm->lock);
6950         list_add_tail(&region->list, &sev->regions_list);
6951         mutex_unlock(&kvm->lock);
6952 
6953         return ret;
6954 
6955 e_free:
6956         kfree(region);
6957         return ret;
6958 }
6959 
6960 static struct enc_region *
6961 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6962 {
6963         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6964         struct list_head *head = &sev->regions_list;
6965         struct enc_region *i;
6966 
6967         list_for_each_entry(i, head, list) {
6968                 if (i->uaddr == range->addr &&
6969                     i->size == range->size)
6970                         return i;
6971         }
6972 
6973         return NULL;
6974 }
6975 
6976 
6977 static int svm_unregister_enc_region(struct kvm *kvm,
6978                                      struct kvm_enc_region *range)
6979 {
6980         struct enc_region *region;
6981         int ret;
6982 
6983         mutex_lock(&kvm->lock);
6984 
6985         if (!sev_guest(kvm)) {
6986                 ret = -ENOTTY;
6987                 goto failed;
6988         }
6989 
6990         region = find_enc_region(kvm, range);
6991         if (!region) {
6992                 ret = -EINVAL;
6993                 goto failed;
6994         }
6995 
6996         __unregister_enc_region_locked(kvm, region);
6997 
6998         mutex_unlock(&kvm->lock);
6999         return 0;
7000 
7001 failed:
7002         mutex_unlock(&kvm->lock);
7003         return ret;
7004 }
7005 
7006 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7007         .cpu_has_kvm_support = has_svm,
7008         .disabled_by_bios = is_disabled,
7009         .hardware_setup = svm_hardware_setup,
7010         .hardware_unsetup = svm_hardware_unsetup,
7011         .check_processor_compatibility = svm_check_processor_compat,
7012         .hardware_enable = svm_hardware_enable,
7013         .hardware_disable = svm_hardware_disable,
7014         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7015         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
7016 
7017         .vcpu_create = svm_create_vcpu,
7018         .vcpu_free = svm_free_vcpu,
7019         .vcpu_reset = svm_vcpu_reset,
7020 
7021         .vm_alloc = svm_vm_alloc,
7022         .vm_free = svm_vm_free,
7023         .vm_init = avic_vm_init,
7024         .vm_destroy = svm_vm_destroy,
7025 
7026         .prepare_guest_switch = svm_prepare_guest_switch,
7027         .vcpu_load = svm_vcpu_load,
7028         .vcpu_put = svm_vcpu_put,
7029         .vcpu_blocking = svm_vcpu_blocking,
7030         .vcpu_unblocking = svm_vcpu_unblocking,
7031 
7032         .update_bp_intercept = update_bp_intercept,
7033         .get_msr_feature = svm_get_msr_feature,
7034         .get_msr = svm_get_msr,
7035         .set_msr = svm_set_msr,
7036         .get_segment_base = svm_get_segment_base,
7037         .get_segment = svm_get_segment,
7038         .set_segment = svm_set_segment,
7039         .get_cpl = svm_get_cpl,
7040         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7041         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7042         .decache_cr3 = svm_decache_cr3,
7043         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7044         .set_cr0 = svm_set_cr0,
7045         .set_cr3 = svm_set_cr3,
7046         .set_cr4 = svm_set_cr4,
7047         .set_efer = svm_set_efer,
7048         .get_idt = svm_get_idt,
7049         .set_idt = svm_set_idt,
7050         .get_gdt = svm_get_gdt,
7051         .set_gdt = svm_set_gdt,
7052         .get_dr6 = svm_get_dr6,
7053         .set_dr6 = svm_set_dr6,
7054         .set_dr7 = svm_set_dr7,
7055         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7056         .cache_reg = svm_cache_reg,
7057         .get_rflags = svm_get_rflags,
7058         .set_rflags = svm_set_rflags,
7059 
7060         .tlb_flush = svm_flush_tlb,
7061 
7062         .run = svm_vcpu_run,
7063         .handle_exit = handle_exit,
7064         .skip_emulated_instruction = skip_emulated_instruction,
7065         .set_interrupt_shadow = svm_set_interrupt_shadow,
7066         .get_interrupt_shadow = svm_get_interrupt_shadow,
7067         .patch_hypercall = svm_patch_hypercall,
7068         .set_irq = svm_set_irq,
7069         .set_nmi = svm_inject_nmi,
7070         .queue_exception = svm_queue_exception,
7071         .cancel_injection = svm_cancel_injection,
7072         .interrupt_allowed = svm_interrupt_allowed,
7073         .nmi_allowed = svm_nmi_allowed,
7074         .get_nmi_mask = svm_get_nmi_mask,
7075         .set_nmi_mask = svm_set_nmi_mask,
7076         .enable_nmi_window = enable_nmi_window,
7077         .enable_irq_window = enable_irq_window,
7078         .update_cr8_intercept = update_cr8_intercept,
7079         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
7080         .get_enable_apicv = svm_get_enable_apicv,
7081         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7082         .load_eoi_exitmap = svm_load_eoi_exitmap,
7083         .hwapic_irr_update = svm_hwapic_irr_update,
7084         .hwapic_isr_update = svm_hwapic_isr_update,
7085         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7086         .apicv_post_state_restore = avic_post_state_restore,
7087 
7088         .set_tss_addr = svm_set_tss_addr,
7089         .set_identity_map_addr = svm_set_identity_map_addr,
7090         .get_tdp_level = get_npt_level,
7091         .get_mt_mask = svm_get_mt_mask,
7092 
7093         .get_exit_info = svm_get_exit_info,
7094 
7095         .get_lpage_level = svm_get_lpage_level,
7096 
7097         .cpuid_update = svm_cpuid_update,
7098 
7099         .rdtscp_supported = svm_rdtscp_supported,
7100         .invpcid_supported = svm_invpcid_supported,
7101         .mpx_supported = svm_mpx_supported,
7102         .xsaves_supported = svm_xsaves_supported,
7103         .umip_emulated = svm_umip_emulated,
7104 
7105         .set_supported_cpuid = svm_set_supported_cpuid,
7106 
7107         .has_wbinvd_exit = svm_has_wbinvd_exit,
7108 
7109         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7110         .write_tsc_offset = svm_write_tsc_offset,
7111 
7112         .set_tdp_cr3 = set_tdp_cr3,
7113 
7114         .check_intercept = svm_check_intercept,
7115         .handle_external_intr = svm_handle_external_intr,
7116 
7117         .sched_in = svm_sched_in,
7118 
7119         .pmu_ops = &amd_pmu_ops,
7120         .deliver_posted_interrupt = svm_deliver_avic_intr,
7121         .update_pi_irte = svm_update_pi_irte,
7122         .setup_mce = svm_setup_mce,
7123 
7124         .smi_allowed = svm_smi_allowed,
7125         .pre_enter_smm = svm_pre_enter_smm,
7126         .pre_leave_smm = svm_pre_leave_smm,
7127         .enable_smi_window = enable_smi_window,
7128 
7129         .mem_enc_op = svm_mem_enc_op,
7130         .mem_enc_reg_region = svm_register_enc_region,
7131         .mem_enc_unreg_region = svm_unregister_enc_region,
7132 };
7133 
7134 static int __init svm_init(void)
7135 {
7136         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7137                         __alignof__(struct vcpu_svm), THIS_MODULE);
7138 }
7139 
7140 static void __exit svm_exit(void)
7141 {
7142         kvm_exit();
7143 }
7144 
7145 module_init(svm_init)
7146 module_exit(svm_exit)
7147 

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