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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/svm.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * AMD SVM support
  5  *
  6  * Copyright (C) 2006 Qumranet, Inc.
  7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  8  *
  9  * Authors:
 10  *   Yaniv Kamay  <yaniv@qumranet.com>
 11  *   Avi Kivity   <avi@qumranet.com>
 12  *
 13  * This work is licensed under the terms of the GNU GPL, version 2.  See
 14  * the COPYING file in the top-level directory.
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) "SVM: " fmt
 19 
 20 #include <linux/kvm_host.h>
 21 
 22 #include "irq.h"
 23 #include "mmu.h"
 24 #include "kvm_cache_regs.h"
 25 #include "x86.h"
 26 #include "cpuid.h"
 27 #include "pmu.h"
 28 
 29 #include <linux/module.h>
 30 #include <linux/mod_devicetable.h>
 31 #include <linux/kernel.h>
 32 #include <linux/vmalloc.h>
 33 #include <linux/highmem.h>
 34 #include <linux/sched.h>
 35 #include <linux/trace_events.h>
 36 #include <linux/slab.h>
 37 #include <linux/amd-iommu.h>
 38 #include <linux/hashtable.h>
 39 #include <linux/frame.h>
 40 #include <linux/psp-sev.h>
 41 #include <linux/file.h>
 42 #include <linux/pagemap.h>
 43 #include <linux/swap.h>
 44 
 45 #include <asm/apic.h>
 46 #include <asm/perf_event.h>
 47 #include <asm/tlbflush.h>
 48 #include <asm/desc.h>
 49 #include <asm/debugreg.h>
 50 #include <asm/kvm_para.h>
 51 #include <asm/irq_remapping.h>
 52 #include <asm/spec-ctrl.h>
 53 
 54 #include <asm/virtext.h>
 55 #include "trace.h"
 56 
 57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 58 
 59 MODULE_AUTHOR("Qumranet");
 60 MODULE_LICENSE("GPL");
 61 
 62 static const struct x86_cpu_id svm_cpu_id[] = {
 63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
 64         {}
 65 };
 66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
 67 
 68 #define IOPM_ALLOC_ORDER 2
 69 #define MSRPM_ALLOC_ORDER 1
 70 
 71 #define SEG_TYPE_LDT 2
 72 #define SEG_TYPE_BUSY_TSS16 3
 73 
 74 #define SVM_FEATURE_NPT            (1 <<  0)
 75 #define SVM_FEATURE_LBRV           (1 <<  1)
 76 #define SVM_FEATURE_SVML           (1 <<  2)
 77 #define SVM_FEATURE_NRIP           (1 <<  3)
 78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
 79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
 80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
 81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
 82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
 83 
 84 #define SVM_AVIC_DOORBELL       0xc001011b
 85 
 86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 89 
 90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
 91 
 92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
 93 #define TSC_RATIO_MIN           0x0000000000000001ULL
 94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
 95 
 96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
 97 
 98 /*
 99  * 0xff is broadcast, so the max index allowed for physical APIC ID
100  * table is 0xfe.  APIC IDs above 0xff are reserved.
101  */
102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
103 
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
107 
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS               8
110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
111 
112 #define AVIC_VM_ID_BITS                 24
113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
115 
116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117                                                 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
120 
121 static bool erratum_383_found __read_mostly;
122 
123 static const u32 host_save_user_msrs[] = {
124 #ifdef CONFIG_X86_64
125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
126         MSR_FS_BASE,
127 #endif
128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
129         MSR_TSC_AUX,
130 };
131 
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
133 
134 struct kvm_sev_info {
135         bool active;            /* SEV enabled guest */
136         unsigned int asid;      /* ASID used for this guest */
137         unsigned int handle;    /* SEV firmware handle */
138         int fd;                 /* SEV device fd */
139         unsigned long pages_locked; /* Number of pages locked */
140         struct list_head regions_list;  /* List of registered regions */
141 };
142 
143 struct kvm_svm {
144         struct kvm kvm;
145 
146         /* Struct members for AVIC */
147         u32 avic_vm_id;
148         u32 ldr_mode;
149         struct page *avic_logical_id_table_page;
150         struct page *avic_physical_id_table_page;
151         struct hlist_node hnode;
152 
153         struct kvm_sev_info sev_info;
154 };
155 
156 struct kvm_vcpu;
157 
158 struct nested_state {
159         struct vmcb *hsave;
160         u64 hsave_msr;
161         u64 vm_cr_msr;
162         u64 vmcb;
163 
164         /* These are the merged vectors */
165         u32 *msrpm;
166 
167         /* gpa pointers to the real vectors */
168         u64 vmcb_msrpm;
169         u64 vmcb_iopm;
170 
171         /* A VMEXIT is required but not yet emulated */
172         bool exit_required;
173 
174         /* cache for intercepts of the guest */
175         u32 intercept_cr;
176         u32 intercept_dr;
177         u32 intercept_exceptions;
178         u64 intercept;
179 
180         /* Nested Paging related state */
181         u64 nested_cr3;
182 };
183 
184 #define MSRPM_OFFSETS   16
185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
186 
187 /*
188  * Set osvw_len to higher value when updated Revision Guides
189  * are published and we know what the new status bits are
190  */
191 static uint64_t osvw_len = 4, osvw_status;
192 
193 struct vcpu_svm {
194         struct kvm_vcpu vcpu;
195         struct vmcb *vmcb;
196         unsigned long vmcb_pa;
197         struct svm_cpu_data *svm_data;
198         uint64_t asid_generation;
199         uint64_t sysenter_esp;
200         uint64_t sysenter_eip;
201         uint64_t tsc_aux;
202 
203         u64 msr_decfg;
204 
205         u64 next_rip;
206 
207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
208         struct {
209                 u16 fs;
210                 u16 gs;
211                 u16 ldt;
212                 u64 gs_base;
213         } host;
214 
215         u64 spec_ctrl;
216         /*
217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
218          * translated into the appropriate L2_CFG bits on the host to
219          * perform speculative control.
220          */
221         u64 virt_spec_ctrl;
222 
223         u32 *msrpm;
224 
225         ulong nmi_iret_rip;
226 
227         struct nested_state nested;
228 
229         bool nmi_singlestep;
230         u64 nmi_singlestep_guest_rflags;
231 
232         unsigned int3_injected;
233         unsigned long int3_rip;
234 
235         /* cached guest cpuid flags for faster access */
236         bool nrips_enabled      : 1;
237 
238         u32 ldr_reg;
239         struct page *avic_backing_page;
240         u64 *avic_physical_id_cache;
241         bool avic_is_running;
242 
243         /*
244          * Per-vcpu list of struct amd_svm_iommu_ir:
245          * This is used mainly to store interrupt remapping information used
246          * when update the vcpu affinity. This avoids the need to scan for
247          * IRTE and try to match ga_tag in the IOMMU driver.
248          */
249         struct list_head ir_list;
250         spinlock_t ir_list_lock;
251 
252         /* which host CPU was used for running this vcpu */
253         unsigned int last_cpu;
254 };
255 
256 /*
257  * This is a wrapper of struct amd_iommu_ir_data.
258  */
259 struct amd_svm_iommu_ir {
260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
261         void *data;             /* Storing pointer to struct amd_ir_data */
262 };
263 
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
266 
267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
271 
272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
274 
275 #define MSR_INVALID                     0xffffffffU
276 
277 static const struct svm_direct_access_msrs {
278         u32 index;   /* Index of the MSR */
279         bool always; /* True if intercept is always on */
280 } direct_access_msrs[] = {
281         { .index = MSR_STAR,                            .always = true  },
282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
283 #ifdef CONFIG_X86_64
284         { .index = MSR_GS_BASE,                         .always = true  },
285         { .index = MSR_FS_BASE,                         .always = true  },
286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
287         { .index = MSR_LSTAR,                           .always = true  },
288         { .index = MSR_CSTAR,                           .always = true  },
289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
290 #endif
291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
297         { .index = MSR_INVALID,                         .always = false },
298 };
299 
300 /* enable NPT for AMD64 and X86 with PAE */
301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
302 static bool npt_enabled = true;
303 #else
304 static bool npt_enabled;
305 #endif
306 
307 /*
308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
309  * pause_filter_count: On processors that support Pause filtering(indicated
310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
311  *      count value. On VMRUN this value is loaded into an internal counter.
312  *      Each time a pause instruction is executed, this counter is decremented
313  *      until it reaches zero at which time a #VMEXIT is generated if pause
314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
315  *      Intercept Filtering for more details.
316  *      This also indicate if ple logic enabled.
317  *
318  * pause_filter_thresh: In addition, some processor families support advanced
319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
320  *      the amount of time a guest is allowed to execute in a pause loop.
321  *      In this mode, a 16-bit pause filter threshold field is added in the
322  *      VMCB. The threshold value is a cycle count that is used to reset the
323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
324  *      count value from VMCB into an internal counter. Then, on each pause
325  *      instruction the hardware checks the elapsed number of cycles since
326  *      the most recent pause instruction against the pause filter threshold.
327  *      If the elapsed cycle count is greater than the pause filter threshold,
328  *      then the internal pause count is reloaded from the VMCB and execution
329  *      continues. If the elapsed cycle count is less than the pause filter
330  *      threshold, then the internal pause count is decremented. If the count
331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
332  *      triggered. If advanced pause filtering is supported and pause filter
333  *      threshold field is set to zero, the filter will operate in the simpler,
334  *      count only mode.
335  */
336 
337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
338 module_param(pause_filter_thresh, ushort, 0444);
339 
340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
341 module_param(pause_filter_count, ushort, 0444);
342 
343 /* Default doubles per-vcpu window every exit. */
344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
345 module_param(pause_filter_count_grow, ushort, 0444);
346 
347 /* Default resets per-vcpu window every exit to pause_filter_count. */
348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
349 module_param(pause_filter_count_shrink, ushort, 0444);
350 
351 /* Default is to compute the maximum so we can never overflow. */
352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
353 module_param(pause_filter_count_max, ushort, 0444);
354 
355 /* allow nested paging (virtualized MMU) for all guests */
356 static int npt = true;
357 module_param(npt, int, S_IRUGO);
358 
359 /* allow nested virtualization in KVM/SVM */
360 static int nested = true;
361 module_param(nested, int, S_IRUGO);
362 
363 /* enable / disable AVIC */
364 static int avic;
365 #ifdef CONFIG_X86_LOCAL_APIC
366 module_param(avic, int, S_IRUGO);
367 #endif
368 
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls = true;
371 module_param(vls, int, 0444);
372 
373 /* enable/disable Virtual GIF */
374 static int vgif = true;
375 module_param(vgif, int, 0444);
376 
377 /* enable/disable SEV support */
378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
379 module_param(sev, int, 0444);
380 
381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
382 
383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
385 static void svm_complete_interrupts(struct vcpu_svm *svm);
386 
387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
388 static int nested_svm_intercept(struct vcpu_svm *svm);
389 static int nested_svm_vmexit(struct vcpu_svm *svm);
390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
391                                       bool has_error_code, u32 error_code);
392 
393 enum {
394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
395                             pause filter count */
396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
397         VMCB_ASID,       /* ASID */
398         VMCB_INTR,       /* int_ctl, int_vector */
399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
401         VMCB_DR,         /* DR6, DR7 */
402         VMCB_DT,         /* GDT, IDT */
403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
404         VMCB_CR2,        /* CR2 only */
405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
407                           * AVIC PHYSICAL_TABLE pointer,
408                           * AVIC LOGICAL_TABLE pointer
409                           */
410         VMCB_DIRTY_MAX,
411 };
412 
413 /* TPR and CR2 are always written before VMRUN */
414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
415 
416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
417 
418 static unsigned int max_sev_asid;
419 static unsigned int min_sev_asid;
420 static unsigned long *sev_asid_bitmap;
421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
422 
423 struct enc_region {
424         struct list_head list;
425         unsigned long npages;
426         struct page **pages;
427         unsigned long uaddr;
428         unsigned long size;
429 };
430 
431 
432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
433 {
434         return container_of(kvm, struct kvm_svm, kvm);
435 }
436 
437 static inline bool svm_sev_enabled(void)
438 {
439         return max_sev_asid;
440 }
441 
442 static inline bool sev_guest(struct kvm *kvm)
443 {
444         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
445 
446         return sev->active;
447 }
448 
449 static inline int sev_get_asid(struct kvm *kvm)
450 {
451         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
452 
453         return sev->asid;
454 }
455 
456 static inline void mark_all_dirty(struct vmcb *vmcb)
457 {
458         vmcb->control.clean = 0;
459 }
460 
461 static inline void mark_all_clean(struct vmcb *vmcb)
462 {
463         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
464                                & ~VMCB_ALWAYS_DIRTY_MASK;
465 }
466 
467 static inline void mark_dirty(struct vmcb *vmcb, int bit)
468 {
469         vmcb->control.clean &= ~(1 << bit);
470 }
471 
472 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
473 {
474         return container_of(vcpu, struct vcpu_svm, vcpu);
475 }
476 
477 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
478 {
479         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
480         mark_dirty(svm->vmcb, VMCB_AVIC);
481 }
482 
483 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
484 {
485         struct vcpu_svm *svm = to_svm(vcpu);
486         u64 *entry = svm->avic_physical_id_cache;
487 
488         if (!entry)
489                 return false;
490 
491         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
492 }
493 
494 static void recalc_intercepts(struct vcpu_svm *svm)
495 {
496         struct vmcb_control_area *c, *h;
497         struct nested_state *g;
498 
499         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
500 
501         if (!is_guest_mode(&svm->vcpu))
502                 return;
503 
504         c = &svm->vmcb->control;
505         h = &svm->nested.hsave->control;
506         g = &svm->nested;
507 
508         c->intercept_cr = h->intercept_cr | g->intercept_cr;
509         c->intercept_dr = h->intercept_dr | g->intercept_dr;
510         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
511         c->intercept = h->intercept | g->intercept;
512 }
513 
514 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
515 {
516         if (is_guest_mode(&svm->vcpu))
517                 return svm->nested.hsave;
518         else
519                 return svm->vmcb;
520 }
521 
522 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
523 {
524         struct vmcb *vmcb = get_host_vmcb(svm);
525 
526         vmcb->control.intercept_cr |= (1U << bit);
527 
528         recalc_intercepts(svm);
529 }
530 
531 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
532 {
533         struct vmcb *vmcb = get_host_vmcb(svm);
534 
535         vmcb->control.intercept_cr &= ~(1U << bit);
536 
537         recalc_intercepts(svm);
538 }
539 
540 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
541 {
542         struct vmcb *vmcb = get_host_vmcb(svm);
543 
544         return vmcb->control.intercept_cr & (1U << bit);
545 }
546 
547 static inline void set_dr_intercepts(struct vcpu_svm *svm)
548 {
549         struct vmcb *vmcb = get_host_vmcb(svm);
550 
551         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
552                 | (1 << INTERCEPT_DR1_READ)
553                 | (1 << INTERCEPT_DR2_READ)
554                 | (1 << INTERCEPT_DR3_READ)
555                 | (1 << INTERCEPT_DR4_READ)
556                 | (1 << INTERCEPT_DR5_READ)
557                 | (1 << INTERCEPT_DR6_READ)
558                 | (1 << INTERCEPT_DR7_READ)
559                 | (1 << INTERCEPT_DR0_WRITE)
560                 | (1 << INTERCEPT_DR1_WRITE)
561                 | (1 << INTERCEPT_DR2_WRITE)
562                 | (1 << INTERCEPT_DR3_WRITE)
563                 | (1 << INTERCEPT_DR4_WRITE)
564                 | (1 << INTERCEPT_DR5_WRITE)
565                 | (1 << INTERCEPT_DR6_WRITE)
566                 | (1 << INTERCEPT_DR7_WRITE);
567 
568         recalc_intercepts(svm);
569 }
570 
571 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
572 {
573         struct vmcb *vmcb = get_host_vmcb(svm);
574 
575         vmcb->control.intercept_dr = 0;
576 
577         recalc_intercepts(svm);
578 }
579 
580 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
581 {
582         struct vmcb *vmcb = get_host_vmcb(svm);
583 
584         vmcb->control.intercept_exceptions |= (1U << bit);
585 
586         recalc_intercepts(svm);
587 }
588 
589 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
590 {
591         struct vmcb *vmcb = get_host_vmcb(svm);
592 
593         vmcb->control.intercept_exceptions &= ~(1U << bit);
594 
595         recalc_intercepts(svm);
596 }
597 
598 static inline void set_intercept(struct vcpu_svm *svm, int bit)
599 {
600         struct vmcb *vmcb = get_host_vmcb(svm);
601 
602         vmcb->control.intercept |= (1ULL << bit);
603 
604         recalc_intercepts(svm);
605 }
606 
607 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
608 {
609         struct vmcb *vmcb = get_host_vmcb(svm);
610 
611         vmcb->control.intercept &= ~(1ULL << bit);
612 
613         recalc_intercepts(svm);
614 }
615 
616 static inline bool vgif_enabled(struct vcpu_svm *svm)
617 {
618         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
619 }
620 
621 static inline void enable_gif(struct vcpu_svm *svm)
622 {
623         if (vgif_enabled(svm))
624                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
625         else
626                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
627 }
628 
629 static inline void disable_gif(struct vcpu_svm *svm)
630 {
631         if (vgif_enabled(svm))
632                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
633         else
634                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
635 }
636 
637 static inline bool gif_set(struct vcpu_svm *svm)
638 {
639         if (vgif_enabled(svm))
640                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
641         else
642                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
643 }
644 
645 static unsigned long iopm_base;
646 
647 struct kvm_ldttss_desc {
648         u16 limit0;
649         u16 base0;
650         unsigned base1:8, type:5, dpl:2, p:1;
651         unsigned limit1:4, zero0:3, g:1, base2:8;
652         u32 base3;
653         u32 zero1;
654 } __attribute__((packed));
655 
656 struct svm_cpu_data {
657         int cpu;
658 
659         u64 asid_generation;
660         u32 max_asid;
661         u32 next_asid;
662         u32 min_asid;
663         struct kvm_ldttss_desc *tss_desc;
664 
665         struct page *save_area;
666         struct vmcb *current_vmcb;
667 
668         /* index = sev_asid, value = vmcb pointer */
669         struct vmcb **sev_vmcbs;
670 };
671 
672 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
673 
674 struct svm_init_data {
675         int cpu;
676         int r;
677 };
678 
679 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
680 
681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
682 #define MSRS_RANGE_SIZE 2048
683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
684 
685 static u32 svm_msrpm_offset(u32 msr)
686 {
687         u32 offset;
688         int i;
689 
690         for (i = 0; i < NUM_MSR_MAPS; i++) {
691                 if (msr < msrpm_ranges[i] ||
692                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
693                         continue;
694 
695                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
696                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
697 
698                 /* Now we have the u8 offset - but need the u32 offset */
699                 return offset / 4;
700         }
701 
702         /* MSR not in any range */
703         return MSR_INVALID;
704 }
705 
706 #define MAX_INST_SIZE 15
707 
708 static inline void clgi(void)
709 {
710         asm volatile (__ex(SVM_CLGI));
711 }
712 
713 static inline void stgi(void)
714 {
715         asm volatile (__ex(SVM_STGI));
716 }
717 
718 static inline void invlpga(unsigned long addr, u32 asid)
719 {
720         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
721 }
722 
723 static int get_npt_level(struct kvm_vcpu *vcpu)
724 {
725 #ifdef CONFIG_X86_64
726         return PT64_ROOT_4LEVEL;
727 #else
728         return PT32E_ROOT_LEVEL;
729 #endif
730 }
731 
732 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
733 {
734         vcpu->arch.efer = efer;
735         if (!npt_enabled && !(efer & EFER_LMA))
736                 efer &= ~EFER_LME;
737 
738         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
739         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
740 }
741 
742 static int is_external_interrupt(u32 info)
743 {
744         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
745         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
746 }
747 
748 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
749 {
750         struct vcpu_svm *svm = to_svm(vcpu);
751         u32 ret = 0;
752 
753         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
754                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
755         return ret;
756 }
757 
758 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
759 {
760         struct vcpu_svm *svm = to_svm(vcpu);
761 
762         if (mask == 0)
763                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
764         else
765                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
766 
767 }
768 
769 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
770 {
771         struct vcpu_svm *svm = to_svm(vcpu);
772 
773         if (svm->vmcb->control.next_rip != 0) {
774                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
775                 svm->next_rip = svm->vmcb->control.next_rip;
776         }
777 
778         if (!svm->next_rip) {
779                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
780                                 EMULATE_DONE)
781                         printk(KERN_DEBUG "%s: NOP\n", __func__);
782                 return;
783         }
784         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
785                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
786                        __func__, kvm_rip_read(vcpu), svm->next_rip);
787 
788         kvm_rip_write(vcpu, svm->next_rip);
789         svm_set_interrupt_shadow(vcpu, 0);
790 }
791 
792 static void svm_queue_exception(struct kvm_vcpu *vcpu)
793 {
794         struct vcpu_svm *svm = to_svm(vcpu);
795         unsigned nr = vcpu->arch.exception.nr;
796         bool has_error_code = vcpu->arch.exception.has_error_code;
797         bool reinject = vcpu->arch.exception.injected;
798         u32 error_code = vcpu->arch.exception.error_code;
799 
800         /*
801          * If we are within a nested VM we'd better #VMEXIT and let the guest
802          * handle the exception
803          */
804         if (!reinject &&
805             nested_svm_check_exception(svm, nr, has_error_code, error_code))
806                 return;
807 
808         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
809                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
810 
811                 /*
812                  * For guest debugging where we have to reinject #BP if some
813                  * INT3 is guest-owned:
814                  * Emulate nRIP by moving RIP forward. Will fail if injection
815                  * raises a fault that is not intercepted. Still better than
816                  * failing in all cases.
817                  */
818                 skip_emulated_instruction(&svm->vcpu);
819                 rip = kvm_rip_read(&svm->vcpu);
820                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
821                 svm->int3_injected = rip - old_rip;
822         }
823 
824         svm->vmcb->control.event_inj = nr
825                 | SVM_EVTINJ_VALID
826                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
827                 | SVM_EVTINJ_TYPE_EXEPT;
828         svm->vmcb->control.event_inj_err = error_code;
829 }
830 
831 static void svm_init_erratum_383(void)
832 {
833         u32 low, high;
834         int err;
835         u64 val;
836 
837         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
838                 return;
839 
840         /* Use _safe variants to not break nested virtualization */
841         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
842         if (err)
843                 return;
844 
845         val |= (1ULL << 47);
846 
847         low  = lower_32_bits(val);
848         high = upper_32_bits(val);
849 
850         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
851 
852         erratum_383_found = true;
853 }
854 
855 static void svm_init_osvw(struct kvm_vcpu *vcpu)
856 {
857         /*
858          * Guests should see errata 400 and 415 as fixed (assuming that
859          * HLT and IO instructions are intercepted).
860          */
861         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
862         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
863 
864         /*
865          * By increasing VCPU's osvw.length to 3 we are telling the guest that
866          * all osvw.status bits inside that length, including bit 0 (which is
867          * reserved for erratum 298), are valid. However, if host processor's
868          * osvw_len is 0 then osvw_status[0] carries no information. We need to
869          * be conservative here and therefore we tell the guest that erratum 298
870          * is present (because we really don't know).
871          */
872         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
873                 vcpu->arch.osvw.status |= 1;
874 }
875 
876 static int has_svm(void)
877 {
878         const char *msg;
879 
880         if (!cpu_has_svm(&msg)) {
881                 printk(KERN_INFO "has_svm: %s\n", msg);
882                 return 0;
883         }
884 
885         return 1;
886 }
887 
888 static void svm_hardware_disable(void)
889 {
890         /* Make sure we clean up behind us */
891         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
892                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
893 
894         cpu_svm_disable();
895 
896         amd_pmu_disable_virt();
897 }
898 
899 static int svm_hardware_enable(void)
900 {
901 
902         struct svm_cpu_data *sd;
903         uint64_t efer;
904         struct desc_struct *gdt;
905         int me = raw_smp_processor_id();
906 
907         rdmsrl(MSR_EFER, efer);
908         if (efer & EFER_SVME)
909                 return -EBUSY;
910 
911         if (!has_svm()) {
912                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
913                 return -EINVAL;
914         }
915         sd = per_cpu(svm_data, me);
916         if (!sd) {
917                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
918                 return -EINVAL;
919         }
920 
921         sd->asid_generation = 1;
922         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
923         sd->next_asid = sd->max_asid + 1;
924         sd->min_asid = max_sev_asid + 1;
925 
926         gdt = get_current_gdt_rw();
927         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
928 
929         wrmsrl(MSR_EFER, efer | EFER_SVME);
930 
931         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
932 
933         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
934                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
935                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
936         }
937 
938 
939         /*
940          * Get OSVW bits.
941          *
942          * Note that it is possible to have a system with mixed processor
943          * revisions and therefore different OSVW bits. If bits are not the same
944          * on different processors then choose the worst case (i.e. if erratum
945          * is present on one processor and not on another then assume that the
946          * erratum is present everywhere).
947          */
948         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
949                 uint64_t len, status = 0;
950                 int err;
951 
952                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
953                 if (!err)
954                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
955                                                       &err);
956 
957                 if (err)
958                         osvw_status = osvw_len = 0;
959                 else {
960                         if (len < osvw_len)
961                                 osvw_len = len;
962                         osvw_status |= status;
963                         osvw_status &= (1ULL << osvw_len) - 1;
964                 }
965         } else
966                 osvw_status = osvw_len = 0;
967 
968         svm_init_erratum_383();
969 
970         amd_pmu_enable_virt();
971 
972         return 0;
973 }
974 
975 static void svm_cpu_uninit(int cpu)
976 {
977         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
978 
979         if (!sd)
980                 return;
981 
982         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
983         kfree(sd->sev_vmcbs);
984         __free_page(sd->save_area);
985         kfree(sd);
986 }
987 
988 static int svm_cpu_init(int cpu)
989 {
990         struct svm_cpu_data *sd;
991         int r;
992 
993         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
994         if (!sd)
995                 return -ENOMEM;
996         sd->cpu = cpu;
997         r = -ENOMEM;
998         sd->save_area = alloc_page(GFP_KERNEL);
999         if (!sd->save_area)
1000                 goto err_1;
1001 
1002         if (svm_sev_enabled()) {
1003                 r = -ENOMEM;
1004                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1005                                               sizeof(void *),
1006                                               GFP_KERNEL);
1007                 if (!sd->sev_vmcbs)
1008                         goto err_1;
1009         }
1010 
1011         per_cpu(svm_data, cpu) = sd;
1012 
1013         return 0;
1014 
1015 err_1:
1016         kfree(sd);
1017         return r;
1018 
1019 }
1020 
1021 static bool valid_msr_intercept(u32 index)
1022 {
1023         int i;
1024 
1025         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1026                 if (direct_access_msrs[i].index == index)
1027                         return true;
1028 
1029         return false;
1030 }
1031 
1032 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1033 {
1034         u8 bit_write;
1035         unsigned long tmp;
1036         u32 offset;
1037         u32 *msrpm;
1038 
1039         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1040                                       to_svm(vcpu)->msrpm;
1041 
1042         offset    = svm_msrpm_offset(msr);
1043         bit_write = 2 * (msr & 0x0f) + 1;
1044         tmp       = msrpm[offset];
1045 
1046         BUG_ON(offset == MSR_INVALID);
1047 
1048         return !!test_bit(bit_write,  &tmp);
1049 }
1050 
1051 static void set_msr_interception(u32 *msrpm, unsigned msr,
1052                                  int read, int write)
1053 {
1054         u8 bit_read, bit_write;
1055         unsigned long tmp;
1056         u32 offset;
1057 
1058         /*
1059          * If this warning triggers extend the direct_access_msrs list at the
1060          * beginning of the file
1061          */
1062         WARN_ON(!valid_msr_intercept(msr));
1063 
1064         offset    = svm_msrpm_offset(msr);
1065         bit_read  = 2 * (msr & 0x0f);
1066         bit_write = 2 * (msr & 0x0f) + 1;
1067         tmp       = msrpm[offset];
1068 
1069         BUG_ON(offset == MSR_INVALID);
1070 
1071         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1072         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1073 
1074         msrpm[offset] = tmp;
1075 }
1076 
1077 static void svm_vcpu_init_msrpm(u32 *msrpm)
1078 {
1079         int i;
1080 
1081         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1082 
1083         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1084                 if (!direct_access_msrs[i].always)
1085                         continue;
1086 
1087                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1088         }
1089 }
1090 
1091 static void add_msr_offset(u32 offset)
1092 {
1093         int i;
1094 
1095         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1096 
1097                 /* Offset already in list? */
1098                 if (msrpm_offsets[i] == offset)
1099                         return;
1100 
1101                 /* Slot used by another offset? */
1102                 if (msrpm_offsets[i] != MSR_INVALID)
1103                         continue;
1104 
1105                 /* Add offset to list */
1106                 msrpm_offsets[i] = offset;
1107 
1108                 return;
1109         }
1110 
1111         /*
1112          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1113          * increase MSRPM_OFFSETS in this case.
1114          */
1115         BUG();
1116 }
1117 
1118 static void init_msrpm_offsets(void)
1119 {
1120         int i;
1121 
1122         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1123 
1124         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1125                 u32 offset;
1126 
1127                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1128                 BUG_ON(offset == MSR_INVALID);
1129 
1130                 add_msr_offset(offset);
1131         }
1132 }
1133 
1134 static void svm_enable_lbrv(struct vcpu_svm *svm)
1135 {
1136         u32 *msrpm = svm->msrpm;
1137 
1138         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1139         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1140         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1141         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1143 }
1144 
1145 static void svm_disable_lbrv(struct vcpu_svm *svm)
1146 {
1147         u32 *msrpm = svm->msrpm;
1148 
1149         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1150         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1151         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1152         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1154 }
1155 
1156 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1157 {
1158         svm->nmi_singlestep = false;
1159 
1160         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1161                 /* Clear our flags if they were not set by the guest */
1162                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1163                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1164                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1165                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1166         }
1167 }
1168 
1169 /* Note:
1170  * This hash table is used to map VM_ID to a struct kvm_svm,
1171  * when handling AMD IOMMU GALOG notification to schedule in
1172  * a particular vCPU.
1173  */
1174 #define SVM_VM_DATA_HASH_BITS   8
1175 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1176 static u32 next_vm_id = 0;
1177 static bool next_vm_id_wrapped = 0;
1178 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1179 
1180 /* Note:
1181  * This function is called from IOMMU driver to notify
1182  * SVM to schedule in a particular vCPU of a particular VM.
1183  */
1184 static int avic_ga_log_notifier(u32 ga_tag)
1185 {
1186         unsigned long flags;
1187         struct kvm_svm *kvm_svm;
1188         struct kvm_vcpu *vcpu = NULL;
1189         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1190         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1191 
1192         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1193 
1194         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1195         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1196                 if (kvm_svm->avic_vm_id != vm_id)
1197                         continue;
1198                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1199                 break;
1200         }
1201         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1202 
1203         /* Note:
1204          * At this point, the IOMMU should have already set the pending
1205          * bit in the vAPIC backing page. So, we just need to schedule
1206          * in the vcpu.
1207          */
1208         if (vcpu)
1209                 kvm_vcpu_wake_up(vcpu);
1210 
1211         return 0;
1212 }
1213 
1214 static __init int sev_hardware_setup(void)
1215 {
1216         struct sev_user_data_status *status;
1217         int rc;
1218 
1219         /* Maximum number of encrypted guests supported simultaneously */
1220         max_sev_asid = cpuid_ecx(0x8000001F);
1221 
1222         if (!max_sev_asid)
1223                 return 1;
1224 
1225         /* Minimum ASID value that should be used for SEV guest */
1226         min_sev_asid = cpuid_edx(0x8000001F);
1227 
1228         /* Initialize SEV ASID bitmap */
1229         sev_asid_bitmap = kcalloc(BITS_TO_LONGS(max_sev_asid),
1230                                 sizeof(unsigned long), GFP_KERNEL);
1231         if (!sev_asid_bitmap)
1232                 return 1;
1233 
1234         status = kmalloc(sizeof(*status), GFP_KERNEL);
1235         if (!status)
1236                 return 1;
1237 
1238         /*
1239          * Check SEV platform status.
1240          *
1241          * PLATFORM_STATUS can be called in any state, if we failed to query
1242          * the PLATFORM status then either PSP firmware does not support SEV
1243          * feature or SEV firmware is dead.
1244          */
1245         rc = sev_platform_status(status, NULL);
1246         if (rc)
1247                 goto err;
1248 
1249         pr_info("SEV supported\n");
1250 
1251 err:
1252         kfree(status);
1253         return rc;
1254 }
1255 
1256 static void grow_ple_window(struct kvm_vcpu *vcpu)
1257 {
1258         struct vcpu_svm *svm = to_svm(vcpu);
1259         struct vmcb_control_area *control = &svm->vmcb->control;
1260         int old = control->pause_filter_count;
1261 
1262         control->pause_filter_count = __grow_ple_window(old,
1263                                                         pause_filter_count,
1264                                                         pause_filter_count_grow,
1265                                                         pause_filter_count_max);
1266 
1267         if (control->pause_filter_count != old)
1268                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1269 
1270         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1271                                   control->pause_filter_count, old);
1272 }
1273 
1274 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277         struct vmcb_control_area *control = &svm->vmcb->control;
1278         int old = control->pause_filter_count;
1279 
1280         control->pause_filter_count =
1281                                 __shrink_ple_window(old,
1282                                                     pause_filter_count,
1283                                                     pause_filter_count_shrink,
1284                                                     pause_filter_count);
1285         if (control->pause_filter_count != old)
1286                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287 
1288         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1289                                     control->pause_filter_count, old);
1290 }
1291 
1292 static __init int svm_hardware_setup(void)
1293 {
1294         int cpu;
1295         struct page *iopm_pages;
1296         void *iopm_va;
1297         int r;
1298 
1299         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1300 
1301         if (!iopm_pages)
1302                 return -ENOMEM;
1303 
1304         iopm_va = page_address(iopm_pages);
1305         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1306         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1307 
1308         init_msrpm_offsets();
1309 
1310         if (boot_cpu_has(X86_FEATURE_NX))
1311                 kvm_enable_efer_bits(EFER_NX);
1312 
1313         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1314                 kvm_enable_efer_bits(EFER_FFXSR);
1315 
1316         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1317                 kvm_has_tsc_control = true;
1318                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1319                 kvm_tsc_scaling_ratio_frac_bits = 32;
1320         }
1321 
1322         /* Check for pause filtering support */
1323         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1324                 pause_filter_count = 0;
1325                 pause_filter_thresh = 0;
1326         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1327                 pause_filter_thresh = 0;
1328         }
1329 
1330         if (nested) {
1331                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1332                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1333         }
1334 
1335         if (sev) {
1336                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1337                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1338                         r = sev_hardware_setup();
1339                         if (r)
1340                                 sev = false;
1341                 } else {
1342                         sev = false;
1343                 }
1344         }
1345 
1346         for_each_possible_cpu(cpu) {
1347                 r = svm_cpu_init(cpu);
1348                 if (r)
1349                         goto err;
1350         }
1351 
1352         if (!boot_cpu_has(X86_FEATURE_NPT))
1353                 npt_enabled = false;
1354 
1355         if (npt_enabled && !npt) {
1356                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1357                 npt_enabled = false;
1358         }
1359 
1360         if (npt_enabled) {
1361                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1362                 kvm_enable_tdp();
1363         } else
1364                 kvm_disable_tdp();
1365 
1366         if (avic) {
1367                 if (!npt_enabled ||
1368                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1369                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1370                         avic = false;
1371                 } else {
1372                         pr_info("AVIC enabled\n");
1373 
1374                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1375                 }
1376         }
1377 
1378         if (vls) {
1379                 if (!npt_enabled ||
1380                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1381                     !IS_ENABLED(CONFIG_X86_64)) {
1382                         vls = false;
1383                 } else {
1384                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1385                 }
1386         }
1387 
1388         if (vgif) {
1389                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1390                         vgif = false;
1391                 else
1392                         pr_info("Virtual GIF supported\n");
1393         }
1394 
1395         return 0;
1396 
1397 err:
1398         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1399         iopm_base = 0;
1400         return r;
1401 }
1402 
1403 static __exit void svm_hardware_unsetup(void)
1404 {
1405         int cpu;
1406 
1407         if (svm_sev_enabled())
1408                 kfree(sev_asid_bitmap);
1409 
1410         for_each_possible_cpu(cpu)
1411                 svm_cpu_uninit(cpu);
1412 
1413         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1414         iopm_base = 0;
1415 }
1416 
1417 static void init_seg(struct vmcb_seg *seg)
1418 {
1419         seg->selector = 0;
1420         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1421                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1422         seg->limit = 0xffff;
1423         seg->base = 0;
1424 }
1425 
1426 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1427 {
1428         seg->selector = 0;
1429         seg->attrib = SVM_SELECTOR_P_MASK | type;
1430         seg->limit = 0xffff;
1431         seg->base = 0;
1432 }
1433 
1434 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1435 {
1436         struct vcpu_svm *svm = to_svm(vcpu);
1437 
1438         if (is_guest_mode(vcpu))
1439                 return svm->nested.hsave->control.tsc_offset;
1440 
1441         return vcpu->arch.tsc_offset;
1442 }
1443 
1444 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1445 {
1446         struct vcpu_svm *svm = to_svm(vcpu);
1447         u64 g_tsc_offset = 0;
1448 
1449         if (is_guest_mode(vcpu)) {
1450                 /* Write L1's TSC offset.  */
1451                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1452                                svm->nested.hsave->control.tsc_offset;
1453                 svm->nested.hsave->control.tsc_offset = offset;
1454         } else
1455                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1456                                            svm->vmcb->control.tsc_offset,
1457                                            offset);
1458 
1459         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1460 
1461         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1462 }
1463 
1464 static void avic_init_vmcb(struct vcpu_svm *svm)
1465 {
1466         struct vmcb *vmcb = svm->vmcb;
1467         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1468         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1469         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1470         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1471 
1472         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1473         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1474         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1475         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1476         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1477 }
1478 
1479 static void init_vmcb(struct vcpu_svm *svm)
1480 {
1481         struct vmcb_control_area *control = &svm->vmcb->control;
1482         struct vmcb_save_area *save = &svm->vmcb->save;
1483 
1484         svm->vcpu.arch.hflags = 0;
1485 
1486         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1487         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1488         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1489         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1490         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1491         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1492         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1493                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1494 
1495         set_dr_intercepts(svm);
1496 
1497         set_exception_intercept(svm, PF_VECTOR);
1498         set_exception_intercept(svm, UD_VECTOR);
1499         set_exception_intercept(svm, MC_VECTOR);
1500         set_exception_intercept(svm, AC_VECTOR);
1501         set_exception_intercept(svm, DB_VECTOR);
1502         /*
1503          * Guest access to VMware backdoor ports could legitimately
1504          * trigger #GP because of TSS I/O permission bitmap.
1505          * We intercept those #GP and allow access to them anyway
1506          * as VMware does.
1507          */
1508         if (enable_vmware_backdoor)
1509                 set_exception_intercept(svm, GP_VECTOR);
1510 
1511         set_intercept(svm, INTERCEPT_INTR);
1512         set_intercept(svm, INTERCEPT_NMI);
1513         set_intercept(svm, INTERCEPT_SMI);
1514         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1515         set_intercept(svm, INTERCEPT_RDPMC);
1516         set_intercept(svm, INTERCEPT_CPUID);
1517         set_intercept(svm, INTERCEPT_INVD);
1518         set_intercept(svm, INTERCEPT_INVLPG);
1519         set_intercept(svm, INTERCEPT_INVLPGA);
1520         set_intercept(svm, INTERCEPT_IOIO_PROT);
1521         set_intercept(svm, INTERCEPT_MSR_PROT);
1522         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1523         set_intercept(svm, INTERCEPT_SHUTDOWN);
1524         set_intercept(svm, INTERCEPT_VMRUN);
1525         set_intercept(svm, INTERCEPT_VMMCALL);
1526         set_intercept(svm, INTERCEPT_VMLOAD);
1527         set_intercept(svm, INTERCEPT_VMSAVE);
1528         set_intercept(svm, INTERCEPT_STGI);
1529         set_intercept(svm, INTERCEPT_CLGI);
1530         set_intercept(svm, INTERCEPT_SKINIT);
1531         set_intercept(svm, INTERCEPT_WBINVD);
1532         set_intercept(svm, INTERCEPT_XSETBV);
1533         set_intercept(svm, INTERCEPT_RSM);
1534 
1535         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1536                 set_intercept(svm, INTERCEPT_MONITOR);
1537                 set_intercept(svm, INTERCEPT_MWAIT);
1538         }
1539 
1540         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1541                 set_intercept(svm, INTERCEPT_HLT);
1542 
1543         control->iopm_base_pa = __sme_set(iopm_base);
1544         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1545         control->int_ctl = V_INTR_MASKING_MASK;
1546 
1547         init_seg(&save->es);
1548         init_seg(&save->ss);
1549         init_seg(&save->ds);
1550         init_seg(&save->fs);
1551         init_seg(&save->gs);
1552 
1553         save->cs.selector = 0xf000;
1554         save->cs.base = 0xffff0000;
1555         /* Executable/Readable Code Segment */
1556         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1557                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1558         save->cs.limit = 0xffff;
1559 
1560         save->gdtr.limit = 0xffff;
1561         save->idtr.limit = 0xffff;
1562 
1563         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1564         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1565 
1566         svm_set_efer(&svm->vcpu, 0);
1567         save->dr6 = 0xffff0ff0;
1568         kvm_set_rflags(&svm->vcpu, 2);
1569         save->rip = 0x0000fff0;
1570         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1571 
1572         /*
1573          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1574          * It also updates the guest-visible cr0 value.
1575          */
1576         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1577         kvm_mmu_reset_context(&svm->vcpu);
1578 
1579         save->cr4 = X86_CR4_PAE;
1580         /* rdx = ?? */
1581 
1582         if (npt_enabled) {
1583                 /* Setup VMCB for Nested Paging */
1584                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1585                 clr_intercept(svm, INTERCEPT_INVLPG);
1586                 clr_exception_intercept(svm, PF_VECTOR);
1587                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1588                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1589                 save->g_pat = svm->vcpu.arch.pat;
1590                 save->cr3 = 0;
1591                 save->cr4 = 0;
1592         }
1593         svm->asid_generation = 0;
1594 
1595         svm->nested.vmcb = 0;
1596         svm->vcpu.arch.hflags = 0;
1597 
1598         if (pause_filter_count) {
1599                 control->pause_filter_count = pause_filter_count;
1600                 if (pause_filter_thresh)
1601                         control->pause_filter_thresh = pause_filter_thresh;
1602                 set_intercept(svm, INTERCEPT_PAUSE);
1603         } else {
1604                 clr_intercept(svm, INTERCEPT_PAUSE);
1605         }
1606 
1607         if (kvm_vcpu_apicv_active(&svm->vcpu))
1608                 avic_init_vmcb(svm);
1609 
1610         /*
1611          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1612          * in VMCB and clear intercepts to avoid #VMEXIT.
1613          */
1614         if (vls) {
1615                 clr_intercept(svm, INTERCEPT_VMLOAD);
1616                 clr_intercept(svm, INTERCEPT_VMSAVE);
1617                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1618         }
1619 
1620         if (vgif) {
1621                 clr_intercept(svm, INTERCEPT_STGI);
1622                 clr_intercept(svm, INTERCEPT_CLGI);
1623                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1624         }
1625 
1626         if (sev_guest(svm->vcpu.kvm)) {
1627                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1628                 clr_exception_intercept(svm, UD_VECTOR);
1629         }
1630 
1631         mark_all_dirty(svm->vmcb);
1632 
1633         enable_gif(svm);
1634 
1635 }
1636 
1637 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1638                                        unsigned int index)
1639 {
1640         u64 *avic_physical_id_table;
1641         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1642 
1643         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1644                 return NULL;
1645 
1646         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1647 
1648         return &avic_physical_id_table[index];
1649 }
1650 
1651 /**
1652  * Note:
1653  * AVIC hardware walks the nested page table to check permissions,
1654  * but does not use the SPA address specified in the leaf page
1655  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1656  * field of the VMCB. Therefore, we set up the
1657  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1658  */
1659 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1660 {
1661         struct kvm *kvm = vcpu->kvm;
1662         int ret;
1663 
1664         if (kvm->arch.apic_access_page_done)
1665                 return 0;
1666 
1667         ret = x86_set_memory_region(kvm,
1668                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1669                                     APIC_DEFAULT_PHYS_BASE,
1670                                     PAGE_SIZE);
1671         if (ret)
1672                 return ret;
1673 
1674         kvm->arch.apic_access_page_done = true;
1675         return 0;
1676 }
1677 
1678 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1679 {
1680         int ret;
1681         u64 *entry, new_entry;
1682         int id = vcpu->vcpu_id;
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684 
1685         ret = avic_init_access_page(vcpu);
1686         if (ret)
1687                 return ret;
1688 
1689         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1690                 return -EINVAL;
1691 
1692         if (!svm->vcpu.arch.apic->regs)
1693                 return -EINVAL;
1694 
1695         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1696 
1697         /* Setting AVIC backing page address in the phy APIC ID table */
1698         entry = avic_get_physical_id_entry(vcpu, id);
1699         if (!entry)
1700                 return -EINVAL;
1701 
1702         new_entry = READ_ONCE(*entry);
1703         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1704                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1705                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1706         WRITE_ONCE(*entry, new_entry);
1707 
1708         svm->avic_physical_id_cache = entry;
1709 
1710         return 0;
1711 }
1712 
1713 static void __sev_asid_free(int asid)
1714 {
1715         struct svm_cpu_data *sd;
1716         int cpu, pos;
1717 
1718         pos = asid - 1;
1719         clear_bit(pos, sev_asid_bitmap);
1720 
1721         for_each_possible_cpu(cpu) {
1722                 sd = per_cpu(svm_data, cpu);
1723                 sd->sev_vmcbs[pos] = NULL;
1724         }
1725 }
1726 
1727 static void sev_asid_free(struct kvm *kvm)
1728 {
1729         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1730 
1731         __sev_asid_free(sev->asid);
1732 }
1733 
1734 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1735 {
1736         struct sev_data_decommission *decommission;
1737         struct sev_data_deactivate *data;
1738 
1739         if (!handle)
1740                 return;
1741 
1742         data = kzalloc(sizeof(*data), GFP_KERNEL);
1743         if (!data)
1744                 return;
1745 
1746         /* deactivate handle */
1747         data->handle = handle;
1748         sev_guest_deactivate(data, NULL);
1749 
1750         wbinvd_on_all_cpus();
1751         sev_guest_df_flush(NULL);
1752         kfree(data);
1753 
1754         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1755         if (!decommission)
1756                 return;
1757 
1758         /* decommission handle */
1759         decommission->handle = handle;
1760         sev_guest_decommission(decommission, NULL);
1761 
1762         kfree(decommission);
1763 }
1764 
1765 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1766                                     unsigned long ulen, unsigned long *n,
1767                                     int write)
1768 {
1769         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1770         unsigned long npages, npinned, size;
1771         unsigned long locked, lock_limit;
1772         struct page **pages;
1773         unsigned long first, last;
1774 
1775         if (ulen == 0 || uaddr + ulen < uaddr)
1776                 return NULL;
1777 
1778         /* Calculate number of pages. */
1779         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1780         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1781         npages = (last - first + 1);
1782 
1783         locked = sev->pages_locked + npages;
1784         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1785         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1786                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1787                 return NULL;
1788         }
1789 
1790         /* Avoid using vmalloc for smaller buffers. */
1791         size = npages * sizeof(struct page *);
1792         if (size > PAGE_SIZE)
1793                 pages = vmalloc(size);
1794         else
1795                 pages = kmalloc(size, GFP_KERNEL);
1796 
1797         if (!pages)
1798                 return NULL;
1799 
1800         /* Pin the user virtual address. */
1801         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1802         if (npinned != npages) {
1803                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1804                 goto err;
1805         }
1806 
1807         *n = npages;
1808         sev->pages_locked = locked;
1809 
1810         return pages;
1811 
1812 err:
1813         if (npinned > 0)
1814                 release_pages(pages, npinned);
1815 
1816         kvfree(pages);
1817         return NULL;
1818 }
1819 
1820 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1821                              unsigned long npages)
1822 {
1823         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1824 
1825         release_pages(pages, npages);
1826         kvfree(pages);
1827         sev->pages_locked -= npages;
1828 }
1829 
1830 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1831 {
1832         uint8_t *page_virtual;
1833         unsigned long i;
1834 
1835         if (npages == 0 || pages == NULL)
1836                 return;
1837 
1838         for (i = 0; i < npages; i++) {
1839                 page_virtual = kmap_atomic(pages[i]);
1840                 clflush_cache_range(page_virtual, PAGE_SIZE);
1841                 kunmap_atomic(page_virtual);
1842         }
1843 }
1844 
1845 static void __unregister_enc_region_locked(struct kvm *kvm,
1846                                            struct enc_region *region)
1847 {
1848         /*
1849          * The guest may change the memory encryption attribute from C=0 -> C=1
1850          * or vice versa for this memory range. Lets make sure caches are
1851          * flushed to ensure that guest data gets written into memory with
1852          * correct C-bit.
1853          */
1854         sev_clflush_pages(region->pages, region->npages);
1855 
1856         sev_unpin_memory(kvm, region->pages, region->npages);
1857         list_del(&region->list);
1858         kfree(region);
1859 }
1860 
1861 static struct kvm *svm_vm_alloc(void)
1862 {
1863         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1864         return &kvm_svm->kvm;
1865 }
1866 
1867 static void svm_vm_free(struct kvm *kvm)
1868 {
1869         vfree(to_kvm_svm(kvm));
1870 }
1871 
1872 static void sev_vm_destroy(struct kvm *kvm)
1873 {
1874         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1875         struct list_head *head = &sev->regions_list;
1876         struct list_head *pos, *q;
1877 
1878         if (!sev_guest(kvm))
1879                 return;
1880 
1881         mutex_lock(&kvm->lock);
1882 
1883         /*
1884          * if userspace was terminated before unregistering the memory regions
1885          * then lets unpin all the registered memory.
1886          */
1887         if (!list_empty(head)) {
1888                 list_for_each_safe(pos, q, head) {
1889                         __unregister_enc_region_locked(kvm,
1890                                 list_entry(pos, struct enc_region, list));
1891                 }
1892         }
1893 
1894         mutex_unlock(&kvm->lock);
1895 
1896         sev_unbind_asid(kvm, sev->handle);
1897         sev_asid_free(kvm);
1898 }
1899 
1900 static void avic_vm_destroy(struct kvm *kvm)
1901 {
1902         unsigned long flags;
1903         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1904 
1905         if (!avic)
1906                 return;
1907 
1908         if (kvm_svm->avic_logical_id_table_page)
1909                 __free_page(kvm_svm->avic_logical_id_table_page);
1910         if (kvm_svm->avic_physical_id_table_page)
1911                 __free_page(kvm_svm->avic_physical_id_table_page);
1912 
1913         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1914         hash_del(&kvm_svm->hnode);
1915         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1916 }
1917 
1918 static void svm_vm_destroy(struct kvm *kvm)
1919 {
1920         avic_vm_destroy(kvm);
1921         sev_vm_destroy(kvm);
1922 }
1923 
1924 static int avic_vm_init(struct kvm *kvm)
1925 {
1926         unsigned long flags;
1927         int err = -ENOMEM;
1928         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1929         struct kvm_svm *k2;
1930         struct page *p_page;
1931         struct page *l_page;
1932         u32 vm_id;
1933 
1934         if (!avic)
1935                 return 0;
1936 
1937         /* Allocating physical APIC ID table (4KB) */
1938         p_page = alloc_page(GFP_KERNEL);
1939         if (!p_page)
1940                 goto free_avic;
1941 
1942         kvm_svm->avic_physical_id_table_page = p_page;
1943         clear_page(page_address(p_page));
1944 
1945         /* Allocating logical APIC ID table (4KB) */
1946         l_page = alloc_page(GFP_KERNEL);
1947         if (!l_page)
1948                 goto free_avic;
1949 
1950         kvm_svm->avic_logical_id_table_page = l_page;
1951         clear_page(page_address(l_page));
1952 
1953         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1954  again:
1955         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1956         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1957                 next_vm_id_wrapped = 1;
1958                 goto again;
1959         }
1960         /* Is it still in use? Only possible if wrapped at least once */
1961         if (next_vm_id_wrapped) {
1962                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1963                         if (k2->avic_vm_id == vm_id)
1964                                 goto again;
1965                 }
1966         }
1967         kvm_svm->avic_vm_id = vm_id;
1968         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1969         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1970 
1971         return 0;
1972 
1973 free_avic:
1974         avic_vm_destroy(kvm);
1975         return err;
1976 }
1977 
1978 static inline int
1979 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1980 {
1981         int ret = 0;
1982         unsigned long flags;
1983         struct amd_svm_iommu_ir *ir;
1984         struct vcpu_svm *svm = to_svm(vcpu);
1985 
1986         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1987                 return 0;
1988 
1989         /*
1990          * Here, we go through the per-vcpu ir_list to update all existing
1991          * interrupt remapping table entry targeting this vcpu.
1992          */
1993         spin_lock_irqsave(&svm->ir_list_lock, flags);
1994 
1995         if (list_empty(&svm->ir_list))
1996                 goto out;
1997 
1998         list_for_each_entry(ir, &svm->ir_list, node) {
1999                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2000                 if (ret)
2001                         break;
2002         }
2003 out:
2004         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2005         return ret;
2006 }
2007 
2008 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2009 {
2010         u64 entry;
2011         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2012         int h_physical_id = kvm_cpu_get_apicid(cpu);
2013         struct vcpu_svm *svm = to_svm(vcpu);
2014 
2015         if (!kvm_vcpu_apicv_active(vcpu))
2016                 return;
2017 
2018         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2019                 return;
2020 
2021         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2022         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2023 
2024         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2025         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2026 
2027         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2028         if (svm->avic_is_running)
2029                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2030 
2031         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2032         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2033                                         svm->avic_is_running);
2034 }
2035 
2036 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2037 {
2038         u64 entry;
2039         struct vcpu_svm *svm = to_svm(vcpu);
2040 
2041         if (!kvm_vcpu_apicv_active(vcpu))
2042                 return;
2043 
2044         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2045         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2046                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2047 
2048         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2049         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2050 }
2051 
2052 /**
2053  * This function is called during VCPU halt/unhalt.
2054  */
2055 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2056 {
2057         struct vcpu_svm *svm = to_svm(vcpu);
2058 
2059         svm->avic_is_running = is_run;
2060         if (is_run)
2061                 avic_vcpu_load(vcpu, vcpu->cpu);
2062         else
2063                 avic_vcpu_put(vcpu);
2064 }
2065 
2066 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2067 {
2068         struct vcpu_svm *svm = to_svm(vcpu);
2069         u32 dummy;
2070         u32 eax = 1;
2071 
2072         vcpu->arch.microcode_version = 0x01000065;
2073         svm->spec_ctrl = 0;
2074         svm->virt_spec_ctrl = 0;
2075 
2076         if (!init_event) {
2077                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2078                                            MSR_IA32_APICBASE_ENABLE;
2079                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2080                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2081         }
2082         init_vmcb(svm);
2083 
2084         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2085         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2086 
2087         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2088                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2089 }
2090 
2091 static int avic_init_vcpu(struct vcpu_svm *svm)
2092 {
2093         int ret;
2094 
2095         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2096                 return 0;
2097 
2098         ret = avic_init_backing_page(&svm->vcpu);
2099         if (ret)
2100                 return ret;
2101 
2102         INIT_LIST_HEAD(&svm->ir_list);
2103         spin_lock_init(&svm->ir_list_lock);
2104 
2105         return ret;
2106 }
2107 
2108 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2109 {
2110         struct vcpu_svm *svm;
2111         struct page *page;
2112         struct page *msrpm_pages;
2113         struct page *hsave_page;
2114         struct page *nested_msrpm_pages;
2115         int err;
2116 
2117         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2118         if (!svm) {
2119                 err = -ENOMEM;
2120                 goto out;
2121         }
2122 
2123         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2124         if (err)
2125                 goto free_svm;
2126 
2127         err = -ENOMEM;
2128         page = alloc_page(GFP_KERNEL);
2129         if (!page)
2130                 goto uninit;
2131 
2132         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2133         if (!msrpm_pages)
2134                 goto free_page1;
2135 
2136         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2137         if (!nested_msrpm_pages)
2138                 goto free_page2;
2139 
2140         hsave_page = alloc_page(GFP_KERNEL);
2141         if (!hsave_page)
2142                 goto free_page3;
2143 
2144         err = avic_init_vcpu(svm);
2145         if (err)
2146                 goto free_page4;
2147 
2148         /* We initialize this flag to true to make sure that the is_running
2149          * bit would be set the first time the vcpu is loaded.
2150          */
2151         svm->avic_is_running = true;
2152 
2153         svm->nested.hsave = page_address(hsave_page);
2154 
2155         svm->msrpm = page_address(msrpm_pages);
2156         svm_vcpu_init_msrpm(svm->msrpm);
2157 
2158         svm->nested.msrpm = page_address(nested_msrpm_pages);
2159         svm_vcpu_init_msrpm(svm->nested.msrpm);
2160 
2161         svm->vmcb = page_address(page);
2162         clear_page(svm->vmcb);
2163         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2164         svm->asid_generation = 0;
2165         init_vmcb(svm);
2166 
2167         svm_init_osvw(&svm->vcpu);
2168 
2169         return &svm->vcpu;
2170 
2171 free_page4:
2172         __free_page(hsave_page);
2173 free_page3:
2174         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2175 free_page2:
2176         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2177 free_page1:
2178         __free_page(page);
2179 uninit:
2180         kvm_vcpu_uninit(&svm->vcpu);
2181 free_svm:
2182         kmem_cache_free(kvm_vcpu_cache, svm);
2183 out:
2184         return ERR_PTR(err);
2185 }
2186 
2187 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2188 {
2189         struct vcpu_svm *svm = to_svm(vcpu);
2190 
2191         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2192         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2193         __free_page(virt_to_page(svm->nested.hsave));
2194         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2195         kvm_vcpu_uninit(vcpu);
2196         kmem_cache_free(kvm_vcpu_cache, svm);
2197         /*
2198          * The vmcb page can be recycled, causing a false negative in
2199          * svm_vcpu_load(). So do a full IBPB now.
2200          */
2201         indirect_branch_prediction_barrier();
2202 }
2203 
2204 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2205 {
2206         struct vcpu_svm *svm = to_svm(vcpu);
2207         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2208         int i;
2209 
2210         if (unlikely(cpu != vcpu->cpu)) {
2211                 svm->asid_generation = 0;
2212                 mark_all_dirty(svm->vmcb);
2213         }
2214 
2215 #ifdef CONFIG_X86_64
2216         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2217 #endif
2218         savesegment(fs, svm->host.fs);
2219         savesegment(gs, svm->host.gs);
2220         svm->host.ldt = kvm_read_ldt();
2221 
2222         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2223                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2224 
2225         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2226                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2227                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2228                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2229                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2230                 }
2231         }
2232         /* This assumes that the kernel never uses MSR_TSC_AUX */
2233         if (static_cpu_has(X86_FEATURE_RDTSCP))
2234                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2235 
2236         if (sd->current_vmcb != svm->vmcb) {
2237                 sd->current_vmcb = svm->vmcb;
2238                 indirect_branch_prediction_barrier();
2239         }
2240         avic_vcpu_load(vcpu, cpu);
2241 }
2242 
2243 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2244 {
2245         struct vcpu_svm *svm = to_svm(vcpu);
2246         int i;
2247 
2248         avic_vcpu_put(vcpu);
2249 
2250         ++vcpu->stat.host_state_reload;
2251         kvm_load_ldt(svm->host.ldt);
2252 #ifdef CONFIG_X86_64
2253         loadsegment(fs, svm->host.fs);
2254         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2255         load_gs_index(svm->host.gs);
2256 #else
2257 #ifdef CONFIG_X86_32_LAZY_GS
2258         loadsegment(gs, svm->host.gs);
2259 #endif
2260 #endif
2261         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2262                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2263 }
2264 
2265 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2266 {
2267         avic_set_running(vcpu, false);
2268 }
2269 
2270 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2271 {
2272         avic_set_running(vcpu, true);
2273 }
2274 
2275 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2276 {
2277         struct vcpu_svm *svm = to_svm(vcpu);
2278         unsigned long rflags = svm->vmcb->save.rflags;
2279 
2280         if (svm->nmi_singlestep) {
2281                 /* Hide our flags if they were not set by the guest */
2282                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2283                         rflags &= ~X86_EFLAGS_TF;
2284                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2285                         rflags &= ~X86_EFLAGS_RF;
2286         }
2287         return rflags;
2288 }
2289 
2290 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2291 {
2292         if (to_svm(vcpu)->nmi_singlestep)
2293                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2294 
2295        /*
2296         * Any change of EFLAGS.VM is accompanied by a reload of SS
2297         * (caused by either a task switch or an inter-privilege IRET),
2298         * so we do not need to update the CPL here.
2299         */
2300         to_svm(vcpu)->vmcb->save.rflags = rflags;
2301 }
2302 
2303 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2304 {
2305         switch (reg) {
2306         case VCPU_EXREG_PDPTR:
2307                 BUG_ON(!npt_enabled);
2308                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2309                 break;
2310         default:
2311                 BUG();
2312         }
2313 }
2314 
2315 static void svm_set_vintr(struct vcpu_svm *svm)
2316 {
2317         set_intercept(svm, INTERCEPT_VINTR);
2318 }
2319 
2320 static void svm_clear_vintr(struct vcpu_svm *svm)
2321 {
2322         clr_intercept(svm, INTERCEPT_VINTR);
2323 }
2324 
2325 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2326 {
2327         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2328 
2329         switch (seg) {
2330         case VCPU_SREG_CS: return &save->cs;
2331         case VCPU_SREG_DS: return &save->ds;
2332         case VCPU_SREG_ES: return &save->es;
2333         case VCPU_SREG_FS: return &save->fs;
2334         case VCPU_SREG_GS: return &save->gs;
2335         case VCPU_SREG_SS: return &save->ss;
2336         case VCPU_SREG_TR: return &save->tr;
2337         case VCPU_SREG_LDTR: return &save->ldtr;
2338         }
2339         BUG();
2340         return NULL;
2341 }
2342 
2343 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2344 {
2345         struct vmcb_seg *s = svm_seg(vcpu, seg);
2346 
2347         return s->base;
2348 }
2349 
2350 static void svm_get_segment(struct kvm_vcpu *vcpu,
2351                             struct kvm_segment *var, int seg)
2352 {
2353         struct vmcb_seg *s = svm_seg(vcpu, seg);
2354 
2355         var->base = s->base;
2356         var->limit = s->limit;
2357         var->selector = s->selector;
2358         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2359         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2360         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2361         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2362         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2363         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2364         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2365 
2366         /*
2367          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2368          * However, the SVM spec states that the G bit is not observed by the
2369          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2370          * So let's synthesize a legal G bit for all segments, this helps
2371          * running KVM nested. It also helps cross-vendor migration, because
2372          * Intel's vmentry has a check on the 'G' bit.
2373          */
2374         var->g = s->limit > 0xfffff;
2375 
2376         /*
2377          * AMD's VMCB does not have an explicit unusable field, so emulate it
2378          * for cross vendor migration purposes by "not present"
2379          */
2380         var->unusable = !var->present;
2381 
2382         switch (seg) {
2383         case VCPU_SREG_TR:
2384                 /*
2385                  * Work around a bug where the busy flag in the tr selector
2386                  * isn't exposed
2387                  */
2388                 var->type |= 0x2;
2389                 break;
2390         case VCPU_SREG_DS:
2391         case VCPU_SREG_ES:
2392         case VCPU_SREG_FS:
2393         case VCPU_SREG_GS:
2394                 /*
2395                  * The accessed bit must always be set in the segment
2396                  * descriptor cache, although it can be cleared in the
2397                  * descriptor, the cached bit always remains at 1. Since
2398                  * Intel has a check on this, set it here to support
2399                  * cross-vendor migration.
2400                  */
2401                 if (!var->unusable)
2402                         var->type |= 0x1;
2403                 break;
2404         case VCPU_SREG_SS:
2405                 /*
2406                  * On AMD CPUs sometimes the DB bit in the segment
2407                  * descriptor is left as 1, although the whole segment has
2408                  * been made unusable. Clear it here to pass an Intel VMX
2409                  * entry check when cross vendor migrating.
2410                  */
2411                 if (var->unusable)
2412                         var->db = 0;
2413                 /* This is symmetric with svm_set_segment() */
2414                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2415                 break;
2416         }
2417 }
2418 
2419 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2420 {
2421         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2422 
2423         return save->cpl;
2424 }
2425 
2426 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2427 {
2428         struct vcpu_svm *svm = to_svm(vcpu);
2429 
2430         dt->size = svm->vmcb->save.idtr.limit;
2431         dt->address = svm->vmcb->save.idtr.base;
2432 }
2433 
2434 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2435 {
2436         struct vcpu_svm *svm = to_svm(vcpu);
2437 
2438         svm->vmcb->save.idtr.limit = dt->size;
2439         svm->vmcb->save.idtr.base = dt->address ;
2440         mark_dirty(svm->vmcb, VMCB_DT);
2441 }
2442 
2443 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2444 {
2445         struct vcpu_svm *svm = to_svm(vcpu);
2446 
2447         dt->size = svm->vmcb->save.gdtr.limit;
2448         dt->address = svm->vmcb->save.gdtr.base;
2449 }
2450 
2451 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2452 {
2453         struct vcpu_svm *svm = to_svm(vcpu);
2454 
2455         svm->vmcb->save.gdtr.limit = dt->size;
2456         svm->vmcb->save.gdtr.base = dt->address ;
2457         mark_dirty(svm->vmcb, VMCB_DT);
2458 }
2459 
2460 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2461 {
2462 }
2463 
2464 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2465 {
2466 }
2467 
2468 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2469 {
2470 }
2471 
2472 static void update_cr0_intercept(struct vcpu_svm *svm)
2473 {
2474         ulong gcr0 = svm->vcpu.arch.cr0;
2475         u64 *hcr0 = &svm->vmcb->save.cr0;
2476 
2477         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2478                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2479 
2480         mark_dirty(svm->vmcb, VMCB_CR);
2481 
2482         if (gcr0 == *hcr0) {
2483                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2484                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2485         } else {
2486                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2487                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2488         }
2489 }
2490 
2491 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2492 {
2493         struct vcpu_svm *svm = to_svm(vcpu);
2494 
2495 #ifdef CONFIG_X86_64
2496         if (vcpu->arch.efer & EFER_LME) {
2497                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2498                         vcpu->arch.efer |= EFER_LMA;
2499                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2500                 }
2501 
2502                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2503                         vcpu->arch.efer &= ~EFER_LMA;
2504                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2505                 }
2506         }
2507 #endif
2508         vcpu->arch.cr0 = cr0;
2509 
2510         if (!npt_enabled)
2511                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2512 
2513         /*
2514          * re-enable caching here because the QEMU bios
2515          * does not do it - this results in some delay at
2516          * reboot
2517          */
2518         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2519                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2520         svm->vmcb->save.cr0 = cr0;
2521         mark_dirty(svm->vmcb, VMCB_CR);
2522         update_cr0_intercept(svm);
2523 }
2524 
2525 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2526 {
2527         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2528         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2529 
2530         if (cr4 & X86_CR4_VMXE)
2531                 return 1;
2532 
2533         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2534                 svm_flush_tlb(vcpu, true);
2535 
2536         vcpu->arch.cr4 = cr4;
2537         if (!npt_enabled)
2538                 cr4 |= X86_CR4_PAE;
2539         cr4 |= host_cr4_mce;
2540         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2541         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2542         return 0;
2543 }
2544 
2545 static void svm_set_segment(struct kvm_vcpu *vcpu,
2546                             struct kvm_segment *var, int seg)
2547 {
2548         struct vcpu_svm *svm = to_svm(vcpu);
2549         struct vmcb_seg *s = svm_seg(vcpu, seg);
2550 
2551         s->base = var->base;
2552         s->limit = var->limit;
2553         s->selector = var->selector;
2554         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2555         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2556         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2557         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2558         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2559         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2560         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2561         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2562 
2563         /*
2564          * This is always accurate, except if SYSRET returned to a segment
2565          * with SS.DPL != 3.  Intel does not have this quirk, and always
2566          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2567          * would entail passing the CPL to userspace and back.
2568          */
2569         if (seg == VCPU_SREG_SS)
2570                 /* This is symmetric with svm_get_segment() */
2571                 svm->vmcb->save.cpl = (var->dpl & 3);
2572 
2573         mark_dirty(svm->vmcb, VMCB_SEG);
2574 }
2575 
2576 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2577 {
2578         struct vcpu_svm *svm = to_svm(vcpu);
2579 
2580         clr_exception_intercept(svm, BP_VECTOR);
2581 
2582         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2583                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2584                         set_exception_intercept(svm, BP_VECTOR);
2585         } else
2586                 vcpu->guest_debug = 0;
2587 }
2588 
2589 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2590 {
2591         if (sd->next_asid > sd->max_asid) {
2592                 ++sd->asid_generation;
2593                 sd->next_asid = sd->min_asid;
2594                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2595         }
2596 
2597         svm->asid_generation = sd->asid_generation;
2598         svm->vmcb->control.asid = sd->next_asid++;
2599 
2600         mark_dirty(svm->vmcb, VMCB_ASID);
2601 }
2602 
2603 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2604 {
2605         return to_svm(vcpu)->vmcb->save.dr6;
2606 }
2607 
2608 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2609 {
2610         struct vcpu_svm *svm = to_svm(vcpu);
2611 
2612         svm->vmcb->save.dr6 = value;
2613         mark_dirty(svm->vmcb, VMCB_DR);
2614 }
2615 
2616 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2617 {
2618         struct vcpu_svm *svm = to_svm(vcpu);
2619 
2620         get_debugreg(vcpu->arch.db[0], 0);
2621         get_debugreg(vcpu->arch.db[1], 1);
2622         get_debugreg(vcpu->arch.db[2], 2);
2623         get_debugreg(vcpu->arch.db[3], 3);
2624         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2625         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2626 
2627         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2628         set_dr_intercepts(svm);
2629 }
2630 
2631 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2632 {
2633         struct vcpu_svm *svm = to_svm(vcpu);
2634 
2635         svm->vmcb->save.dr7 = value;
2636         mark_dirty(svm->vmcb, VMCB_DR);
2637 }
2638 
2639 static int pf_interception(struct vcpu_svm *svm)
2640 {
2641         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2642         u64 error_code = svm->vmcb->control.exit_info_1;
2643 
2644         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2645                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2646                         svm->vmcb->control.insn_bytes : NULL,
2647                         svm->vmcb->control.insn_len);
2648 }
2649 
2650 static int npf_interception(struct vcpu_svm *svm)
2651 {
2652         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2653         u64 error_code = svm->vmcb->control.exit_info_1;
2654 
2655         trace_kvm_page_fault(fault_address, error_code);
2656         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2657                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2658                         svm->vmcb->control.insn_bytes : NULL,
2659                         svm->vmcb->control.insn_len);
2660 }
2661 
2662 static int db_interception(struct vcpu_svm *svm)
2663 {
2664         struct kvm_run *kvm_run = svm->vcpu.run;
2665 
2666         if (!(svm->vcpu.guest_debug &
2667               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2668                 !svm->nmi_singlestep) {
2669                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2670                 return 1;
2671         }
2672 
2673         if (svm->nmi_singlestep) {
2674                 disable_nmi_singlestep(svm);
2675         }
2676 
2677         if (svm->vcpu.guest_debug &
2678             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2679                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2680                 kvm_run->debug.arch.pc =
2681                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2682                 kvm_run->debug.arch.exception = DB_VECTOR;
2683                 return 0;
2684         }
2685 
2686         return 1;
2687 }
2688 
2689 static int bp_interception(struct vcpu_svm *svm)
2690 {
2691         struct kvm_run *kvm_run = svm->vcpu.run;
2692 
2693         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2694         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2695         kvm_run->debug.arch.exception = BP_VECTOR;
2696         return 0;
2697 }
2698 
2699 static int ud_interception(struct vcpu_svm *svm)
2700 {
2701         return handle_ud(&svm->vcpu);
2702 }
2703 
2704 static int ac_interception(struct vcpu_svm *svm)
2705 {
2706         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2707         return 1;
2708 }
2709 
2710 static int gp_interception(struct vcpu_svm *svm)
2711 {
2712         struct kvm_vcpu *vcpu = &svm->vcpu;
2713         u32 error_code = svm->vmcb->control.exit_info_1;
2714         int er;
2715 
2716         WARN_ON_ONCE(!enable_vmware_backdoor);
2717 
2718         er = emulate_instruction(vcpu,
2719                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2720         if (er == EMULATE_USER_EXIT)
2721                 return 0;
2722         else if (er != EMULATE_DONE)
2723                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2724         return 1;
2725 }
2726 
2727 static bool is_erratum_383(void)
2728 {
2729         int err, i;
2730         u64 value;
2731 
2732         if (!erratum_383_found)
2733                 return false;
2734 
2735         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2736         if (err)
2737                 return false;
2738 
2739         /* Bit 62 may or may not be set for this mce */
2740         value &= ~(1ULL << 62);
2741 
2742         if (value != 0xb600000000010015ULL)
2743                 return false;
2744 
2745         /* Clear MCi_STATUS registers */
2746         for (i = 0; i < 6; ++i)
2747                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2748 
2749         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2750         if (!err) {
2751                 u32 low, high;
2752 
2753                 value &= ~(1ULL << 2);
2754                 low    = lower_32_bits(value);
2755                 high   = upper_32_bits(value);
2756 
2757                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2758         }
2759 
2760         /* Flush tlb to evict multi-match entries */
2761         __flush_tlb_all();
2762 
2763         return true;
2764 }
2765 
2766 static void svm_handle_mce(struct vcpu_svm *svm)
2767 {
2768         if (is_erratum_383()) {
2769                 /*
2770                  * Erratum 383 triggered. Guest state is corrupt so kill the
2771                  * guest.
2772                  */
2773                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2774 
2775                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2776 
2777                 return;
2778         }
2779 
2780         /*
2781          * On an #MC intercept the MCE handler is not called automatically in
2782          * the host. So do it by hand here.
2783          */
2784         asm volatile (
2785                 "int $0x12\n");
2786         /* not sure if we ever come back to this point */
2787 
2788         return;
2789 }
2790 
2791 static int mc_interception(struct vcpu_svm *svm)
2792 {
2793         return 1;
2794 }
2795 
2796 static int shutdown_interception(struct vcpu_svm *svm)
2797 {
2798         struct kvm_run *kvm_run = svm->vcpu.run;
2799 
2800         /*
2801          * VMCB is undefined after a SHUTDOWN intercept
2802          * so reinitialize it.
2803          */
2804         clear_page(svm->vmcb);
2805         init_vmcb(svm);
2806 
2807         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2808         return 0;
2809 }
2810 
2811 static int io_interception(struct vcpu_svm *svm)
2812 {
2813         struct kvm_vcpu *vcpu = &svm->vcpu;
2814         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2815         int size, in, string;
2816         unsigned port;
2817 
2818         ++svm->vcpu.stat.io_exits;
2819         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2820         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2821         if (string)
2822                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2823 
2824         port = io_info >> 16;
2825         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2826         svm->next_rip = svm->vmcb->control.exit_info_2;
2827 
2828         return kvm_fast_pio(&svm->vcpu, size, port, in);
2829 }
2830 
2831 static int nmi_interception(struct vcpu_svm *svm)
2832 {
2833         return 1;
2834 }
2835 
2836 static int intr_interception(struct vcpu_svm *svm)
2837 {
2838         ++svm->vcpu.stat.irq_exits;
2839         return 1;
2840 }
2841 
2842 static int nop_on_interception(struct vcpu_svm *svm)
2843 {
2844         return 1;
2845 }
2846 
2847 static int halt_interception(struct vcpu_svm *svm)
2848 {
2849         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2850         return kvm_emulate_halt(&svm->vcpu);
2851 }
2852 
2853 static int vmmcall_interception(struct vcpu_svm *svm)
2854 {
2855         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2856         return kvm_emulate_hypercall(&svm->vcpu);
2857 }
2858 
2859 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2860 {
2861         struct vcpu_svm *svm = to_svm(vcpu);
2862 
2863         return svm->nested.nested_cr3;
2864 }
2865 
2866 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2867 {
2868         struct vcpu_svm *svm = to_svm(vcpu);
2869         u64 cr3 = svm->nested.nested_cr3;
2870         u64 pdpte;
2871         int ret;
2872 
2873         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2874                                        offset_in_page(cr3) + index * 8, 8);
2875         if (ret)
2876                 return 0;
2877         return pdpte;
2878 }
2879 
2880 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2881                                    unsigned long root)
2882 {
2883         struct vcpu_svm *svm = to_svm(vcpu);
2884 
2885         svm->vmcb->control.nested_cr3 = __sme_set(root);
2886         mark_dirty(svm->vmcb, VMCB_NPT);
2887         svm_flush_tlb(vcpu, true);
2888 }
2889 
2890 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2891                                        struct x86_exception *fault)
2892 {
2893         struct vcpu_svm *svm = to_svm(vcpu);
2894 
2895         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2896                 /*
2897                  * TODO: track the cause of the nested page fault, and
2898                  * correctly fill in the high bits of exit_info_1.
2899                  */
2900                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2901                 svm->vmcb->control.exit_code_hi = 0;
2902                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2903                 svm->vmcb->control.exit_info_2 = fault->address;
2904         }
2905 
2906         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2907         svm->vmcb->control.exit_info_1 |= fault->error_code;
2908 
2909         /*
2910          * The present bit is always zero for page structure faults on real
2911          * hardware.
2912          */
2913         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2914                 svm->vmcb->control.exit_info_1 &= ~1;
2915 
2916         nested_svm_vmexit(svm);
2917 }
2918 
2919 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2920 {
2921         WARN_ON(mmu_is_nested(vcpu));
2922         kvm_init_shadow_mmu(vcpu);
2923         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2924         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2925         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2926         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2927         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2928         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2929         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2930 }
2931 
2932 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2933 {
2934         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2935 }
2936 
2937 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2938 {
2939         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2940             !is_paging(&svm->vcpu)) {
2941                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2942                 return 1;
2943         }
2944 
2945         if (svm->vmcb->save.cpl) {
2946                 kvm_inject_gp(&svm->vcpu, 0);
2947                 return 1;
2948         }
2949 
2950         return 0;
2951 }
2952 
2953 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2954                                       bool has_error_code, u32 error_code)
2955 {
2956         int vmexit;
2957 
2958         if (!is_guest_mode(&svm->vcpu))
2959                 return 0;
2960 
2961         vmexit = nested_svm_intercept(svm);
2962         if (vmexit != NESTED_EXIT_DONE)
2963                 return 0;
2964 
2965         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2966         svm->vmcb->control.exit_code_hi = 0;
2967         svm->vmcb->control.exit_info_1 = error_code;
2968 
2969         /*
2970          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2971          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2972          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2973          * written only when inject_pending_event runs (DR6 would written here
2974          * too).  This should be conditional on a new capability---if the
2975          * capability is disabled, kvm_multiple_exception would write the
2976          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2977          */
2978         if (svm->vcpu.arch.exception.nested_apf)
2979                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2980         else
2981                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2982 
2983         svm->nested.exit_required = true;
2984         return vmexit;
2985 }
2986 
2987 /* This function returns true if it is save to enable the irq window */
2988 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2989 {
2990         if (!is_guest_mode(&svm->vcpu))
2991                 return true;
2992 
2993         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2994                 return true;
2995 
2996         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2997                 return false;
2998 
2999         /*
3000          * if vmexit was already requested (by intercepted exception
3001          * for instance) do not overwrite it with "external interrupt"
3002          * vmexit.
3003          */
3004         if (svm->nested.exit_required)
3005                 return false;
3006 
3007         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3008         svm->vmcb->control.exit_info_1 = 0;
3009         svm->vmcb->control.exit_info_2 = 0;
3010 
3011         if (svm->nested.intercept & 1ULL) {
3012                 /*
3013                  * The #vmexit can't be emulated here directly because this
3014                  * code path runs with irqs and preemption disabled. A
3015                  * #vmexit emulation might sleep. Only signal request for
3016                  * the #vmexit here.
3017                  */
3018                 svm->nested.exit_required = true;
3019                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3020                 return false;
3021         }
3022 
3023         return true;
3024 }
3025 
3026 /* This function returns true if it is save to enable the nmi window */
3027 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3028 {
3029         if (!is_guest_mode(&svm->vcpu))
3030                 return true;
3031 
3032         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3033                 return true;
3034 
3035         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3036         svm->nested.exit_required = true;
3037 
3038         return false;
3039 }
3040 
3041 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3042 {
3043         struct page *page;
3044 
3045         might_sleep();
3046 
3047         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3048         if (is_error_page(page))
3049                 goto error;
3050 
3051         *_page = page;
3052 
3053         return kmap(page);
3054 
3055 error:
3056         kvm_inject_gp(&svm->vcpu, 0);
3057 
3058         return NULL;
3059 }
3060 
3061 static void nested_svm_unmap(struct page *page)
3062 {
3063         kunmap(page);
3064         kvm_release_page_dirty(page);
3065 }
3066 
3067 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3068 {
3069         unsigned port, size, iopm_len;
3070         u16 val, mask;
3071         u8 start_bit;
3072         u64 gpa;
3073 
3074         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3075                 return NESTED_EXIT_HOST;
3076 
3077         port = svm->vmcb->control.exit_info_1 >> 16;
3078         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3079                 SVM_IOIO_SIZE_SHIFT;
3080         gpa  = svm->nested.vmcb_iopm + (port / 8);
3081         start_bit = port % 8;
3082         iopm_len = (start_bit + size > 8) ? 2 : 1;
3083         mask = (0xf >> (4 - size)) << start_bit;
3084         val = 0;
3085 
3086         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3087                 return NESTED_EXIT_DONE;
3088 
3089         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3090 }
3091 
3092 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3093 {
3094         u32 offset, msr, value;
3095         int write, mask;
3096 
3097         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3098                 return NESTED_EXIT_HOST;
3099 
3100         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3101         offset = svm_msrpm_offset(msr);
3102         write  = svm->vmcb->control.exit_info_1 & 1;
3103         mask   = 1 << ((2 * (msr & 0xf)) + write);
3104 
3105         if (offset == MSR_INVALID)
3106                 return NESTED_EXIT_DONE;
3107 
3108         /* Offset is in 32 bit units but need in 8 bit units */
3109         offset *= 4;
3110 
3111         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3112                 return NESTED_EXIT_DONE;
3113 
3114         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3115 }
3116 
3117 /* DB exceptions for our internal use must not cause vmexit */
3118 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3119 {
3120         unsigned long dr6;
3121 
3122         /* if we're not singlestepping, it's not ours */
3123         if (!svm->nmi_singlestep)
3124                 return NESTED_EXIT_DONE;
3125 
3126         /* if it's not a singlestep exception, it's not ours */
3127         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3128                 return NESTED_EXIT_DONE;
3129         if (!(dr6 & DR6_BS))
3130                 return NESTED_EXIT_DONE;
3131 
3132         /* if the guest is singlestepping, it should get the vmexit */
3133         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3134                 disable_nmi_singlestep(svm);
3135                 return NESTED_EXIT_DONE;
3136         }
3137 
3138         /* it's ours, the nested hypervisor must not see this one */
3139         return NESTED_EXIT_HOST;
3140 }
3141 
3142 static int nested_svm_exit_special(struct vcpu_svm *svm)
3143 {
3144         u32 exit_code = svm->vmcb->control.exit_code;
3145 
3146         switch (exit_code) {
3147         case SVM_EXIT_INTR:
3148         case SVM_EXIT_NMI:
3149         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3150                 return NESTED_EXIT_HOST;
3151         case SVM_EXIT_NPF:
3152                 /* For now we are always handling NPFs when using them */
3153                 if (npt_enabled)
3154                         return NESTED_EXIT_HOST;
3155                 break;
3156         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3157                 /* When we're shadowing, trap PFs, but not async PF */
3158                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3159                         return NESTED_EXIT_HOST;
3160                 break;
3161         default:
3162                 break;
3163         }
3164 
3165         return NESTED_EXIT_CONTINUE;
3166 }
3167 
3168 /*
3169  * If this function returns true, this #vmexit was already handled
3170  */
3171 static int nested_svm_intercept(struct vcpu_svm *svm)
3172 {
3173         u32 exit_code = svm->vmcb->control.exit_code;
3174         int vmexit = NESTED_EXIT_HOST;
3175 
3176         switch (exit_code) {
3177         case SVM_EXIT_MSR:
3178                 vmexit = nested_svm_exit_handled_msr(svm);
3179                 break;
3180         case SVM_EXIT_IOIO:
3181                 vmexit = nested_svm_intercept_ioio(svm);
3182                 break;
3183         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3184                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3185                 if (svm->nested.intercept_cr & bit)
3186                         vmexit = NESTED_EXIT_DONE;
3187                 break;
3188         }
3189         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3190                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3191                 if (svm->nested.intercept_dr & bit)
3192                         vmexit = NESTED_EXIT_DONE;
3193                 break;
3194         }
3195         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3196                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3197                 if (svm->nested.intercept_exceptions & excp_bits) {
3198                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3199                                 vmexit = nested_svm_intercept_db(svm);
3200                         else
3201                                 vmexit = NESTED_EXIT_DONE;
3202                 }
3203                 /* async page fault always cause vmexit */
3204                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3205                          svm->vcpu.arch.exception.nested_apf != 0)
3206                         vmexit = NESTED_EXIT_DONE;
3207                 break;
3208         }
3209         case SVM_EXIT_ERR: {
3210                 vmexit = NESTED_EXIT_DONE;
3211                 break;
3212         }
3213         default: {
3214                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3215                 if (svm->nested.intercept & exit_bits)
3216                         vmexit = NESTED_EXIT_DONE;
3217         }
3218         }
3219 
3220         return vmexit;
3221 }
3222 
3223 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3224 {
3225         int vmexit;
3226 
3227         vmexit = nested_svm_intercept(svm);
3228 
3229         if (vmexit == NESTED_EXIT_DONE)
3230                 nested_svm_vmexit(svm);
3231 
3232         return vmexit;
3233 }
3234 
3235 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3236 {
3237         struct vmcb_control_area *dst  = &dst_vmcb->control;
3238         struct vmcb_control_area *from = &from_vmcb->control;
3239 
3240         dst->intercept_cr         = from->intercept_cr;
3241         dst->intercept_dr         = from->intercept_dr;
3242         dst->intercept_exceptions = from->intercept_exceptions;
3243         dst->intercept            = from->intercept;
3244         dst->iopm_base_pa         = from->iopm_base_pa;
3245         dst->msrpm_base_pa        = from->msrpm_base_pa;
3246         dst->tsc_offset           = from->tsc_offset;
3247         dst->asid                 = from->asid;
3248         dst->tlb_ctl              = from->tlb_ctl;
3249         dst->int_ctl              = from->int_ctl;
3250         dst->int_vector           = from->int_vector;
3251         dst->int_state            = from->int_state;
3252         dst->exit_code            = from->exit_code;
3253         dst->exit_code_hi         = from->exit_code_hi;
3254         dst->exit_info_1          = from->exit_info_1;
3255         dst->exit_info_2          = from->exit_info_2;
3256         dst->exit_int_info        = from->exit_int_info;
3257         dst->exit_int_info_err    = from->exit_int_info_err;
3258         dst->nested_ctl           = from->nested_ctl;
3259         dst->event_inj            = from->event_inj;
3260         dst->event_inj_err        = from->event_inj_err;
3261         dst->nested_cr3           = from->nested_cr3;
3262         dst->virt_ext              = from->virt_ext;
3263 }
3264 
3265 static int nested_svm_vmexit(struct vcpu_svm *svm)
3266 {
3267         struct vmcb *nested_vmcb;
3268         struct vmcb *hsave = svm->nested.hsave;
3269         struct vmcb *vmcb = svm->vmcb;
3270         struct page *page;
3271 
3272         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3273                                        vmcb->control.exit_info_1,
3274                                        vmcb->control.exit_info_2,
3275                                        vmcb->control.exit_int_info,
3276                                        vmcb->control.exit_int_info_err,
3277                                        KVM_ISA_SVM);
3278 
3279         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3280         if (!nested_vmcb)
3281                 return 1;
3282 
3283         /* Exit Guest-Mode */
3284         leave_guest_mode(&svm->vcpu);
3285         svm->nested.vmcb = 0;
3286 
3287         /* Give the current vmcb to the guest */
3288         disable_gif(svm);
3289 
3290         nested_vmcb->save.es     = vmcb->save.es;
3291         nested_vmcb->save.cs     = vmcb->save.cs;
3292         nested_vmcb->save.ss     = vmcb->save.ss;
3293         nested_vmcb->save.ds     = vmcb->save.ds;
3294         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3295         nested_vmcb->save.idtr   = vmcb->save.idtr;
3296         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3297         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3298         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3299         nested_vmcb->save.cr2    = vmcb->save.cr2;
3300         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3301         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3302         nested_vmcb->save.rip    = vmcb->save.rip;
3303         nested_vmcb->save.rsp    = vmcb->save.rsp;
3304         nested_vmcb->save.rax    = vmcb->save.rax;
3305         nested_vmcb->save.dr7    = vmcb->save.dr7;
3306         nested_vmcb->save.dr6    = vmcb->save.dr6;
3307         nested_vmcb->save.cpl    = vmcb->save.cpl;
3308 
3309         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3310         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3311         nested_vmcb->control.int_state         = vmcb->control.int_state;
3312         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3313         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3314         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3315         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3316         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3317         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3318 
3319         if (svm->nrips_enabled)
3320                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3321 
3322         /*
3323          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3324          * to make sure that we do not lose injected events. So check event_inj
3325          * here and copy it to exit_int_info if it is valid.
3326          * Exit_int_info and event_inj can't be both valid because the case
3327          * below only happens on a VMRUN instruction intercept which has
3328          * no valid exit_int_info set.
3329          */
3330         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3331                 struct vmcb_control_area *nc = &nested_vmcb->control;
3332 
3333                 nc->exit_int_info     = vmcb->control.event_inj;
3334                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3335         }
3336 
3337         nested_vmcb->control.tlb_ctl           = 0;
3338         nested_vmcb->control.event_inj         = 0;
3339         nested_vmcb->control.event_inj_err     = 0;
3340 
3341         /* We always set V_INTR_MASKING and remember the old value in hflags */
3342         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3343                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3344 
3345         /* Restore the original control entries */
3346         copy_vmcb_control_area(vmcb, hsave);
3347 
3348         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3349         kvm_clear_exception_queue(&svm->vcpu);
3350         kvm_clear_interrupt_queue(&svm->vcpu);
3351 
3352         svm->nested.nested_cr3 = 0;
3353 
3354         /* Restore selected save entries */
3355         svm->vmcb->save.es = hsave->save.es;
3356         svm->vmcb->save.cs = hsave->save.cs;
3357         svm->vmcb->save.ss = hsave->save.ss;
3358         svm->vmcb->save.ds = hsave->save.ds;
3359         svm->vmcb->save.gdtr = hsave->save.gdtr;
3360         svm->vmcb->save.idtr = hsave->save.idtr;
3361         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3362         svm_set_efer(&svm->vcpu, hsave->save.efer);
3363         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3364         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3365         if (npt_enabled) {
3366                 svm->vmcb->save.cr3 = hsave->save.cr3;
3367                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3368         } else {
3369                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3370         }
3371         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3372         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3373         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3374         svm->vmcb->save.dr7 = 0;
3375         svm->vmcb->save.cpl = 0;
3376         svm->vmcb->control.exit_int_info = 0;
3377 
3378         mark_all_dirty(svm->vmcb);
3379 
3380         nested_svm_unmap(page);
3381 
3382         nested_svm_uninit_mmu_context(&svm->vcpu);
3383         kvm_mmu_reset_context(&svm->vcpu);
3384         kvm_mmu_load(&svm->vcpu);
3385 
3386         return 0;
3387 }
3388 
3389 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3390 {
3391         /*
3392          * This function merges the msr permission bitmaps of kvm and the
3393          * nested vmcb. It is optimized in that it only merges the parts where
3394          * the kvm msr permission bitmap may contain zero bits
3395          */
3396         int i;
3397 
3398         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3399                 return true;
3400 
3401         for (i = 0; i < MSRPM_OFFSETS; i++) {
3402                 u32 value, p;
3403                 u64 offset;
3404 
3405                 if (msrpm_offsets[i] == 0xffffffff)
3406                         break;
3407 
3408                 p      = msrpm_offsets[i];
3409                 offset = svm->nested.vmcb_msrpm + (p * 4);
3410 
3411                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3412                         return false;
3413 
3414                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3415         }
3416 
3417         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3418 
3419         return true;
3420 }
3421 
3422 static bool nested_vmcb_checks(struct vmcb *vmcb)
3423 {
3424         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3425                 return false;
3426 
3427         if (vmcb->control.asid == 0)
3428                 return false;
3429 
3430         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3431             !npt_enabled)
3432                 return false;
3433 
3434         return true;
3435 }
3436 
3437 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3438                                  struct vmcb *nested_vmcb, struct page *page)
3439 {
3440         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3441                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3442         else
3443                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3444 
3445         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3446                 kvm_mmu_unload(&svm->vcpu);
3447                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3448                 nested_svm_init_mmu_context(&svm->vcpu);
3449         }
3450 
3451         /* Load the nested guest state */
3452         svm->vmcb->save.es = nested_vmcb->save.es;
3453         svm->vmcb->save.cs = nested_vmcb->save.cs;
3454         svm->vmcb->save.ss = nested_vmcb->save.ss;
3455         svm->vmcb->save.ds = nested_vmcb->save.ds;
3456         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3457         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3458         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3459         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3460         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3461         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3462         if (npt_enabled) {
3463                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3464                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3465         } else
3466                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3467 
3468         /* Guest paging mode is active - reset mmu */
3469         kvm_mmu_reset_context(&svm->vcpu);
3470 
3471         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3472         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3473         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3474         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3475 
3476         /* In case we don't even reach vcpu_run, the fields are not updated */
3477         svm->vmcb->save.rax = nested_vmcb->save.rax;
3478         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3479         svm->vmcb->save.rip = nested_vmcb->save.rip;
3480         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3481         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3482         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3483 
3484         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3485         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3486 
3487         /* cache intercepts */
3488         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3489         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3490         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3491         svm->nested.intercept            = nested_vmcb->control.intercept;
3492 
3493         svm_flush_tlb(&svm->vcpu, true);
3494         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3495         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3496                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3497         else
3498                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3499 
3500         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3501                 /* We only want the cr8 intercept bits of the guest */
3502                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3503                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3504         }
3505 
3506         /* We don't want to see VMMCALLs from a nested guest */
3507         clr_intercept(svm, INTERCEPT_VMMCALL);
3508 
3509         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3510         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3511 
3512         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3513         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3514         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3515         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3516         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3517 
3518         nested_svm_unmap(page);
3519 
3520         /* Enter Guest-Mode */
3521         enter_guest_mode(&svm->vcpu);
3522 
3523         /*
3524          * Merge guest and host intercepts - must be called  with vcpu in
3525          * guest-mode to take affect here
3526          */
3527         recalc_intercepts(svm);
3528 
3529         svm->nested.vmcb = vmcb_gpa;
3530 
3531         enable_gif(svm);
3532 
3533         mark_all_dirty(svm->vmcb);
3534 }
3535 
3536 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3537 {
3538         struct vmcb *nested_vmcb;
3539         struct vmcb *hsave = svm->nested.hsave;
3540         struct vmcb *vmcb = svm->vmcb;
3541         struct page *page;
3542         u64 vmcb_gpa;
3543 
3544         vmcb_gpa = svm->vmcb->save.rax;
3545 
3546         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3547         if (!nested_vmcb)
3548                 return false;
3549 
3550         if (!nested_vmcb_checks(nested_vmcb)) {
3551                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3552                 nested_vmcb->control.exit_code_hi = 0;
3553                 nested_vmcb->control.exit_info_1  = 0;
3554                 nested_vmcb->control.exit_info_2  = 0;
3555 
3556                 nested_svm_unmap(page);
3557 
3558                 return false;
3559         }
3560 
3561         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3562                                nested_vmcb->save.rip,
3563                                nested_vmcb->control.int_ctl,
3564                                nested_vmcb->control.event_inj,
3565                                nested_vmcb->control.nested_ctl);
3566 
3567         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3568                                     nested_vmcb->control.intercept_cr >> 16,
3569                                     nested_vmcb->control.intercept_exceptions,
3570                                     nested_vmcb->control.intercept);
3571 
3572         /* Clear internal status */
3573         kvm_clear_exception_queue(&svm->vcpu);
3574         kvm_clear_interrupt_queue(&svm->vcpu);
3575 
3576         /*
3577          * Save the old vmcb, so we don't need to pick what we save, but can
3578          * restore everything when a VMEXIT occurs
3579          */
3580         hsave->save.es     = vmcb->save.es;
3581         hsave->save.cs     = vmcb->save.cs;
3582         hsave->save.ss     = vmcb->save.ss;
3583         hsave->save.ds     = vmcb->save.ds;
3584         hsave->save.gdtr   = vmcb->save.gdtr;
3585         hsave->save.idtr   = vmcb->save.idtr;
3586         hsave->save.efer   = svm->vcpu.arch.efer;
3587         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3588         hsave->save.cr4    = svm->vcpu.arch.cr4;
3589         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3590         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3591         hsave->save.rsp    = vmcb->save.rsp;
3592         hsave->save.rax    = vmcb->save.rax;
3593         if (npt_enabled)
3594                 hsave->save.cr3    = vmcb->save.cr3;
3595         else
3596                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3597 
3598         copy_vmcb_control_area(hsave, vmcb);
3599 
3600         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3601 
3602         return true;
3603 }
3604 
3605 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3606 {
3607         to_vmcb->save.fs = from_vmcb->save.fs;
3608         to_vmcb->save.gs = from_vmcb->save.gs;
3609         to_vmcb->save.tr = from_vmcb->save.tr;
3610         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3611         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3612         to_vmcb->save.star = from_vmcb->save.star;
3613         to_vmcb->save.lstar = from_vmcb->save.lstar;
3614         to_vmcb->save.cstar = from_vmcb->save.cstar;
3615         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3616         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3617         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3618         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3619 }
3620 
3621 static int vmload_interception(struct vcpu_svm *svm)
3622 {
3623         struct vmcb *nested_vmcb;
3624         struct page *page;
3625         int ret;
3626 
3627         if (nested_svm_check_permissions(svm))
3628                 return 1;
3629 
3630         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3631         if (!nested_vmcb)
3632                 return 1;
3633 
3634         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3635         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3636 
3637         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3638         nested_svm_unmap(page);
3639 
3640         return ret;
3641 }
3642 
3643 static int vmsave_interception(struct vcpu_svm *svm)
3644 {
3645         struct vmcb *nested_vmcb;
3646         struct page *page;
3647         int ret;
3648 
3649         if (nested_svm_check_permissions(svm))
3650                 return 1;
3651 
3652         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3653         if (!nested_vmcb)
3654                 return 1;
3655 
3656         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3657         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3658 
3659         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3660         nested_svm_unmap(page);
3661 
3662         return ret;
3663 }
3664 
3665 static int vmrun_interception(struct vcpu_svm *svm)
3666 {
3667         if (nested_svm_check_permissions(svm))
3668                 return 1;
3669 
3670         /* Save rip after vmrun instruction */
3671         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3672 
3673         if (!nested_svm_vmrun(svm))
3674                 return 1;
3675 
3676         if (!nested_svm_vmrun_msrpm(svm))
3677                 goto failed;
3678 
3679         return 1;
3680 
3681 failed:
3682 
3683         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3684         svm->vmcb->control.exit_code_hi = 0;
3685         svm->vmcb->control.exit_info_1  = 0;
3686         svm->vmcb->control.exit_info_2  = 0;
3687 
3688         nested_svm_vmexit(svm);
3689 
3690         return 1;
3691 }
3692 
3693 static int stgi_interception(struct vcpu_svm *svm)
3694 {
3695         int ret;
3696 
3697         if (nested_svm_check_permissions(svm))
3698                 return 1;
3699 
3700         /*
3701          * If VGIF is enabled, the STGI intercept is only added to
3702          * detect the opening of the SMI/NMI window; remove it now.
3703          */
3704         if (vgif_enabled(svm))
3705                 clr_intercept(svm, INTERCEPT_STGI);
3706 
3707         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3708         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3709         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3710 
3711         enable_gif(svm);
3712 
3713         return ret;
3714 }
3715 
3716 static int clgi_interception(struct vcpu_svm *svm)
3717 {
3718         int ret;
3719 
3720         if (nested_svm_check_permissions(svm))
3721                 return 1;
3722 
3723         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3724         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3725 
3726         disable_gif(svm);
3727 
3728         /* After a CLGI no interrupts should come */
3729         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3730                 svm_clear_vintr(svm);
3731                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3732                 mark_dirty(svm->vmcb, VMCB_INTR);
3733         }
3734 
3735         return ret;
3736 }
3737 
3738 static int invlpga_interception(struct vcpu_svm *svm)
3739 {
3740         struct kvm_vcpu *vcpu = &svm->vcpu;
3741 
3742         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3743                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3744 
3745         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3746         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3747 
3748         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3749         return kvm_skip_emulated_instruction(&svm->vcpu);
3750 }
3751 
3752 static int skinit_interception(struct vcpu_svm *svm)
3753 {
3754         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3755 
3756         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3757         return 1;
3758 }
3759 
3760 static int wbinvd_interception(struct vcpu_svm *svm)
3761 {
3762         return kvm_emulate_wbinvd(&svm->vcpu);
3763 }
3764 
3765 static int xsetbv_interception(struct vcpu_svm *svm)
3766 {
3767         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3768         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3769 
3770         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3771                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3772                 return kvm_skip_emulated_instruction(&svm->vcpu);
3773         }
3774 
3775         return 1;
3776 }
3777 
3778 static int task_switch_interception(struct vcpu_svm *svm)
3779 {
3780         u16 tss_selector;
3781         int reason;
3782         int int_type = svm->vmcb->control.exit_int_info &
3783                 SVM_EXITINTINFO_TYPE_MASK;
3784         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3785         uint32_t type =
3786                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3787         uint32_t idt_v =
3788                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3789         bool has_error_code = false;
3790         u32 error_code = 0;
3791 
3792         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3793 
3794         if (svm->vmcb->control.exit_info_2 &
3795             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3796                 reason = TASK_SWITCH_IRET;
3797         else if (svm->vmcb->control.exit_info_2 &
3798                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3799                 reason = TASK_SWITCH_JMP;
3800         else if (idt_v)
3801                 reason = TASK_SWITCH_GATE;
3802         else
3803                 reason = TASK_SWITCH_CALL;
3804 
3805         if (reason == TASK_SWITCH_GATE) {
3806                 switch (type) {
3807                 case SVM_EXITINTINFO_TYPE_NMI:
3808                         svm->vcpu.arch.nmi_injected = false;
3809                         break;
3810                 case SVM_EXITINTINFO_TYPE_EXEPT:
3811                         if (svm->vmcb->control.exit_info_2 &
3812                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3813                                 has_error_code = true;
3814                                 error_code =
3815                                         (u32)svm->vmcb->control.exit_info_2;
3816                         }
3817                         kvm_clear_exception_queue(&svm->vcpu);
3818                         break;
3819                 case SVM_EXITINTINFO_TYPE_INTR:
3820                         kvm_clear_interrupt_queue(&svm->vcpu);
3821                         break;
3822                 default:
3823                         break;
3824                 }
3825         }
3826 
3827         if (reason != TASK_SWITCH_GATE ||
3828             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3829             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3830              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3831                 skip_emulated_instruction(&svm->vcpu);
3832 
3833         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3834                 int_vec = -1;
3835 
3836         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3837                                 has_error_code, error_code) == EMULATE_FAIL) {
3838                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3839                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3840                 svm->vcpu.run->internal.ndata = 0;
3841                 return 0;
3842         }
3843         return 1;
3844 }
3845 
3846 static int cpuid_interception(struct vcpu_svm *svm)
3847 {
3848         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3849         return kvm_emulate_cpuid(&svm->vcpu);
3850 }
3851 
3852 static int iret_interception(struct vcpu_svm *svm)
3853 {
3854         ++svm->vcpu.stat.nmi_window_exits;
3855         clr_intercept(svm, INTERCEPT_IRET);
3856         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3857         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3858         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3859         return 1;
3860 }
3861 
3862 static int invlpg_interception(struct vcpu_svm *svm)
3863 {
3864         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3865                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3866 
3867         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3868         return kvm_skip_emulated_instruction(&svm->vcpu);
3869 }
3870 
3871 static int emulate_on_interception(struct vcpu_svm *svm)
3872 {
3873         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3874 }
3875 
3876 static int rsm_interception(struct vcpu_svm *svm)
3877 {
3878         return x86_emulate_instruction(&svm->vcpu, 0, 0,
3879                                        rsm_ins_bytes, 2) == EMULATE_DONE;
3880 }
3881 
3882 static int rdpmc_interception(struct vcpu_svm *svm)
3883 {
3884         int err;
3885 
3886         if (!static_cpu_has(X86_FEATURE_NRIPS))
3887                 return emulate_on_interception(svm);
3888 
3889         err = kvm_rdpmc(&svm->vcpu);
3890         return kvm_complete_insn_gp(&svm->vcpu, err);
3891 }
3892 
3893 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3894                                             unsigned long val)
3895 {
3896         unsigned long cr0 = svm->vcpu.arch.cr0;
3897         bool ret = false;
3898         u64 intercept;
3899 
3900         intercept = svm->nested.intercept;
3901 
3902         if (!is_guest_mode(&svm->vcpu) ||
3903             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3904                 return false;
3905 
3906         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3907         val &= ~SVM_CR0_SELECTIVE_MASK;
3908 
3909         if (cr0 ^ val) {
3910                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3911                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3912         }
3913 
3914         return ret;
3915 }
3916 
3917 #define CR_VALID (1ULL << 63)
3918 
3919 static int cr_interception(struct vcpu_svm *svm)
3920 {
3921         int reg, cr;
3922         unsigned long val;
3923         int err;
3924 
3925         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3926                 return emulate_on_interception(svm);
3927 
3928         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3929                 return emulate_on_interception(svm);
3930 
3931         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3932         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3933                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3934         else
3935                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3936 
3937         err = 0;
3938         if (cr >= 16) { /* mov to cr */
3939                 cr -= 16;
3940                 val = kvm_register_read(&svm->vcpu, reg);
3941                 switch (cr) {
3942                 case 0:
3943                         if (!check_selective_cr0_intercepted(svm, val))
3944                                 err = kvm_set_cr0(&svm->vcpu, val);
3945                         else
3946                                 return 1;
3947 
3948                         break;
3949                 case 3:
3950                         err = kvm_set_cr3(&svm->vcpu, val);
3951                         break;
3952                 case 4:
3953                         err = kvm_set_cr4(&svm->vcpu, val);
3954                         break;
3955                 case 8:
3956                         err = kvm_set_cr8(&svm->vcpu, val);
3957                         break;
3958                 default:
3959                         WARN(1, "unhandled write to CR%d", cr);
3960                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3961                         return 1;
3962                 }
3963         } else { /* mov from cr */
3964                 switch (cr) {
3965                 case 0:
3966                         val = kvm_read_cr0(&svm->vcpu);
3967                         break;
3968                 case 2:
3969                         val = svm->vcpu.arch.cr2;
3970                         break;
3971                 case 3:
3972                         val = kvm_read_cr3(&svm->vcpu);
3973                         break;
3974                 case 4:
3975                         val = kvm_read_cr4(&svm->vcpu);
3976                         break;
3977                 case 8:
3978                         val = kvm_get_cr8(&svm->vcpu);
3979                         break;
3980                 default:
3981                         WARN(1, "unhandled read from CR%d", cr);
3982                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3983                         return 1;
3984                 }
3985                 kvm_register_write(&svm->vcpu, reg, val);
3986         }
3987         return kvm_complete_insn_gp(&svm->vcpu, err);
3988 }
3989 
3990 static int dr_interception(struct vcpu_svm *svm)
3991 {
3992         int reg, dr;
3993         unsigned long val;
3994 
3995         if (svm->vcpu.guest_debug == 0) {
3996                 /*
3997                  * No more DR vmexits; force a reload of the debug registers
3998                  * and reenter on this instruction.  The next vmexit will
3999                  * retrieve the full state of the debug registers.
4000                  */
4001                 clr_dr_intercepts(svm);
4002                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4003                 return 1;
4004         }
4005 
4006         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4007                 return emulate_on_interception(svm);
4008 
4009         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4010         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4011 
4012         if (dr >= 16) { /* mov to DRn */
4013                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4014                         return 1;
4015                 val = kvm_register_read(&svm->vcpu, reg);
4016                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4017         } else {
4018                 if (!kvm_require_dr(&svm->vcpu, dr))
4019                         return 1;
4020                 kvm_get_dr(&svm->vcpu, dr, &val);
4021                 kvm_register_write(&svm->vcpu, reg, val);
4022         }
4023 
4024         return kvm_skip_emulated_instruction(&svm->vcpu);
4025 }
4026 
4027 static int cr8_write_interception(struct vcpu_svm *svm)
4028 {
4029         struct kvm_run *kvm_run = svm->vcpu.run;
4030         int r;
4031 
4032         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4033         /* instruction emulation calls kvm_set_cr8() */
4034         r = cr_interception(svm);
4035         if (lapic_in_kernel(&svm->vcpu))
4036                 return r;
4037         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4038                 return r;
4039         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4040         return 0;
4041 }
4042 
4043 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4044 {
4045         msr->data = 0;
4046 
4047         switch (msr->index) {
4048         case MSR_F10H_DECFG:
4049                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4050                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4051                 break;
4052         default:
4053                 return 1;
4054         }
4055 
4056         return 0;
4057 }
4058 
4059 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4060 {
4061         struct vcpu_svm *svm = to_svm(vcpu);
4062 
4063         switch (msr_info->index) {
4064         case MSR_STAR:
4065                 msr_info->data = svm->vmcb->save.star;
4066                 break;
4067 #ifdef CONFIG_X86_64
4068         case MSR_LSTAR:
4069                 msr_info->data = svm->vmcb->save.lstar;
4070                 break;
4071         case MSR_CSTAR:
4072                 msr_info->data = svm->vmcb->save.cstar;
4073                 break;
4074         case MSR_KERNEL_GS_BASE:
4075                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4076                 break;
4077         case MSR_SYSCALL_MASK:
4078                 msr_info->data = svm->vmcb->save.sfmask;
4079                 break;
4080 #endif
4081         case MSR_IA32_SYSENTER_CS:
4082                 msr_info->data = svm->vmcb->save.sysenter_cs;
4083                 break;
4084         case MSR_IA32_SYSENTER_EIP:
4085                 msr_info->data = svm->sysenter_eip;
4086                 break;
4087         case MSR_IA32_SYSENTER_ESP:
4088                 msr_info->data = svm->sysenter_esp;
4089                 break;
4090         case MSR_TSC_AUX:
4091                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4092                         return 1;
4093                 msr_info->data = svm->tsc_aux;
4094                 break;
4095         /*
4096          * Nobody will change the following 5 values in the VMCB so we can
4097          * safely return them on rdmsr. They will always be 0 until LBRV is
4098          * implemented.
4099          */
4100         case MSR_IA32_DEBUGCTLMSR:
4101                 msr_info->data = svm->vmcb->save.dbgctl;
4102                 break;
4103         case MSR_IA32_LASTBRANCHFROMIP:
4104                 msr_info->data = svm->vmcb->save.br_from;
4105                 break;
4106         case MSR_IA32_LASTBRANCHTOIP:
4107                 msr_info->data = svm->vmcb->save.br_to;
4108                 break;
4109         case MSR_IA32_LASTINTFROMIP:
4110                 msr_info->data = svm->vmcb->save.last_excp_from;
4111                 break;
4112         case MSR_IA32_LASTINTTOIP:
4113                 msr_info->data = svm->vmcb->save.last_excp_to;
4114                 break;
4115         case MSR_VM_HSAVE_PA:
4116                 msr_info->data = svm->nested.hsave_msr;
4117                 break;
4118         case MSR_VM_CR:
4119                 msr_info->data = svm->nested.vm_cr_msr;
4120                 break;
4121         case MSR_IA32_SPEC_CTRL:
4122                 if (!msr_info->host_initiated &&
4123                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4124                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4125                         return 1;
4126 
4127                 msr_info->data = svm->spec_ctrl;
4128                 break;
4129         case MSR_AMD64_VIRT_SPEC_CTRL:
4130                 if (!msr_info->host_initiated &&
4131                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4132                         return 1;
4133 
4134                 msr_info->data = svm->virt_spec_ctrl;
4135                 break;
4136         case MSR_F15H_IC_CFG: {
4137 
4138                 int family, model;
4139 
4140                 family = guest_cpuid_family(vcpu);
4141                 model  = guest_cpuid_model(vcpu);
4142 
4143                 if (family < 0 || model < 0)
4144                         return kvm_get_msr_common(vcpu, msr_info);
4145 
4146                 msr_info->data = 0;
4147 
4148                 if (family == 0x15 &&
4149                     (model >= 0x2 && model < 0x20))
4150                         msr_info->data = 0x1E;
4151                 }
4152                 break;
4153         case MSR_F10H_DECFG:
4154                 msr_info->data = svm->msr_decfg;
4155                 break;
4156         default:
4157                 return kvm_get_msr_common(vcpu, msr_info);
4158         }
4159         return 0;
4160 }
4161 
4162 static int rdmsr_interception(struct vcpu_svm *svm)
4163 {
4164         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4165         struct msr_data msr_info;
4166 
4167         msr_info.index = ecx;
4168         msr_info.host_initiated = false;
4169         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4170                 trace_kvm_msr_read_ex(ecx);
4171                 kvm_inject_gp(&svm->vcpu, 0);
4172                 return 1;
4173         } else {
4174                 trace_kvm_msr_read(ecx, msr_info.data);
4175 
4176                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4177                                    msr_info.data & 0xffffffff);
4178                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4179                                    msr_info.data >> 32);
4180                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4181                 return kvm_skip_emulated_instruction(&svm->vcpu);
4182         }
4183 }
4184 
4185 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4186 {
4187         struct vcpu_svm *svm = to_svm(vcpu);
4188         int svm_dis, chg_mask;
4189 
4190         if (data & ~SVM_VM_CR_VALID_MASK)
4191                 return 1;
4192 
4193         chg_mask = SVM_VM_CR_VALID_MASK;
4194 
4195         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4196                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4197 
4198         svm->nested.vm_cr_msr &= ~chg_mask;
4199         svm->nested.vm_cr_msr |= (data & chg_mask);
4200 
4201         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4202 
4203         /* check for svm_disable while efer.svme is set */
4204         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4205                 return 1;
4206 
4207         return 0;
4208 }
4209 
4210 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4211 {
4212         struct vcpu_svm *svm = to_svm(vcpu);
4213 
4214         u32 ecx = msr->index;
4215         u64 data = msr->data;
4216         switch (ecx) {
4217         case MSR_IA32_CR_PAT:
4218                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4219                         return 1;
4220                 vcpu->arch.pat = data;
4221                 svm->vmcb->save.g_pat = data;
4222                 mark_dirty(svm->vmcb, VMCB_NPT);
4223                 break;
4224         case MSR_IA32_SPEC_CTRL:
4225                 if (!msr->host_initiated &&
4226                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4227                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4228                         return 1;
4229 
4230                 /* The STIBP bit doesn't fault even if it's not advertised */
4231                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4232                         return 1;
4233 
4234                 svm->spec_ctrl = data;
4235 
4236                 if (!data)
4237                         break;
4238 
4239                 /*
4240                  * For non-nested:
4241                  * When it's written (to non-zero) for the first time, pass
4242                  * it through.
4243                  *
4244                  * For nested:
4245                  * The handling of the MSR bitmap for L2 guests is done in
4246                  * nested_svm_vmrun_msrpm.
4247                  * We update the L1 MSR bit as well since it will end up
4248                  * touching the MSR anyway now.
4249                  */
4250                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4251                 break;
4252         case MSR_IA32_PRED_CMD:
4253                 if (!msr->host_initiated &&
4254                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4255                         return 1;
4256 
4257                 if (data & ~PRED_CMD_IBPB)
4258                         return 1;
4259 
4260                 if (!data)
4261                         break;
4262 
4263                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4264                 if (is_guest_mode(vcpu))
4265                         break;
4266                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4267                 break;
4268         case MSR_AMD64_VIRT_SPEC_CTRL:
4269                 if (!msr->host_initiated &&
4270                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4271                         return 1;
4272 
4273                 if (data & ~SPEC_CTRL_SSBD)
4274                         return 1;
4275 
4276                 svm->virt_spec_ctrl = data;
4277                 break;
4278         case MSR_STAR:
4279                 svm->vmcb->save.star = data;
4280                 break;
4281 #ifdef CONFIG_X86_64
4282         case MSR_LSTAR:
4283                 svm->vmcb->save.lstar = data;
4284                 break;
4285         case MSR_CSTAR:
4286                 svm->vmcb->save.cstar = data;
4287                 break;
4288         case MSR_KERNEL_GS_BASE:
4289                 svm->vmcb->save.kernel_gs_base = data;
4290                 break;
4291         case MSR_SYSCALL_MASK:
4292                 svm->vmcb->save.sfmask = data;
4293                 break;
4294 #endif
4295         case MSR_IA32_SYSENTER_CS:
4296                 svm->vmcb->save.sysenter_cs = data;
4297                 break;
4298         case MSR_IA32_SYSENTER_EIP:
4299                 svm->sysenter_eip = data;
4300                 svm->vmcb->save.sysenter_eip = data;
4301                 break;
4302         case MSR_IA32_SYSENTER_ESP:
4303                 svm->sysenter_esp = data;
4304                 svm->vmcb->save.sysenter_esp = data;
4305                 break;
4306         case MSR_TSC_AUX:
4307                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4308                         return 1;
4309 
4310                 /*
4311                  * This is rare, so we update the MSR here instead of using
4312                  * direct_access_msrs.  Doing that would require a rdmsr in
4313                  * svm_vcpu_put.
4314                  */
4315                 svm->tsc_aux = data;
4316                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4317                 break;
4318         case MSR_IA32_DEBUGCTLMSR:
4319                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4320                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4321                                     __func__, data);
4322                         break;
4323                 }
4324                 if (data & DEBUGCTL_RESERVED_BITS)
4325                         return 1;
4326 
4327                 svm->vmcb->save.dbgctl = data;
4328                 mark_dirty(svm->vmcb, VMCB_LBR);
4329                 if (data & (1ULL<<0))
4330                         svm_enable_lbrv(svm);
4331                 else
4332                         svm_disable_lbrv(svm);
4333                 break;
4334         case MSR_VM_HSAVE_PA:
4335                 svm->nested.hsave_msr = data;
4336                 break;
4337         case MSR_VM_CR:
4338                 return svm_set_vm_cr(vcpu, data);
4339         case MSR_VM_IGNNE:
4340                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4341                 break;
4342         case MSR_F10H_DECFG: {
4343                 struct kvm_msr_entry msr_entry;
4344 
4345                 msr_entry.index = msr->index;
4346                 if (svm_get_msr_feature(&msr_entry))
4347                         return 1;
4348 
4349                 /* Check the supported bits */
4350                 if (data & ~msr_entry.data)
4351                         return 1;
4352 
4353                 /* Don't allow the guest to change a bit, #GP */
4354                 if (!msr->host_initiated && (data ^ msr_entry.data))
4355                         return 1;
4356 
4357                 svm->msr_decfg = data;
4358                 break;
4359         }
4360         case MSR_IA32_APICBASE:
4361                 if (kvm_vcpu_apicv_active(vcpu))
4362                         avic_update_vapic_bar(to_svm(vcpu), data);
4363                 /* Follow through */
4364         default:
4365                 return kvm_set_msr_common(vcpu, msr);
4366         }
4367         return 0;
4368 }
4369 
4370 static int wrmsr_interception(struct vcpu_svm *svm)
4371 {
4372         struct msr_data msr;
4373         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4374         u64 data = kvm_read_edx_eax(&svm->vcpu);
4375 
4376         msr.data = data;
4377         msr.index = ecx;
4378         msr.host_initiated = false;
4379 
4380         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4381         if (kvm_set_msr(&svm->vcpu, &msr)) {
4382                 trace_kvm_msr_write_ex(ecx, data);
4383                 kvm_inject_gp(&svm->vcpu, 0);
4384                 return 1;
4385         } else {
4386                 trace_kvm_msr_write(ecx, data);
4387                 return kvm_skip_emulated_instruction(&svm->vcpu);
4388         }
4389 }
4390 
4391 static int msr_interception(struct vcpu_svm *svm)
4392 {
4393         if (svm->vmcb->control.exit_info_1)
4394                 return wrmsr_interception(svm);
4395         else
4396                 return rdmsr_interception(svm);
4397 }
4398 
4399 static int interrupt_window_interception(struct vcpu_svm *svm)
4400 {
4401         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4402         svm_clear_vintr(svm);
4403         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4404         mark_dirty(svm->vmcb, VMCB_INTR);
4405         ++svm->vcpu.stat.irq_window_exits;
4406         return 1;
4407 }
4408 
4409 static int pause_interception(struct vcpu_svm *svm)
4410 {
4411         struct kvm_vcpu *vcpu = &svm->vcpu;
4412         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4413 
4414         if (pause_filter_thresh)
4415                 grow_ple_window(vcpu);
4416 
4417         kvm_vcpu_on_spin(vcpu, in_kernel);
4418         return 1;
4419 }
4420 
4421 static int nop_interception(struct vcpu_svm *svm)
4422 {
4423         return kvm_skip_emulated_instruction(&(svm->vcpu));
4424 }
4425 
4426 static int monitor_interception(struct vcpu_svm *svm)
4427 {
4428         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4429         return nop_interception(svm);
4430 }
4431 
4432 static int mwait_interception(struct vcpu_svm *svm)
4433 {
4434         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4435         return nop_interception(svm);
4436 }
4437 
4438 enum avic_ipi_failure_cause {
4439         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4440         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4441         AVIC_IPI_FAILURE_INVALID_TARGET,
4442         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4443 };
4444 
4445 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4446 {
4447         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4448         u32 icrl = svm->vmcb->control.exit_info_1;
4449         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4450         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4451         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4452 
4453         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4454 
4455         switch (id) {
4456         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4457                 /*
4458                  * AVIC hardware handles the generation of
4459                  * IPIs when the specified Message Type is Fixed
4460                  * (also known as fixed delivery mode) and
4461                  * the Trigger Mode is edge-triggered. The hardware
4462                  * also supports self and broadcast delivery modes
4463                  * specified via the Destination Shorthand(DSH)
4464                  * field of the ICRL. Logical and physical APIC ID
4465                  * formats are supported. All other IPI types cause
4466                  * a #VMEXIT, which needs to emulated.
4467                  */
4468                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4469                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4470                 break;
4471         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4472                 int i;
4473                 struct kvm_vcpu *vcpu;
4474                 struct kvm *kvm = svm->vcpu.kvm;
4475                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4476 
4477                 /*
4478                  * At this point, we expect that the AVIC HW has already
4479                  * set the appropriate IRR bits on the valid target
4480                  * vcpus. So, we just need to kick the appropriate vcpu.
4481                  */
4482                 kvm_for_each_vcpu(i, vcpu, kvm) {
4483                         bool m = kvm_apic_match_dest(vcpu, apic,
4484                                                      icrl & KVM_APIC_SHORT_MASK,
4485                                                      GET_APIC_DEST_FIELD(icrh),
4486                                                      icrl & KVM_APIC_DEST_MASK);
4487 
4488                         if (m && !avic_vcpu_is_running(vcpu))
4489                                 kvm_vcpu_wake_up(vcpu);
4490                 }
4491                 break;
4492         }
4493         case AVIC_IPI_FAILURE_INVALID_TARGET:
4494                 break;
4495         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4496                 WARN_ONCE(1, "Invalid backing page\n");
4497                 break;
4498         default:
4499                 pr_err("Unknown IPI interception\n");
4500         }
4501 
4502         return 1;
4503 }
4504 
4505 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4506 {
4507         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4508         int index;
4509         u32 *logical_apic_id_table;
4510         int dlid = GET_APIC_LOGICAL_ID(ldr);
4511 
4512         if (!dlid)
4513                 return NULL;
4514 
4515         if (flat) { /* flat */
4516                 index = ffs(dlid) - 1;
4517                 if (index > 7)
4518                         return NULL;
4519         } else { /* cluster */
4520                 int cluster = (dlid & 0xf0) >> 4;
4521                 int apic = ffs(dlid & 0x0f) - 1;
4522 
4523                 if ((apic < 0) || (apic > 7) ||
4524                     (cluster >= 0xf))
4525                         return NULL;
4526                 index = (cluster << 2) + apic;
4527         }
4528 
4529         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4530 
4531         return &logical_apic_id_table[index];
4532 }
4533 
4534 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4535                           bool valid)
4536 {
4537         bool flat;
4538         u32 *entry, new_entry;
4539 
4540         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4541         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4542         if (!entry)
4543                 return -EINVAL;
4544 
4545         new_entry = READ_ONCE(*entry);
4546         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4547         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4548         if (valid)
4549                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4550         else
4551                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4552         WRITE_ONCE(*entry, new_entry);
4553 
4554         return 0;
4555 }
4556 
4557 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4558 {
4559         int ret;
4560         struct vcpu_svm *svm = to_svm(vcpu);
4561         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4562 
4563         if (!ldr)
4564                 return 1;
4565 
4566         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4567         if (ret && svm->ldr_reg) {
4568                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4569                 svm->ldr_reg = 0;
4570         } else {
4571                 svm->ldr_reg = ldr;
4572         }
4573         return ret;
4574 }
4575 
4576 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4577 {
4578         u64 *old, *new;
4579         struct vcpu_svm *svm = to_svm(vcpu);
4580         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4581         u32 id = (apic_id_reg >> 24) & 0xff;
4582 
4583         if (vcpu->vcpu_id == id)
4584                 return 0;
4585 
4586         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4587         new = avic_get_physical_id_entry(vcpu, id);
4588         if (!new || !old)
4589                 return 1;
4590 
4591         /* We need to move physical_id_entry to new offset */
4592         *new = *old;
4593         *old = 0ULL;
4594         to_svm(vcpu)->avic_physical_id_cache = new;
4595 
4596         /*
4597          * Also update the guest physical APIC ID in the logical
4598          * APIC ID table entry if already setup the LDR.
4599          */
4600         if (svm->ldr_reg)
4601                 avic_handle_ldr_update(vcpu);
4602 
4603         return 0;
4604 }
4605 
4606 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4607 {
4608         struct vcpu_svm *svm = to_svm(vcpu);
4609         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4610         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4611         u32 mod = (dfr >> 28) & 0xf;
4612 
4613         /*
4614          * We assume that all local APICs are using the same type.
4615          * If this changes, we need to flush the AVIC logical
4616          * APID id table.
4617          */
4618         if (kvm_svm->ldr_mode == mod)
4619                 return 0;
4620 
4621         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4622         kvm_svm->ldr_mode = mod;
4623 
4624         if (svm->ldr_reg)
4625                 avic_handle_ldr_update(vcpu);
4626         return 0;
4627 }
4628 
4629 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4630 {
4631         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4632         u32 offset = svm->vmcb->control.exit_info_1 &
4633                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4634 
4635         switch (offset) {
4636         case APIC_ID:
4637                 if (avic_handle_apic_id_update(&svm->vcpu))
4638                         return 0;
4639                 break;
4640         case APIC_LDR:
4641                 if (avic_handle_ldr_update(&svm->vcpu))
4642                         return 0;
4643                 break;
4644         case APIC_DFR:
4645                 avic_handle_dfr_update(&svm->vcpu);
4646                 break;
4647         default:
4648                 break;
4649         }
4650 
4651         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4652 
4653         return 1;
4654 }
4655 
4656 static bool is_avic_unaccelerated_access_trap(u32 offset)
4657 {
4658         bool ret = false;
4659 
4660         switch (offset) {
4661         case APIC_ID:
4662         case APIC_EOI:
4663         case APIC_RRR:
4664         case APIC_LDR:
4665         case APIC_DFR:
4666         case APIC_SPIV:
4667         case APIC_ESR:
4668         case APIC_ICR:
4669         case APIC_LVTT:
4670         case APIC_LVTTHMR:
4671         case APIC_LVTPC:
4672         case APIC_LVT0:
4673         case APIC_LVT1:
4674         case APIC_LVTERR:
4675         case APIC_TMICT:
4676         case APIC_TDCR:
4677                 ret = true;
4678                 break;
4679         default:
4680                 break;
4681         }
4682         return ret;
4683 }
4684 
4685 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4686 {
4687         int ret = 0;
4688         u32 offset = svm->vmcb->control.exit_info_1 &
4689                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4690         u32 vector = svm->vmcb->control.exit_info_2 &
4691                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4692         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4693                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4694         bool trap = is_avic_unaccelerated_access_trap(offset);
4695 
4696         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4697                                             trap, write, vector);
4698         if (trap) {
4699                 /* Handling Trap */
4700                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4701                 ret = avic_unaccel_trap_write(svm);
4702         } else {
4703                 /* Handling Fault */
4704                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4705         }
4706 
4707         return ret;
4708 }
4709 
4710 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4711         [SVM_EXIT_READ_CR0]                     = cr_interception,
4712         [SVM_EXIT_READ_CR3]                     = cr_interception,
4713         [SVM_EXIT_READ_CR4]                     = cr_interception,
4714         [SVM_EXIT_READ_CR8]                     = cr_interception,
4715         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4716         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4717         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4718         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4719         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4720         [SVM_EXIT_READ_DR0]                     = dr_interception,
4721         [SVM_EXIT_READ_DR1]                     = dr_interception,
4722         [SVM_EXIT_READ_DR2]                     = dr_interception,
4723         [SVM_EXIT_READ_DR3]                     = dr_interception,
4724         [SVM_EXIT_READ_DR4]                     = dr_interception,
4725         [SVM_EXIT_READ_DR5]                     = dr_interception,
4726         [SVM_EXIT_READ_DR6]                     = dr_interception,
4727         [SVM_EXIT_READ_DR7]                     = dr_interception,
4728         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4729         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4730         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4731         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4732         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4733         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4734         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4735         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4736         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4737         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4738         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4739         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4740         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4741         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4742         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4743         [SVM_EXIT_INTR]                         = intr_interception,
4744         [SVM_EXIT_NMI]                          = nmi_interception,
4745         [SVM_EXIT_SMI]                          = nop_on_interception,
4746         [SVM_EXIT_INIT]                         = nop_on_interception,
4747         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4748         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4749         [SVM_EXIT_CPUID]                        = cpuid_interception,
4750         [SVM_EXIT_IRET]                         = iret_interception,
4751         [SVM_EXIT_INVD]                         = emulate_on_interception,
4752         [SVM_EXIT_PAUSE]                        = pause_interception,
4753         [SVM_EXIT_HLT]                          = halt_interception,
4754         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4755         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4756         [SVM_EXIT_IOIO]                         = io_interception,
4757         [SVM_EXIT_MSR]                          = msr_interception,
4758         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4759         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4760         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4761         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4762         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4763         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4764         [SVM_EXIT_STGI]                         = stgi_interception,
4765         [SVM_EXIT_CLGI]                         = clgi_interception,
4766         [SVM_EXIT_SKINIT]                       = skinit_interception,
4767         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4768         [SVM_EXIT_MONITOR]                      = monitor_interception,
4769         [SVM_EXIT_MWAIT]                        = mwait_interception,
4770         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4771         [SVM_EXIT_NPF]                          = npf_interception,
4772         [SVM_EXIT_RSM]                          = rsm_interception,
4773         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4774         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4775 };
4776 
4777 static void dump_vmcb(struct kvm_vcpu *vcpu)
4778 {
4779         struct vcpu_svm *svm = to_svm(vcpu);
4780         struct vmcb_control_area *control = &svm->vmcb->control;
4781         struct vmcb_save_area *save = &svm->vmcb->save;
4782 
4783         pr_err("VMCB Control Area:\n");
4784         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4785         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4786         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4787         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4788         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4789         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4790         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4791         pr_err("%-20s%d\n", "pause filter threshold:",
4792                control->pause_filter_thresh);
4793         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4794         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4795         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4796         pr_err("%-20s%d\n", "asid:", control->asid);
4797         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4798         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4799         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4800         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4801         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4802         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4803         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4804         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4805         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4806         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4807         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4808         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4809         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4810         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4811         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4812         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4813         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4814         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4815         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4816         pr_err("VMCB State Save Area:\n");
4817         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4818                "es:",
4819                save->es.selector, save->es.attrib,
4820                save->es.limit, save->es.base);
4821         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4822                "cs:",
4823                save->cs.selector, save->cs.attrib,
4824                save->cs.limit, save->cs.base);
4825         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4826                "ss:",
4827                save->ss.selector, save->ss.attrib,
4828                save->ss.limit, save->ss.base);
4829         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4830                "ds:",
4831                save->ds.selector, save->ds.attrib,
4832                save->ds.limit, save->ds.base);
4833         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4834                "fs:",
4835                save->fs.selector, save->fs.attrib,
4836                save->fs.limit, save->fs.base);
4837         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4838                "gs:",
4839                save->gs.selector, save->gs.attrib,
4840                save->gs.limit, save->gs.base);
4841         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4842                "gdtr:",
4843                save->gdtr.selector, save->gdtr.attrib,
4844                save->gdtr.limit, save->gdtr.base);
4845         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4846                "ldtr:",
4847                save->ldtr.selector, save->ldtr.attrib,
4848                save->ldtr.limit, save->ldtr.base);
4849         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4850                "idtr:",
4851                save->idtr.selector, save->idtr.attrib,
4852                save->idtr.limit, save->idtr.base);
4853         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4854                "tr:",
4855                save->tr.selector, save->tr.attrib,
4856                save->tr.limit, save->tr.base);
4857         pr_err("cpl:            %d                efer:         %016llx\n",
4858                 save->cpl, save->efer);
4859         pr_err("%-15s %016llx %-13s %016llx\n",
4860                "cr0:", save->cr0, "cr2:", save->cr2);
4861         pr_err("%-15s %016llx %-13s %016llx\n",
4862                "cr3:", save->cr3, "cr4:", save->cr4);
4863         pr_err("%-15s %016llx %-13s %016llx\n",
4864                "dr6:", save->dr6, "dr7:", save->dr7);
4865         pr_err("%-15s %016llx %-13s %016llx\n",
4866                "rip:", save->rip, "rflags:", save->rflags);
4867         pr_err("%-15s %016llx %-13s %016llx\n",
4868                "rsp:", save->rsp, "rax:", save->rax);
4869         pr_err("%-15s %016llx %-13s %016llx\n",
4870                "star:", save->star, "lstar:", save->lstar);
4871         pr_err("%-15s %016llx %-13s %016llx\n",
4872                "cstar:", save->cstar, "sfmask:", save->sfmask);
4873         pr_err("%-15s %016llx %-13s %016llx\n",
4874                "kernel_gs_base:", save->kernel_gs_base,
4875                "sysenter_cs:", save->sysenter_cs);
4876         pr_err("%-15s %016llx %-13s %016llx\n",
4877                "sysenter_esp:", save->sysenter_esp,
4878                "sysenter_eip:", save->sysenter_eip);
4879         pr_err("%-15s %016llx %-13s %016llx\n",
4880                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4881         pr_err("%-15s %016llx %-13s %016llx\n",
4882                "br_from:", save->br_from, "br_to:", save->br_to);
4883         pr_err("%-15s %016llx %-13s %016llx\n",
4884                "excp_from:", save->last_excp_from,
4885                "excp_to:", save->last_excp_to);
4886 }
4887 
4888 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4889 {
4890         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4891 
4892         *info1 = control->exit_info_1;
4893         *info2 = control->exit_info_2;
4894 }
4895 
4896 static int handle_exit(struct kvm_vcpu *vcpu)
4897 {
4898         struct vcpu_svm *svm = to_svm(vcpu);
4899         struct kvm_run *kvm_run = vcpu->run;
4900         u32 exit_code = svm->vmcb->control.exit_code;
4901 
4902         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4903 
4904         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4905                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4906         if (npt_enabled)
4907                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4908 
4909         if (unlikely(svm->nested.exit_required)) {
4910                 nested_svm_vmexit(svm);
4911                 svm->nested.exit_required = false;
4912 
4913                 return 1;
4914         }
4915 
4916         if (is_guest_mode(vcpu)) {
4917                 int vmexit;
4918 
4919                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4920                                         svm->vmcb->control.exit_info_1,
4921                                         svm->vmcb->control.exit_info_2,
4922                                         svm->vmcb->control.exit_int_info,
4923                                         svm->vmcb->control.exit_int_info_err,
4924                                         KVM_ISA_SVM);
4925 
4926                 vmexit = nested_svm_exit_special(svm);
4927 
4928                 if (vmexit == NESTED_EXIT_CONTINUE)
4929                         vmexit = nested_svm_exit_handled(svm);
4930 
4931                 if (vmexit == NESTED_EXIT_DONE)
4932                         return 1;
4933         }
4934 
4935         svm_complete_interrupts(svm);
4936 
4937         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4938                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4939                 kvm_run->fail_entry.hardware_entry_failure_reason
4940                         = svm->vmcb->control.exit_code;
4941                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4942                 dump_vmcb(vcpu);
4943                 return 0;
4944         }
4945 
4946         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4947             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4948             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4949             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4950                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4951                        "exit_code 0x%x\n",
4952                        __func__, svm->vmcb->control.exit_int_info,
4953                        exit_code);
4954 
4955         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4956             || !svm_exit_handlers[exit_code]) {
4957                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4958                 kvm_queue_exception(vcpu, UD_VECTOR);
4959                 return 1;
4960         }
4961 
4962         return svm_exit_handlers[exit_code](svm);
4963 }
4964 
4965 static void reload_tss(struct kvm_vcpu *vcpu)
4966 {
4967         int cpu = raw_smp_processor_id();
4968 
4969         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4970         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4971         load_TR_desc();
4972 }
4973 
4974 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4975 {
4976         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4977         int asid = sev_get_asid(svm->vcpu.kvm);
4978 
4979         /* Assign the asid allocated with this SEV guest */
4980         svm->vmcb->control.asid = asid;
4981 
4982         /*
4983          * Flush guest TLB:
4984          *
4985          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4986          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4987          */
4988         if (sd->sev_vmcbs[asid] == svm->vmcb &&
4989             svm->last_cpu == cpu)
4990                 return;
4991 
4992         svm->last_cpu = cpu;
4993         sd->sev_vmcbs[asid] = svm->vmcb;
4994         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4995         mark_dirty(svm->vmcb, VMCB_ASID);
4996 }
4997 
4998 static void pre_svm_run(struct vcpu_svm *svm)
4999 {
5000         int cpu = raw_smp_processor_id();
5001 
5002         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5003 
5004         if (sev_guest(svm->vcpu.kvm))
5005                 return pre_sev_run(svm, cpu);
5006 
5007         /* FIXME: handle wraparound of asid_generation */
5008         if (svm->asid_generation != sd->asid_generation)
5009                 new_asid(svm, sd);
5010 }
5011 
5012 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5013 {
5014         struct vcpu_svm *svm = to_svm(vcpu);
5015 
5016         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5017         vcpu->arch.hflags |= HF_NMI_MASK;
5018         set_intercept(svm, INTERCEPT_IRET);
5019         ++vcpu->stat.nmi_injections;
5020 }
5021 
5022 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5023 {
5024         struct vmcb_control_area *control;
5025 
5026         /* The following fields are ignored when AVIC is enabled */
5027         control = &svm->vmcb->control;
5028         control->int_vector = irq;
5029         control->int_ctl &= ~V_INTR_PRIO_MASK;
5030         control->int_ctl |= V_IRQ_MASK |
5031                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5032         mark_dirty(svm->vmcb, VMCB_INTR);
5033 }
5034 
5035 static void svm_set_irq(struct kvm_vcpu *vcpu)
5036 {
5037         struct vcpu_svm *svm = to_svm(vcpu);
5038 
5039         BUG_ON(!(gif_set(svm)));
5040 
5041         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5042         ++vcpu->stat.irq_injections;
5043 
5044         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5045                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5046 }
5047 
5048 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5049 {
5050         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5051 }
5052 
5053 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5054 {
5055         struct vcpu_svm *svm = to_svm(vcpu);
5056 
5057         if (svm_nested_virtualize_tpr(vcpu) ||
5058             kvm_vcpu_apicv_active(vcpu))
5059                 return;
5060 
5061         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5062 
5063         if (irr == -1)
5064                 return;
5065 
5066         if (tpr >= irr)
5067                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5068 }
5069 
5070 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5071 {
5072         return;
5073 }
5074 
5075 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5076 {
5077         return avic && irqchip_split(vcpu->kvm);
5078 }
5079 
5080 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5081 {
5082 }
5083 
5084 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5085 {
5086 }
5087 
5088 /* Note: Currently only used by Hyper-V. */
5089 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5090 {
5091         struct vcpu_svm *svm = to_svm(vcpu);
5092         struct vmcb *vmcb = svm->vmcb;
5093 
5094         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5095                 return;
5096 
5097         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5098         mark_dirty(vmcb, VMCB_INTR);
5099 }
5100 
5101 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5102 {
5103         return;
5104 }
5105 
5106 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5107 {
5108         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5109         smp_mb__after_atomic();
5110 
5111         if (avic_vcpu_is_running(vcpu))
5112                 wrmsrl(SVM_AVIC_DOORBELL,
5113                        kvm_cpu_get_apicid(vcpu->cpu));
5114         else
5115                 kvm_vcpu_wake_up(vcpu);
5116 }
5117 
5118 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5119 {
5120         unsigned long flags;
5121         struct amd_svm_iommu_ir *cur;
5122 
5123         spin_lock_irqsave(&svm->ir_list_lock, flags);
5124         list_for_each_entry(cur, &svm->ir_list, node) {
5125                 if (cur->data != pi->ir_data)
5126                         continue;
5127                 list_del(&cur->node);
5128                 kfree(cur);
5129                 break;
5130         }
5131         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5132 }
5133 
5134 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5135 {
5136         int ret = 0;
5137         unsigned long flags;
5138         struct amd_svm_iommu_ir *ir;
5139 
5140         /**
5141          * In some cases, the existing irte is updaed and re-set,
5142          * so we need to check here if it's already been * added
5143          * to the ir_list.
5144          */
5145         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5146                 struct kvm *kvm = svm->vcpu.kvm;
5147                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5148                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5149                 struct vcpu_svm *prev_svm;
5150 
5151                 if (!prev_vcpu) {
5152                         ret = -EINVAL;
5153                         goto out;
5154                 }
5155 
5156                 prev_svm = to_svm(prev_vcpu);
5157                 svm_ir_list_del(prev_svm, pi);
5158         }
5159 
5160         /**
5161          * Allocating new amd_iommu_pi_data, which will get
5162          * add to the per-vcpu ir_list.
5163          */
5164         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5165         if (!ir) {
5166                 ret = -ENOMEM;
5167                 goto out;
5168         }
5169         ir->data = pi->ir_data;
5170 
5171         spin_lock_irqsave(&svm->ir_list_lock, flags);
5172         list_add(&ir->node, &svm->ir_list);
5173         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5174 out:
5175         return ret;
5176 }
5177 
5178 /**
5179  * Note:
5180  * The HW cannot support posting multicast/broadcast
5181  * interrupts to a vCPU. So, we still use legacy interrupt
5182  * remapping for these kind of interrupts.
5183  *
5184  * For lowest-priority interrupts, we only support
5185  * those with single CPU as the destination, e.g. user
5186  * configures the interrupts via /proc/irq or uses
5187  * irqbalance to make the interrupts single-CPU.
5188  */
5189 static int
5190 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5191                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5192 {
5193         struct kvm_lapic_irq irq;
5194         struct kvm_vcpu *vcpu = NULL;
5195 
5196         kvm_set_msi_irq(kvm, e, &irq);
5197 
5198         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5199                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5200                          __func__, irq.vector);
5201                 return -1;
5202         }
5203 
5204         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5205                  irq.vector);
5206         *svm = to_svm(vcpu);
5207         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5208         vcpu_info->vector = irq.vector;
5209 
5210         return 0;
5211 }
5212 
5213 /*
5214  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5215  *
5216  * @kvm: kvm
5217  * @host_irq: host irq of the interrupt
5218  * @guest_irq: gsi of the interrupt
5219  * @set: set or unset PI
5220  * returns 0 on success, < 0 on failure
5221  */
5222 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5223                               uint32_t guest_irq, bool set)
5224 {
5225         struct kvm_kernel_irq_routing_entry *e;
5226         struct kvm_irq_routing_table *irq_rt;
5227         int idx, ret = -EINVAL;
5228 
5229         if (!kvm_arch_has_assigned_device(kvm) ||
5230             !irq_remapping_cap(IRQ_POSTING_CAP))
5231                 return 0;
5232 
5233         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5234                  __func__, host_irq, guest_irq, set);
5235 
5236         idx = srcu_read_lock(&kvm->irq_srcu);
5237         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5238         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5239 
5240         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5241                 struct vcpu_data vcpu_info;
5242                 struct vcpu_svm *svm = NULL;
5243 
5244                 if (e->type != KVM_IRQ_ROUTING_MSI)
5245                         continue;
5246 
5247                 /**
5248                  * Here, we setup with legacy mode in the following cases:
5249                  * 1. When cannot target interrupt to a specific vcpu.
5250                  * 2. Unsetting posted interrupt.
5251                  * 3. APIC virtialization is disabled for the vcpu.
5252                  */
5253                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5254                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5255                         struct amd_iommu_pi_data pi;
5256 
5257                         /* Try to enable guest_mode in IRTE */
5258                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5259                                             AVIC_HPA_MASK);
5260                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5261                                                      svm->vcpu.vcpu_id);
5262                         pi.is_guest_mode = true;
5263                         pi.vcpu_data = &vcpu_info;
5264                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5265 
5266                         /**
5267                          * Here, we successfully setting up vcpu affinity in
5268                          * IOMMU guest mode. Now, we need to store the posted
5269                          * interrupt information in a per-vcpu ir_list so that
5270                          * we can reference to them directly when we update vcpu
5271                          * scheduling information in IOMMU irte.
5272                          */
5273                         if (!ret && pi.is_guest_mode)
5274                                 svm_ir_list_add(svm, &pi);
5275                 } else {
5276                         /* Use legacy mode in IRTE */
5277                         struct amd_iommu_pi_data pi;
5278 
5279                         /**
5280                          * Here, pi is used to:
5281                          * - Tell IOMMU to use legacy mode for this interrupt.
5282                          * - Retrieve ga_tag of prior interrupt remapping data.
5283                          */
5284                         pi.is_guest_mode = false;
5285                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5286 
5287                         /**
5288                          * Check if the posted interrupt was previously
5289                          * setup with the guest_mode by checking if the ga_tag
5290                          * was cached. If so, we need to clean up the per-vcpu
5291                          * ir_list.
5292                          */
5293                         if (!ret && pi.prev_ga_tag) {
5294                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5295                                 struct kvm_vcpu *vcpu;
5296 
5297                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5298                                 if (vcpu)
5299                                         svm_ir_list_del(to_svm(vcpu), &pi);
5300                         }
5301                 }
5302 
5303                 if (!ret && svm) {
5304                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5305                                                  e->gsi, vcpu_info.vector,
5306                                                  vcpu_info.pi_desc_addr, set);
5307                 }
5308 
5309                 if (ret < 0) {
5310                         pr_err("%s: failed to update PI IRTE\n", __func__);
5311                         goto out;
5312                 }
5313         }
5314 
5315         ret = 0;
5316 out:
5317         srcu_read_unlock(&kvm->irq_srcu, idx);
5318         return ret;
5319 }
5320 
5321 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5322 {
5323         struct vcpu_svm *svm = to_svm(vcpu);
5324         struct vmcb *vmcb = svm->vmcb;
5325         int ret;
5326         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5327               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5328         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5329 
5330         return ret;
5331 }
5332 
5333 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5334 {
5335         struct vcpu_svm *svm = to_svm(vcpu);
5336 
5337         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5338 }
5339 
5340 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5341 {
5342         struct vcpu_svm *svm = to_svm(vcpu);
5343 
5344         if (masked) {
5345                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5346                 set_intercept(svm, INTERCEPT_IRET);
5347         } else {
5348                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5349                 clr_intercept(svm, INTERCEPT_IRET);
5350         }
5351 }
5352 
5353 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5354 {
5355         struct vcpu_svm *svm = to_svm(vcpu);
5356         struct vmcb *vmcb = svm->vmcb;
5357         int ret;
5358 
5359         if (!gif_set(svm) ||
5360              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5361                 return 0;
5362 
5363         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5364 
5365         if (is_guest_mode(vcpu))
5366                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5367 
5368         return ret;
5369 }
5370 
5371 static void enable_irq_window(struct kvm_vcpu *vcpu)
5372 {
5373         struct vcpu_svm *svm = to_svm(vcpu);
5374 
5375         if (kvm_vcpu_apicv_active(vcpu))
5376                 return;
5377 
5378         /*
5379          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5380          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5381          * get that intercept, this function will be called again though and
5382          * we'll get the vintr intercept. However, if the vGIF feature is
5383          * enabled, the STGI interception will not occur. Enable the irq
5384          * window under the assumption that the hardware will set the GIF.
5385          */
5386         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5387                 svm_set_vintr(svm);
5388                 svm_inject_irq(svm, 0x0);
5389         }
5390 }
5391 
5392 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5393 {
5394         struct vcpu_svm *svm = to_svm(vcpu);
5395 
5396         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5397             == HF_NMI_MASK)
5398                 return; /* IRET will cause a vm exit */
5399 
5400         if (!gif_set(svm)) {
5401                 if (vgif_enabled(svm))
5402                         set_intercept(svm, INTERCEPT_STGI);
5403                 return; /* STGI will cause a vm exit */
5404         }
5405 
5406         if (svm->nested.exit_required)
5407                 return; /* we're not going to run the guest yet */
5408 
5409         /*
5410          * Something prevents NMI from been injected. Single step over possible
5411          * problem (IRET or exception injection or interrupt shadow)
5412          */
5413         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5414         svm->nmi_singlestep = true;
5415         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5416 }
5417 
5418 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5419 {
5420         return 0;
5421 }
5422 
5423 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5424 {
5425         return 0;
5426 }
5427 
5428 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5429 {
5430         struct vcpu_svm *svm = to_svm(vcpu);
5431 
5432         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5433                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5434         else
5435                 svm->asid_generation--;
5436 }
5437 
5438 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5439 {
5440 }
5441 
5442 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5443 {
5444         struct vcpu_svm *svm = to_svm(vcpu);
5445 
5446         if (svm_nested_virtualize_tpr(vcpu))
5447                 return;
5448 
5449         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5450                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5451                 kvm_set_cr8(vcpu, cr8);
5452         }
5453 }
5454 
5455 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5456 {
5457         struct vcpu_svm *svm = to_svm(vcpu);
5458         u64 cr8;
5459 
5460         if (svm_nested_virtualize_tpr(vcpu) ||
5461             kvm_vcpu_apicv_active(vcpu))
5462                 return;
5463 
5464         cr8 = kvm_get_cr8(vcpu);
5465         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5466         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5467 }
5468 
5469 static void svm_complete_interrupts(struct vcpu_svm *svm)
5470 {
5471         u8 vector;
5472         int type;
5473         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5474         unsigned int3_injected = svm->int3_injected;
5475 
5476         svm->int3_injected = 0;
5477 
5478         /*
5479          * If we've made progress since setting HF_IRET_MASK, we've
5480          * executed an IRET and can allow NMI injection.
5481          */
5482         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5483             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5484                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5485                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5486         }
5487 
5488         svm->vcpu.arch.nmi_injected = false;
5489         kvm_clear_exception_queue(&svm->vcpu);
5490         kvm_clear_interrupt_queue(&svm->vcpu);
5491 
5492         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5493                 return;
5494 
5495         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5496 
5497         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5498         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5499 
5500         switch (type) {
5501         case SVM_EXITINTINFO_TYPE_NMI:
5502                 svm->vcpu.arch.nmi_injected = true;
5503                 break;
5504         case SVM_EXITINTINFO_TYPE_EXEPT:
5505                 /*
5506                  * In case of software exceptions, do not reinject the vector,
5507                  * but re-execute the instruction instead. Rewind RIP first
5508                  * if we emulated INT3 before.
5509                  */
5510                 if (kvm_exception_is_soft(vector)) {
5511                         if (vector == BP_VECTOR && int3_injected &&
5512                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5513                                 kvm_rip_write(&svm->vcpu,
5514                                               kvm_rip_read(&svm->vcpu) -
5515                                               int3_injected);
5516                         break;
5517                 }
5518                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5519                         u32 err = svm->vmcb->control.exit_int_info_err;
5520                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5521 
5522                 } else
5523                         kvm_requeue_exception(&svm->vcpu, vector);
5524                 break;
5525         case SVM_EXITINTINFO_TYPE_INTR:
5526                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5527                 break;
5528         default:
5529                 break;
5530         }
5531 }
5532 
5533 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5534 {
5535         struct vcpu_svm *svm = to_svm(vcpu);
5536         struct vmcb_control_area *control = &svm->vmcb->control;
5537 
5538         control->exit_int_info = control->event_inj;
5539         control->exit_int_info_err = control->event_inj_err;
5540         control->event_inj = 0;
5541         svm_complete_interrupts(svm);
5542 }
5543 
5544 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5545 {
5546         struct vcpu_svm *svm = to_svm(vcpu);
5547 
5548         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5549         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5550         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5551 
5552         /*
5553          * A vmexit emulation is required before the vcpu can be executed
5554          * again.
5555          */
5556         if (unlikely(svm->nested.exit_required))
5557                 return;
5558 
5559         /*
5560          * Disable singlestep if we're injecting an interrupt/exception.
5561          * We don't want our modified rflags to be pushed on the stack where
5562          * we might not be able to easily reset them if we disabled NMI
5563          * singlestep later.
5564          */
5565         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5566                 /*
5567                  * Event injection happens before external interrupts cause a
5568                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5569                  * is enough to force an immediate vmexit.
5570                  */
5571                 disable_nmi_singlestep(svm);
5572                 smp_send_reschedule(vcpu->cpu);
5573         }
5574 
5575         pre_svm_run(svm);
5576 
5577         sync_lapic_to_cr8(vcpu);
5578 
5579         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5580 
5581         clgi();
5582 
5583         local_irq_enable();
5584 
5585         /*
5586          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5587          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5588          * is no need to worry about the conditional branch over the wrmsr
5589          * being speculatively taken.
5590          */
5591         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5592 
5593         asm volatile (
5594                 "push %%" _ASM_BP "; \n\t"
5595                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5596                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5597                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5598                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5599                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5600                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5601 #ifdef CONFIG_X86_64
5602                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5603                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5604                 "mov %c[r10](%[svm]), %%r10 \n\t"
5605                 "mov %c[r11](%[svm]), %%r11 \n\t"
5606                 "mov %c[r12](%[svm]), %%r12 \n\t"
5607                 "mov %c[r13](%[svm]), %%r13 \n\t"
5608                 "mov %c[r14](%[svm]), %%r14 \n\t"
5609                 "mov %c[r15](%[svm]), %%r15 \n\t"
5610 #endif
5611 
5612                 /* Enter guest mode */
5613                 "push %%" _ASM_AX " \n\t"
5614                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5615                 __ex(SVM_VMLOAD) "\n\t"
5616                 __ex(SVM_VMRUN) "\n\t"
5617                 __ex(SVM_VMSAVE) "\n\t"
5618                 "pop %%" _ASM_AX " \n\t"
5619 
5620                 /* Save guest registers, load host registers */
5621                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5622                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5623                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5624                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5625                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5626                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5627 #ifdef CONFIG_X86_64
5628                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5629                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5630                 "mov %%r10, %c[r10](%[svm]) \n\t"
5631                 "mov %%r11, %c[r11](%[svm]) \n\t"
5632                 "mov %%r12, %c[r12](%[svm]) \n\t"
5633                 "mov %%r13, %c[r13](%[svm]) \n\t"
5634                 "mov %%r14, %c[r14](%[svm]) \n\t"
5635                 "mov %%r15, %c[r15](%[svm]) \n\t"
5636 #endif
5637                 /*
5638                 * Clear host registers marked as clobbered to prevent
5639                 * speculative use.
5640                 */
5641                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5642                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5643                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5644                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5645                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5646 #ifdef CONFIG_X86_64
5647                 "xor %%r8, %%r8 \n\t"
5648                 "xor %%r9, %%r9 \n\t"
5649                 "xor %%r10, %%r10 \n\t"
5650                 "xor %%r11, %%r11 \n\t"
5651                 "xor %%r12, %%r12 \n\t"
5652                 "xor %%r13, %%r13 \n\t"
5653                 "xor %%r14, %%r14 \n\t"
5654                 "xor %%r15, %%r15 \n\t"
5655 #endif
5656                 "pop %%" _ASM_BP
5657                 :
5658                 : [svm]"a"(svm),
5659                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5660                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5661                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5662                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5663                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5664                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5665                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5666 #ifdef CONFIG_X86_64
5667                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5668                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5669                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5670                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5671                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5672                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5673                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5674                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5675 #endif
5676                 : "cc", "memory"
5677 #ifdef CONFIG_X86_64
5678                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5679                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5680 #else
5681                 , "ebx", "ecx", "edx", "esi", "edi"
5682 #endif
5683                 );
5684 
5685         /* Eliminate branch target predictions from guest mode */
5686         vmexit_fill_RSB();
5687 
5688 #ifdef CONFIG_X86_64
5689         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5690 #else
5691         loadsegment(fs, svm->host.fs);
5692 #ifndef CONFIG_X86_32_LAZY_GS
5693         loadsegment(gs, svm->host.gs);
5694 #endif
5695 #endif
5696 
5697         /*
5698          * We do not use IBRS in the kernel. If this vCPU has used the
5699          * SPEC_CTRL MSR it may have left it on; save the value and
5700          * turn it off. This is much more efficient than blindly adding
5701          * it to the atomic save/restore list. Especially as the former
5702          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5703          *
5704          * For non-nested case:
5705          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5706          * save it.
5707          *
5708          * For nested case:
5709          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5710          * save it.
5711          */
5712         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5713                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5714 
5715         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5716 
5717         reload_tss(vcpu);
5718 
5719         local_irq_disable();
5720 
5721         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5722         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5723         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5724         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5725 
5726         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5727                 kvm_before_interrupt(&svm->vcpu);
5728 
5729         stgi();
5730 
5731         /* Any pending NMI will happen here */
5732 
5733         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5734                 kvm_after_interrupt(&svm->vcpu);
5735 
5736         sync_cr8_to_lapic(vcpu);
5737 
5738         svm->next_rip = 0;
5739 
5740         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5741 
5742         /* if exit due to PF check for async PF */
5743         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5744                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5745 
5746         if (npt_enabled) {
5747                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5748                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5749         }
5750 
5751         /*
5752          * We need to handle MC intercepts here before the vcpu has a chance to
5753          * change the physical cpu
5754          */
5755         if (unlikely(svm->vmcb->control.exit_code ==
5756                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5757                 svm_handle_mce(svm);
5758 
5759         mark_all_clean(svm->vmcb);
5760 }
5761 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5762 
5763 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5764 {
5765         struct vcpu_svm *svm = to_svm(vcpu);
5766 
5767         svm->vmcb->save.cr3 = __sme_set(root);
5768         mark_dirty(svm->vmcb, VMCB_CR);
5769         svm_flush_tlb(vcpu, true);
5770 }
5771 
5772 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5773 {
5774         struct vcpu_svm *svm = to_svm(vcpu);
5775 
5776         svm->vmcb->control.nested_cr3 = __sme_set(root);
5777         mark_dirty(svm->vmcb, VMCB_NPT);
5778 
5779         /* Also sync guest cr3 here in case we live migrate */
5780         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5781         mark_dirty(svm->vmcb, VMCB_CR);
5782 
5783         svm_flush_tlb(vcpu, true);
5784 }
5785 
5786 static int is_disabled(void)
5787 {
5788         u64 vm_cr;
5789 
5790         rdmsrl(MSR_VM_CR, vm_cr);
5791         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5792                 return 1;
5793 
5794         return 0;
5795 }
5796 
5797 static void
5798 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5799 {
5800         /*
5801          * Patch in the VMMCALL instruction:
5802          */
5803         hypercall[0] = 0x0f;
5804         hypercall[1] = 0x01;
5805         hypercall[2] = 0xd9;
5806 }
5807 
5808 static void svm_check_processor_compat(void *rtn)
5809 {
5810         *(int *)rtn = 0;
5811 }
5812 
5813 static bool svm_cpu_has_accelerated_tpr(void)
5814 {
5815         return false;
5816 }
5817 
5818 static bool svm_has_emulated_msr(int index)
5819 {
5820         return true;
5821 }
5822 
5823 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5824 {
5825         return 0;
5826 }
5827 
5828 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5829 {
5830         struct vcpu_svm *svm = to_svm(vcpu);
5831 
5832         /* Update nrips enabled cache */
5833         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5834 
5835         if (!kvm_vcpu_apicv_active(vcpu))
5836                 return;
5837 
5838         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5839 }
5840 
5841 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5842 {
5843         switch (func) {
5844         case 0x1:
5845                 if (avic)
5846                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5847                 break;
5848         case 0x80000001:
5849                 if (nested)
5850                         entry->ecx |= (1 << 2); /* Set SVM bit */
5851                 break;
5852         case 0x8000000A:
5853                 entry->eax = 1; /* SVM revision 1 */
5854                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5855                                    ASID emulation to nested SVM */
5856                 entry->ecx = 0; /* Reserved */
5857                 entry->edx = 0; /* Per default do not support any
5858                                    additional features */
5859 
5860                 /* Support next_rip if host supports it */
5861                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5862                         entry->edx |= SVM_FEATURE_NRIP;
5863 
5864                 /* Support NPT for the guest if enabled */
5865                 if (npt_enabled)
5866                         entry->edx |= SVM_FEATURE_NPT;
5867 
5868                 break;
5869         case 0x8000001F:
5870                 /* Support memory encryption cpuid if host supports it */
5871                 if (boot_cpu_has(X86_FEATURE_SEV))
5872                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5873                                 &entry->ecx, &entry->edx);
5874 
5875         }
5876 }
5877 
5878 static int svm_get_lpage_level(void)
5879 {
5880         return PT_PDPE_LEVEL;
5881 }
5882 
5883 static bool svm_rdtscp_supported(void)
5884 {
5885         return boot_cpu_has(X86_FEATURE_RDTSCP);
5886 }
5887 
5888 static bool svm_invpcid_supported(void)
5889 {
5890         return false;
5891 }
5892 
5893 static bool svm_mpx_supported(void)
5894 {
5895         return false;
5896 }
5897 
5898 static bool svm_xsaves_supported(void)
5899 {
5900         return false;
5901 }
5902 
5903 static bool svm_umip_emulated(void)
5904 {
5905         return false;
5906 }
5907 
5908 static bool svm_has_wbinvd_exit(void)
5909 {
5910         return true;
5911 }
5912 
5913 #define PRE_EX(exit)  { .exit_code = (exit), \
5914                         .stage = X86_ICPT_PRE_EXCEPT, }
5915 #define POST_EX(exit) { .exit_code = (exit), \
5916                         .stage = X86_ICPT_POST_EXCEPT, }
5917 #define POST_MEM(exit) { .exit_code = (exit), \
5918                         .stage = X86_ICPT_POST_MEMACCESS, }
5919 
5920 static const struct __x86_intercept {
5921         u32 exit_code;
5922         enum x86_intercept_stage stage;
5923 } x86_intercept_map[] = {
5924         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5925         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5926         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5927         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5928         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5929         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5930         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5931         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5932         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5933         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5934         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5935         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5936         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5937         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5938         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5939         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5940         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5941         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5942         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5943         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5944         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5945         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5946         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5947         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5948         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5949         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5950         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5951         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5952         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5953         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5954         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5955         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5956         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5957         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5958         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5959         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5960         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5961         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5962         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5963         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5964         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5965         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5966         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5967         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5968         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5969         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5970 };
5971 
5972 #undef PRE_EX
5973 #undef POST_EX
5974 #undef POST_MEM
5975 
5976 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5977                                struct x86_instruction_info *info,
5978                                enum x86_intercept_stage stage)
5979 {
5980         struct vcpu_svm *svm = to_svm(vcpu);
5981         int vmexit, ret = X86EMUL_CONTINUE;
5982         struct __x86_intercept icpt_info;
5983         struct vmcb *vmcb = svm->vmcb;
5984 
5985         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5986                 goto out;
5987 
5988         icpt_info = x86_intercept_map[info->intercept];
5989 
5990         if (stage != icpt_info.stage)
5991                 goto out;
5992 
5993         switch (icpt_info.exit_code) {
5994         case SVM_EXIT_READ_CR0:
5995                 if (info->intercept == x86_intercept_cr_read)
5996                         icpt_info.exit_code += info->modrm_reg;
5997                 break;
5998         case SVM_EXIT_WRITE_CR0: {
5999                 unsigned long cr0, val;
6000                 u64 intercept;
6001 
6002                 if (info->intercept == x86_intercept_cr_write)
6003                         icpt_info.exit_code += info->modrm_reg;
6004 
6005                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6006                     info->intercept == x86_intercept_clts)
6007                         break;
6008 
6009                 intercept = svm->nested.intercept;
6010 
6011                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6012                         break;
6013 
6014                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6015                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6016 
6017                 if (info->intercept == x86_intercept_lmsw) {
6018                         cr0 &= 0xfUL;
6019                         val &= 0xfUL;
6020                         /* lmsw can't clear PE - catch this here */
6021                         if (cr0 & X86_CR0_PE)
6022                                 val |= X86_CR0_PE;
6023                 }
6024 
6025                 if (cr0 ^ val)
6026                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6027 
6028                 break;
6029         }
6030         case SVM_EXIT_READ_DR0:
6031         case SVM_EXIT_WRITE_DR0:
6032                 icpt_info.exit_code += info->modrm_reg;
6033                 break;
6034         case SVM_EXIT_MSR:
6035                 if (info->intercept == x86_intercept_wrmsr)
6036                         vmcb->control.exit_info_1 = 1;
6037                 else
6038                         vmcb->control.exit_info_1 = 0;
6039                 break;
6040         case SVM_EXIT_PAUSE:
6041                 /*
6042                  * We get this for NOP only, but pause
6043                  * is rep not, check this here
6044                  */
6045                 if (info->rep_prefix != REPE_PREFIX)
6046                         goto out;
6047                 break;
6048         case SVM_EXIT_IOIO: {
6049                 u64 exit_info;
6050                 u32 bytes;
6051 
6052                 if (info->intercept == x86_intercept_in ||
6053                     info->intercept == x86_intercept_ins) {
6054                         exit_info = ((info->src_val & 0xffff) << 16) |
6055                                 SVM_IOIO_TYPE_MASK;
6056                         bytes = info->dst_bytes;
6057                 } else {
6058                         exit_info = (info->dst_val & 0xffff) << 16;
6059                         bytes = info->src_bytes;
6060                 }
6061 
6062                 if (info->intercept == x86_intercept_outs ||
6063                     info->intercept == x86_intercept_ins)
6064                         exit_info |= SVM_IOIO_STR_MASK;
6065 
6066                 if (info->rep_prefix)
6067                         exit_info |= SVM_IOIO_REP_MASK;
6068 
6069                 bytes = min(bytes, 4u);
6070 
6071                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6072 
6073                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6074 
6075                 vmcb->control.exit_info_1 = exit_info;
6076                 vmcb->control.exit_info_2 = info->next_rip;
6077 
6078                 break;
6079         }
6080         default:
6081                 break;
6082         }
6083 
6084         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6085         if (static_cpu_has(X86_FEATURE_NRIPS))
6086                 vmcb->control.next_rip  = info->next_rip;
6087         vmcb->control.exit_code = icpt_info.exit_code;
6088         vmexit = nested_svm_exit_handled(svm);
6089 
6090         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6091                                            : X86EMUL_CONTINUE;
6092 
6093 out:
6094         return ret;
6095 }
6096 
6097 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6098 {
6099         local_irq_enable();
6100         /*
6101          * We must have an instruction with interrupts enabled, so
6102          * the timer interrupt isn't delayed by the interrupt shadow.
6103          */
6104         asm("nop");
6105         local_irq_disable();
6106 }
6107 
6108 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6109 {
6110         if (pause_filter_thresh)
6111                 shrink_ple_window(vcpu);
6112 }
6113 
6114 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6115 {
6116         if (avic_handle_apic_id_update(vcpu) != 0)
6117                 return;
6118         if (avic_handle_dfr_update(vcpu) != 0)
6119                 return;
6120         avic_handle_ldr_update(vcpu);
6121 }
6122 
6123 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6124 {
6125         /* [63:9] are reserved. */
6126         vcpu->arch.mcg_cap &= 0x1ff;
6127 }
6128 
6129 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6130 {
6131         struct vcpu_svm *svm = to_svm(vcpu);
6132 
6133         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6134         if (!gif_set(svm))
6135                 return 0;
6136 
6137         if (is_guest_mode(&svm->vcpu) &&
6138             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6139                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6140                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6141                 svm->nested.exit_required = true;
6142                 return 0;
6143         }
6144 
6145         return 1;
6146 }
6147 
6148 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6149 {
6150         struct vcpu_svm *svm = to_svm(vcpu);
6151         int ret;
6152 
6153         if (is_guest_mode(vcpu)) {
6154                 /* FED8h - SVM Guest */
6155                 put_smstate(u64, smstate, 0x7ed8, 1);
6156                 /* FEE0h - SVM Guest VMCB Physical Address */
6157                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6158 
6159                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6160                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6161                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6162 
6163                 ret = nested_svm_vmexit(svm);
6164                 if (ret)
6165                         return ret;
6166         }
6167         return 0;
6168 }
6169 
6170 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6171 {
6172         struct vcpu_svm *svm = to_svm(vcpu);
6173         struct vmcb *nested_vmcb;
6174         struct page *page;
6175         struct {
6176                 u64 guest;
6177                 u64 vmcb;
6178         } svm_state_save;
6179         int ret;
6180 
6181         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6182                                   sizeof(svm_state_save));
6183         if (ret)
6184                 return ret;
6185 
6186         if (svm_state_save.guest) {
6187                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6188                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6189                 if (nested_vmcb)
6190                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6191                 else
6192                         ret = 1;
6193                 vcpu->arch.hflags |= HF_SMM_MASK;
6194         }
6195         return ret;
6196 }
6197 
6198 static int enable_smi_window(struct kvm_vcpu *vcpu)
6199 {
6200         struct vcpu_svm *svm = to_svm(vcpu);
6201 
6202         if (!gif_set(svm)) {
6203                 if (vgif_enabled(svm))
6204                         set_intercept(svm, INTERCEPT_STGI);
6205                 /* STGI will cause a vm exit */
6206                 return 1;
6207         }
6208         return 0;
6209 }
6210 
6211 static int sev_asid_new(void)
6212 {
6213         int pos;
6214 
6215         /*
6216          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6217          */
6218         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6219         if (pos >= max_sev_asid)
6220                 return -EBUSY;
6221 
6222         set_bit(pos, sev_asid_bitmap);
6223         return pos + 1;
6224 }
6225 
6226 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6227 {
6228         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6229         int asid, ret;
6230 
6231         ret = -EBUSY;
6232         asid = sev_asid_new();
6233         if (asid < 0)
6234                 return ret;
6235 
6236         ret = sev_platform_init(&argp->error);
6237         if (ret)
6238                 goto e_free;
6239 
6240         sev->active = true;
6241         sev->asid = asid;
6242         INIT_LIST_HEAD(&sev->regions_list);
6243 
6244         return 0;
6245 
6246 e_free:
6247         __sev_asid_free(asid);
6248         return ret;
6249 }
6250 
6251 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6252 {
6253         struct sev_data_activate *data;
6254         int asid = sev_get_asid(kvm);
6255         int ret;
6256 
6257         wbinvd_on_all_cpus();
6258 
6259         ret = sev_guest_df_flush(error);
6260         if (ret)
6261                 return ret;
6262 
6263         data = kzalloc(sizeof(*data), GFP_KERNEL);
6264         if (!data)
6265                 return -ENOMEM;
6266 
6267         /* activate ASID on the given handle */
6268         data->handle = handle;
6269         data->asid   = asid;
6270         ret = sev_guest_activate(data, error);
6271         kfree(data);
6272 
6273         return ret;
6274 }
6275 
6276 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6277 {
6278         struct fd f;
6279         int ret;
6280 
6281         f = fdget(fd);
6282         if (!f.file)
6283                 return -EBADF;
6284 
6285         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6286 
6287         fdput(f);
6288         return ret;
6289 }
6290 
6291 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6292 {
6293         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6294 
6295         return __sev_issue_cmd(sev->fd, id, data, error);
6296 }
6297 
6298 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6299 {
6300         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6301         struct sev_data_launch_start *start;
6302         struct kvm_sev_launch_start params;
6303         void *dh_blob, *session_blob;
6304         int *error = &argp->error;
6305         int ret;
6306 
6307         if (!sev_guest(kvm))
6308                 return -ENOTTY;
6309 
6310         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6311                 return -EFAULT;
6312 
6313         start = kzalloc(sizeof(*start), GFP_KERNEL);
6314         if (!start)
6315                 return -ENOMEM;
6316 
6317         dh_blob = NULL;
6318         if (params.dh_uaddr) {
6319                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6320                 if (IS_ERR(dh_blob)) {
6321                         ret = PTR_ERR(dh_blob);
6322                         goto e_free;
6323                 }
6324 
6325                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6326                 start->dh_cert_len = params.dh_len;
6327         }
6328 
6329         session_blob = NULL;
6330         if (params.session_uaddr) {
6331                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6332                 if (IS_ERR(session_blob)) {
6333                         ret = PTR_ERR(session_blob);
6334                         goto e_free_dh;
6335                 }
6336 
6337                 start->session_address = __sme_set(__pa(session_blob));
6338                 start->session_len = params.session_len;
6339         }
6340 
6341         start->handle = params.handle;
6342         start->policy = params.policy;
6343 
6344         /* create memory encryption context */
6345         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6346         if (ret)
6347                 goto e_free_session;
6348 
6349         /* Bind ASID to this guest */
6350         ret = sev_bind_asid(kvm, start->handle, error);
6351         if (ret)
6352                 goto e_free_session;
6353 
6354         /* return handle to userspace */
6355         params.handle = start->handle;
6356         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6357                 sev_unbind_asid(kvm, start->handle);
6358                 ret = -EFAULT;
6359                 goto e_free_session;
6360         }
6361 
6362         sev->handle = start->handle;
6363         sev->fd = argp->sev_fd;
6364 
6365 e_free_session:
6366         kfree(session_blob);
6367 e_free_dh:
6368         kfree(dh_blob);
6369 e_free:
6370         kfree(start);
6371         return ret;
6372 }
6373 
6374 static int get_num_contig_pages(int idx, struct page **inpages,
6375                                 unsigned long npages)
6376 {
6377         unsigned long paddr, next_paddr;
6378         int i = idx + 1, pages = 1;
6379 
6380         /* find the number of contiguous pages starting from idx */
6381         paddr = __sme_page_pa(inpages[idx]);
6382         while (i < npages) {
6383                 next_paddr = __sme_page_pa(inpages[i++]);
6384                 if ((paddr + PAGE_SIZE) == next_paddr) {
6385                         pages++;
6386                         paddr = next_paddr;
6387                         continue;
6388                 }
6389                 break;
6390         }
6391 
6392         return pages;
6393 }
6394 
6395 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6396 {
6397         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6398         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6399         struct kvm_sev_launch_update_data params;
6400         struct sev_data_launch_update_data *data;
6401         struct page **inpages;
6402         int i, ret, pages;
6403 
6404         if (!sev_guest(kvm))
6405                 return -ENOTTY;
6406 
6407         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6408                 return -EFAULT;
6409 
6410         data = kzalloc(sizeof(*data), GFP_KERNEL);
6411         if (!data)
6412                 return -ENOMEM;
6413 
6414         vaddr = params.uaddr;
6415         size = params.len;
6416         vaddr_end = vaddr + size;
6417 
6418         /* Lock the user memory. */
6419         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6420         if (!inpages) {
6421                 ret = -ENOMEM;
6422                 goto e_free;
6423         }
6424 
6425         /*
6426          * The LAUNCH_UPDATE command will perform in-place encryption of the
6427          * memory content (i.e it will write the same memory region with C=1).
6428          * It's possible that the cache may contain the data with C=0, i.e.,
6429          * unencrypted so invalidate it first.
6430          */
6431         sev_clflush_pages(inpages, npages);
6432 
6433         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6434                 int offset, len;
6435 
6436                 /*
6437                  * If the user buffer is not page-aligned, calculate the offset
6438                  * within the page.
6439                  */
6440                 offset = vaddr & (PAGE_SIZE - 1);
6441 
6442                 /* Calculate the number of pages that can be encrypted in one go. */
6443                 pages = get_num_contig_pages(i, inpages, npages);
6444 
6445                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6446 
6447                 data->handle = sev->handle;
6448                 data->len = len;
6449                 data->address = __sme_page_pa(inpages[i]) + offset;
6450                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6451                 if (ret)
6452                         goto e_unpin;
6453 
6454                 size -= len;
6455                 next_vaddr = vaddr + len;
6456         }
6457 
6458 e_unpin:
6459         /* content of memory is updated, mark pages dirty */
6460         for (i = 0; i < npages; i++) {
6461                 set_page_dirty_lock(inpages[i]);
6462                 mark_page_accessed(inpages[i]);
6463         }
6464         /* unlock the user pages */
6465         sev_unpin_memory(kvm, inpages, npages);
6466 e_free:
6467         kfree(data);
6468         return ret;
6469 }
6470 
6471 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6472 {
6473         void __user *measure = (void __user *)(uintptr_t)argp->data;
6474         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6475         struct sev_data_launch_measure *data;
6476         struct kvm_sev_launch_measure params;
6477         void __user *p = NULL;
6478         void *blob = NULL;
6479         int ret;
6480 
6481         if (!sev_guest(kvm))
6482                 return -ENOTTY;
6483 
6484         if (copy_from_user(&params, measure, sizeof(params)))
6485                 return -EFAULT;
6486 
6487         data = kzalloc(sizeof(*data), GFP_KERNEL);
6488         if (!data)
6489                 return -ENOMEM;
6490 
6491         /* User wants to query the blob length */
6492         if (!params.len)
6493                 goto cmd;
6494 
6495         p = (void __user *)(uintptr_t)params.uaddr;
6496         if (p) {
6497                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6498                         ret = -EINVAL;
6499                         goto e_free;
6500                 }
6501 
6502                 ret = -ENOMEM;
6503                 blob = kmalloc(params.len, GFP_KERNEL);
6504                 if (!blob)
6505                         goto e_free;
6506 
6507                 data->address = __psp_pa(blob);
6508                 data->len = params.len;
6509         }
6510 
6511 cmd:
6512         data->handle = sev->handle;
6513         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6514 
6515         /*
6516          * If we query the session length, FW responded with expected data.
6517          */
6518         if (!params.len)
6519                 goto done;
6520 
6521         if (ret)
6522                 goto e_free_blob;
6523 
6524         if (blob) {
6525                 if (copy_to_user(p, blob, params.len))
6526                         ret = -EFAULT;
6527         }
6528 
6529 done:
6530         params.len = data->len;
6531         if (copy_to_user(measure, &params, sizeof(params)))
6532                 ret = -EFAULT;
6533 e_free_blob:
6534         kfree(blob);
6535 e_free:
6536         kfree(data);
6537         return ret;
6538 }
6539 
6540 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6541 {
6542         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6543         struct sev_data_launch_finish *data;
6544         int ret;
6545 
6546         if (!sev_guest(kvm))
6547                 return -ENOTTY;
6548 
6549         data = kzalloc(sizeof(*data), GFP_KERNEL);
6550         if (!data)
6551                 return -ENOMEM;
6552 
6553         data->handle = sev->handle;
6554         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6555 
6556         kfree(data);
6557         return ret;
6558 }
6559 
6560 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6561 {
6562         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6563         struct kvm_sev_guest_status params;
6564         struct sev_data_guest_status *data;
6565         int ret;
6566 
6567         if (!sev_guest(kvm))
6568                 return -ENOTTY;
6569 
6570         data = kzalloc(sizeof(*data), GFP_KERNEL);
6571         if (!data)
6572                 return -ENOMEM;
6573 
6574         data->handle = sev->handle;
6575         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6576         if (ret)
6577                 goto e_free;
6578 
6579         params.policy = data->policy;
6580         params.state = data->state;
6581         params.handle = data->handle;
6582 
6583         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6584                 ret = -EFAULT;
6585 e_free:
6586         kfree(data);
6587         return ret;
6588 }
6589 
6590 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6591                                unsigned long dst, int size,
6592                                int *error, bool enc)
6593 {
6594         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6595         struct sev_data_dbg *data;
6596         int ret;
6597 
6598         data = kzalloc(sizeof(*data), GFP_KERNEL);
6599         if (!data)
6600                 return -ENOMEM;
6601 
6602         data->handle = sev->handle;
6603         data->dst_addr = dst;
6604         data->src_addr = src;
6605         data->len = size;
6606 
6607         ret = sev_issue_cmd(kvm,
6608                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6609                             data, error);
6610         kfree(data);
6611         return ret;
6612 }
6613 
6614 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6615                              unsigned long dst_paddr, int sz, int *err)
6616 {
6617         int offset;
6618 
6619         /*
6620          * Its safe to read more than we are asked, caller should ensure that
6621          * destination has enough space.
6622          */
6623         src_paddr = round_down(src_paddr, 16);
6624         offset = src_paddr & 15;
6625         sz = round_up(sz + offset, 16);
6626 
6627         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6628 }
6629 
6630 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6631                                   unsigned long __user dst_uaddr,
6632                                   unsigned long dst_paddr,
6633                                   int size, int *err)
6634 {
6635         struct page *tpage = NULL;
6636         int ret, offset;
6637 
6638         /* if inputs are not 16-byte then use intermediate buffer */
6639         if (!IS_ALIGNED(dst_paddr, 16) ||
6640             !IS_ALIGNED(paddr,     16) ||
6641             !IS_ALIGNED(size,      16)) {
6642                 tpage = (void *)alloc_page(GFP_KERNEL);
6643                 if (!tpage)
6644                         return -ENOMEM;
6645 
6646                 dst_paddr = __sme_page_pa(tpage);
6647         }
6648 
6649         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6650         if (ret)
6651                 goto e_free;
6652 
6653         if (tpage) {
6654                 offset = paddr & 15;
6655                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6656                                  page_address(tpage) + offset, size))
6657                         ret = -EFAULT;
6658         }
6659 
6660 e_free:
6661         if (tpage)
6662                 __free_page(tpage);
6663 
6664         return ret;
6665 }
6666 
6667 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6668                                   unsigned long __user vaddr,
6669                                   unsigned long dst_paddr,
6670                                   unsigned long __user dst_vaddr,
6671                                   int size, int *error)
6672 {
6673         struct page *src_tpage = NULL;
6674         struct page *dst_tpage = NULL;
6675         int ret, len = size;
6676 
6677         /* If source buffer is not aligned then use an intermediate buffer */
6678         if (!IS_ALIGNED(vaddr, 16)) {
6679                 src_tpage = alloc_page(GFP_KERNEL);
6680                 if (!src_tpage)
6681                         return -ENOMEM;
6682 
6683                 if (copy_from_user(page_address(src_tpage),
6684                                 (void __user *)(uintptr_t)vaddr, size)) {
6685                         __free_page(src_tpage);
6686                         return -EFAULT;
6687                 }
6688 
6689                 paddr = __sme_page_pa(src_tpage);
6690         }
6691 
6692         /*
6693          *  If destination buffer or length is not aligned then do read-modify-write:
6694          *   - decrypt destination in an intermediate buffer
6695          *   - copy the source buffer in an intermediate buffer
6696          *   - use the intermediate buffer as source buffer
6697          */
6698         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6699                 int dst_offset;
6700 
6701                 dst_tpage = alloc_page(GFP_KERNEL);
6702                 if (!dst_tpage) {
6703                         ret = -ENOMEM;
6704                         goto e_free;
6705                 }
6706 
6707                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6708                                         __sme_page_pa(dst_tpage), size, error);
6709                 if (ret)
6710                         goto e_free;
6711 
6712                 /*
6713                  *  If source is kernel buffer then use memcpy() otherwise
6714                  *  copy_from_user().
6715                  */
6716                 dst_offset = dst_paddr & 15;
6717 
6718                 if (src_tpage)
6719                         memcpy(page_address(dst_tpage) + dst_offset,
6720                                page_address(src_tpage), size);
6721                 else {
6722                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6723                                            (void __user *)(uintptr_t)vaddr, size)) {
6724                                 ret = -EFAULT;
6725                                 goto e_free;
6726                         }
6727                 }
6728 
6729                 paddr = __sme_page_pa(dst_tpage);
6730                 dst_paddr = round_down(dst_paddr, 16);
6731                 len = round_up(size, 16);
6732         }
6733 
6734         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6735 
6736 e_free:
6737         if (src_tpage)
6738                 __free_page(src_tpage);
6739         if (dst_tpage)
6740                 __free_page(dst_tpage);
6741         return ret;
6742 }
6743 
6744 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6745 {
6746         unsigned long vaddr, vaddr_end, next_vaddr;
6747         unsigned long dst_vaddr, dst_vaddr_end;
6748         struct page **src_p, **dst_p;
6749         struct kvm_sev_dbg debug;
6750         unsigned long n;
6751         int ret, size;
6752 
6753         if (!sev_guest(kvm))
6754                 return -ENOTTY;
6755 
6756         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6757                 return -EFAULT;
6758 
6759         vaddr = debug.src_uaddr;
6760         size = debug.len;
6761         vaddr_end = vaddr + size;
6762         dst_vaddr = debug.dst_uaddr;
6763         dst_vaddr_end = dst_vaddr + size;
6764 
6765         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6766                 int len, s_off, d_off;
6767 
6768                 /* lock userspace source and destination page */
6769                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6770                 if (!src_p)
6771                         return -EFAULT;
6772 
6773                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6774                 if (!dst_p) {
6775                         sev_unpin_memory(kvm, src_p, n);
6776                         return -EFAULT;
6777                 }
6778 
6779                 /*
6780                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6781                  * memory content (i.e it will write the same memory region with C=1).
6782                  * It's possible that the cache may contain the data with C=0, i.e.,
6783                  * unencrypted so invalidate it first.
6784                  */
6785                 sev_clflush_pages(src_p, 1);
6786                 sev_clflush_pages(dst_p, 1);
6787 
6788                 /*
6789                  * Since user buffer may not be page aligned, calculate the
6790                  * offset within the page.
6791                  */
6792                 s_off = vaddr & ~PAGE_MASK;
6793                 d_off = dst_vaddr & ~PAGE_MASK;
6794                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6795 
6796                 if (dec)
6797                         ret = __sev_dbg_decrypt_user(kvm,
6798                                                      __sme_page_pa(src_p[0]) + s_off,
6799                                                      dst_vaddr,
6800                                                      __sme_page_pa(dst_p[0]) + d_off,
6801                                                      len, &argp->error);
6802                 else
6803                         ret = __sev_dbg_encrypt_user(kvm,
6804                                                      __sme_page_pa(src_p[0]) + s_off,
6805                                                      vaddr,
6806                                                      __sme_page_pa(dst_p[0]) + d_off,
6807                                                      dst_vaddr,
6808                                                      len, &argp->error);
6809 
6810                 sev_unpin_memory(kvm, src_p, 1);
6811                 sev_unpin_memory(kvm, dst_p, 1);
6812 
6813                 if (ret)
6814                         goto err;
6815 
6816                 next_vaddr = vaddr + len;
6817                 dst_vaddr = dst_vaddr + len;
6818                 size -= len;
6819         }
6820 err:
6821         return ret;
6822 }
6823 
6824 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6825 {
6826         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6827         struct sev_data_launch_secret *data;
6828         struct kvm_sev_launch_secret params;
6829         struct page **pages;
6830         void *blob, *hdr;
6831         unsigned long n;
6832         int ret, offset;
6833 
6834         if (!sev_guest(kvm))
6835                 return -ENOTTY;
6836 
6837         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6838                 return -EFAULT;
6839 
6840         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6841         if (!pages)
6842                 return -ENOMEM;
6843 
6844         /*
6845          * The secret must be copied into contiguous memory region, lets verify
6846          * that userspace memory pages are contiguous before we issue command.
6847          */
6848         if (get_num_contig_pages(0, pages, n) != n) {
6849                 ret = -EINVAL;
6850                 goto e_unpin_memory;
6851         }
6852 
6853         ret = -ENOMEM;
6854         data = kzalloc(sizeof(*data), GFP_KERNEL);
6855         if (!data)
6856                 goto e_unpin_memory;
6857 
6858         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6859         data->guest_address = __sme_page_pa(pages[0]) + offset;
6860         data->guest_len = params.guest_len;
6861 
6862         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6863         if (IS_ERR(blob)) {
6864                 ret = PTR_ERR(blob);
6865                 goto e_free;
6866         }
6867 
6868         data->trans_address = __psp_pa(blob);
6869         data->trans_len = params.trans_len;
6870 
6871         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6872         if (IS_ERR(hdr)) {
6873                 ret = PTR_ERR(hdr);
6874                 goto e_free_blob;
6875         }
6876         data->hdr_address = __psp_pa(hdr);
6877         data->hdr_len = params.hdr_len;
6878 
6879         data->handle = sev->handle;
6880         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6881 
6882         kfree(hdr);
6883 
6884 e_free_blob:
6885         kfree(blob);
6886 e_free:
6887         kfree(data);
6888 e_unpin_memory:
6889         sev_unpin_memory(kvm, pages, n);
6890         return ret;
6891 }
6892 
6893 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6894 {
6895         struct kvm_sev_cmd sev_cmd;
6896         int r;
6897 
6898         if (!svm_sev_enabled())
6899                 return -ENOTTY;
6900 
6901         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6902                 return -EFAULT;
6903 
6904         mutex_lock(&kvm->lock);
6905 
6906         switch (sev_cmd.id) {
6907         case KVM_SEV_INIT:
6908                 r = sev_guest_init(kvm, &sev_cmd);
6909                 break;
6910         case KVM_SEV_LAUNCH_START:
6911                 r = sev_launch_start(kvm, &sev_cmd);
6912                 break;
6913         case KVM_SEV_LAUNCH_UPDATE_DATA:
6914                 r = sev_launch_update_data(kvm, &sev_cmd);
6915                 break;
6916         case KVM_SEV_LAUNCH_MEASURE:
6917                 r = sev_launch_measure(kvm, &sev_cmd);
6918                 break;
6919         case KVM_SEV_LAUNCH_FINISH:
6920                 r = sev_launch_finish(kvm, &sev_cmd);
6921                 break;
6922         case KVM_SEV_GUEST_STATUS:
6923                 r = sev_guest_status(kvm, &sev_cmd);
6924                 break;
6925         case KVM_SEV_DBG_DECRYPT:
6926                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6927                 break;
6928         case KVM_SEV_DBG_ENCRYPT:
6929                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6930                 break;
6931         case KVM_SEV_LAUNCH_SECRET:
6932                 r = sev_launch_secret(kvm, &sev_cmd);
6933                 break;
6934         default:
6935                 r = -EINVAL;
6936                 goto out;
6937         }
6938 
6939         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6940                 r = -EFAULT;
6941 
6942 out:
6943         mutex_unlock(&kvm->lock);
6944         return r;
6945 }
6946 
6947 static int svm_register_enc_region(struct kvm *kvm,
6948                                    struct kvm_enc_region *range)
6949 {
6950         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6951         struct enc_region *region;
6952         int ret = 0;
6953 
6954         if (!sev_guest(kvm))
6955                 return -ENOTTY;
6956 
6957         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6958                 return -EINVAL;
6959 
6960         region = kzalloc(sizeof(*region), GFP_KERNEL);
6961         if (!region)
6962                 return -ENOMEM;
6963 
6964         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6965         if (!region->pages) {
6966                 ret = -ENOMEM;
6967                 goto e_free;
6968         }
6969 
6970         /*
6971          * The guest may change the memory encryption attribute from C=0 -> C=1
6972          * or vice versa for this memory range. Lets make sure caches are
6973          * flushed to ensure that guest data gets written into memory with
6974          * correct C-bit.
6975          */
6976         sev_clflush_pages(region->pages, region->npages);
6977 
6978         region->uaddr = range->addr;
6979         region->size = range->size;
6980 
6981         mutex_lock(&kvm->lock);
6982         list_add_tail(&region->list, &sev->regions_list);
6983         mutex_unlock(&kvm->lock);
6984 
6985         return ret;
6986 
6987 e_free:
6988         kfree(region);
6989         return ret;
6990 }
6991 
6992 static struct enc_region *
6993 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6994 {
6995         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6996         struct list_head *head = &sev->regions_list;
6997         struct enc_region *i;
6998 
6999         list_for_each_entry(i, head, list) {
7000                 if (i->uaddr == range->addr &&
7001                     i->size == range->size)
7002                         return i;
7003         }
7004 
7005         return NULL;
7006 }
7007 
7008 
7009 static int svm_unregister_enc_region(struct kvm *kvm,
7010                                      struct kvm_enc_region *range)
7011 {
7012         struct enc_region *region;
7013         int ret;
7014 
7015         mutex_lock(&kvm->lock);
7016 
7017         if (!sev_guest(kvm)) {
7018                 ret = -ENOTTY;
7019                 goto failed;
7020         }
7021 
7022         region = find_enc_region(kvm, range);
7023         if (!region) {
7024                 ret = -EINVAL;
7025                 goto failed;
7026         }
7027 
7028         __unregister_enc_region_locked(kvm, region);
7029 
7030         mutex_unlock(&kvm->lock);
7031         return 0;
7032 
7033 failed:
7034         mutex_unlock(&kvm->lock);
7035         return ret;
7036 }
7037 
7038 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7039         .cpu_has_kvm_support = has_svm,
7040         .disabled_by_bios = is_disabled,
7041         .hardware_setup = svm_hardware_setup,
7042         .hardware_unsetup = svm_hardware_unsetup,
7043         .check_processor_compatibility = svm_check_processor_compat,
7044         .hardware_enable = svm_hardware_enable,
7045         .hardware_disable = svm_hardware_disable,
7046         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7047         .has_emulated_msr = svm_has_emulated_msr,
7048 
7049         .vcpu_create = svm_create_vcpu,
7050         .vcpu_free = svm_free_vcpu,
7051         .vcpu_reset = svm_vcpu_reset,
7052 
7053         .vm_alloc = svm_vm_alloc,
7054         .vm_free = svm_vm_free,
7055         .vm_init = avic_vm_init,
7056         .vm_destroy = svm_vm_destroy,
7057 
7058         .prepare_guest_switch = svm_prepare_guest_switch,
7059         .vcpu_load = svm_vcpu_load,
7060         .vcpu_put = svm_vcpu_put,
7061         .vcpu_blocking = svm_vcpu_blocking,
7062         .vcpu_unblocking = svm_vcpu_unblocking,
7063 
7064         .update_bp_intercept = update_bp_intercept,
7065         .get_msr_feature = svm_get_msr_feature,
7066         .get_msr = svm_get_msr,
7067         .set_msr = svm_set_msr,
7068         .get_segment_base = svm_get_segment_base,
7069         .get_segment = svm_get_segment,
7070         .set_segment = svm_set_segment,
7071         .get_cpl = svm_get_cpl,
7072         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7073         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7074         .decache_cr3 = svm_decache_cr3,
7075         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7076         .set_cr0 = svm_set_cr0,
7077         .set_cr3 = svm_set_cr3,
7078         .set_cr4 = svm_set_cr4,
7079         .set_efer = svm_set_efer,
7080         .get_idt = svm_get_idt,
7081         .set_idt = svm_set_idt,
7082         .get_gdt = svm_get_gdt,
7083         .set_gdt = svm_set_gdt,
7084         .get_dr6 = svm_get_dr6,
7085         .set_dr6 = svm_set_dr6,
7086         .set_dr7 = svm_set_dr7,
7087         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7088         .cache_reg = svm_cache_reg,
7089         .get_rflags = svm_get_rflags,
7090         .set_rflags = svm_set_rflags,
7091 
7092         .tlb_flush = svm_flush_tlb,
7093 
7094         .run = svm_vcpu_run,
7095         .handle_exit = handle_exit,
7096         .skip_emulated_instruction = skip_emulated_instruction,
7097         .set_interrupt_shadow = svm_set_interrupt_shadow,
7098         .get_interrupt_shadow = svm_get_interrupt_shadow,
7099         .patch_hypercall = svm_patch_hypercall,
7100         .set_irq = svm_set_irq,
7101         .set_nmi = svm_inject_nmi,
7102         .queue_exception = svm_queue_exception,
7103         .cancel_injection = svm_cancel_injection,
7104         .interrupt_allowed = svm_interrupt_allowed,
7105         .nmi_allowed = svm_nmi_allowed,
7106         .get_nmi_mask = svm_get_nmi_mask,
7107         .set_nmi_mask = svm_set_nmi_mask,
7108         .enable_nmi_window = enable_nmi_window,
7109         .enable_irq_window = enable_irq_window,
7110         .update_cr8_intercept = update_cr8_intercept,
7111         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7112         .get_enable_apicv = svm_get_enable_apicv,
7113         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7114         .load_eoi_exitmap = svm_load_eoi_exitmap,
7115         .hwapic_irr_update = svm_hwapic_irr_update,
7116         .hwapic_isr_update = svm_hwapic_isr_update,
7117         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7118         .apicv_post_state_restore = avic_post_state_restore,
7119 
7120         .set_tss_addr = svm_set_tss_addr,
7121         .set_identity_map_addr = svm_set_identity_map_addr,
7122         .get_tdp_level = get_npt_level,
7123         .get_mt_mask = svm_get_mt_mask,
7124 
7125         .get_exit_info = svm_get_exit_info,
7126 
7127         .get_lpage_level = svm_get_lpage_level,
7128 
7129         .cpuid_update = svm_cpuid_update,
7130 
7131         .rdtscp_supported = svm_rdtscp_supported,
7132         .invpcid_supported = svm_invpcid_supported,
7133         .mpx_supported = svm_mpx_supported,
7134         .xsaves_supported = svm_xsaves_supported,
7135         .umip_emulated = svm_umip_emulated,
7136 
7137         .set_supported_cpuid = svm_set_supported_cpuid,
7138 
7139         .has_wbinvd_exit = svm_has_wbinvd_exit,
7140 
7141         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7142         .write_tsc_offset = svm_write_tsc_offset,
7143 
7144         .set_tdp_cr3 = set_tdp_cr3,
7145 
7146         .check_intercept = svm_check_intercept,
7147         .handle_external_intr = svm_handle_external_intr,
7148 
7149         .sched_in = svm_sched_in,
7150 
7151         .pmu_ops = &amd_pmu_ops,
7152         .deliver_posted_interrupt = svm_deliver_avic_intr,
7153         .update_pi_irte = svm_update_pi_irte,
7154         .setup_mce = svm_setup_mce,
7155 
7156         .smi_allowed = svm_smi_allowed,
7157         .pre_enter_smm = svm_pre_enter_smm,
7158         .pre_leave_smm = svm_pre_leave_smm,
7159         .enable_smi_window = enable_smi_window,
7160 
7161         .mem_enc_op = svm_mem_enc_op,
7162         .mem_enc_reg_region = svm_register_enc_region,
7163         .mem_enc_unreg_region = svm_unregister_enc_region,
7164 };
7165 
7166 static int __init svm_init(void)
7167 {
7168         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7169                         __alignof__(struct vcpu_svm), THIS_MODULE);
7170 }
7171 
7172 static void __exit svm_exit(void)
7173 {
7174         kvm_exit();
7175 }
7176 
7177 module_init(svm_init)
7178 module_exit(svm_exit)
7179 

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