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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/vmx.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * Copyright (C) 2006 Qumranet, Inc.
  8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  9  *
 10  * Authors:
 11  *   Avi Kivity   <avi@qumranet.com>
 12  *   Yaniv Kamay  <yaniv@qumranet.com>
 13  *
 14  * This work is licensed under the terms of the GNU GPL, version 2.  See
 15  * the COPYING file in the top-level directory.
 16  *
 17  */
 18 
 19 #include "irq.h"
 20 #include "mmu.h"
 21 #include "cpuid.h"
 22 #include "lapic.h"
 23 
 24 #include <linux/kvm_host.h>
 25 #include <linux/module.h>
 26 #include <linux/kernel.h>
 27 #include <linux/mm.h>
 28 #include <linux/highmem.h>
 29 #include <linux/sched.h>
 30 #include <linux/moduleparam.h>
 31 #include <linux/mod_devicetable.h>
 32 #include <linux/trace_events.h>
 33 #include <linux/slab.h>
 34 #include <linux/tboot.h>
 35 #include <linux/hrtimer.h>
 36 #include <linux/frame.h>
 37 #include <linux/nospec.h>
 38 #include "kvm_cache_regs.h"
 39 #include "x86.h"
 40 
 41 #include <asm/cpu.h>
 42 #include <asm/io.h>
 43 #include <asm/desc.h>
 44 #include <asm/vmx.h>
 45 #include <asm/virtext.h>
 46 #include <asm/mce.h>
 47 #include <asm/fpu/internal.h>
 48 #include <asm/perf_event.h>
 49 #include <asm/debugreg.h>
 50 #include <asm/kexec.h>
 51 #include <asm/apic.h>
 52 #include <asm/irq_remapping.h>
 53 #include <asm/mmu_context.h>
 54 #include <asm/spec-ctrl.h>
 55 #include <asm/mshyperv.h>
 56 
 57 #include "trace.h"
 58 #include "pmu.h"
 59 #include "vmx_evmcs.h"
 60 
 61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 62 #define __ex_clear(x, reg) \
 63         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
 64 
 65 MODULE_AUTHOR("Qumranet");
 66 MODULE_LICENSE("GPL");
 67 
 68 static const struct x86_cpu_id vmx_cpu_id[] = {
 69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
 70         {}
 71 };
 72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
 73 
 74 static bool __read_mostly enable_vpid = 1;
 75 module_param_named(vpid, enable_vpid, bool, 0444);
 76 
 77 static bool __read_mostly enable_vnmi = 1;
 78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
 79 
 80 static bool __read_mostly flexpriority_enabled = 1;
 81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
 82 
 83 static bool __read_mostly enable_ept = 1;
 84 module_param_named(ept, enable_ept, bool, S_IRUGO);
 85 
 86 static bool __read_mostly enable_unrestricted_guest = 1;
 87 module_param_named(unrestricted_guest,
 88                         enable_unrestricted_guest, bool, S_IRUGO);
 89 
 90 static bool __read_mostly enable_ept_ad_bits = 1;
 91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
 92 
 93 static bool __read_mostly emulate_invalid_guest_state = true;
 94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 95 
 96 static bool __read_mostly fasteoi = 1;
 97 module_param(fasteoi, bool, S_IRUGO);
 98 
 99 static bool __read_mostly enable_apicv = 1;
100 module_param(enable_apicv, bool, S_IRUGO);
101 
102 static bool __read_mostly enable_shadow_vmcs = 1;
103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
104 /*
105  * If nested=1, nested virtualization is supported, i.e., guests may use
106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107  * use VMX instructions.
108  */
109 static bool __read_mostly nested = 0;
110 module_param(nested, bool, S_IRUGO);
111 
112 static u64 __read_mostly host_xss;
113 
114 static bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
116 
117 #define MSR_TYPE_R      1
118 #define MSR_TYPE_W      2
119 #define MSR_TYPE_RW     3
120 
121 #define MSR_BITMAP_MODE_X2APIC          1
122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
123 #define MSR_BITMAP_MODE_LM              4
124 
125 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
126 
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
128 static int __read_mostly cpu_preemption_timer_multi;
129 static bool __read_mostly enable_preemption_timer = 1;
130 #ifdef CONFIG_X86_64
131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
132 #endif
133 
134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON                            \
137         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
138          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS                                      \
140         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
141          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
142 
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
146 
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
148 
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
150 
151 /*
152  * Hyper-V requires all of these, so mark them as supported even though
153  * they are just treated the same as all-context.
154  */
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
156         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
157         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
158         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
159         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
160 
161 /*
162  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163  * ple_gap:    upper bound on the amount of time between two successive
164  *             executions of PAUSE in a loop. Also indicate if ple enabled.
165  *             According to test, this time is usually smaller than 128 cycles.
166  * ple_window: upper bound on the amount of time a guest is allowed to execute
167  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
168  *             less than 2^12 cycles
169  * Time is measured based on a counter that runs at the same rate as the TSC,
170  * refer SDM volume 3b section 21.6.13 & 22.1.3.
171  */
172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
173 
174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175 module_param(ple_window, uint, 0444);
176 
177 /* Default doubles per-vcpu window every exit. */
178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
179 module_param(ple_window_grow, uint, 0444);
180 
181 /* Default resets per-vcpu window every exit to ple_window. */
182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
183 module_param(ple_window_shrink, uint, 0444);
184 
185 /* Default is to compute the maximum so we can never overflow. */
186 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187 module_param(ple_window_max, uint, 0444);
188 
189 extern const ulong vmx_return;
190 
191 struct kvm_vmx {
192         struct kvm kvm;
193 
194         unsigned int tss_addr;
195         bool ept_identity_pagetable_done;
196         gpa_t ept_identity_map_addr;
197 };
198 
199 #define NR_AUTOLOAD_MSRS 8
200 
201 struct vmcs {
202         u32 revision_id;
203         u32 abort;
204         char data[0];
205 };
206 
207 /*
208  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
209  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
210  * loaded on this CPU (so we can clear them if the CPU goes down).
211  */
212 struct loaded_vmcs {
213         struct vmcs *vmcs;
214         struct vmcs *shadow_vmcs;
215         int cpu;
216         bool launched;
217         bool nmi_known_unmasked;
218         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
219         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
220         /* Support for vnmi-less CPUs */
221         int soft_vnmi_blocked;
222         ktime_t entry_time;
223         s64 vnmi_blocked_time;
224         unsigned long *msr_bitmap;
225         struct list_head loaded_vmcss_on_cpu_link;
226 };
227 
228 struct shared_msr_entry {
229         unsigned index;
230         u64 data;
231         u64 mask;
232 };
233 
234 /*
235  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
236  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
237  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
238  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
239  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
240  * More than one of these structures may exist, if L1 runs multiple L2 guests.
241  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
242  * underlying hardware which will be used to run L2.
243  * This structure is packed to ensure that its layout is identical across
244  * machines (necessary for live migration).
245  *
246  * IMPORTANT: Changing the layout of existing fields in this structure
247  * will break save/restore compatibility with older kvm releases. When
248  * adding new fields, either use space in the reserved padding* arrays
249  * or add the new fields to the end of the structure.
250  */
251 typedef u64 natural_width;
252 struct __packed vmcs12 {
253         /* According to the Intel spec, a VMCS region must start with the
254          * following two fields. Then follow implementation-specific data.
255          */
256         u32 revision_id;
257         u32 abort;
258 
259         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
260         u32 padding[7]; /* room for future expansion */
261 
262         u64 io_bitmap_a;
263         u64 io_bitmap_b;
264         u64 msr_bitmap;
265         u64 vm_exit_msr_store_addr;
266         u64 vm_exit_msr_load_addr;
267         u64 vm_entry_msr_load_addr;
268         u64 tsc_offset;
269         u64 virtual_apic_page_addr;
270         u64 apic_access_addr;
271         u64 posted_intr_desc_addr;
272         u64 ept_pointer;
273         u64 eoi_exit_bitmap0;
274         u64 eoi_exit_bitmap1;
275         u64 eoi_exit_bitmap2;
276         u64 eoi_exit_bitmap3;
277         u64 xss_exit_bitmap;
278         u64 guest_physical_address;
279         u64 vmcs_link_pointer;
280         u64 guest_ia32_debugctl;
281         u64 guest_ia32_pat;
282         u64 guest_ia32_efer;
283         u64 guest_ia32_perf_global_ctrl;
284         u64 guest_pdptr0;
285         u64 guest_pdptr1;
286         u64 guest_pdptr2;
287         u64 guest_pdptr3;
288         u64 guest_bndcfgs;
289         u64 host_ia32_pat;
290         u64 host_ia32_efer;
291         u64 host_ia32_perf_global_ctrl;
292         u64 vmread_bitmap;
293         u64 vmwrite_bitmap;
294         u64 vm_function_control;
295         u64 eptp_list_address;
296         u64 pml_address;
297         u64 padding64[3]; /* room for future expansion */
298         /*
299          * To allow migration of L1 (complete with its L2 guests) between
300          * machines of different natural widths (32 or 64 bit), we cannot have
301          * unsigned long fields with no explict size. We use u64 (aliased
302          * natural_width) instead. Luckily, x86 is little-endian.
303          */
304         natural_width cr0_guest_host_mask;
305         natural_width cr4_guest_host_mask;
306         natural_width cr0_read_shadow;
307         natural_width cr4_read_shadow;
308         natural_width cr3_target_value0;
309         natural_width cr3_target_value1;
310         natural_width cr3_target_value2;
311         natural_width cr3_target_value3;
312         natural_width exit_qualification;
313         natural_width guest_linear_address;
314         natural_width guest_cr0;
315         natural_width guest_cr3;
316         natural_width guest_cr4;
317         natural_width guest_es_base;
318         natural_width guest_cs_base;
319         natural_width guest_ss_base;
320         natural_width guest_ds_base;
321         natural_width guest_fs_base;
322         natural_width guest_gs_base;
323         natural_width guest_ldtr_base;
324         natural_width guest_tr_base;
325         natural_width guest_gdtr_base;
326         natural_width guest_idtr_base;
327         natural_width guest_dr7;
328         natural_width guest_rsp;
329         natural_width guest_rip;
330         natural_width guest_rflags;
331         natural_width guest_pending_dbg_exceptions;
332         natural_width guest_sysenter_esp;
333         natural_width guest_sysenter_eip;
334         natural_width host_cr0;
335         natural_width host_cr3;
336         natural_width host_cr4;
337         natural_width host_fs_base;
338         natural_width host_gs_base;
339         natural_width host_tr_base;
340         natural_width host_gdtr_base;
341         natural_width host_idtr_base;
342         natural_width host_ia32_sysenter_esp;
343         natural_width host_ia32_sysenter_eip;
344         natural_width host_rsp;
345         natural_width host_rip;
346         natural_width paddingl[8]; /* room for future expansion */
347         u32 pin_based_vm_exec_control;
348         u32 cpu_based_vm_exec_control;
349         u32 exception_bitmap;
350         u32 page_fault_error_code_mask;
351         u32 page_fault_error_code_match;
352         u32 cr3_target_count;
353         u32 vm_exit_controls;
354         u32 vm_exit_msr_store_count;
355         u32 vm_exit_msr_load_count;
356         u32 vm_entry_controls;
357         u32 vm_entry_msr_load_count;
358         u32 vm_entry_intr_info_field;
359         u32 vm_entry_exception_error_code;
360         u32 vm_entry_instruction_len;
361         u32 tpr_threshold;
362         u32 secondary_vm_exec_control;
363         u32 vm_instruction_error;
364         u32 vm_exit_reason;
365         u32 vm_exit_intr_info;
366         u32 vm_exit_intr_error_code;
367         u32 idt_vectoring_info_field;
368         u32 idt_vectoring_error_code;
369         u32 vm_exit_instruction_len;
370         u32 vmx_instruction_info;
371         u32 guest_es_limit;
372         u32 guest_cs_limit;
373         u32 guest_ss_limit;
374         u32 guest_ds_limit;
375         u32 guest_fs_limit;
376         u32 guest_gs_limit;
377         u32 guest_ldtr_limit;
378         u32 guest_tr_limit;
379         u32 guest_gdtr_limit;
380         u32 guest_idtr_limit;
381         u32 guest_es_ar_bytes;
382         u32 guest_cs_ar_bytes;
383         u32 guest_ss_ar_bytes;
384         u32 guest_ds_ar_bytes;
385         u32 guest_fs_ar_bytes;
386         u32 guest_gs_ar_bytes;
387         u32 guest_ldtr_ar_bytes;
388         u32 guest_tr_ar_bytes;
389         u32 guest_interruptibility_info;
390         u32 guest_activity_state;
391         u32 guest_sysenter_cs;
392         u32 host_ia32_sysenter_cs;
393         u32 vmx_preemption_timer_value;
394         u32 padding32[7]; /* room for future expansion */
395         u16 virtual_processor_id;
396         u16 posted_intr_nv;
397         u16 guest_es_selector;
398         u16 guest_cs_selector;
399         u16 guest_ss_selector;
400         u16 guest_ds_selector;
401         u16 guest_fs_selector;
402         u16 guest_gs_selector;
403         u16 guest_ldtr_selector;
404         u16 guest_tr_selector;
405         u16 guest_intr_status;
406         u16 host_es_selector;
407         u16 host_cs_selector;
408         u16 host_ss_selector;
409         u16 host_ds_selector;
410         u16 host_fs_selector;
411         u16 host_gs_selector;
412         u16 host_tr_selector;
413         u16 guest_pml_index;
414 };
415 
416 /*
417  * For save/restore compatibility, the vmcs12 field offsets must not change.
418  */
419 #define CHECK_OFFSET(field, loc)                                \
420         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
421                 "Offset of " #field " in struct vmcs12 has changed.")
422 
423 static inline void vmx_check_vmcs12_offsets(void) {
424         CHECK_OFFSET(revision_id, 0);
425         CHECK_OFFSET(abort, 4);
426         CHECK_OFFSET(launch_state, 8);
427         CHECK_OFFSET(io_bitmap_a, 40);
428         CHECK_OFFSET(io_bitmap_b, 48);
429         CHECK_OFFSET(msr_bitmap, 56);
430         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
431         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
432         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
433         CHECK_OFFSET(tsc_offset, 88);
434         CHECK_OFFSET(virtual_apic_page_addr, 96);
435         CHECK_OFFSET(apic_access_addr, 104);
436         CHECK_OFFSET(posted_intr_desc_addr, 112);
437         CHECK_OFFSET(ept_pointer, 120);
438         CHECK_OFFSET(eoi_exit_bitmap0, 128);
439         CHECK_OFFSET(eoi_exit_bitmap1, 136);
440         CHECK_OFFSET(eoi_exit_bitmap2, 144);
441         CHECK_OFFSET(eoi_exit_bitmap3, 152);
442         CHECK_OFFSET(xss_exit_bitmap, 160);
443         CHECK_OFFSET(guest_physical_address, 168);
444         CHECK_OFFSET(vmcs_link_pointer, 176);
445         CHECK_OFFSET(guest_ia32_debugctl, 184);
446         CHECK_OFFSET(guest_ia32_pat, 192);
447         CHECK_OFFSET(guest_ia32_efer, 200);
448         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
449         CHECK_OFFSET(guest_pdptr0, 216);
450         CHECK_OFFSET(guest_pdptr1, 224);
451         CHECK_OFFSET(guest_pdptr2, 232);
452         CHECK_OFFSET(guest_pdptr3, 240);
453         CHECK_OFFSET(guest_bndcfgs, 248);
454         CHECK_OFFSET(host_ia32_pat, 256);
455         CHECK_OFFSET(host_ia32_efer, 264);
456         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
457         CHECK_OFFSET(vmread_bitmap, 280);
458         CHECK_OFFSET(vmwrite_bitmap, 288);
459         CHECK_OFFSET(vm_function_control, 296);
460         CHECK_OFFSET(eptp_list_address, 304);
461         CHECK_OFFSET(pml_address, 312);
462         CHECK_OFFSET(cr0_guest_host_mask, 344);
463         CHECK_OFFSET(cr4_guest_host_mask, 352);
464         CHECK_OFFSET(cr0_read_shadow, 360);
465         CHECK_OFFSET(cr4_read_shadow, 368);
466         CHECK_OFFSET(cr3_target_value0, 376);
467         CHECK_OFFSET(cr3_target_value1, 384);
468         CHECK_OFFSET(cr3_target_value2, 392);
469         CHECK_OFFSET(cr3_target_value3, 400);
470         CHECK_OFFSET(exit_qualification, 408);
471         CHECK_OFFSET(guest_linear_address, 416);
472         CHECK_OFFSET(guest_cr0, 424);
473         CHECK_OFFSET(guest_cr3, 432);
474         CHECK_OFFSET(guest_cr4, 440);
475         CHECK_OFFSET(guest_es_base, 448);
476         CHECK_OFFSET(guest_cs_base, 456);
477         CHECK_OFFSET(guest_ss_base, 464);
478         CHECK_OFFSET(guest_ds_base, 472);
479         CHECK_OFFSET(guest_fs_base, 480);
480         CHECK_OFFSET(guest_gs_base, 488);
481         CHECK_OFFSET(guest_ldtr_base, 496);
482         CHECK_OFFSET(guest_tr_base, 504);
483         CHECK_OFFSET(guest_gdtr_base, 512);
484         CHECK_OFFSET(guest_idtr_base, 520);
485         CHECK_OFFSET(guest_dr7, 528);
486         CHECK_OFFSET(guest_rsp, 536);
487         CHECK_OFFSET(guest_rip, 544);
488         CHECK_OFFSET(guest_rflags, 552);
489         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
490         CHECK_OFFSET(guest_sysenter_esp, 568);
491         CHECK_OFFSET(guest_sysenter_eip, 576);
492         CHECK_OFFSET(host_cr0, 584);
493         CHECK_OFFSET(host_cr3, 592);
494         CHECK_OFFSET(host_cr4, 600);
495         CHECK_OFFSET(host_fs_base, 608);
496         CHECK_OFFSET(host_gs_base, 616);
497         CHECK_OFFSET(host_tr_base, 624);
498         CHECK_OFFSET(host_gdtr_base, 632);
499         CHECK_OFFSET(host_idtr_base, 640);
500         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
501         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
502         CHECK_OFFSET(host_rsp, 664);
503         CHECK_OFFSET(host_rip, 672);
504         CHECK_OFFSET(pin_based_vm_exec_control, 744);
505         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
506         CHECK_OFFSET(exception_bitmap, 752);
507         CHECK_OFFSET(page_fault_error_code_mask, 756);
508         CHECK_OFFSET(page_fault_error_code_match, 760);
509         CHECK_OFFSET(cr3_target_count, 764);
510         CHECK_OFFSET(vm_exit_controls, 768);
511         CHECK_OFFSET(vm_exit_msr_store_count, 772);
512         CHECK_OFFSET(vm_exit_msr_load_count, 776);
513         CHECK_OFFSET(vm_entry_controls, 780);
514         CHECK_OFFSET(vm_entry_msr_load_count, 784);
515         CHECK_OFFSET(vm_entry_intr_info_field, 788);
516         CHECK_OFFSET(vm_entry_exception_error_code, 792);
517         CHECK_OFFSET(vm_entry_instruction_len, 796);
518         CHECK_OFFSET(tpr_threshold, 800);
519         CHECK_OFFSET(secondary_vm_exec_control, 804);
520         CHECK_OFFSET(vm_instruction_error, 808);
521         CHECK_OFFSET(vm_exit_reason, 812);
522         CHECK_OFFSET(vm_exit_intr_info, 816);
523         CHECK_OFFSET(vm_exit_intr_error_code, 820);
524         CHECK_OFFSET(idt_vectoring_info_field, 824);
525         CHECK_OFFSET(idt_vectoring_error_code, 828);
526         CHECK_OFFSET(vm_exit_instruction_len, 832);
527         CHECK_OFFSET(vmx_instruction_info, 836);
528         CHECK_OFFSET(guest_es_limit, 840);
529         CHECK_OFFSET(guest_cs_limit, 844);
530         CHECK_OFFSET(guest_ss_limit, 848);
531         CHECK_OFFSET(guest_ds_limit, 852);
532         CHECK_OFFSET(guest_fs_limit, 856);
533         CHECK_OFFSET(guest_gs_limit, 860);
534         CHECK_OFFSET(guest_ldtr_limit, 864);
535         CHECK_OFFSET(guest_tr_limit, 868);
536         CHECK_OFFSET(guest_gdtr_limit, 872);
537         CHECK_OFFSET(guest_idtr_limit, 876);
538         CHECK_OFFSET(guest_es_ar_bytes, 880);
539         CHECK_OFFSET(guest_cs_ar_bytes, 884);
540         CHECK_OFFSET(guest_ss_ar_bytes, 888);
541         CHECK_OFFSET(guest_ds_ar_bytes, 892);
542         CHECK_OFFSET(guest_fs_ar_bytes, 896);
543         CHECK_OFFSET(guest_gs_ar_bytes, 900);
544         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
545         CHECK_OFFSET(guest_tr_ar_bytes, 908);
546         CHECK_OFFSET(guest_interruptibility_info, 912);
547         CHECK_OFFSET(guest_activity_state, 916);
548         CHECK_OFFSET(guest_sysenter_cs, 920);
549         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
550         CHECK_OFFSET(vmx_preemption_timer_value, 928);
551         CHECK_OFFSET(virtual_processor_id, 960);
552         CHECK_OFFSET(posted_intr_nv, 962);
553         CHECK_OFFSET(guest_es_selector, 964);
554         CHECK_OFFSET(guest_cs_selector, 966);
555         CHECK_OFFSET(guest_ss_selector, 968);
556         CHECK_OFFSET(guest_ds_selector, 970);
557         CHECK_OFFSET(guest_fs_selector, 972);
558         CHECK_OFFSET(guest_gs_selector, 974);
559         CHECK_OFFSET(guest_ldtr_selector, 976);
560         CHECK_OFFSET(guest_tr_selector, 978);
561         CHECK_OFFSET(guest_intr_status, 980);
562         CHECK_OFFSET(host_es_selector, 982);
563         CHECK_OFFSET(host_cs_selector, 984);
564         CHECK_OFFSET(host_ss_selector, 986);
565         CHECK_OFFSET(host_ds_selector, 988);
566         CHECK_OFFSET(host_fs_selector, 990);
567         CHECK_OFFSET(host_gs_selector, 992);
568         CHECK_OFFSET(host_tr_selector, 994);
569         CHECK_OFFSET(guest_pml_index, 996);
570 }
571 
572 /*
573  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
574  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
575  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
576  *
577  * IMPORTANT: Changing this value will break save/restore compatibility with
578  * older kvm releases.
579  */
580 #define VMCS12_REVISION 0x11e57ed0
581 
582 /*
583  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
584  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
585  * current implementation, 4K are reserved to avoid future complications.
586  */
587 #define VMCS12_SIZE 0x1000
588 
589 /*
590  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
591  * supported VMCS12 field encoding.
592  */
593 #define VMCS12_MAX_FIELD_INDEX 0x17
594 
595 struct nested_vmx_msrs {
596         /*
597          * We only store the "true" versions of the VMX capability MSRs. We
598          * generate the "non-true" versions by setting the must-be-1 bits
599          * according to the SDM.
600          */
601         u32 procbased_ctls_low;
602         u32 procbased_ctls_high;
603         u32 secondary_ctls_low;
604         u32 secondary_ctls_high;
605         u32 pinbased_ctls_low;
606         u32 pinbased_ctls_high;
607         u32 exit_ctls_low;
608         u32 exit_ctls_high;
609         u32 entry_ctls_low;
610         u32 entry_ctls_high;
611         u32 misc_low;
612         u32 misc_high;
613         u32 ept_caps;
614         u32 vpid_caps;
615         u64 basic;
616         u64 cr0_fixed0;
617         u64 cr0_fixed1;
618         u64 cr4_fixed0;
619         u64 cr4_fixed1;
620         u64 vmcs_enum;
621         u64 vmfunc_controls;
622 };
623 
624 /*
625  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
626  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
627  */
628 struct nested_vmx {
629         /* Has the level1 guest done vmxon? */
630         bool vmxon;
631         gpa_t vmxon_ptr;
632         bool pml_full;
633 
634         /* The guest-physical address of the current VMCS L1 keeps for L2 */
635         gpa_t current_vmptr;
636         /*
637          * Cache of the guest's VMCS, existing outside of guest memory.
638          * Loaded from guest memory during VMPTRLD. Flushed to guest
639          * memory during VMCLEAR and VMPTRLD.
640          */
641         struct vmcs12 *cached_vmcs12;
642         /*
643          * Indicates if the shadow vmcs must be updated with the
644          * data hold by vmcs12
645          */
646         bool sync_shadow_vmcs;
647         bool dirty_vmcs12;
648 
649         bool change_vmcs01_virtual_apic_mode;
650 
651         /* L2 must run next, and mustn't decide to exit to L1. */
652         bool nested_run_pending;
653 
654         struct loaded_vmcs vmcs02;
655 
656         /*
657          * Guest pages referred to in the vmcs02 with host-physical
658          * pointers, so we must keep them pinned while L2 runs.
659          */
660         struct page *apic_access_page;
661         struct page *virtual_apic_page;
662         struct page *pi_desc_page;
663         struct pi_desc *pi_desc;
664         bool pi_pending;
665         u16 posted_intr_nv;
666 
667         struct hrtimer preemption_timer;
668         bool preemption_timer_expired;
669 
670         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
671         u64 vmcs01_debugctl;
672 
673         u16 vpid02;
674         u16 last_vpid;
675 
676         struct nested_vmx_msrs msrs;
677 
678         /* SMM related state */
679         struct {
680                 /* in VMX operation on SMM entry? */
681                 bool vmxon;
682                 /* in guest mode on SMM entry? */
683                 bool guest_mode;
684         } smm;
685 };
686 
687 #define POSTED_INTR_ON  0
688 #define POSTED_INTR_SN  1
689 
690 /* Posted-Interrupt Descriptor */
691 struct pi_desc {
692         u32 pir[8];     /* Posted interrupt requested */
693         union {
694                 struct {
695                                 /* bit 256 - Outstanding Notification */
696                         u16     on      : 1,
697                                 /* bit 257 - Suppress Notification */
698                                 sn      : 1,
699                                 /* bit 271:258 - Reserved */
700                                 rsvd_1  : 14;
701                                 /* bit 279:272 - Notification Vector */
702                         u8      nv;
703                                 /* bit 287:280 - Reserved */
704                         u8      rsvd_2;
705                                 /* bit 319:288 - Notification Destination */
706                         u32     ndst;
707                 };
708                 u64 control;
709         };
710         u32 rsvd[6];
711 } __aligned(64);
712 
713 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
714 {
715         return test_and_set_bit(POSTED_INTR_ON,
716                         (unsigned long *)&pi_desc->control);
717 }
718 
719 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
720 {
721         return test_and_clear_bit(POSTED_INTR_ON,
722                         (unsigned long *)&pi_desc->control);
723 }
724 
725 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
726 {
727         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
728 }
729 
730 static inline void pi_clear_sn(struct pi_desc *pi_desc)
731 {
732         return clear_bit(POSTED_INTR_SN,
733                         (unsigned long *)&pi_desc->control);
734 }
735 
736 static inline void pi_set_sn(struct pi_desc *pi_desc)
737 {
738         return set_bit(POSTED_INTR_SN,
739                         (unsigned long *)&pi_desc->control);
740 }
741 
742 static inline void pi_clear_on(struct pi_desc *pi_desc)
743 {
744         clear_bit(POSTED_INTR_ON,
745                   (unsigned long *)&pi_desc->control);
746 }
747 
748 static inline int pi_test_on(struct pi_desc *pi_desc)
749 {
750         return test_bit(POSTED_INTR_ON,
751                         (unsigned long *)&pi_desc->control);
752 }
753 
754 static inline int pi_test_sn(struct pi_desc *pi_desc)
755 {
756         return test_bit(POSTED_INTR_SN,
757                         (unsigned long *)&pi_desc->control);
758 }
759 
760 struct vcpu_vmx {
761         struct kvm_vcpu       vcpu;
762         unsigned long         host_rsp;
763         u8                    fail;
764         u8                    msr_bitmap_mode;
765         u32                   exit_intr_info;
766         u32                   idt_vectoring_info;
767         ulong                 rflags;
768         struct shared_msr_entry *guest_msrs;
769         int                   nmsrs;
770         int                   save_nmsrs;
771         unsigned long         host_idt_base;
772 #ifdef CONFIG_X86_64
773         u64                   msr_host_kernel_gs_base;
774         u64                   msr_guest_kernel_gs_base;
775 #endif
776 
777         u64                   arch_capabilities;
778         u64                   spec_ctrl;
779 
780         u32 vm_entry_controls_shadow;
781         u32 vm_exit_controls_shadow;
782         u32 secondary_exec_control;
783 
784         /*
785          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
786          * non-nested (L1) guest, it always points to vmcs01. For a nested
787          * guest (L2), it points to a different VMCS.
788          */
789         struct loaded_vmcs    vmcs01;
790         struct loaded_vmcs   *loaded_vmcs;
791         bool                  __launched; /* temporary, used in vmx_vcpu_run */
792         struct msr_autoload {
793                 unsigned nr;
794                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
795                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
796         } msr_autoload;
797         struct {
798                 int           loaded;
799                 u16           fs_sel, gs_sel, ldt_sel;
800 #ifdef CONFIG_X86_64
801                 u16           ds_sel, es_sel;
802 #endif
803                 int           gs_ldt_reload_needed;
804                 int           fs_reload_needed;
805                 u64           msr_host_bndcfgs;
806         } host_state;
807         struct {
808                 int vm86_active;
809                 ulong save_rflags;
810                 struct kvm_segment segs[8];
811         } rmode;
812         struct {
813                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
814                 struct kvm_save_segment {
815                         u16 selector;
816                         unsigned long base;
817                         u32 limit;
818                         u32 ar;
819                 } seg[8];
820         } segment_cache;
821         int vpid;
822         bool emulation_required;
823 
824         u32 exit_reason;
825 
826         /* Posted interrupt descriptor */
827         struct pi_desc pi_desc;
828 
829         /* Support for a guest hypervisor (nested VMX) */
830         struct nested_vmx nested;
831 
832         /* Dynamic PLE window. */
833         int ple_window;
834         bool ple_window_dirty;
835 
836         /* Support for PML */
837 #define PML_ENTITY_NUM          512
838         struct page *pml_pg;
839 
840         /* apic deadline value in host tsc */
841         u64 hv_deadline_tsc;
842 
843         u64 current_tsc_ratio;
844 
845         u32 host_pkru;
846 
847         unsigned long host_debugctlmsr;
848 
849         /*
850          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
851          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
852          * in msr_ia32_feature_control_valid_bits.
853          */
854         u64 msr_ia32_feature_control;
855         u64 msr_ia32_feature_control_valid_bits;
856 };
857 
858 enum segment_cache_field {
859         SEG_FIELD_SEL = 0,
860         SEG_FIELD_BASE = 1,
861         SEG_FIELD_LIMIT = 2,
862         SEG_FIELD_AR = 3,
863 
864         SEG_FIELD_NR = 4
865 };
866 
867 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
868 {
869         return container_of(kvm, struct kvm_vmx, kvm);
870 }
871 
872 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
873 {
874         return container_of(vcpu, struct vcpu_vmx, vcpu);
875 }
876 
877 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
878 {
879         return &(to_vmx(vcpu)->pi_desc);
880 }
881 
882 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
883 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
884 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
885 #define FIELD64(number, name)                                           \
886         FIELD(number, name),                                            \
887         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
888 
889 
890 static u16 shadow_read_only_fields[] = {
891 #define SHADOW_FIELD_RO(x) x,
892 #include "vmx_shadow_fields.h"
893 };
894 static int max_shadow_read_only_fields =
895         ARRAY_SIZE(shadow_read_only_fields);
896 
897 static u16 shadow_read_write_fields[] = {
898 #define SHADOW_FIELD_RW(x) x,
899 #include "vmx_shadow_fields.h"
900 };
901 static int max_shadow_read_write_fields =
902         ARRAY_SIZE(shadow_read_write_fields);
903 
904 static const unsigned short vmcs_field_to_offset_table[] = {
905         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
906         FIELD(POSTED_INTR_NV, posted_intr_nv),
907         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
908         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
909         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
910         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
911         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
912         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
913         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
914         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
915         FIELD(GUEST_INTR_STATUS, guest_intr_status),
916         FIELD(GUEST_PML_INDEX, guest_pml_index),
917         FIELD(HOST_ES_SELECTOR, host_es_selector),
918         FIELD(HOST_CS_SELECTOR, host_cs_selector),
919         FIELD(HOST_SS_SELECTOR, host_ss_selector),
920         FIELD(HOST_DS_SELECTOR, host_ds_selector),
921         FIELD(HOST_FS_SELECTOR, host_fs_selector),
922         FIELD(HOST_GS_SELECTOR, host_gs_selector),
923         FIELD(HOST_TR_SELECTOR, host_tr_selector),
924         FIELD64(IO_BITMAP_A, io_bitmap_a),
925         FIELD64(IO_BITMAP_B, io_bitmap_b),
926         FIELD64(MSR_BITMAP, msr_bitmap),
927         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
928         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
929         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
930         FIELD64(PML_ADDRESS, pml_address),
931         FIELD64(TSC_OFFSET, tsc_offset),
932         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
933         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
934         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
935         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
936         FIELD64(EPT_POINTER, ept_pointer),
937         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
938         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
939         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
940         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
941         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
942         FIELD64(VMREAD_BITMAP, vmread_bitmap),
943         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
944         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
945         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
946         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
947         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
948         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
949         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
950         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
951         FIELD64(GUEST_PDPTR0, guest_pdptr0),
952         FIELD64(GUEST_PDPTR1, guest_pdptr1),
953         FIELD64(GUEST_PDPTR2, guest_pdptr2),
954         FIELD64(GUEST_PDPTR3, guest_pdptr3),
955         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
956         FIELD64(HOST_IA32_PAT, host_ia32_pat),
957         FIELD64(HOST_IA32_EFER, host_ia32_efer),
958         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
959         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
960         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
961         FIELD(EXCEPTION_BITMAP, exception_bitmap),
962         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
963         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
964         FIELD(CR3_TARGET_COUNT, cr3_target_count),
965         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
966         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
967         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
968         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
969         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
970         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
971         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
972         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
973         FIELD(TPR_THRESHOLD, tpr_threshold),
974         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
975         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
976         FIELD(VM_EXIT_REASON, vm_exit_reason),
977         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
978         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
979         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
980         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
981         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
982         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
983         FIELD(GUEST_ES_LIMIT, guest_es_limit),
984         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
985         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
986         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
987         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
988         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
989         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
990         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
991         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
992         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
993         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
994         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
995         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
996         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
997         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
998         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
999         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1000         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1001         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1002         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1003         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1004         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1005         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1006         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1007         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1008         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1009         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1010         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1011         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1012         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1013         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1014         FIELD(EXIT_QUALIFICATION, exit_qualification),
1015         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1016         FIELD(GUEST_CR0, guest_cr0),
1017         FIELD(GUEST_CR3, guest_cr3),
1018         FIELD(GUEST_CR4, guest_cr4),
1019         FIELD(GUEST_ES_BASE, guest_es_base),
1020         FIELD(GUEST_CS_BASE, guest_cs_base),
1021         FIELD(GUEST_SS_BASE, guest_ss_base),
1022         FIELD(GUEST_DS_BASE, guest_ds_base),
1023         FIELD(GUEST_FS_BASE, guest_fs_base),
1024         FIELD(GUEST_GS_BASE, guest_gs_base),
1025         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1026         FIELD(GUEST_TR_BASE, guest_tr_base),
1027         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1028         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1029         FIELD(GUEST_DR7, guest_dr7),
1030         FIELD(GUEST_RSP, guest_rsp),
1031         FIELD(GUEST_RIP, guest_rip),
1032         FIELD(GUEST_RFLAGS, guest_rflags),
1033         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1034         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1035         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1036         FIELD(HOST_CR0, host_cr0),
1037         FIELD(HOST_CR3, host_cr3),
1038         FIELD(HOST_CR4, host_cr4),
1039         FIELD(HOST_FS_BASE, host_fs_base),
1040         FIELD(HOST_GS_BASE, host_gs_base),
1041         FIELD(HOST_TR_BASE, host_tr_base),
1042         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1043         FIELD(HOST_IDTR_BASE, host_idtr_base),
1044         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1045         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1046         FIELD(HOST_RSP, host_rsp),
1047         FIELD(HOST_RIP, host_rip),
1048 };
1049 
1050 static inline short vmcs_field_to_offset(unsigned long field)
1051 {
1052         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1053         unsigned short offset;
1054         unsigned index;
1055 
1056         if (field >> 15)
1057                 return -ENOENT;
1058 
1059         index = ROL16(field, 6);
1060         if (index >= size)
1061                 return -ENOENT;
1062 
1063         index = array_index_nospec(index, size);
1064         offset = vmcs_field_to_offset_table[index];
1065         if (offset == 0)
1066                 return -ENOENT;
1067         return offset;
1068 }
1069 
1070 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1071 {
1072         return to_vmx(vcpu)->nested.cached_vmcs12;
1073 }
1074 
1075 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1076 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1077 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1078 static bool vmx_xsaves_supported(void);
1079 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1080                             struct kvm_segment *var, int seg);
1081 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1082                             struct kvm_segment *var, int seg);
1083 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1084 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1085 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1086 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1087 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1088 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1089                                             u16 error_code);
1090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1091 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1092                                                           u32 msr, int type);
1093 
1094 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1095 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1096 /*
1097  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1098  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1099  */
1100 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1101 
1102 /*
1103  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1104  * can find which vCPU should be waken up.
1105  */
1106 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1107 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1108 
1109 enum {
1110         VMX_VMREAD_BITMAP,
1111         VMX_VMWRITE_BITMAP,
1112         VMX_BITMAP_NR
1113 };
1114 
1115 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1116 
1117 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1118 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1119 
1120 static bool cpu_has_load_ia32_efer;
1121 static bool cpu_has_load_perf_global_ctrl;
1122 
1123 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1124 static DEFINE_SPINLOCK(vmx_vpid_lock);
1125 
1126 static struct vmcs_config {
1127         int size;
1128         int order;
1129         u32 basic_cap;
1130         u32 revision_id;
1131         u32 pin_based_exec_ctrl;
1132         u32 cpu_based_exec_ctrl;
1133         u32 cpu_based_2nd_exec_ctrl;
1134         u32 vmexit_ctrl;
1135         u32 vmentry_ctrl;
1136         struct nested_vmx_msrs nested;
1137 } vmcs_config;
1138 
1139 static struct vmx_capability {
1140         u32 ept;
1141         u32 vpid;
1142 } vmx_capability;
1143 
1144 #define VMX_SEGMENT_FIELD(seg)                                  \
1145         [VCPU_SREG_##seg] = {                                   \
1146                 .selector = GUEST_##seg##_SELECTOR,             \
1147                 .base = GUEST_##seg##_BASE,                     \
1148                 .limit = GUEST_##seg##_LIMIT,                   \
1149                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1150         }
1151 
1152 static const struct kvm_vmx_segment_field {
1153         unsigned selector;
1154         unsigned base;
1155         unsigned limit;
1156         unsigned ar_bytes;
1157 } kvm_vmx_segment_fields[] = {
1158         VMX_SEGMENT_FIELD(CS),
1159         VMX_SEGMENT_FIELD(DS),
1160         VMX_SEGMENT_FIELD(ES),
1161         VMX_SEGMENT_FIELD(FS),
1162         VMX_SEGMENT_FIELD(GS),
1163         VMX_SEGMENT_FIELD(SS),
1164         VMX_SEGMENT_FIELD(TR),
1165         VMX_SEGMENT_FIELD(LDTR),
1166 };
1167 
1168 static u64 host_efer;
1169 
1170 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1171 
1172 /*
1173  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1174  * away by decrementing the array size.
1175  */
1176 static const u32 vmx_msr_index[] = {
1177 #ifdef CONFIG_X86_64
1178         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1179 #endif
1180         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1181 };
1182 
1183 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1184 
1185 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1186 
1187 #define KVM_EVMCS_VERSION 1
1188 
1189 #if IS_ENABLED(CONFIG_HYPERV)
1190 static bool __read_mostly enlightened_vmcs = true;
1191 module_param(enlightened_vmcs, bool, 0444);
1192 
1193 static inline void evmcs_write64(unsigned long field, u64 value)
1194 {
1195         u16 clean_field;
1196         int offset = get_evmcs_offset(field, &clean_field);
1197 
1198         if (offset < 0)
1199                 return;
1200 
1201         *(u64 *)((char *)current_evmcs + offset) = value;
1202 
1203         current_evmcs->hv_clean_fields &= ~clean_field;
1204 }
1205 
1206 static inline void evmcs_write32(unsigned long field, u32 value)
1207 {
1208         u16 clean_field;
1209         int offset = get_evmcs_offset(field, &clean_field);
1210 
1211         if (offset < 0)
1212                 return;
1213 
1214         *(u32 *)((char *)current_evmcs + offset) = value;
1215         current_evmcs->hv_clean_fields &= ~clean_field;
1216 }
1217 
1218 static inline void evmcs_write16(unsigned long field, u16 value)
1219 {
1220         u16 clean_field;
1221         int offset = get_evmcs_offset(field, &clean_field);
1222 
1223         if (offset < 0)
1224                 return;
1225 
1226         *(u16 *)((char *)current_evmcs + offset) = value;
1227         current_evmcs->hv_clean_fields &= ~clean_field;
1228 }
1229 
1230 static inline u64 evmcs_read64(unsigned long field)
1231 {
1232         int offset = get_evmcs_offset(field, NULL);
1233 
1234         if (offset < 0)
1235                 return 0;
1236 
1237         return *(u64 *)((char *)current_evmcs + offset);
1238 }
1239 
1240 static inline u32 evmcs_read32(unsigned long field)
1241 {
1242         int offset = get_evmcs_offset(field, NULL);
1243 
1244         if (offset < 0)
1245                 return 0;
1246 
1247         return *(u32 *)((char *)current_evmcs + offset);
1248 }
1249 
1250 static inline u16 evmcs_read16(unsigned long field)
1251 {
1252         int offset = get_evmcs_offset(field, NULL);
1253 
1254         if (offset < 0)
1255                 return 0;
1256 
1257         return *(u16 *)((char *)current_evmcs + offset);
1258 }
1259 
1260 static inline void evmcs_touch_msr_bitmap(void)
1261 {
1262         if (unlikely(!current_evmcs))
1263                 return;
1264 
1265         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1266                 current_evmcs->hv_clean_fields &=
1267                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1268 }
1269 
1270 static void evmcs_load(u64 phys_addr)
1271 {
1272         struct hv_vp_assist_page *vp_ap =
1273                 hv_get_vp_assist_page(smp_processor_id());
1274 
1275         vp_ap->current_nested_vmcs = phys_addr;
1276         vp_ap->enlighten_vmentry = 1;
1277 }
1278 
1279 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1280 {
1281         /*
1282          * Enlightened VMCSv1 doesn't support these:
1283          *
1284          *      POSTED_INTR_NV                  = 0x00000002,
1285          *      GUEST_INTR_STATUS               = 0x00000810,
1286          *      APIC_ACCESS_ADDR                = 0x00002014,
1287          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1288          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1289          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1290          *      EOI_EXIT_BITMAP2                = 0x00002020,
1291          *      EOI_EXIT_BITMAP3                = 0x00002022,
1292          */
1293         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1294         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1295                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1296         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1297                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1298         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1299                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1300 
1301         /*
1302          *      GUEST_PML_INDEX                 = 0x00000812,
1303          *      PML_ADDRESS                     = 0x0000200e,
1304          */
1305         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1306 
1307         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1308         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1309 
1310         /*
1311          *      EPTP_LIST_ADDRESS               = 0x00002024,
1312          *      VMREAD_BITMAP                   = 0x00002026,
1313          *      VMWRITE_BITMAP                  = 0x00002028,
1314          */
1315         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1316 
1317         /*
1318          *      TSC_MULTIPLIER                  = 0x00002032,
1319          */
1320         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1321 
1322         /*
1323          *      PLE_GAP                         = 0x00004020,
1324          *      PLE_WINDOW                      = 0x00004022,
1325          */
1326         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1327 
1328         /*
1329          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1330          */
1331         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1332 
1333         /*
1334          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1335          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1336          */
1337         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1338         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1339 
1340         /*
1341          * Currently unsupported in KVM:
1342          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1343          */
1344 }
1345 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1346 static inline void evmcs_write64(unsigned long field, u64 value) {}
1347 static inline void evmcs_write32(unsigned long field, u32 value) {}
1348 static inline void evmcs_write16(unsigned long field, u16 value) {}
1349 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1350 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1351 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1352 static inline void evmcs_load(u64 phys_addr) {}
1353 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1354 static inline void evmcs_touch_msr_bitmap(void) {}
1355 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1356 
1357 static inline bool is_exception_n(u32 intr_info, u8 vector)
1358 {
1359         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1360                              INTR_INFO_VALID_MASK)) ==
1361                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1362 }
1363 
1364 static inline bool is_debug(u32 intr_info)
1365 {
1366         return is_exception_n(intr_info, DB_VECTOR);
1367 }
1368 
1369 static inline bool is_breakpoint(u32 intr_info)
1370 {
1371         return is_exception_n(intr_info, BP_VECTOR);
1372 }
1373 
1374 static inline bool is_page_fault(u32 intr_info)
1375 {
1376         return is_exception_n(intr_info, PF_VECTOR);
1377 }
1378 
1379 static inline bool is_no_device(u32 intr_info)
1380 {
1381         return is_exception_n(intr_info, NM_VECTOR);
1382 }
1383 
1384 static inline bool is_invalid_opcode(u32 intr_info)
1385 {
1386         return is_exception_n(intr_info, UD_VECTOR);
1387 }
1388 
1389 static inline bool is_gp_fault(u32 intr_info)
1390 {
1391         return is_exception_n(intr_info, GP_VECTOR);
1392 }
1393 
1394 static inline bool is_external_interrupt(u32 intr_info)
1395 {
1396         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1398 }
1399 
1400 static inline bool is_machine_check(u32 intr_info)
1401 {
1402         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1403                              INTR_INFO_VALID_MASK)) ==
1404                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1405 }
1406 
1407 /* Undocumented: icebp/int1 */
1408 static inline bool is_icebp(u32 intr_info)
1409 {
1410         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1411                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1412 }
1413 
1414 static inline bool cpu_has_vmx_msr_bitmap(void)
1415 {
1416         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1417 }
1418 
1419 static inline bool cpu_has_vmx_tpr_shadow(void)
1420 {
1421         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1422 }
1423 
1424 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1425 {
1426         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1427 }
1428 
1429 static inline bool cpu_has_secondary_exec_ctrls(void)
1430 {
1431         return vmcs_config.cpu_based_exec_ctrl &
1432                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1433 }
1434 
1435 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1436 {
1437         return vmcs_config.cpu_based_2nd_exec_ctrl &
1438                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1439 }
1440 
1441 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1442 {
1443         return vmcs_config.cpu_based_2nd_exec_ctrl &
1444                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1445 }
1446 
1447 static inline bool cpu_has_vmx_apic_register_virt(void)
1448 {
1449         return vmcs_config.cpu_based_2nd_exec_ctrl &
1450                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1451 }
1452 
1453 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1454 {
1455         return vmcs_config.cpu_based_2nd_exec_ctrl &
1456                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1457 }
1458 
1459 /*
1460  * Comment's format: document - errata name - stepping - processor name.
1461  * Refer from
1462  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1463  */
1464 static u32 vmx_preemption_cpu_tfms[] = {
1465 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1466 0x000206E6,
1467 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1468 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1469 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1470 0x00020652,
1471 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1472 0x00020655,
1473 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1474 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1475 /*
1476  * 320767.pdf - AAP86  - B1 -
1477  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1478  */
1479 0x000106E5,
1480 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1481 0x000106A0,
1482 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1483 0x000106A1,
1484 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1485 0x000106A4,
1486  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1487  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1488  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1489 0x000106A5,
1490 };
1491 
1492 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1493 {
1494         u32 eax = cpuid_eax(0x00000001), i;
1495 
1496         /* Clear the reserved bits */
1497         eax &= ~(0x3U << 14 | 0xfU << 28);
1498         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1499                 if (eax == vmx_preemption_cpu_tfms[i])
1500                         return true;
1501 
1502         return false;
1503 }
1504 
1505 static inline bool cpu_has_vmx_preemption_timer(void)
1506 {
1507         return vmcs_config.pin_based_exec_ctrl &
1508                 PIN_BASED_VMX_PREEMPTION_TIMER;
1509 }
1510 
1511 static inline bool cpu_has_vmx_posted_intr(void)
1512 {
1513         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1514                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1515 }
1516 
1517 static inline bool cpu_has_vmx_apicv(void)
1518 {
1519         return cpu_has_vmx_apic_register_virt() &&
1520                 cpu_has_vmx_virtual_intr_delivery() &&
1521                 cpu_has_vmx_posted_intr();
1522 }
1523 
1524 static inline bool cpu_has_vmx_flexpriority(void)
1525 {
1526         return cpu_has_vmx_tpr_shadow() &&
1527                 cpu_has_vmx_virtualize_apic_accesses();
1528 }
1529 
1530 static inline bool cpu_has_vmx_ept_execute_only(void)
1531 {
1532         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1533 }
1534 
1535 static inline bool cpu_has_vmx_ept_2m_page(void)
1536 {
1537         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1538 }
1539 
1540 static inline bool cpu_has_vmx_ept_1g_page(void)
1541 {
1542         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1543 }
1544 
1545 static inline bool cpu_has_vmx_ept_4levels(void)
1546 {
1547         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1548 }
1549 
1550 static inline bool cpu_has_vmx_ept_mt_wb(void)
1551 {
1552         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1553 }
1554 
1555 static inline bool cpu_has_vmx_ept_5levels(void)
1556 {
1557         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1558 }
1559 
1560 static inline bool cpu_has_vmx_ept_ad_bits(void)
1561 {
1562         return vmx_capability.ept & VMX_EPT_AD_BIT;
1563 }
1564 
1565 static inline bool cpu_has_vmx_invept_context(void)
1566 {
1567         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1568 }
1569 
1570 static inline bool cpu_has_vmx_invept_global(void)
1571 {
1572         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1573 }
1574 
1575 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1576 {
1577         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1578 }
1579 
1580 static inline bool cpu_has_vmx_invvpid_single(void)
1581 {
1582         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1583 }
1584 
1585 static inline bool cpu_has_vmx_invvpid_global(void)
1586 {
1587         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1588 }
1589 
1590 static inline bool cpu_has_vmx_invvpid(void)
1591 {
1592         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1593 }
1594 
1595 static inline bool cpu_has_vmx_ept(void)
1596 {
1597         return vmcs_config.cpu_based_2nd_exec_ctrl &
1598                 SECONDARY_EXEC_ENABLE_EPT;
1599 }
1600 
1601 static inline bool cpu_has_vmx_unrestricted_guest(void)
1602 {
1603         return vmcs_config.cpu_based_2nd_exec_ctrl &
1604                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1605 }
1606 
1607 static inline bool cpu_has_vmx_ple(void)
1608 {
1609         return vmcs_config.cpu_based_2nd_exec_ctrl &
1610                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1611 }
1612 
1613 static inline bool cpu_has_vmx_basic_inout(void)
1614 {
1615         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1616 }
1617 
1618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1619 {
1620         return flexpriority_enabled && lapic_in_kernel(vcpu);
1621 }
1622 
1623 static inline bool cpu_has_vmx_vpid(void)
1624 {
1625         return vmcs_config.cpu_based_2nd_exec_ctrl &
1626                 SECONDARY_EXEC_ENABLE_VPID;
1627 }
1628 
1629 static inline bool cpu_has_vmx_rdtscp(void)
1630 {
1631         return vmcs_config.cpu_based_2nd_exec_ctrl &
1632                 SECONDARY_EXEC_RDTSCP;
1633 }
1634 
1635 static inline bool cpu_has_vmx_invpcid(void)
1636 {
1637         return vmcs_config.cpu_based_2nd_exec_ctrl &
1638                 SECONDARY_EXEC_ENABLE_INVPCID;
1639 }
1640 
1641 static inline bool cpu_has_virtual_nmis(void)
1642 {
1643         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1644 }
1645 
1646 static inline bool cpu_has_vmx_wbinvd_exit(void)
1647 {
1648         return vmcs_config.cpu_based_2nd_exec_ctrl &
1649                 SECONDARY_EXEC_WBINVD_EXITING;
1650 }
1651 
1652 static inline bool cpu_has_vmx_shadow_vmcs(void)
1653 {
1654         u64 vmx_msr;
1655         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1656         /* check if the cpu supports writing r/o exit information fields */
1657         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1658                 return false;
1659 
1660         return vmcs_config.cpu_based_2nd_exec_ctrl &
1661                 SECONDARY_EXEC_SHADOW_VMCS;
1662 }
1663 
1664 static inline bool cpu_has_vmx_pml(void)
1665 {
1666         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1667 }
1668 
1669 static inline bool cpu_has_vmx_tsc_scaling(void)
1670 {
1671         return vmcs_config.cpu_based_2nd_exec_ctrl &
1672                 SECONDARY_EXEC_TSC_SCALING;
1673 }
1674 
1675 static inline bool cpu_has_vmx_vmfunc(void)
1676 {
1677         return vmcs_config.cpu_based_2nd_exec_ctrl &
1678                 SECONDARY_EXEC_ENABLE_VMFUNC;
1679 }
1680 
1681 static bool vmx_umip_emulated(void)
1682 {
1683         return vmcs_config.cpu_based_2nd_exec_ctrl &
1684                 SECONDARY_EXEC_DESC;
1685 }
1686 
1687 static inline bool report_flexpriority(void)
1688 {
1689         return flexpriority_enabled;
1690 }
1691 
1692 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1693 {
1694         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1695 }
1696 
1697 /*
1698  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1699  * to modify any valid field of the VMCS, or are the VM-exit
1700  * information fields read-only?
1701  */
1702 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1703 {
1704         return to_vmx(vcpu)->nested.msrs.misc_low &
1705                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1706 }
1707 
1708 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1709 {
1710         return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1711 }
1712 
1713 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1714 {
1715         return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1716                         CPU_BASED_MONITOR_TRAP_FLAG;
1717 }
1718 
1719 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1720 {
1721         return vmcs12->cpu_based_vm_exec_control & bit;
1722 }
1723 
1724 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1725 {
1726         return (vmcs12->cpu_based_vm_exec_control &
1727                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1728                 (vmcs12->secondary_vm_exec_control & bit);
1729 }
1730 
1731 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1732 {
1733         return vmcs12->pin_based_vm_exec_control &
1734                 PIN_BASED_VMX_PREEMPTION_TIMER;
1735 }
1736 
1737 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1738 {
1739         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1740 }
1741 
1742 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1743 {
1744         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1745 }
1746 
1747 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1748 {
1749         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1750 }
1751 
1752 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1753 {
1754         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1755 }
1756 
1757 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1758 {
1759         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1760 }
1761 
1762 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1763 {
1764         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1765 }
1766 
1767 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1768 {
1769         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1770 }
1771 
1772 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1773 {
1774         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1775 }
1776 
1777 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1778 {
1779         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1780 }
1781 
1782 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1783 {
1784         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1785 }
1786 
1787 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1788 {
1789         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1790 }
1791 
1792 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1793 {
1794         return nested_cpu_has_vmfunc(vmcs12) &&
1795                 (vmcs12->vm_function_control &
1796                  VMX_VMFUNC_EPTP_SWITCHING);
1797 }
1798 
1799 static inline bool is_nmi(u32 intr_info)
1800 {
1801         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1802                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1803 }
1804 
1805 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1806                               u32 exit_intr_info,
1807                               unsigned long exit_qualification);
1808 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1809                         struct vmcs12 *vmcs12,
1810                         u32 reason, unsigned long qualification);
1811 
1812 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1813 {
1814         int i;
1815 
1816         for (i = 0; i < vmx->nmsrs; ++i)
1817                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1818                         return i;
1819         return -1;
1820 }
1821 
1822 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1823 {
1824     struct {
1825         u64 vpid : 16;
1826         u64 rsvd : 48;
1827         u64 gva;
1828     } operand = { vpid, 0, gva };
1829 
1830     asm volatile (__ex(ASM_VMX_INVVPID)
1831                   /* CF==1 or ZF==1 --> rc = -1 */
1832                   "; ja 1f ; ud2 ; 1:"
1833                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1834 }
1835 
1836 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1837 {
1838         struct {
1839                 u64 eptp, gpa;
1840         } operand = {eptp, gpa};
1841 
1842         asm volatile (__ex(ASM_VMX_INVEPT)
1843                         /* CF==1 or ZF==1 --> rc = -1 */
1844                         "; ja 1f ; ud2 ; 1:\n"
1845                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1846 }
1847 
1848 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1849 {
1850         int i;
1851 
1852         i = __find_msr_index(vmx, msr);
1853         if (i >= 0)
1854                 return &vmx->guest_msrs[i];
1855         return NULL;
1856 }
1857 
1858 static void vmcs_clear(struct vmcs *vmcs)
1859 {
1860         u64 phys_addr = __pa(vmcs);
1861         u8 error;
1862 
1863         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1864                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1865                       : "cc", "memory");
1866         if (error)
1867                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1868                        vmcs, phys_addr);
1869 }
1870 
1871 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1872 {
1873         vmcs_clear(loaded_vmcs->vmcs);
1874         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1875                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1876         loaded_vmcs->cpu = -1;
1877         loaded_vmcs->launched = 0;
1878 }
1879 
1880 static void vmcs_load(struct vmcs *vmcs)
1881 {
1882         u64 phys_addr = __pa(vmcs);
1883         u8 error;
1884 
1885         if (static_branch_unlikely(&enable_evmcs))
1886                 return evmcs_load(phys_addr);
1887 
1888         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1889                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1890                         : "cc", "memory");
1891         if (error)
1892                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1893                        vmcs, phys_addr);
1894 }
1895 
1896 #ifdef CONFIG_KEXEC_CORE
1897 /*
1898  * This bitmap is used to indicate whether the vmclear
1899  * operation is enabled on all cpus. All disabled by
1900  * default.
1901  */
1902 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1903 
1904 static inline void crash_enable_local_vmclear(int cpu)
1905 {
1906         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1907 }
1908 
1909 static inline void crash_disable_local_vmclear(int cpu)
1910 {
1911         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1912 }
1913 
1914 static inline int crash_local_vmclear_enabled(int cpu)
1915 {
1916         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1917 }
1918 
1919 static void crash_vmclear_local_loaded_vmcss(void)
1920 {
1921         int cpu = raw_smp_processor_id();
1922         struct loaded_vmcs *v;
1923 
1924         if (!crash_local_vmclear_enabled(cpu))
1925                 return;
1926 
1927         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1928                             loaded_vmcss_on_cpu_link)
1929                 vmcs_clear(v->vmcs);
1930 }
1931 #else
1932 static inline void crash_enable_local_vmclear(int cpu) { }
1933 static inline void crash_disable_local_vmclear(int cpu) { }
1934 #endif /* CONFIG_KEXEC_CORE */
1935 
1936 static void __loaded_vmcs_clear(void *arg)
1937 {
1938         struct loaded_vmcs *loaded_vmcs = arg;
1939         int cpu = raw_smp_processor_id();
1940 
1941         if (loaded_vmcs->cpu != cpu)
1942                 return; /* vcpu migration can race with cpu offline */
1943         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1944                 per_cpu(current_vmcs, cpu) = NULL;
1945         crash_disable_local_vmclear(cpu);
1946         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1947 
1948         /*
1949          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1950          * is before setting loaded_vmcs->vcpu to -1 which is done in
1951          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1952          * then adds the vmcs into percpu list before it is deleted.
1953          */
1954         smp_wmb();
1955 
1956         loaded_vmcs_init(loaded_vmcs);
1957         crash_enable_local_vmclear(cpu);
1958 }
1959 
1960 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1961 {
1962         int cpu = loaded_vmcs->cpu;
1963 
1964         if (cpu != -1)
1965                 smp_call_function_single(cpu,
1966                          __loaded_vmcs_clear, loaded_vmcs, 1);
1967 }
1968 
1969 static inline void vpid_sync_vcpu_single(int vpid)
1970 {
1971         if (vpid == 0)
1972                 return;
1973 
1974         if (cpu_has_vmx_invvpid_single())
1975                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1976 }
1977 
1978 static inline void vpid_sync_vcpu_global(void)
1979 {
1980         if (cpu_has_vmx_invvpid_global())
1981                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1982 }
1983 
1984 static inline void vpid_sync_context(int vpid)
1985 {
1986         if (cpu_has_vmx_invvpid_single())
1987                 vpid_sync_vcpu_single(vpid);
1988         else
1989                 vpid_sync_vcpu_global();
1990 }
1991 
1992 static inline void ept_sync_global(void)
1993 {
1994         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1995 }
1996 
1997 static inline void ept_sync_context(u64 eptp)
1998 {
1999         if (cpu_has_vmx_invept_context())
2000                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2001         else
2002                 ept_sync_global();
2003 }
2004 
2005 static __always_inline void vmcs_check16(unsigned long field)
2006 {
2007         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2008                          "16-bit accessor invalid for 64-bit field");
2009         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2010                          "16-bit accessor invalid for 64-bit high field");
2011         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2012                          "16-bit accessor invalid for 32-bit high field");
2013         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2014                          "16-bit accessor invalid for natural width field");
2015 }
2016 
2017 static __always_inline void vmcs_check32(unsigned long field)
2018 {
2019         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2020                          "32-bit accessor invalid for 16-bit field");
2021         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2022                          "32-bit accessor invalid for natural width field");
2023 }
2024 
2025 static __always_inline void vmcs_check64(unsigned long field)
2026 {
2027         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2028                          "64-bit accessor invalid for 16-bit field");
2029         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2030                          "64-bit accessor invalid for 64-bit high field");
2031         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2032                          "64-bit accessor invalid for 32-bit field");
2033         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2034                          "64-bit accessor invalid for natural width field");
2035 }
2036 
2037 static __always_inline void vmcs_checkl(unsigned long field)
2038 {
2039         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2040                          "Natural width accessor invalid for 16-bit field");
2041         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2042                          "Natural width accessor invalid for 64-bit field");
2043         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2044                          "Natural width accessor invalid for 64-bit high field");
2045         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2046                          "Natural width accessor invalid for 32-bit field");
2047 }
2048 
2049 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2050 {
2051         unsigned long value;
2052 
2053         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2054                       : "=a"(value) : "d"(field) : "cc");
2055         return value;
2056 }
2057 
2058 static __always_inline u16 vmcs_read16(unsigned long field)
2059 {
2060         vmcs_check16(field);
2061         if (static_branch_unlikely(&enable_evmcs))
2062                 return evmcs_read16(field);
2063         return __vmcs_readl(field);
2064 }
2065 
2066 static __always_inline u32 vmcs_read32(unsigned long field)
2067 {
2068         vmcs_check32(field);
2069         if (static_branch_unlikely(&enable_evmcs))
2070                 return evmcs_read32(field);
2071         return __vmcs_readl(field);
2072 }
2073 
2074 static __always_inline u64 vmcs_read64(unsigned long field)
2075 {
2076         vmcs_check64(field);
2077         if (static_branch_unlikely(&enable_evmcs))
2078                 return evmcs_read64(field);
2079 #ifdef CONFIG_X86_64
2080         return __vmcs_readl(field);
2081 #else
2082         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2083 #endif
2084 }
2085 
2086 static __always_inline unsigned long vmcs_readl(unsigned long field)
2087 {
2088         vmcs_checkl(field);
2089         if (static_branch_unlikely(&enable_evmcs))
2090                 return evmcs_read64(field);
2091         return __vmcs_readl(field);
2092 }
2093 
2094 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2095 {
2096         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2097                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2098         dump_stack();
2099 }
2100 
2101 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2102 {
2103         u8 error;
2104 
2105         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2106                        : "=q"(error) : "a"(value), "d"(field) : "cc");
2107         if (unlikely(error))
2108                 vmwrite_error(field, value);
2109 }
2110 
2111 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2112 {
2113         vmcs_check16(field);
2114         if (static_branch_unlikely(&enable_evmcs))
2115                 return evmcs_write16(field, value);
2116 
2117         __vmcs_writel(field, value);
2118 }
2119 
2120 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2121 {
2122         vmcs_check32(field);
2123         if (static_branch_unlikely(&enable_evmcs))
2124                 return evmcs_write32(field, value);
2125 
2126         __vmcs_writel(field, value);
2127 }
2128 
2129 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2130 {
2131         vmcs_check64(field);
2132         if (static_branch_unlikely(&enable_evmcs))
2133                 return evmcs_write64(field, value);
2134 
2135         __vmcs_writel(field, value);
2136 #ifndef CONFIG_X86_64
2137         asm volatile ("");
2138         __vmcs_writel(field+1, value >> 32);
2139 #endif
2140 }
2141 
2142 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2143 {
2144         vmcs_checkl(field);
2145         if (static_branch_unlikely(&enable_evmcs))
2146                 return evmcs_write64(field, value);
2147 
2148         __vmcs_writel(field, value);
2149 }
2150 
2151 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2152 {
2153         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2154                          "vmcs_clear_bits does not support 64-bit fields");
2155         if (static_branch_unlikely(&enable_evmcs))
2156                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2157 
2158         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2159 }
2160 
2161 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2162 {
2163         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2164                          "vmcs_set_bits does not support 64-bit fields");
2165         if (static_branch_unlikely(&enable_evmcs))
2166                 return evmcs_write32(field, evmcs_read32(field) | mask);
2167 
2168         __vmcs_writel(field, __vmcs_readl(field) | mask);
2169 }
2170 
2171 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2172 {
2173         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2174 }
2175 
2176 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2177 {
2178         vmcs_write32(VM_ENTRY_CONTROLS, val);
2179         vmx->vm_entry_controls_shadow = val;
2180 }
2181 
2182 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2183 {
2184         if (vmx->vm_entry_controls_shadow != val)
2185                 vm_entry_controls_init(vmx, val);
2186 }
2187 
2188 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2189 {
2190         return vmx->vm_entry_controls_shadow;
2191 }
2192 
2193 
2194 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2195 {
2196         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2197 }
2198 
2199 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2200 {
2201         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2202 }
2203 
2204 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2205 {
2206         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2207 }
2208 
2209 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2210 {
2211         vmcs_write32(VM_EXIT_CONTROLS, val);
2212         vmx->vm_exit_controls_shadow = val;
2213 }
2214 
2215 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2216 {
2217         if (vmx->vm_exit_controls_shadow != val)
2218                 vm_exit_controls_init(vmx, val);
2219 }
2220 
2221 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2222 {
2223         return vmx->vm_exit_controls_shadow;
2224 }
2225 
2226 
2227 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2228 {
2229         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2230 }
2231 
2232 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2233 {
2234         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2235 }
2236 
2237 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2238 {
2239         vmx->segment_cache.bitmask = 0;
2240 }
2241 
2242 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2243                                        unsigned field)
2244 {
2245         bool ret;
2246         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2247 
2248         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2249                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2250                 vmx->segment_cache.bitmask = 0;
2251         }
2252         ret = vmx->segment_cache.bitmask & mask;
2253         vmx->segment_cache.bitmask |= mask;
2254         return ret;
2255 }
2256 
2257 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2258 {
2259         u16 *p = &vmx->segment_cache.seg[seg].selector;
2260 
2261         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2262                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2263         return *p;
2264 }
2265 
2266 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2267 {
2268         ulong *p = &vmx->segment_cache.seg[seg].base;
2269 
2270         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2271                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2272         return *p;
2273 }
2274 
2275 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2276 {
2277         u32 *p = &vmx->segment_cache.seg[seg].limit;
2278 
2279         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2280                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2281         return *p;
2282 }
2283 
2284 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2285 {
2286         u32 *p = &vmx->segment_cache.seg[seg].ar;
2287 
2288         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2289                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2290         return *p;
2291 }
2292 
2293 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2294 {
2295         u32 eb;
2296 
2297         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2298              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2299         /*
2300          * Guest access to VMware backdoor ports could legitimately
2301          * trigger #GP because of TSS I/O permission bitmap.
2302          * We intercept those #GP and allow access to them anyway
2303          * as VMware does.
2304          */
2305         if (enable_vmware_backdoor)
2306                 eb |= (1u << GP_VECTOR);
2307         if ((vcpu->guest_debug &
2308              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2309             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2310                 eb |= 1u << BP_VECTOR;
2311         if (to_vmx(vcpu)->rmode.vm86_active)
2312                 eb = ~0;
2313         if (enable_ept)
2314                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2315 
2316         /* When we are running a nested L2 guest and L1 specified for it a
2317          * certain exception bitmap, we must trap the same exceptions and pass
2318          * them to L1. When running L2, we will only handle the exceptions
2319          * specified above if L1 did not want them.
2320          */
2321         if (is_guest_mode(vcpu))
2322                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2323 
2324         vmcs_write32(EXCEPTION_BITMAP, eb);
2325 }
2326 
2327 /*
2328  * Check if MSR is intercepted for currently loaded MSR bitmap.
2329  */
2330 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2331 {
2332         unsigned long *msr_bitmap;
2333         int f = sizeof(unsigned long);
2334 
2335         if (!cpu_has_vmx_msr_bitmap())
2336                 return true;
2337 
2338         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2339 
2340         if (msr <= 0x1fff) {
2341                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2342         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2343                 msr &= 0x1fff;
2344                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2345         }
2346 
2347         return true;
2348 }
2349 
2350 /*
2351  * Check if MSR is intercepted for L01 MSR bitmap.
2352  */
2353 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2354 {
2355         unsigned long *msr_bitmap;
2356         int f = sizeof(unsigned long);
2357 
2358         if (!cpu_has_vmx_msr_bitmap())
2359                 return true;
2360 
2361         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2362 
2363         if (msr <= 0x1fff) {
2364                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2365         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2366                 msr &= 0x1fff;
2367                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2368         }
2369 
2370         return true;
2371 }
2372 
2373 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2374                 unsigned long entry, unsigned long exit)
2375 {
2376         vm_entry_controls_clearbit(vmx, entry);
2377         vm_exit_controls_clearbit(vmx, exit);
2378 }
2379 
2380 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2381 {
2382         unsigned i;
2383         struct msr_autoload *m = &vmx->msr_autoload;
2384 
2385         switch (msr) {
2386         case MSR_EFER:
2387                 if (cpu_has_load_ia32_efer) {
2388                         clear_atomic_switch_msr_special(vmx,
2389                                         VM_ENTRY_LOAD_IA32_EFER,
2390                                         VM_EXIT_LOAD_IA32_EFER);
2391                         return;
2392                 }
2393                 break;
2394         case MSR_CORE_PERF_GLOBAL_CTRL:
2395                 if (cpu_has_load_perf_global_ctrl) {
2396                         clear_atomic_switch_msr_special(vmx,
2397                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2398                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2399                         return;
2400                 }
2401                 break;
2402         }
2403 
2404         for (i = 0; i < m->nr; ++i)
2405                 if (m->guest[i].index == msr)
2406                         break;
2407 
2408         if (i == m->nr)
2409                 return;
2410         --m->nr;
2411         m->guest[i] = m->guest[m->nr];
2412         m->host[i] = m->host[m->nr];
2413         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2414         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2415 }
2416 
2417 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2418                 unsigned long entry, unsigned long exit,
2419                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2420                 u64 guest_val, u64 host_val)
2421 {
2422         vmcs_write64(guest_val_vmcs, guest_val);
2423         vmcs_write64(host_val_vmcs, host_val);
2424         vm_entry_controls_setbit(vmx, entry);
2425         vm_exit_controls_setbit(vmx, exit);
2426 }
2427 
2428 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2429                                   u64 guest_val, u64 host_val)
2430 {
2431         unsigned i;
2432         struct msr_autoload *m = &vmx->msr_autoload;
2433 
2434         switch (msr) {
2435         case MSR_EFER:
2436                 if (cpu_has_load_ia32_efer) {
2437                         add_atomic_switch_msr_special(vmx,
2438                                         VM_ENTRY_LOAD_IA32_EFER,
2439                                         VM_EXIT_LOAD_IA32_EFER,
2440                                         GUEST_IA32_EFER,
2441                                         HOST_IA32_EFER,
2442                                         guest_val, host_val);
2443                         return;
2444                 }
2445                 break;
2446         case MSR_CORE_PERF_GLOBAL_CTRL:
2447                 if (cpu_has_load_perf_global_ctrl) {
2448                         add_atomic_switch_msr_special(vmx,
2449                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2450                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2451                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2452                                         HOST_IA32_PERF_GLOBAL_CTRL,
2453                                         guest_val, host_val);
2454                         return;
2455                 }
2456                 break;
2457         case MSR_IA32_PEBS_ENABLE:
2458                 /* PEBS needs a quiescent period after being disabled (to write
2459                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2460                  * provide that period, so a CPU could write host's record into
2461                  * guest's memory.
2462                  */
2463                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2464         }
2465 
2466         for (i = 0; i < m->nr; ++i)
2467                 if (m->guest[i].index == msr)
2468                         break;
2469 
2470         if (i == NR_AUTOLOAD_MSRS) {
2471                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2472                                 "Can't add msr %x\n", msr);
2473                 return;
2474         } else if (i == m->nr) {
2475                 ++m->nr;
2476                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2477                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2478         }
2479 
2480         m->guest[i].index = msr;
2481         m->guest[i].value = guest_val;
2482         m->host[i].index = msr;
2483         m->host[i].value = host_val;
2484 }
2485 
2486 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2487 {
2488         u64 guest_efer = vmx->vcpu.arch.efer;
2489         u64 ignore_bits = 0;
2490 
2491         if (!enable_ept) {
2492                 /*
2493                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2494                  * host CPUID is more efficient than testing guest CPUID
2495                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2496                  */
2497                 if (boot_cpu_has(X86_FEATURE_SMEP))
2498                         guest_efer |= EFER_NX;
2499                 else if (!(guest_efer & EFER_NX))
2500                         ignore_bits |= EFER_NX;
2501         }
2502 
2503         /*
2504          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2505          */
2506         ignore_bits |= EFER_SCE;
2507 #ifdef CONFIG_X86_64
2508         ignore_bits |= EFER_LMA | EFER_LME;
2509         /* SCE is meaningful only in long mode on Intel */
2510         if (guest_efer & EFER_LMA)
2511                 ignore_bits &= ~(u64)EFER_SCE;
2512 #endif
2513 
2514         clear_atomic_switch_msr(vmx, MSR_EFER);
2515 
2516         /*
2517          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2518          * On CPUs that support "load IA32_EFER", always switch EFER
2519          * atomically, since it's faster than switching it manually.
2520          */
2521         if (cpu_has_load_ia32_efer ||
2522             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2523                 if (!(guest_efer & EFER_LMA))
2524                         guest_efer &= ~EFER_LME;
2525                 if (guest_efer != host_efer)
2526                         add_atomic_switch_msr(vmx, MSR_EFER,
2527                                               guest_efer, host_efer);
2528                 return false;
2529         } else {
2530                 guest_efer &= ~ignore_bits;
2531                 guest_efer |= host_efer & ignore_bits;
2532 
2533                 vmx->guest_msrs[efer_offset].data = guest_efer;
2534                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2535 
2536                 return true;
2537         }
2538 }
2539 
2540 #ifdef CONFIG_X86_32
2541 /*
2542  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2543  * VMCS rather than the segment table.  KVM uses this helper to figure
2544  * out the current bases to poke them into the VMCS before entry.
2545  */
2546 static unsigned long segment_base(u16 selector)
2547 {
2548         struct desc_struct *table;
2549         unsigned long v;
2550 
2551         if (!(selector & ~SEGMENT_RPL_MASK))
2552                 return 0;
2553 
2554         table = get_current_gdt_ro();
2555 
2556         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2557                 u16 ldt_selector = kvm_read_ldt();
2558 
2559                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2560                         return 0;
2561 
2562                 table = (struct desc_struct *)segment_base(ldt_selector);
2563         }
2564         v = get_desc_base(&table[selector >> 3]);
2565         return v;
2566 }
2567 #endif
2568 
2569 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2570 {
2571         struct vcpu_vmx *vmx = to_vmx(vcpu);
2572 #ifdef CONFIG_X86_64
2573         int cpu = raw_smp_processor_id();
2574         unsigned long fs_base, kernel_gs_base;
2575 #endif
2576         int i;
2577 
2578         if (vmx->host_state.loaded)
2579                 return;
2580 
2581         vmx->host_state.loaded = 1;
2582         /*
2583          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2584          * allow segment selectors with cpl > 0 or ti == 1.
2585          */
2586         vmx->host_state.ldt_sel = kvm_read_ldt();
2587         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2588 
2589 #ifdef CONFIG_X86_64
2590         if (likely(is_64bit_mm(current->mm))) {
2591                 save_fsgs_for_kvm();
2592                 vmx->host_state.fs_sel = current->thread.fsindex;
2593                 vmx->host_state.gs_sel = current->thread.gsindex;
2594                 fs_base = current->thread.fsbase;
2595                 kernel_gs_base = current->thread.gsbase;
2596         } else {
2597 #endif
2598                 savesegment(fs, vmx->host_state.fs_sel);
2599                 savesegment(gs, vmx->host_state.gs_sel);
2600 #ifdef CONFIG_X86_64
2601                 fs_base = read_msr(MSR_FS_BASE);
2602                 kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2603         }
2604 #endif
2605         if (!(vmx->host_state.fs_sel & 7)) {
2606                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2607                 vmx->host_state.fs_reload_needed = 0;
2608         } else {
2609                 vmcs_write16(HOST_FS_SELECTOR, 0);
2610                 vmx->host_state.fs_reload_needed = 1;
2611         }
2612         if (!(vmx->host_state.gs_sel & 7))
2613                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2614         else {
2615                 vmcs_write16(HOST_GS_SELECTOR, 0);
2616                 vmx->host_state.gs_ldt_reload_needed = 1;
2617         }
2618 
2619 #ifdef CONFIG_X86_64
2620         savesegment(ds, vmx->host_state.ds_sel);
2621         savesegment(es, vmx->host_state.es_sel);
2622 
2623         vmcs_writel(HOST_FS_BASE, fs_base);
2624         vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2625 
2626         vmx->msr_host_kernel_gs_base = kernel_gs_base;
2627         if (is_long_mode(&vmx->vcpu))
2628                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2629 #else
2630         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2631         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2632 #endif
2633         if (boot_cpu_has(X86_FEATURE_MPX))
2634                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2635         for (i = 0; i < vmx->save_nmsrs; ++i)
2636                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2637                                    vmx->guest_msrs[i].data,
2638                                    vmx->guest_msrs[i].mask);
2639 }
2640 
2641 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2642 {
2643         if (!vmx->host_state.loaded)
2644                 return;
2645 
2646         ++vmx->vcpu.stat.host_state_reload;
2647         vmx->host_state.loaded = 0;
2648 #ifdef CONFIG_X86_64
2649         if (is_long_mode(&vmx->vcpu))
2650                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2651 #endif
2652         if (vmx->host_state.gs_ldt_reload_needed) {
2653                 kvm_load_ldt(vmx->host_state.ldt_sel);
2654 #ifdef CONFIG_X86_64
2655                 load_gs_index(vmx->host_state.gs_sel);
2656 #else
2657                 loadsegment(gs, vmx->host_state.gs_sel);
2658 #endif
2659         }
2660         if (vmx->host_state.fs_reload_needed)
2661                 loadsegment(fs, vmx->host_state.fs_sel);
2662 #ifdef CONFIG_X86_64
2663         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2664                 loadsegment(ds, vmx->host_state.ds_sel);
2665                 loadsegment(es, vmx->host_state.es_sel);
2666         }
2667 #endif
2668         invalidate_tss_limit();
2669 #ifdef CONFIG_X86_64
2670         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2671 #endif
2672         if (vmx->host_state.msr_host_bndcfgs)
2673                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2674         load_fixmap_gdt(raw_smp_processor_id());
2675 }
2676 
2677 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2678 {
2679         preempt_disable();
2680         __vmx_load_host_state(vmx);
2681         preempt_enable();
2682 }
2683 
2684 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2685 {
2686         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2687         struct pi_desc old, new;
2688         unsigned int dest;
2689 
2690         /*
2691          * In case of hot-plug or hot-unplug, we may have to undo
2692          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2693          * always keep PI.NDST up to date for simplicity: it makes the
2694          * code easier, and CPU migration is not a fast path.
2695          */
2696         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2697                 return;
2698 
2699         /*
2700          * First handle the simple case where no cmpxchg is necessary; just
2701          * allow posting non-urgent interrupts.
2702          *
2703          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2704          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2705          * expects the VCPU to be on the blocked_vcpu_list that matches
2706          * PI.NDST.
2707          */
2708         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2709             vcpu->cpu == cpu) {
2710                 pi_clear_sn(pi_desc);
2711                 return;
2712         }
2713 
2714         /* The full case.  */
2715         do {
2716                 old.control = new.control = pi_desc->control;
2717 
2718                 dest = cpu_physical_id(cpu);
2719 
2720                 if (x2apic_enabled())
2721                         new.ndst = dest;
2722                 else
2723                         new.ndst = (dest << 8) & 0xFF00;
2724 
2725                 new.sn = 0;
2726         } while (cmpxchg64(&pi_desc->control, old.control,
2727                            new.control) != old.control);
2728 }
2729 
2730 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2731 {
2732         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2733         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2734 }
2735 
2736 /*
2737  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2738  * vcpu mutex is already taken.
2739  */
2740 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2741 {
2742         struct vcpu_vmx *vmx = to_vmx(vcpu);
2743         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2744 
2745         if (!already_loaded) {
2746                 loaded_vmcs_clear(vmx->loaded_vmcs);
2747                 local_irq_disable();
2748                 crash_disable_local_vmclear(cpu);
2749 
2750                 /*
2751                  * Read loaded_vmcs->cpu should be before fetching
2752                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2753                  * See the comments in __loaded_vmcs_clear().
2754                  */
2755                 smp_rmb();
2756 
2757                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2758                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2759                 crash_enable_local_vmclear(cpu);
2760                 local_irq_enable();
2761         }
2762 
2763         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2764                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2765                 vmcs_load(vmx->loaded_vmcs->vmcs);
2766                 indirect_branch_prediction_barrier();
2767         }
2768 
2769         if (!already_loaded) {
2770                 void *gdt = get_current_gdt_ro();
2771                 unsigned long sysenter_esp;
2772 
2773                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2774 
2775                 /*
2776                  * Linux uses per-cpu TSS and GDT, so set these when switching
2777                  * processors.  See 22.2.4.
2778                  */
2779                 vmcs_writel(HOST_TR_BASE,
2780                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2781                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2782 
2783                 /*
2784                  * VM exits change the host TR limit to 0x67 after a VM
2785                  * exit.  This is okay, since 0x67 covers everything except
2786                  * the IO bitmap and have have code to handle the IO bitmap
2787                  * being lost after a VM exit.
2788                  */
2789                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2790 
2791                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2792                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2793 
2794                 vmx->loaded_vmcs->cpu = cpu;
2795         }
2796 
2797         /* Setup TSC multiplier */
2798         if (kvm_has_tsc_control &&
2799             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2800                 decache_tsc_multiplier(vmx);
2801 
2802         vmx_vcpu_pi_load(vcpu, cpu);
2803         vmx->host_pkru = read_pkru();
2804         vmx->host_debugctlmsr = get_debugctlmsr();
2805 }
2806 
2807 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2808 {
2809         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2810 
2811         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2812                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2813                 !kvm_vcpu_apicv_active(vcpu))
2814                 return;
2815 
2816         /* Set SN when the vCPU is preempted */
2817         if (vcpu->preempted)
2818                 pi_set_sn(pi_desc);
2819 }
2820 
2821 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2822 {
2823         vmx_vcpu_pi_put(vcpu);
2824 
2825         __vmx_load_host_state(to_vmx(vcpu));
2826 }
2827 
2828 static bool emulation_required(struct kvm_vcpu *vcpu)
2829 {
2830         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2831 }
2832 
2833 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2834 
2835 /*
2836  * Return the cr0 value that a nested guest would read. This is a combination
2837  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2838  * its hypervisor (cr0_read_shadow).
2839  */
2840 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2841 {
2842         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2843                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2844 }
2845 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2846 {
2847         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2848                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2849 }
2850 
2851 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2852 {
2853         unsigned long rflags, save_rflags;
2854 
2855         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2856                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2857                 rflags = vmcs_readl(GUEST_RFLAGS);
2858                 if (to_vmx(vcpu)->rmode.vm86_active) {
2859                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2860                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2861                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2862                 }
2863                 to_vmx(vcpu)->rflags = rflags;
2864         }
2865         return to_vmx(vcpu)->rflags;
2866 }
2867 
2868 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2869 {
2870         unsigned long old_rflags = vmx_get_rflags(vcpu);
2871 
2872         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2873         to_vmx(vcpu)->rflags = rflags;
2874         if (to_vmx(vcpu)->rmode.vm86_active) {
2875                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2876                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2877         }
2878         vmcs_writel(GUEST_RFLAGS, rflags);
2879 
2880         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2881                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2882 }
2883 
2884 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2885 {
2886         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2887         int ret = 0;
2888 
2889         if (interruptibility & GUEST_INTR_STATE_STI)
2890                 ret |= KVM_X86_SHADOW_INT_STI;
2891         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2892                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2893 
2894         return ret;
2895 }
2896 
2897 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2898 {
2899         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2900         u32 interruptibility = interruptibility_old;
2901 
2902         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2903 
2904         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2905                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2906         else if (mask & KVM_X86_SHADOW_INT_STI)
2907                 interruptibility |= GUEST_INTR_STATE_STI;
2908 
2909         if ((interruptibility != interruptibility_old))
2910                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2911 }
2912 
2913 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2914 {
2915         unsigned long rip;
2916 
2917         rip = kvm_rip_read(vcpu);
2918         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2919         kvm_rip_write(vcpu, rip);
2920 
2921         /* skipping an emulated instruction also counts */
2922         vmx_set_interrupt_shadow(vcpu, 0);
2923 }
2924 
2925 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2926                                                unsigned long exit_qual)
2927 {
2928         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2929         unsigned int nr = vcpu->arch.exception.nr;
2930         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2931 
2932         if (vcpu->arch.exception.has_error_code) {
2933                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2934                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2935         }
2936 
2937         if (kvm_exception_is_soft(nr))
2938                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2939         else
2940                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2941 
2942         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2943             vmx_get_nmi_mask(vcpu))
2944                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2945 
2946         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2947 }
2948 
2949 /*
2950  * KVM wants to inject page-faults which it got to the guest. This function
2951  * checks whether in a nested guest, we need to inject them to L1 or L2.
2952  */
2953 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2954 {
2955         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2956         unsigned int nr = vcpu->arch.exception.nr;
2957 
2958         if (nr == PF_VECTOR) {
2959                 if (vcpu->arch.exception.nested_apf) {
2960                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2961                         return 1;
2962                 }
2963                 /*
2964                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2965                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2966                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2967                  * can be written only when inject_pending_event runs.  This should be
2968                  * conditional on a new capability---if the capability is disabled,
2969                  * kvm_multiple_exception would write the ancillary information to
2970                  * CR2 or DR6, for backwards ABI-compatibility.
2971                  */
2972                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2973                                                     vcpu->arch.exception.error_code)) {
2974                         *exit_qual = vcpu->arch.cr2;
2975                         return 1;
2976                 }
2977         } else {
2978                 if (vmcs12->exception_bitmap & (1u << nr)) {
2979                         if (nr == DB_VECTOR)
2980                                 *exit_qual = vcpu->arch.dr6;
2981                         else
2982                                 *exit_qual = 0;
2983                         return 1;
2984                 }
2985         }
2986 
2987         return 0;
2988 }
2989 
2990 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2991 {
2992         /*
2993          * Ensure that we clear the HLT state in the VMCS.  We don't need to
2994          * explicitly skip the instruction because if the HLT state is set,
2995          * then the instruction is already executing and RIP has already been
2996          * advanced.
2997          */
2998         if (kvm_hlt_in_guest(vcpu->kvm) &&
2999                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3000                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3001 }
3002 
3003 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3004 {
3005         struct vcpu_vmx *vmx = to_vmx(vcpu);
3006         unsigned nr = vcpu->arch.exception.nr;
3007         bool has_error_code = vcpu->arch.exception.has_error_code;
3008         u32 error_code = vcpu->arch.exception.error_code;
3009         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3010 
3011         if (has_error_code) {
3012                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3013                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3014         }
3015 
3016         if (vmx->rmode.vm86_active) {
3017                 int inc_eip = 0;
3018                 if (kvm_exception_is_soft(nr))
3019                         inc_eip = vcpu->arch.event_exit_inst_len;
3020                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3021                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3022                 return;
3023         }
3024 
3025         WARN_ON_ONCE(vmx->emulation_required);
3026 
3027         if (kvm_exception_is_soft(nr)) {
3028                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3029                              vmx->vcpu.arch.event_exit_inst_len);
3030                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3031         } else
3032                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3033 
3034         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3035 
3036         vmx_clear_hlt(vcpu);
3037 }
3038 
3039 static bool vmx_rdtscp_supported(void)
3040 {
3041         return cpu_has_vmx_rdtscp();
3042 }
3043 
3044 static bool vmx_invpcid_supported(void)
3045 {
3046         return cpu_has_vmx_invpcid() && enable_ept;
3047 }
3048 
3049 /*
3050  * Swap MSR entry in host/guest MSR entry array.
3051  */
3052 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3053 {
3054         struct shared_msr_entry tmp;
3055 
3056         tmp = vmx->guest_msrs[to];
3057         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3058         vmx->guest_msrs[from] = tmp;
3059 }
3060 
3061 /*
3062  * Set up the vmcs to automatically save and restore system
3063  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3064  * mode, as fiddling with msrs is very expensive.
3065  */
3066 static void setup_msrs(struct vcpu_vmx *vmx)
3067 {
3068         int save_nmsrs, index;
3069 
3070         save_nmsrs = 0;
3071 #ifdef CONFIG_X86_64
3072         if (is_long_mode(&vmx->vcpu)) {
3073                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3074                 if (index >= 0)
3075                         move_msr_up(vmx, index, save_nmsrs++);
3076                 index = __find_msr_index(vmx, MSR_LSTAR);
3077                 if (index >= 0)
3078                         move_msr_up(vmx, index, save_nmsrs++);
3079                 index = __find_msr_index(vmx, MSR_CSTAR);
3080                 if (index >= 0)
3081                         move_msr_up(vmx, index, save_nmsrs++);
3082                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3083                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3084                         move_msr_up(vmx, index, save_nmsrs++);
3085                 /*
3086                  * MSR_STAR is only needed on long mode guests, and only
3087                  * if efer.sce is enabled.
3088                  */
3089                 index = __find_msr_index(vmx, MSR_STAR);
3090                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3091                         move_msr_up(vmx, index, save_nmsrs++);
3092         }
3093 #endif
3094         index = __find_msr_index(vmx, MSR_EFER);
3095         if (index >= 0 && update_transition_efer(vmx, index))
3096                 move_msr_up(vmx, index, save_nmsrs++);
3097 
3098         vmx->save_nmsrs = save_nmsrs;
3099 
3100         if (cpu_has_vmx_msr_bitmap())
3101                 vmx_update_msr_bitmap(&vmx->vcpu);
3102 }
3103 
3104 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3105 {
3106         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3107 
3108         if (is_guest_mode(vcpu) &&
3109             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3110                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3111 
3112         return vcpu->arch.tsc_offset;
3113 }
3114 
3115 /*
3116  * writes 'offset' into guest's timestamp counter offset register
3117  */
3118 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3119 {
3120         if (is_guest_mode(vcpu)) {
3121                 /*
3122                  * We're here if L1 chose not to trap WRMSR to TSC. According
3123                  * to the spec, this should set L1's TSC; The offset that L1
3124                  * set for L2 remains unchanged, and still needs to be added
3125                  * to the newly set TSC to get L2's TSC.
3126                  */
3127                 struct vmcs12 *vmcs12;
3128                 /* recalculate vmcs02.TSC_OFFSET: */
3129                 vmcs12 = get_vmcs12(vcpu);
3130                 vmcs_write64(TSC_OFFSET, offset +
3131                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3132                          vmcs12->tsc_offset : 0));
3133         } else {
3134                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3135                                            vmcs_read64(TSC_OFFSET), offset);
3136                 vmcs_write64(TSC_OFFSET, offset);
3137         }
3138 }
3139 
3140 /*
3141  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3142  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3143  * all guests if the "nested" module option is off, and can also be disabled
3144  * for a single guest by disabling its VMX cpuid bit.
3145  */
3146 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3147 {
3148         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3149 }
3150 
3151 /*
3152  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3153  * returned for the various VMX controls MSRs when nested VMX is enabled.
3154  * The same values should also be used to verify that vmcs12 control fields are
3155  * valid during nested entry from L1 to L2.
3156  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3157  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3158  * bit in the high half is on if the corresponding bit in the control field
3159  * may be on. See also vmx_control_verify().
3160  */
3161 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3162 {
3163         if (!nested) {
3164                 memset(msrs, 0, sizeof(*msrs));
3165                 return;
3166         }
3167 
3168         /*
3169          * Note that as a general rule, the high half of the MSRs (bits in
3170          * the control fields which may be 1) should be initialized by the
3171          * intersection of the underlying hardware's MSR (i.e., features which
3172          * can be supported) and the list of features we want to expose -
3173          * because they are known to be properly supported in our code.
3174          * Also, usually, the low half of the MSRs (bits which must be 1) can
3175          * be set to 0, meaning that L1 may turn off any of these bits. The
3176          * reason is that if one of these bits is necessary, it will appear
3177          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3178          * fields of vmcs01 and vmcs02, will turn these bits off - and
3179          * nested_vmx_exit_reflected() will not pass related exits to L1.
3180          * These rules have exceptions below.
3181          */
3182 
3183         /* pin-based controls */
3184         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3185                 msrs->pinbased_ctls_low,
3186                 msrs->pinbased_ctls_high);
3187         msrs->pinbased_ctls_low |=
3188                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3189         msrs->pinbased_ctls_high &=
3190                 PIN_BASED_EXT_INTR_MASK |
3191                 PIN_BASED_NMI_EXITING |
3192                 PIN_BASED_VIRTUAL_NMIS |
3193                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3194         msrs->pinbased_ctls_high |=
3195                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3196                 PIN_BASED_VMX_PREEMPTION_TIMER;
3197 
3198         /* exit controls */
3199         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3200                 msrs->exit_ctls_low,
3201                 msrs->exit_ctls_high);
3202         msrs->exit_ctls_low =
3203                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3204 
3205         msrs->exit_ctls_high &=
3206 #ifdef CONFIG_X86_64
3207                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3208 #endif
3209                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3210         msrs->exit_ctls_high |=
3211                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3212                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3213                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3214 
3215         if (kvm_mpx_supported())
3216                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3217 
3218         /* We support free control of debug control saving. */
3219         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3220 
3221         /* entry controls */
3222         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3223                 msrs->entry_ctls_low,
3224                 msrs->entry_ctls_high);
3225         msrs->entry_ctls_low =
3226                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3227         msrs->entry_ctls_high &=
3228 #ifdef CONFIG_X86_64
3229                 VM_ENTRY_IA32E_MODE |
3230 #endif
3231                 VM_ENTRY_LOAD_IA32_PAT;
3232         msrs->entry_ctls_high |=
3233                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3234         if (kvm_mpx_supported())
3235                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3236 
3237         /* We support free control of debug control loading. */
3238         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3239 
3240         /* cpu-based controls */
3241         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3242                 msrs->procbased_ctls_low,
3243                 msrs->procbased_ctls_high);
3244         msrs->procbased_ctls_low =
3245                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3246         msrs->procbased_ctls_high &=
3247                 CPU_BASED_VIRTUAL_INTR_PENDING |
3248                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3249                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3250                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3251                 CPU_BASED_CR3_STORE_EXITING |
3252 #ifdef CONFIG_X86_64
3253                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3254 #endif
3255                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3256                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3257                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3258                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3259                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3260         /*
3261          * We can allow some features even when not supported by the
3262          * hardware. For example, L1 can specify an MSR bitmap - and we
3263          * can use it to avoid exits to L1 - even when L0 runs L2
3264          * without MSR bitmaps.
3265          */
3266         msrs->procbased_ctls_high |=
3267                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3268                 CPU_BASED_USE_MSR_BITMAPS;
3269 
3270         /* We support free control of CR3 access interception. */
3271         msrs->procbased_ctls_low &=
3272                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3273 
3274         /*
3275          * secondary cpu-based controls.  Do not include those that
3276          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3277          */
3278         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3279                 msrs->secondary_ctls_low,
3280                 msrs->secondary_ctls_high);
3281         msrs->secondary_ctls_low = 0;
3282         msrs->secondary_ctls_high &=
3283                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3284                 SECONDARY_EXEC_DESC |
3285                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3286                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3287                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3288                 SECONDARY_EXEC_WBINVD_EXITING;
3289 
3290         if (enable_ept) {
3291                 /* nested EPT: emulate EPT also to L1 */
3292                 msrs->secondary_ctls_high |=
3293                         SECONDARY_EXEC_ENABLE_EPT;
3294                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3295                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3296                 if (cpu_has_vmx_ept_execute_only())
3297                         msrs->ept_caps |=
3298                                 VMX_EPT_EXECUTE_ONLY_BIT;
3299                 msrs->ept_caps &= vmx_capability.ept;
3300                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3301                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3302                         VMX_EPT_1GB_PAGE_BIT;
3303                 if (enable_ept_ad_bits) {
3304                         msrs->secondary_ctls_high |=
3305                                 SECONDARY_EXEC_ENABLE_PML;
3306                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3307                 }
3308         }
3309 
3310         if (cpu_has_vmx_vmfunc()) {
3311                 msrs->secondary_ctls_high |=
3312                         SECONDARY_EXEC_ENABLE_VMFUNC;
3313                 /*
3314                  * Advertise EPTP switching unconditionally
3315                  * since we emulate it
3316                  */
3317                 if (enable_ept)
3318                         msrs->vmfunc_controls =
3319                                 VMX_VMFUNC_EPTP_SWITCHING;
3320         }
3321 
3322         /*
3323          * Old versions of KVM use the single-context version without
3324          * checking for support, so declare that it is supported even
3325          * though it is treated as global context.  The alternative is
3326          * not failing the single-context invvpid, and it is worse.
3327          */
3328         if (enable_vpid) {
3329                 msrs->secondary_ctls_high |=
3330                         SECONDARY_EXEC_ENABLE_VPID;
3331                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3332                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3333         }
3334 
3335         if (enable_unrestricted_guest)
3336                 msrs->secondary_ctls_high |=
3337                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3338 
3339         /* miscellaneous data */
3340         rdmsr(MSR_IA32_VMX_MISC,
3341                 msrs->misc_low,
3342                 msrs->misc_high);
3343         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3344         msrs->misc_low |=
3345                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3346                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3347                 VMX_MISC_ACTIVITY_HLT;
3348         msrs->misc_high = 0;
3349 
3350         /*
3351          * This MSR reports some information about VMX support. We
3352          * should return information about the VMX we emulate for the
3353          * guest, and the VMCS structure we give it - not about the
3354          * VMX support of the underlying hardware.
3355          */
3356         msrs->basic =
3357                 VMCS12_REVISION |
3358                 VMX_BASIC_TRUE_CTLS |
3359                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3360                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3361 
3362         if (cpu_has_vmx_basic_inout())
3363                 msrs->basic |= VMX_BASIC_INOUT;
3364 
3365         /*
3366          * These MSRs specify bits which the guest must keep fixed on
3367          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3368          * We picked the standard core2 setting.
3369          */
3370 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3371 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3372         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3373         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3374 
3375         /* These MSRs specify bits which the guest must keep fixed off. */
3376         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3377         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3378 
3379         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3380         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3381 }
3382 
3383 /*
3384  * if fixed0[i] == 1: val[i] must be 1
3385  * if fixed1[i] == 0: val[i] must be 0
3386  */
3387 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3388 {
3389         return ((val & fixed1) | fixed0) == val;
3390 }
3391 
3392 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3393 {
3394         return fixed_bits_valid(control, low, high);
3395 }
3396 
3397 static inline u64 vmx_control_msr(u32 low, u32 high)
3398 {
3399         return low | ((u64)high << 32);
3400 }
3401 
3402 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3403 {
3404         superset &= mask;
3405         subset &= mask;
3406 
3407         return (superset | subset) == superset;
3408 }
3409 
3410 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3411 {
3412         const u64 feature_and_reserved =
3413                 /* feature (except bit 48; see below) */
3414                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3415                 /* reserved */
3416                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3417         u64 vmx_basic = vmx->nested.msrs.basic;
3418 
3419         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3420                 return -EINVAL;
3421 
3422         /*
3423          * KVM does not emulate a version of VMX that constrains physical
3424          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3425          */
3426         if (data & BIT_ULL(48))
3427                 return -EINVAL;
3428 
3429         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3430             vmx_basic_vmcs_revision_id(data))
3431                 return -EINVAL;
3432 
3433         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3434                 return -EINVAL;
3435 
3436         vmx->nested.msrs.basic = data;
3437         return 0;
3438 }
3439 
3440 static int
3441 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3442 {
3443         u64 supported;
3444         u32 *lowp, *highp;
3445 
3446         switch (msr_index) {
3447         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3448                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3449                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3450                 break;
3451         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3452                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3453                 highp = &vmx->nested.msrs.procbased_ctls_high;
3454                 break;
3455         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3456                 lowp = &vmx->nested.msrs.exit_ctls_low;
3457                 highp = &vmx->nested.msrs.exit_ctls_high;
3458                 break;
3459         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3460                 lowp = &vmx->nested.msrs.entry_ctls_low;
3461                 highp = &vmx->nested.msrs.entry_ctls_high;
3462                 break;
3463         case MSR_IA32_VMX_PROCBASED_CTLS2:
3464                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3465                 highp = &vmx->nested.msrs.secondary_ctls_high;
3466                 break;
3467         default:
3468                 BUG();
3469         }
3470 
3471         supported = vmx_control_msr(*lowp, *highp);
3472 
3473         /* Check must-be-1 bits are still 1. */
3474         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3475                 return -EINVAL;
3476 
3477         /* Check must-be-0 bits are still 0. */
3478         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3479                 return -EINVAL;
3480 
3481         *lowp = data;
3482         *highp = data >> 32;
3483         return 0;
3484 }
3485 
3486 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3487 {
3488         const u64 feature_and_reserved_bits =
3489                 /* feature */
3490                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3491                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3492                 /* reserved */
3493                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3494         u64 vmx_misc;
3495 
3496         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3497                                    vmx->nested.msrs.misc_high);
3498 
3499         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3500                 return -EINVAL;
3501 
3502         if ((vmx->nested.msrs.pinbased_ctls_high &
3503              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3504             vmx_misc_preemption_timer_rate(data) !=
3505             vmx_misc_preemption_timer_rate(vmx_misc))
3506                 return -EINVAL;
3507 
3508         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3509                 return -EINVAL;
3510 
3511         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3512                 return -EINVAL;
3513 
3514         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3515                 return -EINVAL;
3516 
3517         vmx->nested.msrs.misc_low = data;
3518         vmx->nested.msrs.misc_high = data >> 32;
3519 
3520         /*
3521          * If L1 has read-only VM-exit information fields, use the
3522          * less permissive vmx_vmwrite_bitmap to specify write
3523          * permissions for the shadow VMCS.
3524          */
3525         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3526                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3527 
3528         return 0;
3529 }
3530 
3531 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3532 {
3533         u64 vmx_ept_vpid_cap;
3534 
3535         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3536                                            vmx->nested.msrs.vpid_caps);
3537 
3538         /* Every bit is either reserved or a feature bit. */
3539         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3540                 return -EINVAL;
3541 
3542         vmx->nested.msrs.ept_caps = data;
3543         vmx->nested.msrs.vpid_caps = data >> 32;
3544         return 0;
3545 }
3546 
3547 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3548 {
3549         u64 *msr;
3550 
3551         switch (msr_index) {
3552         case MSR_IA32_VMX_CR0_FIXED0:
3553                 msr = &vmx->nested.msrs.cr0_fixed0;
3554                 break;
3555         case MSR_IA32_VMX_CR4_FIXED0:
3556                 msr = &vmx->nested.msrs.cr4_fixed0;
3557                 break;
3558         default:
3559                 BUG();
3560         }
3561 
3562         /*
3563          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3564          * must be 1 in the restored value.
3565          */
3566         if (!is_bitwise_subset(data, *msr, -1ULL))
3567                 return -EINVAL;
3568 
3569         *msr = data;
3570         return 0;
3571 }
3572 
3573 /*
3574  * Called when userspace is restoring VMX MSRs.
3575  *
3576  * Returns 0 on success, non-0 otherwise.
3577  */
3578 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3579 {
3580         struct vcpu_vmx *vmx = to_vmx(vcpu);
3581 
3582         /*
3583          * Don't allow changes to the VMX capability MSRs while the vCPU
3584          * is in VMX operation.
3585          */
3586         if (vmx->nested.vmxon)
3587                 return -EBUSY;
3588 
3589         switch (msr_index) {
3590         case MSR_IA32_VMX_BASIC:
3591                 return vmx_restore_vmx_basic(vmx, data);
3592         case MSR_IA32_VMX_PINBASED_CTLS:
3593         case MSR_IA32_VMX_PROCBASED_CTLS:
3594         case MSR_IA32_VMX_EXIT_CTLS:
3595         case MSR_IA32_VMX_ENTRY_CTLS:
3596                 /*
3597                  * The "non-true" VMX capability MSRs are generated from the
3598                  * "true" MSRs, so we do not support restoring them directly.
3599                  *
3600                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3601                  * should restore the "true" MSRs with the must-be-1 bits
3602                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3603                  * DEFAULT SETTINGS".
3604                  */
3605                 return -EINVAL;
3606         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3607         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3608         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3609         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3610         case MSR_IA32_VMX_PROCBASED_CTLS2:
3611                 return vmx_restore_control_msr(vmx, msr_index, data);
3612         case MSR_IA32_VMX_MISC:
3613                 return vmx_restore_vmx_misc(vmx, data);
3614         case MSR_IA32_VMX_CR0_FIXED0:
3615         case MSR_IA32_VMX_CR4_FIXED0:
3616                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3617         case MSR_IA32_VMX_CR0_FIXED1:
3618         case MSR_IA32_VMX_CR4_FIXED1:
3619                 /*
3620                  * These MSRs are generated based on the vCPU's CPUID, so we
3621                  * do not support restoring them directly.
3622                  */
3623                 return -EINVAL;
3624         case MSR_IA32_VMX_EPT_VPID_CAP:
3625                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3626         case MSR_IA32_VMX_VMCS_ENUM:
3627                 vmx->nested.msrs.vmcs_enum = data;
3628                 return 0;
3629         default:
3630                 /*
3631                  * The rest of the VMX capability MSRs do not support restore.
3632                  */
3633                 return -EINVAL;
3634         }
3635 }
3636 
3637 /* Returns 0 on success, non-0 otherwise. */
3638 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3639 {
3640         switch (msr_index) {
3641         case MSR_IA32_VMX_BASIC:
3642                 *pdata = msrs->basic;
3643                 break;
3644         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3645         case MSR_IA32_VMX_PINBASED_CTLS:
3646                 *pdata = vmx_control_msr(
3647                         msrs->pinbased_ctls_low,
3648                         msrs->pinbased_ctls_high);
3649                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3650                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3651                 break;
3652         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3653         case MSR_IA32_VMX_PROCBASED_CTLS:
3654                 *pdata = vmx_control_msr(
3655                         msrs->procbased_ctls_low,
3656                         msrs->procbased_ctls_high);
3657                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3658                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3659                 break;
3660         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3661         case MSR_IA32_VMX_EXIT_CTLS:
3662                 *pdata = vmx_control_msr(
3663                         msrs->exit_ctls_low,
3664                         msrs->exit_ctls_high);
3665                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3666                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3667                 break;
3668         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3669         case MSR_IA32_VMX_ENTRY_CTLS:
3670                 *pdata = vmx_control_msr(
3671                         msrs->entry_ctls_low,
3672                         msrs->entry_ctls_high);
3673                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3674                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3675                 break;
3676         case MSR_IA32_VMX_MISC:
3677                 *pdata = vmx_control_msr(
3678                         msrs->misc_low,
3679                         msrs->misc_high);
3680                 break;
3681         case MSR_IA32_VMX_CR0_FIXED0:
3682                 *pdata = msrs->cr0_fixed0;
3683                 break;
3684         case MSR_IA32_VMX_CR0_FIXED1:
3685                 *pdata = msrs->cr0_fixed1;
3686                 break;
3687         case MSR_IA32_VMX_CR4_FIXED0:
3688                 *pdata = msrs->cr4_fixed0;
3689                 break;
3690         case MSR_IA32_VMX_CR4_FIXED1:
3691                 *pdata = msrs->cr4_fixed1;
3692                 break;
3693         case MSR_IA32_VMX_VMCS_ENUM:
3694                 *pdata = msrs->vmcs_enum;
3695                 break;
3696         case MSR_IA32_VMX_PROCBASED_CTLS2:
3697                 *pdata = vmx_control_msr(
3698                         msrs->secondary_ctls_low,
3699                         msrs->secondary_ctls_high);
3700                 break;
3701         case MSR_IA32_VMX_EPT_VPID_CAP:
3702                 *pdata = msrs->ept_caps |
3703                         ((u64)msrs->vpid_caps << 32);
3704                 break;
3705         case MSR_IA32_VMX_VMFUNC:
3706                 *pdata = msrs->vmfunc_controls;
3707                 break;
3708         default:
3709                 return 1;
3710         }
3711 
3712         return 0;
3713 }
3714 
3715 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3716                                                  uint64_t val)
3717 {
3718         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3719 
3720         return !(val & ~valid_bits);
3721 }
3722 
3723 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3724 {
3725         switch (msr->index) {
3726         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3727                 if (!nested)
3728                         return 1;
3729                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3730         default:
3731                 return 1;
3732         }
3733 
3734         return 0;
3735 }
3736 
3737 /*
3738  * Reads an msr value (of 'msr_index') into 'pdata'.
3739  * Returns 0 on success, non-0 otherwise.
3740  * Assumes vcpu_load() was already called.
3741  */
3742 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3743 {
3744         struct vcpu_vmx *vmx = to_vmx(vcpu);
3745         struct shared_msr_entry *msr;
3746 
3747         switch (msr_info->index) {
3748 #ifdef CONFIG_X86_64
3749         case MSR_FS_BASE:
3750                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3751                 break;
3752         case MSR_GS_BASE:
3753                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3754                 break;
3755         case MSR_KERNEL_GS_BASE:
3756                 vmx_load_host_state(vmx);
3757                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3758                 break;
3759 #endif
3760         case MSR_EFER:
3761                 return kvm_get_msr_common(vcpu, msr_info);
3762         case MSR_IA32_SPEC_CTRL:
3763                 if (!msr_info->host_initiated &&
3764                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3765                         return 1;
3766 
3767                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3768                 break;
3769         case MSR_IA32_ARCH_CAPABILITIES:
3770                 if (!msr_info->host_initiated &&
3771                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3772                         return 1;
3773                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3774                 break;
3775         case MSR_IA32_SYSENTER_CS:
3776                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3777                 break;
3778         case MSR_IA32_SYSENTER_EIP:
3779                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3780                 break;
3781         case MSR_IA32_SYSENTER_ESP:
3782                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3783                 break;
3784         case MSR_IA32_BNDCFGS:
3785                 if (!kvm_mpx_supported() ||
3786                     (!msr_info->host_initiated &&
3787                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3788                         return 1;
3789                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3790                 break;
3791         case MSR_IA32_MCG_EXT_CTL:
3792                 if (!msr_info->host_initiated &&
3793                     !(vmx->msr_ia32_feature_control &
3794                       FEATURE_CONTROL_LMCE))
3795                         return 1;
3796                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3797                 break;
3798         case MSR_IA32_FEATURE_CONTROL:
3799                 msr_info->data = vmx->msr_ia32_feature_control;
3800                 break;
3801         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3802                 if (!nested_vmx_allowed(vcpu))
3803                         return 1;
3804                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3805                                        &msr_info->data);
3806         case MSR_IA32_XSS:
3807                 if (!vmx_xsaves_supported())
3808                         return 1;
3809                 msr_info->data = vcpu->arch.ia32_xss;
3810                 break;
3811         case MSR_TSC_AUX:
3812                 if (!msr_info->host_initiated &&
3813                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3814                         return 1;
3815                 /* Otherwise falls through */
3816         default:
3817                 msr = find_msr_entry(vmx, msr_info->index);
3818                 if (msr) {
3819                         msr_info->data = msr->data;
3820                         break;
3821                 }
3822                 return kvm_get_msr_common(vcpu, msr_info);
3823         }
3824 
3825         return 0;
3826 }
3827 
3828 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3829 
3830 /*
3831  * Writes msr value into into the appropriate "register".
3832  * Returns 0 on success, non-0 otherwise.
3833  * Assumes vcpu_load() was already called.
3834  */
3835 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3836 {
3837         struct vcpu_vmx *vmx = to_vmx(vcpu);
3838         struct shared_msr_entry *msr;
3839         int ret = 0;
3840         u32 msr_index = msr_info->index;
3841         u64 data = msr_info->data;
3842 
3843         switch (msr_index) {
3844         case MSR_EFER:
3845                 ret = kvm_set_msr_common(vcpu, msr_info);
3846                 break;
3847 #ifdef CONFIG_X86_64
3848         case MSR_FS_BASE:
3849                 vmx_segment_cache_clear(vmx);
3850                 vmcs_writel(GUEST_FS_BASE, data);
3851                 break;
3852         case MSR_GS_BASE:
3853                 vmx_segment_cache_clear(vmx);
3854                 vmcs_writel(GUEST_GS_BASE, data);
3855                 break;
3856         case MSR_KERNEL_GS_BASE:
3857                 vmx_load_host_state(vmx);
3858                 vmx->msr_guest_kernel_gs_base = data;
3859                 break;
3860 #endif
3861         case MSR_IA32_SYSENTER_CS:
3862                 vmcs_write32(GUEST_SYSENTER_CS, data);
3863                 break;
3864         case MSR_IA32_SYSENTER_EIP:
3865                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3866                 break;
3867         case MSR_IA32_SYSENTER_ESP:
3868                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3869                 break;
3870         case MSR_IA32_BNDCFGS:
3871                 if (!kvm_mpx_supported() ||
3872                     (!msr_info->host_initiated &&
3873                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3874                         return 1;
3875                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3876                     (data & MSR_IA32_BNDCFGS_RSVD))
3877                         return 1;
3878                 vmcs_write64(GUEST_BNDCFGS, data);
3879                 break;
3880         case MSR_IA32_SPEC_CTRL:
3881                 if (!msr_info->host_initiated &&
3882                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3883                         return 1;
3884 
3885                 /* The STIBP bit doesn't fault even if it's not advertised */
3886                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3887                         return 1;
3888 
3889                 vmx->spec_ctrl = data;
3890 
3891                 if (!data)
3892                         break;
3893 
3894                 /*
3895                  * For non-nested:
3896                  * When it's written (to non-zero) for the first time, pass
3897                  * it through.
3898                  *
3899                  * For nested:
3900                  * The handling of the MSR bitmap for L2 guests is done in
3901                  * nested_vmx_merge_msr_bitmap. We should not touch the
3902                  * vmcs02.msr_bitmap here since it gets completely overwritten
3903                  * in the merging. We update the vmcs01 here for L1 as well
3904                  * since it will end up touching the MSR anyway now.
3905                  */
3906                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3907                                               MSR_IA32_SPEC_CTRL,
3908                                               MSR_TYPE_RW);
3909                 break;
3910         case MSR_IA32_PRED_CMD:
3911                 if (!msr_info->host_initiated &&
3912                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3913                         return 1;
3914 
3915                 if (data & ~PRED_CMD_IBPB)
3916                         return 1;
3917 
3918                 if (!data)
3919                         break;
3920 
3921                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3922 
3923                 /*
3924                  * For non-nested:
3925                  * When it's written (to non-zero) for the first time, pass
3926                  * it through.
3927                  *
3928                  * For nested:
3929                  * The handling of the MSR bitmap for L2 guests is done in
3930                  * nested_vmx_merge_msr_bitmap. We should not touch the
3931                  * vmcs02.msr_bitmap here since it gets completely overwritten
3932                  * in the merging.
3933                  */
3934                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3935                                               MSR_TYPE_W);
3936                 break;
3937         case MSR_IA32_ARCH_CAPABILITIES:
3938                 if (!msr_info->host_initiated)
3939                         return 1;
3940                 vmx->arch_capabilities = data;
3941                 break;
3942         case MSR_IA32_CR_PAT:
3943                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3944                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3945                                 return 1;
3946                         vmcs_write64(GUEST_IA32_PAT, data);
3947                         vcpu->arch.pat = data;
3948                         break;
3949                 }
3950                 ret = kvm_set_msr_common(vcpu, msr_info);
3951                 break;
3952         case MSR_IA32_TSC_ADJUST:
3953                 ret = kvm_set_msr_common(vcpu, msr_info);
3954                 break;
3955         case MSR_IA32_MCG_EXT_CTL:
3956                 if ((!msr_info->host_initiated &&
3957                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3958                        FEATURE_CONTROL_LMCE)) ||
3959                     (data & ~MCG_EXT_CTL_LMCE_EN))
3960                         return 1;
3961                 vcpu->arch.mcg_ext_ctl = data;
3962                 break;
3963         case MSR_IA32_FEATURE_CONTROL:
3964                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3965                     (to_vmx(vcpu)->msr_ia32_feature_control &
3966                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3967                         return 1;
3968                 vmx->msr_ia32_feature_control = data;
3969                 if (msr_info->host_initiated && data == 0)
3970                         vmx_leave_nested(vcpu);
3971                 break;
3972         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3973                 if (!msr_info->host_initiated)
3974                         return 1; /* they are read-only */
3975                 if (!nested_vmx_allowed(vcpu))
3976                         return 1;
3977                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3978         case MSR_IA32_XSS:
3979                 if (!vmx_xsaves_supported())
3980                         return 1;
3981                 /*
3982                  * The only supported bit as of Skylake is bit 8, but
3983                  * it is not supported on KVM.
3984                  */
3985                 if (data != 0)
3986                         return 1;
3987                 vcpu->arch.ia32_xss = data;
3988                 if (vcpu->arch.ia32_xss != host_xss)
3989                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3990                                 vcpu->arch.ia32_xss, host_xss);
3991                 else
3992                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3993                 break;
3994         case MSR_TSC_AUX:
3995                 if (!msr_info->host_initiated &&
3996                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3997                         return 1;
3998                 /* Check reserved bit, higher 32 bits should be zero */
3999                 if ((data >> 32) != 0)
4000                         return 1;
4001                 /* Otherwise falls through */
4002         default:
4003                 msr = find_msr_entry(vmx, msr_index);
4004                 if (msr) {
4005                         u64 old_msr_data = msr->data;
4006                         msr->data = data;
4007                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4008                                 preempt_disable();
4009                                 ret = kvm_set_shared_msr(msr->index, msr->data,
4010                                                          msr->mask);
4011                                 preempt_enable();
4012                                 if (ret)
4013                                         msr->data = old_msr_data;
4014                         }
4015                         break;
4016                 }
4017                 ret = kvm_set_msr_common(vcpu, msr_info);
4018         }
4019 
4020         return ret;
4021 }
4022 
4023 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4024 {
4025         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4026         switch (reg) {
4027         case VCPU_REGS_RSP:
4028                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4029                 break;
4030         case VCPU_REGS_RIP:
4031                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4032                 break;
4033         case VCPU_EXREG_PDPTR:
4034                 if (enable_ept)
4035                         ept_save_pdptrs(vcpu);
4036                 break;
4037         default:
4038                 break;
4039         }
4040 }
4041 
4042 static __init int cpu_has_kvm_support(void)
4043 {
4044         return cpu_has_vmx();
4045 }
4046 
4047 static __init int vmx_disabled_by_bios(void)
4048 {
4049         u64 msr;
4050 
4051         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4052         if (msr & FEATURE_CONTROL_LOCKED) {
4053                 /* launched w/ TXT and VMX disabled */
4054                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4055                         && tboot_enabled())
4056                         return 1;
4057                 /* launched w/o TXT and VMX only enabled w/ TXT */
4058                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4059                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4060                         && !tboot_enabled()) {
4061                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4062                                 "activate TXT before enabling KVM\n");
4063                         return 1;
4064                 }
4065                 /* launched w/o TXT and VMX disabled */
4066                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4067                         && !tboot_enabled())
4068                         return 1;
4069         }
4070 
4071         return 0;
4072 }
4073 
4074 static void kvm_cpu_vmxon(u64 addr)
4075 {
4076         cr4_set_bits(X86_CR4_VMXE);
4077         intel_pt_handle_vmx(1);
4078 
4079         asm volatile (ASM_VMX_VMXON_RAX
4080                         : : "a"(&addr), "m"(addr)
4081                         : "memory", "cc");
4082 }
4083 
4084 static int hardware_enable(void)
4085 {
4086         int cpu = raw_smp_processor_id();
4087         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4088         u64 old, test_bits;
4089 
4090         if (cr4_read_shadow() & X86_CR4_VMXE)
4091                 return -EBUSY;
4092 
4093         /*
4094          * This can happen if we hot-added a CPU but failed to allocate
4095          * VP assist page for it.
4096          */
4097         if (static_branch_unlikely(&enable_evmcs) &&
4098             !hv_get_vp_assist_page(cpu))
4099                 return -EFAULT;
4100 
4101         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4102         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4103         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4104 
4105         /*
4106          * Now we can enable the vmclear operation in kdump
4107          * since the loaded_vmcss_on_cpu list on this cpu
4108          * has been initialized.
4109          *
4110          * Though the cpu is not in VMX operation now, there
4111          * is no problem to enable the vmclear operation
4112          * for the loaded_vmcss_on_cpu list is empty!
4113          */
4114         crash_enable_local_vmclear(cpu);
4115 
4116         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4117 
4118         test_bits = FEATURE_CONTROL_LOCKED;
4119         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4120         if (tboot_enabled())
4121                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4122 
4123         if ((old & test_bits) != test_bits) {
4124                 /* enable and lock */
4125                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4126         }
4127         kvm_cpu_vmxon(phys_addr);
4128         if (enable_ept)
4129                 ept_sync_global();
4130 
4131         return 0;
4132 }
4133 
4134 static void vmclear_local_loaded_vmcss(void)
4135 {
4136         int cpu = raw_smp_processor_id();
4137         struct loaded_vmcs *v, *n;
4138 
4139         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4140                                  loaded_vmcss_on_cpu_link)
4141                 __loaded_vmcs_clear(v);
4142 }
4143 
4144 
4145 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4146  * tricks.
4147  */
4148 static void kvm_cpu_vmxoff(void)
4149 {
4150         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4151 
4152         intel_pt_handle_vmx(0);
4153         cr4_clear_bits(X86_CR4_VMXE);
4154 }
4155 
4156 static void hardware_disable(void)
4157 {
4158         vmclear_local_loaded_vmcss();
4159         kvm_cpu_vmxoff();
4160 }
4161 
4162 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4163                                       u32 msr, u32 *result)
4164 {
4165         u32 vmx_msr_low, vmx_msr_high;
4166         u32 ctl = ctl_min | ctl_opt;
4167 
4168         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4169 
4170         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4171         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4172 
4173         /* Ensure minimum (required) set of control bits are supported. */
4174         if (ctl_min & ~ctl)
4175                 return -EIO;
4176 
4177         *result = ctl;
4178         return 0;
4179 }
4180 
4181 static __init bool allow_1_setting(u32 msr, u32 ctl)
4182 {
4183         u32 vmx_msr_low, vmx_msr_high;
4184 
4185         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4186         return vmx_msr_high & ctl;
4187 }
4188 
4189 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4190 {
4191         u32 vmx_msr_low, vmx_msr_high;
4192         u32 min, opt, min2, opt2;
4193         u32 _pin_based_exec_control = 0;
4194         u32 _cpu_based_exec_control = 0;
4195         u32 _cpu_based_2nd_exec_control = 0;
4196         u32 _vmexit_control = 0;
4197         u32 _vmentry_control = 0;
4198 
4199         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4200         min = CPU_BASED_HLT_EXITING |
4201 #ifdef CONFIG_X86_64
4202               CPU_BASED_CR8_LOAD_EXITING |
4203               CPU_BASED_CR8_STORE_EXITING |
4204 #endif
4205               CPU_BASED_CR3_LOAD_EXITING |
4206               CPU_BASED_CR3_STORE_EXITING |
4207               CPU_BASED_UNCOND_IO_EXITING |
4208               CPU_BASED_MOV_DR_EXITING |
4209               CPU_BASED_USE_TSC_OFFSETING |
4210               CPU_BASED_MWAIT_EXITING |
4211               CPU_BASED_MONITOR_EXITING |
4212               CPU_BASED_INVLPG_EXITING |
4213               CPU_BASED_RDPMC_EXITING;
4214 
4215         opt = CPU_BASED_TPR_SHADOW |
4216               CPU_BASED_USE_MSR_BITMAPS |
4217               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4218         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4219                                 &_cpu_based_exec_control) < 0)
4220                 return -EIO;
4221 #ifdef CONFIG_X86_64
4222         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4223                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4224                                            ~CPU_BASED_CR8_STORE_EXITING;
4225 #endif
4226         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4227                 min2 = 0;
4228                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4229                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4230                         SECONDARY_EXEC_WBINVD_EXITING |
4231                         SECONDARY_EXEC_ENABLE_VPID |
4232                         SECONDARY_EXEC_ENABLE_EPT |
4233                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4234                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4235                         SECONDARY_EXEC_DESC |
4236                         SECONDARY_EXEC_RDTSCP |
4237                         SECONDARY_EXEC_ENABLE_INVPCID |
4238                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4239                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4240                         SECONDARY_EXEC_SHADOW_VMCS |
4241                         SECONDARY_EXEC_XSAVES |
4242                         SECONDARY_EXEC_RDSEED_EXITING |
4243                         SECONDARY_EXEC_RDRAND_EXITING |
4244                         SECONDARY_EXEC_ENABLE_PML |
4245                         SECONDARY_EXEC_TSC_SCALING |
4246                         SECONDARY_EXEC_ENABLE_VMFUNC;
4247                 if (adjust_vmx_controls(min2, opt2,
4248                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4249                                         &_cpu_based_2nd_exec_control) < 0)
4250                         return -EIO;
4251         }
4252 #ifndef CONFIG_X86_64
4253         if (!(_cpu_based_2nd_exec_control &
4254                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4255                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4256 #endif
4257 
4258         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4259                 _cpu_based_2nd_exec_control &= ~(
4260                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4261                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4262                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4263 
4264         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4265                 &vmx_capability.ept, &vmx_capability.vpid);
4266 
4267         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4268                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4269                    enabled */
4270                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4271                                              CPU_BASED_CR3_STORE_EXITING |
4272                                              CPU_BASED_INVLPG_EXITING);
4273         } else if (vmx_capability.ept) {
4274                 vmx_capability.ept = 0;
4275                 pr_warn_once("EPT CAP should not exist if not support "
4276                                 "1-setting enable EPT VM-execution control\n");
4277         }
4278         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4279                 vmx_capability.vpid) {
4280                 vmx_capability.vpid = 0;
4281                 pr_warn_once("VPID CAP should not exist if not support "
4282                                 "1-setting enable VPID VM-execution control\n");
4283         }
4284 
4285         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4286 #ifdef CONFIG_X86_64
4287         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4288 #endif
4289         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4290                 VM_EXIT_CLEAR_BNDCFGS;
4291         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4292                                 &_vmexit_control) < 0)
4293                 return -EIO;
4294 
4295         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4296         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4297                  PIN_BASED_VMX_PREEMPTION_TIMER;
4298         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4299                                 &_pin_based_exec_control) < 0)
4300                 return -EIO;
4301 
4302         if (cpu_has_broken_vmx_preemption_timer())
4303                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4304         if (!(_cpu_based_2nd_exec_control &
4305                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4306                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4307 
4308         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4309         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4310         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4311                                 &_vmentry_control) < 0)
4312                 return -EIO;
4313 
4314         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4315 
4316         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4317         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4318                 return -EIO;
4319 
4320 #ifdef CONFIG_X86_64
4321         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4322         if (vmx_msr_high & (1u<<16))
4323                 return -EIO;
4324 #endif
4325 
4326         /* Require Write-Back (WB) memory type for VMCS accesses. */
4327         if (((vmx_msr_high >> 18) & 15) != 6)
4328                 return -EIO;
4329 
4330         vmcs_conf->size = vmx_msr_high & 0x1fff;
4331         vmcs_conf->order = get_order(vmcs_conf->size);
4332         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4333 
4334         vmcs_conf->revision_id = vmx_msr_low;
4335 
4336         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4337         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4338         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4339         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4340         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4341 
4342         if (static_branch_unlikely(&enable_evmcs))
4343                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4344 
4345         cpu_has_load_ia32_efer =
4346                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4347                                 VM_ENTRY_LOAD_IA32_EFER)
4348                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4349                                    VM_EXIT_LOAD_IA32_EFER);
4350 
4351         cpu_has_load_perf_global_ctrl =
4352                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4353                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4354                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4355                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4356 
4357         /*
4358          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4359          * but due to errata below it can't be used. Workaround is to use
4360          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4361          *
4362          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4363          *
4364          * AAK155             (model 26)
4365          * AAP115             (model 30)
4366          * AAT100             (model 37)
4367          * BC86,AAY89,BD102   (model 44)
4368          * BA97               (model 46)
4369          *
4370          */
4371         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4372                 switch (boot_cpu_data.x86_model) {
4373                 case 26:
4374                 case 30:
4375                 case 37:
4376                 case 44:
4377                 case 46:
4378                         cpu_has_load_perf_global_ctrl = false;
4379                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4380                                         "does not work properly. Using workaround\n");
4381                         break;
4382                 default:
4383                         break;
4384                 }
4385         }
4386 
4387         if (boot_cpu_has(X86_FEATURE_XSAVES))
4388                 rdmsrl(MSR_IA32_XSS, host_xss);
4389 
4390         return 0;
4391 }
4392 
4393 static struct vmcs *alloc_vmcs_cpu(int cpu)
4394 {
4395         int node = cpu_to_node(cpu);
4396         struct page *pages;
4397         struct vmcs *vmcs;
4398 
4399         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4400         if (!pages)
4401                 return NULL;
4402         vmcs = page_address(pages);
4403         memset(vmcs, 0, vmcs_config.size);
4404 
4405         /* KVM supports Enlightened VMCS v1 only */
4406         if (static_branch_unlikely(&enable_evmcs))
4407                 vmcs->revision_id = KVM_EVMCS_VERSION;
4408         else
4409                 vmcs->revision_id = vmcs_config.revision_id;
4410 
4411         return vmcs;
4412 }
4413 
4414 static void free_vmcs(struct vmcs *vmcs)
4415 {
4416         free_pages((unsigned long)vmcs, vmcs_config.order);
4417 }
4418 
4419 /*
4420  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4421  */
4422 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4423 {
4424         if (!loaded_vmcs->vmcs)
4425                 return;
4426         loaded_vmcs_clear(loaded_vmcs);
4427         free_vmcs(loaded_vmcs->vmcs);
4428         loaded_vmcs->vmcs = NULL;
4429         if (loaded_vmcs->msr_bitmap)
4430                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4431         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4432 }
4433 
4434 static struct vmcs *alloc_vmcs(void)
4435 {
4436         return alloc_vmcs_cpu(raw_smp_processor_id());
4437 }
4438 
4439 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4440 {
4441         loaded_vmcs->vmcs = alloc_vmcs();
4442         if (!loaded_vmcs->vmcs)
4443                 return -ENOMEM;
4444 
4445         loaded_vmcs->shadow_vmcs = NULL;
4446         loaded_vmcs_init(loaded_vmcs);
4447 
4448         if (cpu_has_vmx_msr_bitmap()) {
4449                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4450                 if (!loaded_vmcs->msr_bitmap)
4451                         goto out_vmcs;
4452                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4453 
4454                 if (IS_ENABLED(CONFIG_HYPERV) &&
4455                     static_branch_unlikely(&enable_evmcs) &&
4456                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4457                         struct hv_enlightened_vmcs *evmcs =
4458                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4459 
4460                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4461                 }
4462         }
4463         return 0;
4464 
4465 out_vmcs:
4466         free_loaded_vmcs(loaded_vmcs);
4467         return -ENOMEM;
4468 }
4469 
4470 static void free_kvm_area(void)
4471 {
4472         int cpu;
4473 
4474         for_each_possible_cpu(cpu) {
4475                 free_vmcs(per_cpu(vmxarea, cpu));
4476                 per_cpu(vmxarea, cpu) = NULL;
4477         }
4478 }
4479 
4480 enum vmcs_field_width {
4481         VMCS_FIELD_WIDTH_U16 = 0,
4482         VMCS_FIELD_WIDTH_U64 = 1,
4483         VMCS_FIELD_WIDTH_U32 = 2,
4484         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4485 };
4486 
4487 static inline int vmcs_field_width(unsigned long field)
4488 {
4489         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4490                 return VMCS_FIELD_WIDTH_U32;
4491         return (field >> 13) & 0x3 ;
4492 }
4493 
4494 static inline int vmcs_field_readonly(unsigned long field)
4495 {
4496         return (((field >> 10) & 0x3) == 1);
4497 }
4498 
4499 static void init_vmcs_shadow_fields(void)
4500 {
4501         int i, j;
4502 
4503         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4504                 u16 field = shadow_read_only_fields[i];
4505                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4506                     (i + 1 == max_shadow_read_only_fields ||
4507                      shadow_read_only_fields[i + 1] != field + 1))
4508                         pr_err("Missing field from shadow_read_only_field %x\n",
4509                                field + 1);
4510 
4511                 clear_bit(field, vmx_vmread_bitmap);
4512 #ifdef CONFIG_X86_64
4513                 if (field & 1)
4514                         continue;
4515 #endif
4516                 if (j < i)
4517                         shadow_read_only_fields[j] = field;
4518                 j++;
4519         }
4520         max_shadow_read_only_fields = j;
4521 
4522         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4523                 u16 field = shadow_read_write_fields[i];
4524                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4525                     (i + 1 == max_shadow_read_write_fields ||
4526                      shadow_read_write_fields[i + 1] != field + 1))
4527                         pr_err("Missing field from shadow_read_write_field %x\n",
4528                                field + 1);
4529 
4530                 /*
4531                  * PML and the preemption timer can be emulated, but the
4532                  * processor cannot vmwrite to fields that don't exist
4533                  * on bare metal.
4534                  */
4535                 switch (field) {
4536                 case GUEST_PML_INDEX:
4537                         if (!cpu_has_vmx_pml())
4538                                 continue;
4539                         break;
4540                 case VMX_PREEMPTION_TIMER_VALUE:
4541                         if (!cpu_has_vmx_preemption_timer())
4542                                 continue;
4543                         break;
4544                 case GUEST_INTR_STATUS:
4545                         if (!cpu_has_vmx_apicv())
4546                                 continue;
4547                         break;
4548                 default:
4549                         break;
4550                 }
4551 
4552                 clear_bit(field, vmx_vmwrite_bitmap);
4553                 clear_bit(field, vmx_vmread_bitmap);
4554 #ifdef CONFIG_X86_64
4555                 if (field & 1)
4556                         continue;
4557 #endif
4558                 if (j < i)
4559                         shadow_read_write_fields[j] = field;
4560                 j++;
4561         }
4562         max_shadow_read_write_fields = j;
4563 }
4564 
4565 static __init int alloc_kvm_area(void)
4566 {
4567         int cpu;
4568 
4569         for_each_possible_cpu(cpu) {
4570                 struct vmcs *vmcs;
4571 
4572                 vmcs = alloc_vmcs_cpu(cpu);
4573                 if (!vmcs) {
4574                         free_kvm_area();
4575                         return -ENOMEM;
4576                 }
4577 
4578                 /*
4579                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
4580                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4581                  * revision_id reported by MSR_IA32_VMX_BASIC.
4582                  *
4583                  * However, even though not explictly documented by
4584                  * TLFS, VMXArea passed as VMXON argument should
4585                  * still be marked with revision_id reported by
4586                  * physical CPU.
4587                  */
4588                 if (static_branch_unlikely(&enable_evmcs))
4589                         vmcs->revision_id = vmcs_config.revision_id;
4590 
4591                 per_cpu(vmxarea, cpu) = vmcs;
4592         }
4593         return 0;
4594 }
4595 
4596 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4597                 struct kvm_segment *save)
4598 {
4599         if (!emulate_invalid_guest_state) {
4600                 /*
4601                  * CS and SS RPL should be equal during guest entry according
4602                  * to VMX spec, but in reality it is not always so. Since vcpu
4603                  * is in the middle of the transition from real mode to
4604                  * protected mode it is safe to assume that RPL 0 is a good
4605                  * default value.
4606                  */
4607                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4608                         save->selector &= ~SEGMENT_RPL_MASK;
4609                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4610                 save->s = 1;
4611         }
4612         vmx_set_segment(vcpu, save, seg);
4613 }
4614 
4615 static void enter_pmode(struct kvm_vcpu *vcpu)
4616 {
4617         unsigned long flags;
4618         struct vcpu_vmx *vmx = to_vmx(vcpu);
4619 
4620         /*
4621          * Update real mode segment cache. It may be not up-to-date if sement
4622          * register was written while vcpu was in a guest mode.
4623          */
4624         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4625         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4626         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4627         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4628         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4629         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4630 
4631         vmx->rmode.vm86_active = 0;
4632 
4633         vmx_segment_cache_clear(vmx);
4634 
4635         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4636 
4637         flags = vmcs_readl(GUEST_RFLAGS);
4638         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4639         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4640         vmcs_writel(GUEST_RFLAGS, flags);
4641 
4642         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4643                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4644 
4645         update_exception_bitmap(vcpu);
4646 
4647         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4648         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4649         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4650         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4651         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4652         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4653 }
4654 
4655 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4656 {
4657         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4658         struct kvm_segment var = *save;
4659 
4660         var.dpl = 0x3;
4661         if (seg == VCPU_SREG_CS)
4662                 var.type = 0x3;
4663 
4664         if (!emulate_invalid_guest_state) {
4665                 var.selector = var.base >> 4;
4666                 var.base = var.base & 0xffff0;
4667                 var.limit = 0xffff;
4668                 var.g = 0;
4669                 var.db = 0;
4670                 var.present = 1;
4671                 var.s = 1;
4672                 var.l = 0;
4673                 var.unusable = 0;
4674                 var.type = 0x3;
4675                 var.avl = 0;
4676                 if (save->base & 0xf)
4677                         printk_once(KERN_WARNING "kvm: segment base is not "
4678                                         "paragraph aligned when entering "
4679                                         "protected mode (seg=%d)", seg);
4680         }
4681 
4682         vmcs_write16(sf->selector, var.selector);
4683         vmcs_writel(sf->base, var.base);
4684         vmcs_write32(sf->limit, var.limit);
4685         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4686 }
4687 
4688 static void enter_rmode(struct kvm_vcpu *vcpu)
4689 {
4690         unsigned long flags;
4691         struct vcpu_vmx *vmx = to_vmx(vcpu);
4692         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4693 
4694         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4695         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4696         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4697         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4698         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4699         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4700         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4701 
4702         vmx->rmode.vm86_active = 1;
4703 
4704         /*
4705          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4706          * vcpu. Warn the user that an update is overdue.
4707          */
4708         if (!kvm_vmx->tss_addr)
4709                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4710                              "called before entering vcpu\n");
4711 
4712         vmx_segment_cache_clear(vmx);
4713 
4714         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4715         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4716         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4717 
4718         flags = vmcs_readl(GUEST_RFLAGS);
4719         vmx->rmode.save_rflags = flags;
4720 
4721         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4722 
4723         vmcs_writel(GUEST_RFLAGS, flags);
4724         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4725         update_exception_bitmap(vcpu);
4726 
4727         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4728         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4729         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4730         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4731         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4732         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4733 
4734         kvm_mmu_reset_context(vcpu);
4735 }
4736 
4737 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4738 {
4739         struct vcpu_vmx *vmx = to_vmx(vcpu);
4740         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4741 
4742         if (!msr)
4743                 return;
4744 
4745         /*
4746          * Force kernel_gs_base reloading before EFER changes, as control
4747          * of this msr depends on is_long_mode().
4748          */
4749         vmx_load_host_state(to_vmx(vcpu));
4750         vcpu->arch.efer = efer;
4751         if (efer & EFER_LMA) {
4752                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4753                 msr->data = efer;
4754         } else {
4755                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4756 
4757                 msr->data = efer & ~EFER_LME;
4758         }
4759         setup_msrs(vmx);
4760 }
4761 
4762 #ifdef CONFIG_X86_64
4763 
4764 static void enter_lmode(struct kvm_vcpu *vcpu)
4765 {
4766         u32 guest_tr_ar;
4767 
4768         vmx_segment_cache_clear(to_vmx(vcpu));
4769 
4770         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4771         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4772                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4773                                      __func__);
4774                 vmcs_write32(GUEST_TR_AR_BYTES,
4775                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4776                              | VMX_AR_TYPE_BUSY_64_TSS);
4777         }
4778         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4779 }
4780 
4781 static void exit_lmode(struct kvm_vcpu *vcpu)
4782 {
4783         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4784         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4785 }
4786 
4787 #endif
4788 
4789 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4790                                 bool invalidate_gpa)
4791 {
4792         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4793                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4794                         return;
4795                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4796         } else {
4797                 vpid_sync_context(vpid);
4798         }
4799 }
4800 
4801 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4802 {
4803         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4804 }
4805 
4806 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4807 {
4808         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4809 
4810         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4811         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4812 }
4813 
4814 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4815 {
4816         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4817                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4818         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4819 }
4820 
4821 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4822 {
4823         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4824 
4825         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4826         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4827 }
4828 
4829 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4830 {
4831         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4832 
4833         if (!test_bit(VCPU_EXREG_PDPTR,
4834                       (unsigned long *)&vcpu->arch.regs_dirty))
4835                 return;
4836 
4837         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4838                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4839                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4840                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4841                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4842         }
4843 }
4844 
4845 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4846 {
4847         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4848 
4849         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4850                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4851                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4852                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4853                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4854         }
4855 
4856         __set_bit(VCPU_EXREG_PDPTR,
4857                   (unsigned long *)&vcpu->arch.regs_avail);
4858         __set_bit(VCPU_EXREG_PDPTR,
4859                   (unsigned long *)&vcpu->arch.regs_dirty);
4860 }
4861 
4862 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4863 {
4864         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4865         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4866         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4867 
4868         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4869                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4870             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4871                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4872 
4873         return fixed_bits_valid(val, fixed0, fixed1);
4874 }
4875 
4876 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4877 {
4878         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4879         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4880 
4881         return fixed_bits_valid(val, fixed0, fixed1);
4882 }
4883 
4884 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4885 {
4886         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4887         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4888 
4889         return fixed_bits_valid(val, fixed0, fixed1);
4890 }
4891 
4892 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4893 #define nested_guest_cr4_valid  nested_cr4_valid
4894 #define nested_host_cr4_valid   nested_cr4_valid
4895 
4896 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4897 
4898 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4899                                         unsigned long cr0,
4900                                         struct kvm_vcpu *vcpu)
4901 {
4902         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4903                 vmx_decache_cr3(vcpu);
4904         if (!(cr0 & X86_CR0_PG)) {
4905                 /* From paging/starting to nonpaging */
4906                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4907                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4908                              (CPU_BASED_CR3_LOAD_EXITING |
4909                               CPU_BASED_CR3_STORE_EXITING));
4910                 vcpu->arch.cr0 = cr0;
4911                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4912         } else if (!is_paging(vcpu)) {
4913                 /* From nonpaging to paging */
4914                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4915                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4916                              ~(CPU_BASED_CR3_LOAD_EXITING |
4917                                CPU_BASED_CR3_STORE_EXITING));
4918                 vcpu->arch.cr0 = cr0;
4919                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4920         }
4921 
4922         if (!(cr0 & X86_CR0_WP))
4923                 *hw_cr0 &= ~X86_CR0_WP;
4924 }
4925 
4926 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4927 {
4928         struct vcpu_vmx *vmx = to_vmx(vcpu);
4929         unsigned long hw_cr0;
4930 
4931         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4932         if (enable_unrestricted_guest)
4933                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4934         else {
4935                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4936 
4937                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4938                         enter_pmode(vcpu);
4939 
4940                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4941                         enter_rmode(vcpu);
4942         }
4943 
4944 #ifdef CONFIG_X86_64
4945         if (vcpu->arch.efer & EFER_LME) {
4946                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4947                         enter_lmode(vcpu);
4948                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4949                         exit_lmode(vcpu);
4950         }
4951 #endif
4952 
4953         if (enable_ept && !enable_unrestricted_guest)
4954                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4955 
4956         vmcs_writel(CR0_READ_SHADOW, cr0);
4957         vmcs_writel(GUEST_CR0, hw_cr0);
4958         vcpu->arch.cr0 = cr0;
4959 
4960         /* depends on vcpu->arch.cr0 to be set to a new value */
4961         vmx->emulation_required = emulation_required(vcpu);
4962 }
4963 
4964 static int get_ept_level(struct kvm_vcpu *vcpu)
4965 {
4966         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4967                 return 5;
4968         return 4;
4969 }
4970 
4971 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4972 {
4973         u64 eptp = VMX_EPTP_MT_WB;
4974 
4975         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4976 
4977         if (enable_ept_ad_bits &&
4978             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4979                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4980         eptp |= (root_hpa & PAGE_MASK);
4981 
4982         return eptp;
4983 }
4984 
4985 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4986 {
4987         unsigned long guest_cr3;
4988         u64 eptp;
4989 
4990         guest_cr3 = cr3;
4991         if (enable_ept) {
4992                 eptp = construct_eptp(vcpu, cr3);
4993                 vmcs_write64(EPT_POINTER, eptp);
4994                 if (enable_unrestricted_guest || is_paging(vcpu) ||
4995                     is_guest_mode(vcpu))
4996                         guest_cr3 = kvm_read_cr3(vcpu);
4997                 else
4998                         guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4999                 ept_load_pdptrs(vcpu);
5000         }
5001 
5002         vmx_flush_tlb(vcpu, true);
5003         vmcs_writel(GUEST_CR3, guest_cr3);
5004 }
5005 
5006 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5007 {
5008         /*
5009          * Pass through host's Machine Check Enable value to hw_cr4, which
5010          * is in force while we are in guest mode.  Do not let guests control
5011          * this bit, even if host CR4.MCE == 0.
5012          */
5013         unsigned long hw_cr4;
5014 
5015         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5016         if (enable_unrestricted_guest)
5017                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5018         else if (to_vmx(vcpu)->rmode.vm86_active)
5019                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5020         else
5021                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5022 
5023         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5024                 if (cr4 & X86_CR4_UMIP) {
5025                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5026                                 SECONDARY_EXEC_DESC);
5027                         hw_cr4 &= ~X86_CR4_UMIP;
5028                 } else if (!is_guest_mode(vcpu) ||
5029                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5030                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5031                                         SECONDARY_EXEC_DESC);
5032         }
5033 
5034         if (cr4 & X86_CR4_VMXE) {
5035                 /*
5036                  * To use VMXON (and later other VMX instructions), a guest
5037                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5038                  * So basically the check on whether to allow nested VMX
5039                  * is here.
5040                  */
5041                 if (!nested_vmx_allowed(vcpu))
5042                         return 1;
5043         }
5044 
5045         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5046                 return 1;
5047 
5048         vcpu->arch.cr4 = cr4;
5049 
5050         if (!enable_unrestricted_guest) {
5051                 if (enable_ept) {
5052                         if (!is_paging(vcpu)) {
5053                                 hw_cr4 &= ~X86_CR4_PAE;
5054                                 hw_cr4 |= X86_CR4_PSE;
5055                         } else if (!(cr4 & X86_CR4_PAE)) {
5056                                 hw_cr4 &= ~X86_CR4_PAE;
5057                         }
5058                 }
5059 
5060                 /*
5061                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5062                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5063                  * to be manually disabled when guest switches to non-paging
5064                  * mode.
5065                  *
5066                  * If !enable_unrestricted_guest, the CPU is always running
5067                  * with CR0.PG=1 and CR4 needs to be modified.
5068                  * If enable_unrestricted_guest, the CPU automatically
5069                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5070                  */
5071                 if (!is_paging(vcpu))
5072                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5073         }
5074 
5075         vmcs_writel(CR4_READ_SHADOW, cr4);
5076         vmcs_writel(GUEST_CR4, hw_cr4);
5077         return 0;
5078 }
5079 
5080 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5081                             struct kvm_segment *var, int seg)
5082 {
5083         struct vcpu_vmx *vmx = to_vmx(vcpu);
5084         u32 ar;
5085 
5086         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5087                 *var = vmx->rmode.segs[seg];
5088                 if (seg == VCPU_SREG_TR
5089                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5090                         return;
5091                 var->base = vmx_read_guest_seg_base(vmx, seg);
5092                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5093                 return;
5094         }
5095         var->base = vmx_read_guest_seg_base(vmx, seg);
5096         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5097         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5098         ar = vmx_read_guest_seg_ar(vmx, seg);
5099         var->unusable = (ar >> 16) & 1;
5100         var->type = ar & 15;
5101         var->s = (ar >> 4) & 1;
5102         var->dpl = (ar >> 5) & 3;
5103         /*
5104          * Some userspaces do not preserve unusable property. Since usable
5105          * segment has to be present according to VMX spec we can use present
5106          * property to amend userspace bug by making unusable segment always
5107          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5108          * segment as unusable.
5109          */
5110         var->present = !var->unusable;
5111         var->avl = (ar >> 12) & 1;
5112         var->l = (ar >> 13) & 1;
5113         var->db = (ar >> 14) & 1;
5114         var->g = (ar >> 15) & 1;
5115 }
5116 
5117 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5118 {
5119         struct kvm_segment s;
5120 
5121         if (to_vmx(vcpu)->rmode.vm86_active) {
5122                 vmx_get_segment(vcpu, &s, seg);
5123                 return s.base;
5124         }
5125         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5126 }
5127 
5128 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5129 {
5130         struct vcpu_vmx *vmx = to_vmx(vcpu);
5131 
5132         if (unlikely(vmx->rmode.vm86_active))
5133                 return 0;
5134         else {
5135                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5136                 return VMX_AR_DPL(ar);
5137         }
5138 }
5139 
5140 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5141 {
5142         u32 ar;
5143 
5144         if (var->unusable || !var->present)
5145                 ar = 1 << 16;
5146         else {
5147                 ar = var->type & 15;
5148                 ar |= (var->s & 1) << 4;
5149                 ar |= (var->dpl & 3) << 5;
5150                 ar |= (var->present & 1) << 7;
5151                 ar |= (var->avl & 1) << 12;
5152                 ar |= (var->l & 1) << 13;
5153                 ar |= (var->db & 1) << 14;
5154                 ar |= (var->g & 1) << 15;
5155         }
5156 
5157         return ar;
5158 }
5159 
5160 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5161                             struct kvm_segment *var, int seg)
5162 {
5163         struct vcpu_vmx *vmx = to_vmx(vcpu);
5164         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5165 
5166         vmx_segment_cache_clear(vmx);
5167 
5168         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5169                 vmx->rmode.segs[seg] = *var;
5170                 if (seg == VCPU_SREG_TR)
5171                         vmcs_write16(sf->selector, var->selector);
5172                 else if (var->s)
5173                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5174                 goto out;
5175         }
5176 
5177         vmcs_writel(sf->base, var->base);
5178         vmcs_write32(sf->limit, var->limit);
5179         vmcs_write16(sf->selector, var->selector);
5180 
5181         /*
5182          *   Fix the "Accessed" bit in AR field of segment registers for older
5183          * qemu binaries.
5184          *   IA32 arch specifies that at the time of processor reset the
5185          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5186          * is setting it to 0 in the userland code. This causes invalid guest
5187          * state vmexit when "unrestricted guest" mode is turned on.
5188          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5189          * tree. Newer qemu binaries with that qemu fix would not need this
5190          * kvm hack.
5191          */
5192         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5193                 var->type |= 0x1; /* Accessed */
5194 
5195         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5196 
5197 out:
5198         vmx->emulation_required = emulation_required(vcpu);
5199 }
5200 
5201 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5202 {
5203         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5204 
5205         *db = (ar >> 14) & 1;
5206         *l = (ar >> 13) & 1;
5207 }
5208 
5209 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5210 {
5211         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5212         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5213 }
5214 
5215 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5216 {
5217         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5218         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5219 }
5220 
5221 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5222 {
5223         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5224         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5225 }
5226 
5227 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5228 {
5229         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5230         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5231 }
5232 
5233 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5234 {
5235         struct kvm_segment var;
5236         u32 ar;
5237 
5238         vmx_get_segment(vcpu, &var, seg);
5239         var.dpl = 0x3;
5240         if (seg == VCPU_SREG_CS)
5241                 var.type = 0x3;
5242         ar = vmx_segment_access_rights(&var);
5243 
5244         if (var.base != (var.selector << 4))
5245                 return false;
5246         if (var.limit != 0xffff)
5247                 return false;
5248         if (ar != 0xf3)
5249                 return false;
5250 
5251         return true;
5252 }
5253 
5254 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5255 {
5256         struct kvm_segment cs;
5257         unsigned int cs_rpl;
5258 
5259         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5260         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5261 
5262         if (cs.unusable)
5263                 return false;
5264         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5265                 return false;
5266         if (!cs.s)
5267                 return false;
5268         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5269                 if (cs.dpl > cs_rpl)
5270                         return false;
5271         } else {
5272                 if (cs.dpl != cs_rpl)
5273                         return false;
5274         }
5275         if (!cs.present)
5276                 return false;
5277 
5278         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5279         return true;
5280 }
5281 
5282 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5283 {
5284         struct kvm_segment ss;
5285         unsigned int ss_rpl;
5286 
5287         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5288         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5289 
5290         if (ss.unusable)
5291                 return true;
5292         if (ss.type != 3 && ss.type != 7)
5293                 return false;
5294         if (!ss.s)
5295                 return false;
5296         if (ss.dpl != ss_rpl) /* DPL != RPL */
5297                 return false;
5298         if (!ss.present)
5299                 return false;
5300 
5301         return true;
5302 }
5303 
5304 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5305 {
5306         struct kvm_segment var;
5307         unsigned int rpl;
5308 
5309         vmx_get_segment(vcpu, &var, seg);
5310         rpl = var.selector & SEGMENT_RPL_MASK;
5311 
5312         if (var.unusable)
5313                 return true;
5314         if (!var.s)
5315                 return false;
5316         if (!var.present)
5317                 return false;
5318         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5319                 if (var.dpl < rpl) /* DPL < RPL */
5320                         return false;
5321         }
5322 
5323         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5324          * rights flags
5325          */
5326         return true;
5327 }
5328 
5329 static bool tr_valid(struct kvm_vcpu *vcpu)
5330 {
5331         struct kvm_segment tr;
5332 
5333         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5334 
5335         if (tr.unusable)
5336                 return false;
5337         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5338                 return false;
5339         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5340                 return false;
5341         if (!tr.present)
5342                 return false;
5343 
5344         return true;
5345 }
5346 
5347 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5348 {
5349         struct kvm_segment ldtr;
5350 
5351         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5352 
5353         if (ldtr.unusable)
5354                 return true;
5355         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5356                 return false;
5357         if (ldtr.type != 2)
5358                 return false;
5359         if (!ldtr.present)
5360                 return false;
5361 
5362         return true;
5363 }
5364 
5365 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5366 {
5367         struct kvm_segment cs, ss;
5368 
5369         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5370         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5371 
5372         return ((cs.selector & SEGMENT_RPL_MASK) ==
5373                  (ss.selector & SEGMENT_RPL_MASK));
5374 }
5375 
5376 /*
5377  * Check if guest state is valid. Returns true if valid, false if
5378  * not.
5379  * We assume that registers are always usable
5380  */
5381 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5382 {
5383         if (enable_unrestricted_guest)
5384                 return true;
5385 
5386         /* real mode guest state checks */
5387         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5388                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5389                         return false;
5390                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5391                         return false;
5392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5393                         return false;
5394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5395                         return false;
5396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5397                         return false;
5398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5399                         return false;
5400         } else {
5401         /* protected mode guest state checks */
5402                 if (!cs_ss_rpl_check(vcpu))
5403                         return false;
5404                 if (!code_segment_valid(vcpu))
5405                         return false;
5406                 if (!stack_segment_valid(vcpu))
5407                         return false;
5408                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5409                         return false;
5410                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5411                         return false;
5412                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5413                         return false;
5414                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5415                         return false;
5416                 if (!tr_valid(vcpu))
5417                         return false;
5418                 if (!ldtr_valid(vcpu))
5419                         return false;
5420         }
5421         /* TODO:
5422          * - Add checks on RIP
5423          * - Add checks on RFLAGS
5424          */
5425 
5426         return true;
5427 }
5428 
5429 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5430 {
5431         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5432 }
5433 
5434 static int init_rmode_tss(struct kvm *kvm)
5435 {
5436         gfn_t fn;
5437         u16 data = 0;
5438         int idx, r;
5439 
5440         idx = srcu_read_lock(&kvm->srcu);
5441         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5442         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5443         if (r < 0)
5444                 goto out;
5445         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5446         r = kvm_write_guest_page(kvm, fn++, &data,
5447                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5448         if (r < 0)
5449                 goto out;
5450         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5451         if (r < 0)
5452                 goto out;
5453         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5454         if (r < 0)
5455                 goto out;
5456         data = ~0;
5457         r = kvm_write_guest_page(kvm, fn, &data,
5458                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5459                                  sizeof(u8));
5460 out:
5461         srcu_read_unlock(&kvm->srcu, idx);
5462         return r;
5463 }
5464 
5465 static int init_rmode_identity_map(struct kvm *kvm)
5466 {
5467         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5468         int i, idx, r = 0;
5469         kvm_pfn_t identity_map_pfn;
5470         u32 tmp;
5471 
5472         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5473         mutex_lock(&kvm->slots_lock);
5474 
5475         if (likely(kvm_vmx->ept_identity_pagetable_done))
5476                 goto out2;
5477 
5478         if (!kvm_vmx->ept_identity_map_addr)
5479                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5480         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5481 
5482         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5483                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5484         if (r < 0)
5485                 goto out2;
5486 
5487         idx = srcu_read_lock(&kvm->srcu);
5488         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5489         if (r < 0)
5490                 goto out;
5491         /* Set up identity-mapping pagetable for EPT in real mode */
5492         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5493                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5494                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5495                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5496                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5497                 if (r < 0)
5498                         goto out;
5499         }
5500         kvm_vmx->ept_identity_pagetable_done = true;
5501 
5502 out:
5503         srcu_read_unlock(&kvm->srcu, idx);
5504 
5505 out2:
5506         mutex_unlock(&kvm->slots_lock);
5507         return r;
5508 }
5509 
5510 static void seg_setup(int seg)
5511 {
5512         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5513         unsigned int ar;
5514 
5515         vmcs_write16(sf->selector, 0);
5516         vmcs_writel(sf->base, 0);
5517         vmcs_write32(sf->limit, 0xffff);
5518         ar = 0x93;
5519         if (seg == VCPU_SREG_CS)
5520                 ar |= 0x08; /* code segment */
5521 
5522         vmcs_write32(sf->ar_bytes, ar);
5523 }
5524 
5525 static int alloc_apic_access_page(struct kvm *kvm)
5526 {
5527         struct page *page;
5528         int r = 0;
5529 
5530         mutex_lock(&kvm->slots_lock);
5531         if (kvm->arch.apic_access_page_done)
5532                 goto out;
5533         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5534                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5535         if (r)
5536                 goto out;
5537 
5538         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5539         if (is_error_page(page)) {
5540                 r = -EFAULT;
5541                 goto out;
5542         }
5543 
5544         /*
5545          * Do not pin the page in memory, so that memory hot-unplug
5546          * is able to migrate it.
5547          */
5548         put_page(page);
5549         kvm->arch.apic_access_page_done = true;
5550 out:
5551         mutex_unlock(&kvm->slots_lock);
5552         return r;
5553 }
5554 
5555 static int allocate_vpid(void)
5556 {
5557         int vpid;
5558 
5559         if (!enable_vpid)
5560                 return 0;
5561         spin_lock(&vmx_vpid_lock);
5562         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5563         if (vpid < VMX_NR_VPIDS)
5564                 __set_bit(vpid, vmx_vpid_bitmap);
5565         else
5566                 vpid = 0;
5567         spin_unlock(&vmx_vpid_lock);
5568         return vpid;
5569 }
5570 
5571 static void free_vpid(int vpid)
5572 {
5573         if (!enable_vpid || vpid == 0)
5574                 return;
5575         spin_lock(&vmx_vpid_lock);
5576         __clear_bit(vpid, vmx_vpid_bitmap);
5577         spin_unlock(&vmx_vpid_lock);
5578 }
5579 
5580 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5581                                                           u32 msr, int type)
5582 {
5583         int f = sizeof(unsigned long);
5584 
5585         if (!cpu_has_vmx_msr_bitmap())
5586                 return;
5587 
5588         if (static_branch_unlikely(&enable_evmcs))
5589                 evmcs_touch_msr_bitmap();
5590 
5591         /*
5592          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5593          * have the write-low and read-high bitmap offsets the wrong way round.
5594          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5595          */
5596         if (msr <= 0x1fff) {
5597                 if (type & MSR_TYPE_R)
5598                         /* read-low */
5599                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5600 
5601                 if (type & MSR_TYPE_W)
5602                         /* write-low */
5603                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5604 
5605         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5606                 msr &= 0x1fff;
5607                 if (type & MSR_TYPE_R)
5608                         /* read-high */
5609                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5610 
5611                 if (type & MSR_TYPE_W)
5612                         /* write-high */
5613                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5614 
5615         }
5616 }
5617 
5618 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5619                                                          u32 msr, int type)
5620 {
5621         int f = sizeof(unsigned long);
5622 
5623         if (!cpu_has_vmx_msr_bitmap())
5624                 return;
5625 
5626         if (static_branch_unlikely(&enable_evmcs))
5627                 evmcs_touch_msr_bitmap();
5628 
5629         /*
5630          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5631          * have the write-low and read-high bitmap offsets the wrong way round.
5632          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5633          */
5634         if (msr <= 0x1fff) {
5635                 if (type & MSR_TYPE_R)
5636                         /* read-low */
5637                         __set_bit(msr, msr_bitmap + 0x000 / f);
5638 
5639                 if (type & MSR_TYPE_W)
5640                         /* write-low */
5641                         __set_bit(msr, msr_bitmap + 0x800 / f);
5642 
5643         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5644                 msr &= 0x1fff;
5645                 if (type & MSR_TYPE_R)
5646                         /* read-high */
5647                         __set_bit(msr, msr_bitmap + 0x400 / f);
5648 
5649                 if (type & MSR_TYPE_W)
5650                         /* write-high */
5651                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5652 
5653         }
5654 }
5655 
5656 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5657                                                       u32 msr, int type, bool value)
5658 {
5659         if (value)
5660                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5661         else
5662                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5663 }
5664 
5665 /*
5666  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5667  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5668  */
5669 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5670                                                unsigned long *msr_bitmap_nested,
5671                                                u32 msr, int type)
5672 {
5673         int f = sizeof(unsigned long);
5674 
5675         /*
5676          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5677          * have the write-low and read-high bitmap offsets the wrong way round.
5678          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5679          */
5680         if (msr <= 0x1fff) {
5681                 if (type & MSR_TYPE_R &&
5682                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5683                         /* read-low */
5684                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5685 
5686                 if (type & MSR_TYPE_W &&
5687                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5688                         /* write-low */
5689                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5690 
5691         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5692                 msr &= 0x1fff;
5693                 if (type & MSR_TYPE_R &&
5694                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5695                         /* read-high */
5696                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5697 
5698                 if (type & MSR_TYPE_W &&
5699                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5700                         /* write-high */
5701                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5702 
5703         }
5704 }
5705 
5706 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5707 {
5708         u8 mode = 0;
5709 
5710         if (cpu_has_secondary_exec_ctrls() &&
5711             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5712              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5713                 mode |= MSR_BITMAP_MODE_X2APIC;
5714                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5715                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5716         }
5717 
5718         if (is_long_mode(vcpu))
5719                 mode |= MSR_BITMAP_MODE_LM;
5720 
5721         return mode;
5722 }
5723 
5724 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5725 
5726 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5727                                          u8 mode)
5728 {
5729         int msr;
5730 
5731         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5732                 unsigned word = msr / BITS_PER_LONG;
5733                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5734                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5735         }
5736 
5737         if (mode & MSR_BITMAP_MODE_X2APIC) {
5738                 /*
5739                  * TPR reads and writes can be virtualized even if virtual interrupt
5740                  * delivery is not in use.
5741                  */
5742                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5743                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5744                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5745                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5746                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5747                 }
5748         }
5749 }
5750 
5751 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5752 {
5753         struct vcpu_vmx *vmx = to_vmx(vcpu);
5754         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5755         u8 mode = vmx_msr_bitmap_mode(vcpu);
5756         u8 changed = mode ^ vmx->msr_bitmap_mode;
5757 
5758         if (!changed)
5759                 return;
5760 
5761         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5762                                   !(mode & MSR_BITMAP_MODE_LM));
5763 
5764         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5765                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5766 
5767         vmx->msr_bitmap_mode = mode;
5768 }
5769 
5770 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5771 {
5772         return enable_apicv;
5773 }
5774 
5775 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5776 {
5777         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5778         gfn_t gfn;
5779 
5780         /*
5781          * Don't need to mark the APIC access page dirty; it is never
5782          * written to by the CPU during APIC virtualization.
5783          */
5784 
5785         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5786                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5787                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5788         }
5789 
5790         if (nested_cpu_has_posted_intr(vmcs12)) {
5791                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5792                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5793         }
5794 }
5795 
5796 
5797 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5798 {
5799         struct vcpu_vmx *vmx = to_vmx(vcpu);
5800         int max_irr;
5801         void *vapic_page;
5802         u16 status;
5803 
5804         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5805                 return;
5806 
5807         vmx->nested.pi_pending = false;
5808         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5809                 return;
5810 
5811         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5812         if (max_irr != 256) {
5813                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5814                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5815                         vapic_page, &max_irr);
5816                 kunmap(vmx->nested.virtual_apic_page);
5817 
5818                 status = vmcs_read16(GUEST_INTR_STATUS);
5819                 if ((u8)max_irr > ((u8)status & 0xff)) {
5820                         status &= ~0xff;
5821                         status |= (u8)max_irr;
5822                         vmcs_write16(GUEST_INTR_STATUS, status);
5823                 }
5824         }
5825 
5826         nested_mark_vmcs12_pages_dirty(vcpu);
5827 }
5828 
5829 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5830                                                      bool nested)
5831 {
5832 #ifdef CONFIG_SMP
5833         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5834 
5835         if (vcpu->mode == IN_GUEST_MODE) {
5836                 /*
5837                  * The vector of interrupt to be delivered to vcpu had
5838                  * been set in PIR before this function.
5839                  *
5840                  * Following cases will be reached in this block, and
5841                  * we always send a notification event in all cases as
5842                  * explained below.
5843                  *
5844                  * Case 1: vcpu keeps in non-root mode. Sending a
5845                  * notification event posts the interrupt to vcpu.
5846                  *
5847                  * Case 2: vcpu exits to root mode and is still
5848                  * runnable. PIR will be synced to vIRR before the
5849                  * next vcpu entry. Sending a notification event in
5850                  * this case has no effect, as vcpu is not in root
5851                  * mode.
5852                  *
5853                  * Case 3: vcpu exits to root mode and is blocked.
5854                  * vcpu_block() has already synced PIR to vIRR and
5855                  * never blocks vcpu if vIRR is not cleared. Therefore,
5856                  * a blocked vcpu here does not wait for any requested
5857                  * interrupts in PIR, and sending a notification event
5858                  * which has no effect is safe here.
5859                  */
5860 
5861                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5862                 return true;
5863         }
5864 #endif
5865         return false;
5866 }
5867 
5868 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5869                                                 int vector)
5870 {
5871         struct vcpu_vmx *vmx = to_vmx(vcpu);
5872 
5873         if (is_guest_mode(vcpu) &&
5874             vector == vmx->nested.posted_intr_nv) {
5875                 /*
5876                  * If a posted intr is not recognized by hardware,
5877                  * we will accomplish it in the next vmentry.
5878                  */
5879                 vmx->nested.pi_pending = true;
5880                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5881                 /* the PIR and ON have been set by L1. */
5882                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5883                         kvm_vcpu_kick(vcpu);
5884                 return 0;
5885         }
5886         return -1;
5887 }
5888 /*
5889  * Send interrupt to vcpu via posted interrupt way.
5890  * 1. If target vcpu is running(non-root mode), send posted interrupt
5891  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5892  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5893  * interrupt from PIR in next vmentry.
5894  */
5895 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5896 {
5897         struct vcpu_vmx *vmx = to_vmx(vcpu);
5898         int r;
5899 
5900         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5901         if (!r)
5902                 return;
5903 
5904         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5905                 return;
5906 
5907         /* If a previous notification has sent the IPI, nothing to do.  */
5908         if (pi_test_and_set_on(&vmx->pi_desc))
5909                 return;
5910 
5911         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5912                 kvm_vcpu_kick(vcpu);
5913 }
5914 
5915 /*
5916  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5917  * will not change in the lifetime of the guest.
5918  * Note that host-state that does change is set elsewhere. E.g., host-state
5919  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5920  */
5921 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5922 {
5923         u32 low32, high32;
5924         unsigned long tmpl;
5925         struct desc_ptr dt;
5926         unsigned long cr0, cr3, cr4;
5927 
5928         cr0 = read_cr0();
5929         WARN_ON(cr0 & X86_CR0_TS);
5930         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5931 
5932         /*
5933          * Save the most likely value for this task's CR3 in the VMCS.
5934          * We can't use __get_current_cr3_fast() because we're not atomic.
5935          */
5936         cr3 = __read_cr3();
5937         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5938         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5939 
5940         /* Save the most likely value for this task's CR4 in the VMCS. */
5941         cr4 = cr4_read_shadow();
5942         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5943         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5944 
5945         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5946 #ifdef CONFIG_X86_64
5947         /*
5948          * Load null selectors, so we can avoid reloading them in
5949          * __vmx_load_host_state(), in case userspace uses the null selectors
5950          * too (the expected case).
5951          */
5952         vmcs_write16(HOST_DS_SELECTOR, 0);
5953         vmcs_write16(HOST_ES_SELECTOR, 0);
5954 #else
5955         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5956         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5957 #endif
5958         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5959         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5960 
5961         store_idt(&dt);
5962         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5963         vmx->host_idt_base = dt.address;
5964 
5965         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5966 
5967         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5968         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5969         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5970         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5971 
5972         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5973                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5974                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5975         }
5976 }
5977 
5978 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5979 {
5980         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5981         if (enable_ept)
5982                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5983         if (is_guest_mode(&vmx->vcpu))
5984                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5985                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5986         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5987 }
5988 
5989 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5990 {
5991         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5992 
5993         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5994                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5995 
5996         if (!enable_vnmi)
5997                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5998 
5999         /* Enable the preemption timer dynamically */
6000         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6001         return pin_based_exec_ctrl;
6002 }
6003 
6004 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6005 {
6006         struct vcpu_vmx *vmx = to_vmx(vcpu);
6007 
6008         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6009         if (cpu_has_secondary_exec_ctrls()) {
6010                 if (kvm_vcpu_apicv_active(vcpu))
6011                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6012                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
6013                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6014                 else
6015                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6016                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
6017                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6018         }
6019 
6020         if (cpu_has_vmx_msr_bitmap())
6021                 vmx_update_msr_bitmap(vcpu);
6022 }
6023 
6024 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6025 {
6026         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6027 
6028         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6029                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6030 
6031         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6032                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6033 #ifdef CONFIG_X86_64
6034                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6035                                 CPU_BASED_CR8_LOAD_EXITING;
6036 #endif
6037         }
6038         if (!enable_ept)
6039                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6040                                 CPU_BASED_CR3_LOAD_EXITING  |
6041                                 CPU_BASED_INVLPG_EXITING;
6042         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6043                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6044                                 CPU_BASED_MONITOR_EXITING);
6045         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6046                 exec_control &= ~CPU_BASED_HLT_EXITING;
6047         return exec_control;
6048 }
6049 
6050 static bool vmx_rdrand_supported(void)
6051 {
6052         return vmcs_config.cpu_based_2nd_exec_ctrl &
6053                 SECONDARY_EXEC_RDRAND_EXITING;
6054 }
6055 
6056 static bool vmx_rdseed_supported(void)
6057 {
6058         return vmcs_config.cpu_based_2nd_exec_ctrl &
6059                 SECONDARY_EXEC_RDSEED_EXITING;
6060 }
6061 
6062 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6063 {
6064         struct kvm_vcpu *vcpu = &vmx->vcpu;
6065 
6066         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6067 
6068         if (!cpu_need_virtualize_apic_accesses(vcpu))
6069                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6070         if (vmx->vpid == 0)
6071                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6072         if (!enable_ept) {
6073                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6074                 enable_unrestricted_guest = 0;
6075                 /* Enable INVPCID for non-ept guests may cause performance regression. */
6076                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6077         }
6078         if (!enable_unrestricted_guest)
6079                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6080         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6081                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6082         if (!kvm_vcpu_apicv_active(vcpu))
6083                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6084                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6085         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6086 
6087         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6088          * in vmx_set_cr4.  */
6089         exec_control &= ~SECONDARY_EXEC_DESC;
6090 
6091         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6092            (handle_vmptrld).
6093            We can NOT enable shadow_vmcs here because we don't have yet
6094            a current VMCS12
6095         */
6096         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6097 
6098         if (!enable_pml)
6099                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6100 
6101         if (vmx_xsaves_supported()) {
6102                 /* Exposing XSAVES only when XSAVE is exposed */
6103                 bool xsaves_enabled =
6104                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6105                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6106 
6107                 if (!xsaves_enabled)
6108                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6109 
6110                 if (nested) {
6111                         if (xsaves_enabled)
6112                                 vmx->nested.msrs.secondary_ctls_high |=
6113                                         SECONDARY_EXEC_XSAVES;
6114                         else
6115                                 vmx->nested.msrs.secondary_ctls_high &=
6116                                         ~SECONDARY_EXEC_XSAVES;
6117                 }
6118         }
6119 
6120         if (vmx_rdtscp_supported()) {
6121                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6122                 if (!rdtscp_enabled)
6123                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6124 
6125                 if (nested) {
6126                         if (rdtscp_enabled)
6127                                 vmx->nested.msrs.secondary_ctls_high |=
6128                                         SECONDARY_EXEC_RDTSCP;
6129                         else
6130                                 vmx->nested.msrs.secondary_ctls_high &=
6131                                         ~SECONDARY_EXEC_RDTSCP;
6132                 }
6133         }
6134 
6135         if (vmx_invpcid_supported()) {
6136                 /* Exposing INVPCID only when PCID is exposed */
6137                 bool invpcid_enabled =
6138                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6139                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6140 
6141                 if (!invpcid_enabled) {
6142                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6143                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6144                 }
6145 
6146                 if (nested) {
6147                         if (invpcid_enabled)
6148                                 vmx->nested.msrs.secondary_ctls_high |=
6149                                         SECONDARY_EXEC_ENABLE_INVPCID;
6150                         else
6151                                 vmx->nested.msrs.secondary_ctls_high &=
6152                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6153                 }
6154         }
6155 
6156         if (vmx_rdrand_supported()) {
6157                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6158                 if (rdrand_enabled)
6159                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6160 
6161                 if (nested) {
6162                         if (rdrand_enabled)
6163                                 vmx->nested.msrs.secondary_ctls_high |=
6164                                         SECONDARY_EXEC_RDRAND_EXITING;
6165                         else
6166                                 vmx->nested.msrs.secondary_ctls_high &=
6167                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6168                 }
6169         }
6170 
6171         if (vmx_rdseed_supported()) {
6172                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6173                 if (rdseed_enabled)
6174                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6175 
6176                 if (nested) {
6177                         if (rdseed_enabled)
6178                                 vmx->nested.msrs.secondary_ctls_high |=
6179                                         SECONDARY_EXEC_RDSEED_EXITING;
6180                         else
6181                                 vmx->nested.msrs.secondary_ctls_high &=
6182                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6183                 }
6184         }
6185 
6186         vmx->secondary_exec_control = exec_control;
6187 }
6188 
6189 static void ept_set_mmio_spte_mask(void)
6190 {
6191         /*
6192          * EPT Misconfigurations can be generated if the value of bits 2:0
6193          * of an EPT paging-structure entry is 110b (write/execute).
6194          */
6195         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6196                                    VMX_EPT_MISCONFIG_WX_VALUE);
6197 }
6198 
6199 #define VMX_XSS_EXIT_BITMAP 0
6200 /*
6201  * Sets up the vmcs for emulated real mode.
6202  */
6203 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6204 {
6205 #ifdef CONFIG_X86_64
6206         unsigned long a;
6207 #endif
6208         int i;
6209 
6210         if (enable_shadow_vmcs) {
6211                 /*
6212                  * At vCPU creation, "VMWRITE to any supported field
6213                  * in the VMCS" is supported, so use the more
6214                  * permissive vmx_vmread_bitmap to specify both read
6215                  * and write permissions for the shadow VMCS.
6216                  */
6217                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6218                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6219         }
6220         if (cpu_has_vmx_msr_bitmap())
6221                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6222 
6223         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6224 
6225         /* Control */
6226         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6227         vmx->hv_deadline_tsc = -1;
6228 
6229         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6230 
6231         if (cpu_has_secondary_exec_ctrls()) {
6232                 vmx_compute_secondary_exec_control(vmx);
6233                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6234                              vmx->secondary_exec_control);
6235         }
6236 
6237         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6238                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6239                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6240                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6241                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6242 
6243                 vmcs_write16(GUEST_INTR_STATUS, 0);
6244 
6245                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6246                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6247         }
6248 
6249         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6250                 vmcs_write32(PLE_GAP, ple_gap);
6251                 vmx->ple_window = ple_window;
6252                 vmx->ple_window_dirty = true;
6253         }
6254 
6255         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6256         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6257         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6258 
6259         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6260         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6261         vmx_set_constant_host_state(vmx);
6262 #ifdef CONFIG_X86_64
6263         rdmsrl(MSR_FS_BASE, a);
6264         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6265         rdmsrl(MSR_GS_BASE, a);
6266         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6267 #else
6268         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6269         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6270 #endif
6271 
6272         if (cpu_has_vmx_vmfunc())
6273                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6274 
6275         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6276         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6277         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6278         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6279         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6280 
6281         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6282                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6283 
6284         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6285                 u32 index = vmx_msr_index[i];
6286                 u32 data_low, data_high;
6287                 int j = vmx->nmsrs;
6288 
6289                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6290                         continue;
6291                 if (wrmsr_safe(index, data_low, data_high) < 0)
6292                         continue;
6293                 vmx->guest_msrs[j].index = i;
6294                 vmx->guest_msrs[j].data = 0;
6295                 vmx->guest_msrs[j].mask = -1ull;
6296                 ++vmx->nmsrs;
6297         }
6298 
6299         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6300                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6301 
6302         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6303 
6304         /* 22.2.1, 20.8.1 */
6305         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6306 
6307         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6308         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6309 
6310         set_cr4_guest_host_mask(vmx);
6311 
6312         if (vmx_xsaves_supported())
6313                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6314 
6315         if (enable_pml) {
6316                 ASSERT(vmx->pml_pg);
6317                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6318                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6319         }
6320 }
6321 
6322 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6323 {
6324         struct vcpu_vmx *vmx = to_vmx(vcpu);
6325         struct msr_data apic_base_msr;
6326         u64 cr0;
6327 
6328         vmx->rmode.vm86_active = 0;
6329         vmx->spec_ctrl = 0;
6330 
6331         vcpu->arch.microcode_version = 0x100000000ULL;
6332         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6333         kvm_set_cr8(vcpu, 0);
6334 
6335         if (!init_event) {
6336                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6337                                      MSR_IA32_APICBASE_ENABLE;
6338                 if (kvm_vcpu_is_reset_bsp(vcpu))
6339                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6340                 apic_base_msr.host_initiated = true;
6341                 kvm_set_apic_base(vcpu, &apic_base_msr);
6342         }
6343 
6344         vmx_segment_cache_clear(vmx);
6345 
6346         seg_setup(VCPU_SREG_CS);
6347         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6348         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6349 
6350         seg_setup(VCPU_SREG_DS);
6351         seg_setup(VCPU_SREG_ES);
6352         seg_setup(VCPU_SREG_FS);
6353         seg_setup(VCPU_SREG_GS);
6354         seg_setup(VCPU_SREG_SS);
6355 
6356         vmcs_write16(GUEST_TR_SELECTOR, 0);
6357         vmcs_writel(GUEST_TR_BASE, 0);
6358         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6359         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6360 
6361         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6362         vmcs_writel(GUEST_LDTR_BASE, 0);
6363         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6364         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6365 
6366         if (!init_event) {
6367                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6368                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6369                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6370                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6371         }
6372 
6373         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6374         kvm_rip_write(vcpu, 0xfff0);
6375 
6376         vmcs_writel(GUEST_GDTR_BASE, 0);
6377         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6378 
6379         vmcs_writel(GUEST_IDTR_BASE, 0);
6380         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6381 
6382         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6383         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6384         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6385         if (kvm_mpx_supported())
6386                 vmcs_write64(GUEST_BNDCFGS, 0);
6387 
6388         setup_msrs(vmx);
6389 
6390         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6391 
6392         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6393                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6394                 if (cpu_need_tpr_shadow(vcpu))
6395                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6396                                      __pa(vcpu->arch.apic->regs));
6397                 vmcs_write32(TPR_THRESHOLD, 0);
6398         }
6399 
6400         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6401 
6402         if (vmx->vpid != 0)
6403                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6404 
6405         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6406         vmx->vcpu.arch.cr0 = cr0;
6407         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6408         vmx_set_cr4(vcpu, 0);
6409         vmx_set_efer(vcpu, 0);
6410 
6411         update_exception_bitmap(vcpu);
6412 
6413         vpid_sync_context(vmx->vpid);
6414         if (init_event)
6415                 vmx_clear_hlt(vcpu);
6416 }
6417 
6418 /*
6419  * In nested virtualization, check if L1 asked to exit on external interrupts.
6420  * For most existing hypervisors, this will always return true.
6421  */
6422 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6423 {
6424         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6425                 PIN_BASED_EXT_INTR_MASK;
6426 }
6427 
6428 /*
6429  * In nested virtualization, check if L1 has set
6430  * VM_EXIT_ACK_INTR_ON_EXIT
6431  */
6432 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6433 {
6434         return get_vmcs12(vcpu)->vm_exit_controls &
6435                 VM_EXIT_ACK_INTR_ON_EXIT;
6436 }
6437 
6438 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6439 {
6440         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6441 }
6442 
6443 static void enable_irq_window(struct kvm_vcpu *vcpu)
6444 {
6445         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6446                       CPU_BASED_VIRTUAL_INTR_PENDING);
6447 }
6448 
6449 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6450 {
6451         if (!enable_vnmi ||
6452             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6453                 enable_irq_window(vcpu);
6454                 return;
6455         }
6456 
6457         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6458                       CPU_BASED_VIRTUAL_NMI_PENDING);
6459 }
6460 
6461 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6462 {
6463         struct vcpu_vmx *vmx = to_vmx(vcpu);
6464         uint32_t intr;
6465         int irq = vcpu->arch.interrupt.nr;
6466 
6467         trace_kvm_inj_virq(irq);
6468 
6469         ++vcpu->stat.irq_injections;
6470         if (vmx->rmode.vm86_active) {
6471                 int inc_eip = 0;
6472                 if (vcpu->arch.interrupt.soft)
6473                         inc_eip = vcpu->arch.event_exit_inst_len;
6474                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6475                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6476                 return;
6477         }
6478         intr = irq | INTR_INFO_VALID_MASK;
6479         if (vcpu->arch.interrupt.soft) {
6480                 intr |= INTR_TYPE_SOFT_INTR;
6481                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6482                              vmx->vcpu.arch.event_exit_inst_len);
6483         } else
6484                 intr |= INTR_TYPE_EXT_INTR;
6485         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6486 
6487         vmx_clear_hlt(vcpu);
6488 }
6489 
6490 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6491 {
6492         struct vcpu_vmx *vmx = to_vmx(vcpu);
6493 
6494         if (!enable_vnmi) {
6495                 /*
6496                  * Tracking the NMI-blocked state in software is built upon
6497                  * finding the next open IRQ window. This, in turn, depends on
6498                  * well-behaving guests: They have to keep IRQs disabled at
6499                  * least as long as the NMI handler runs. Otherwise we may
6500                  * cause NMI nesting, maybe breaking the guest. But as this is
6501                  * highly unlikely, we can live with the residual risk.
6502                  */
6503                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6504                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6505         }
6506 
6507         ++vcpu->stat.nmi_injections;
6508         vmx->loaded_vmcs->nmi_known_unmasked = false;
6509 
6510         if (vmx->rmode.vm86_active) {
6511                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6512                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6513                 return;
6514         }
6515 
6516         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6517                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6518 
6519         vmx_clear_hlt(vcpu);
6520 }
6521 
6522 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6523 {
6524         struct vcpu_vmx *vmx = to_vmx(vcpu);
6525         bool masked;
6526 
6527         if (!enable_vnmi)
6528                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6529         if (vmx->loaded_vmcs->nmi_known_unmasked)
6530                 return false;
6531         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6532         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6533         return masked;
6534 }
6535 
6536 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6537 {
6538         struct vcpu_vmx *vmx = to_vmx(vcpu);
6539 
6540         if (!enable_vnmi) {
6541                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6542                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6543                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6544                 }
6545         } else {
6546                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6547                 if (masked)
6548                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6549                                       GUEST_INTR_STATE_NMI);
6550                 else
6551                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6552                                         GUEST_INTR_STATE_NMI);
6553         }
6554 }
6555 
6556 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6557 {
6558         if (to_vmx(vcpu)->nested.nested_run_pending)
6559                 return 0;
6560 
6561         if (!enable_vnmi &&
6562             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6563                 return 0;
6564 
6565         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6566                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6567                    | GUEST_INTR_STATE_NMI));
6568 }
6569 
6570 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6571 {
6572         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6573                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6574                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6575                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6576 }
6577 
6578 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6579 {
6580         int ret;
6581 
6582         if (enable_unrestricted_guest)
6583                 return 0;
6584 
6585         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6586                                     PAGE_SIZE * 3);
6587         if (ret)
6588                 return ret;
6589         to_kvm_vmx(kvm)->tss_addr = addr;
6590         return init_rmode_tss(kvm);
6591 }
6592 
6593 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6594 {
6595         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6596         return 0;
6597 }
6598 
6599 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6600 {
6601         switch (vec) {
6602         case BP_VECTOR:
6603                 /*
6604                  * Update instruction length as we may reinject the exception
6605                  * from user space while in guest debugging mode.
6606                  */
6607                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6608                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6609                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6610                         return false;
6611                 /* fall through */
6612         case DB_VECTOR:
6613                 if (vcpu->guest_debug &
6614                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6615                         return false;
6616                 /* fall through */
6617         case DE_VECTOR:
6618         case OF_VECTOR:
6619         case BR_VECTOR:
6620         case UD_VECTOR:
6621         case DF_VECTOR:
6622         case SS_VECTOR:
6623         case GP_VECTOR:
6624         case MF_VECTOR:
6625                 return true;
6626         break;
6627         }
6628         return false;
6629 }
6630 
6631 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6632                                   int vec, u32 err_code)
6633 {
6634         /*
6635          * Instruction with address size override prefix opcode 0x67
6636          * Cause the #SS fault with 0 error code in VM86 mode.
6637          */
6638         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6639                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6640                         if (vcpu->arch.halt_request) {
6641                                 vcpu->arch.halt_request = 0;
6642                                 return kvm_vcpu_halt(vcpu);
6643                         }
6644                         return 1;
6645                 }
6646                 return 0;
6647         }
6648 
6649         /*
6650          * Forward all other exceptions that are valid in real mode.
6651          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6652          *        the required debugging infrastructure rework.
6653          */
6654         kvm_queue_exception(vcpu, vec);
6655         return 1;
6656 }
6657 
6658 /*
6659  * Trigger machine check on the host. We assume all the MSRs are already set up
6660  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6661  * We pass a fake environment to the machine check handler because we want
6662  * the guest to be always treated like user space, no matter what context
6663  * it used internally.
6664  */
6665 static void kvm_machine_check(void)
6666 {
6667 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6668         struct pt_regs regs = {
6669                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6670                 .flags = X86_EFLAGS_IF,
6671         };
6672 
6673         do_machine_check(&regs, 0);
6674 #endif
6675 }
6676 
6677 static int handle_machine_check(struct kvm_vcpu *vcpu)
6678 {
6679         /* already handled by vcpu_run */
6680         return 1;
6681 }
6682 
6683 static int handle_exception(struct kvm_vcpu *vcpu)
6684 {
6685         struct vcpu_vmx *vmx = to_vmx(vcpu);
6686         struct kvm_run *kvm_run = vcpu->run;
6687         u32 intr_info, ex_no, error_code;
6688         unsigned long cr2, rip, dr6;
6689         u32 vect_info;
6690         enum emulation_result er;
6691 
6692         vect_info = vmx->idt_vectoring_info;
6693         intr_info = vmx->exit_intr_info;
6694 
6695         if (is_machine_check(intr_info))
6696                 return handle_machine_check(vcpu);
6697 
6698         if (is_nmi(intr_info))
6699                 return 1;  /* already handled by vmx_vcpu_run() */
6700 
6701         if (is_invalid_opcode(intr_info))
6702                 return handle_ud(vcpu);
6703 
6704         error_code = 0;
6705         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6706                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6707 
6708         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6709                 WARN_ON_ONCE(!enable_vmware_backdoor);
6710                 er = emulate_instruction(vcpu,
6711                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6712                 if (er == EMULATE_USER_EXIT)
6713                         return 0;
6714                 else if (er != EMULATE_DONE)
6715                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6716                 return 1;
6717         }
6718 
6719         /*
6720          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6721          * MMIO, it is better to report an internal error.
6722          * See the comments in vmx_handle_exit.
6723          */
6724         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6725             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6726                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6727                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6728                 vcpu->run->internal.ndata = 3;
6729                 vcpu->run->internal.data[0] = vect_info;
6730                 vcpu->run->internal.data[1] = intr_info;
6731                 vcpu->run->internal.data[2] = error_code;
6732                 return 0;
6733         }
6734 
6735         if (is_page_fault(intr_info)) {
6736                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6737                 /* EPT won't cause page fault directly */
6738                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6739                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6740         }
6741 
6742         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6743 
6744         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6745                 return handle_rmode_exception(vcpu, ex_no, error_code);
6746 
6747         switch (ex_no) {
6748         case AC_VECTOR:
6749                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6750                 return 1;
6751         case DB_VECTOR:
6752                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6753                 if (!(vcpu->guest_debug &
6754                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6755                         vcpu->arch.dr6 &= ~15;
6756                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6757                         if (is_icebp(intr_info))
6758                                 skip_emulated_instruction(vcpu);
6759 
6760                         kvm_queue_exception(vcpu, DB_VECTOR);
6761                         return 1;
6762                 }
6763                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6764                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6765                 /* fall through */
6766         case BP_VECTOR:
6767                 /*
6768                  * Update instruction length as we may reinject #BP from
6769                  * user space while in guest debugging mode. Reading it for
6770                  * #DB as well causes no harm, it is not used in that case.
6771                  */
6772                 vmx->vcpu.arch.event_exit_inst_len =
6773                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6774                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6775                 rip = kvm_rip_read(vcpu);
6776                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6777                 kvm_run->debug.arch.exception = ex_no;
6778                 break;
6779         default:
6780                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6781                 kvm_run->ex.exception = ex_no;
6782                 kvm_run->ex.error_code = error_code;
6783                 break;
6784         }
6785         return 0;
6786 }
6787 
6788 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6789 {
6790         ++vcpu->stat.irq_exits;
6791         return 1;
6792 }
6793 
6794 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6795 {
6796         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6797         vcpu->mmio_needed = 0;
6798         return 0;
6799 }
6800 
6801 static int handle_io(struct kvm_vcpu *vcpu)
6802 {
6803         unsigned long exit_qualification;
6804         int size, in, string;
6805         unsigned port;
6806 
6807         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6808         string = (exit_qualification & 16) != 0;
6809 
6810         ++vcpu->stat.io_exits;
6811 
6812         if (string)
6813                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6814 
6815         port = exit_qualification >> 16;
6816         size = (exit_qualification & 7) + 1;
6817         in = (exit_qualification & 8) != 0;
6818 
6819         return kvm_fast_pio(vcpu, size, port, in);
6820 }
6821 
6822 static void
6823 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6824 {
6825         /*
6826          * Patch in the VMCALL instruction:
6827          */
6828         hypercall[0] = 0x0f;
6829         hypercall[1] = 0x01;
6830         hypercall[2] = 0xc1;
6831 }
6832 
6833 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6834 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6835 {
6836         if (is_guest_mode(vcpu)) {
6837                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6838                 unsigned long orig_val = val;
6839 
6840                 /*
6841                  * We get here when L2 changed cr0 in a way that did not change
6842                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6843                  * but did change L0 shadowed bits. So we first calculate the
6844                  * effective cr0 value that L1 would like to write into the
6845                  * hardware. It consists of the L2-owned bits from the new
6846                  * value combined with the L1-owned bits from L1's guest_cr0.
6847                  */
6848                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6849                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6850 
6851                 if (!nested_guest_cr0_valid(vcpu, val))
6852                         return 1;
6853 
6854                 if (kvm_set_cr0(vcpu, val))
6855                         return 1;
6856                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6857                 return 0;
6858         } else {
6859                 if (to_vmx(vcpu)->nested.vmxon &&
6860                     !nested_host_cr0_valid(vcpu, val))
6861                         return 1;
6862 
6863                 return kvm_set_cr0(vcpu, val);
6864         }
6865 }
6866 
6867 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6868 {
6869         if (is_guest_mode(vcpu)) {
6870                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6871                 unsigned long orig_val = val;
6872 
6873                 /* analogously to handle_set_cr0 */
6874                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6875                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6876                 if (kvm_set_cr4(vcpu, val))
6877                         return 1;
6878                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6879                 return 0;
6880         } else
6881                 return kvm_set_cr4(vcpu, val);
6882 }
6883 
6884 static int handle_desc(struct kvm_vcpu *vcpu)
6885 {
6886         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6887         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6888 }
6889 
6890 static int handle_cr(struct kvm_vcpu *vcpu)
6891 {
6892         unsigned long exit_qualification, val;
6893         int cr;
6894         int reg;
6895         int err;
6896         int ret;
6897 
6898         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6899         cr = exit_qualification & 15;
6900         reg = (exit_qualification >> 8) & 15;
6901         switch ((exit_qualification >> 4) & 3) {
6902         case 0: /* mov to cr */
6903                 val = kvm_register_readl(vcpu, reg);
6904                 trace_kvm_cr_write(cr, val);
6905                 switch (cr) {
6906                 case 0:
6907                         err = handle_set_cr0(vcpu, val);
6908                         return kvm_complete_insn_gp(vcpu, err);
6909                 case 3:
6910                         WARN_ON_ONCE(enable_unrestricted_guest);
6911                         err = kvm_set_cr3(vcpu, val);
6912                         return kvm_complete_insn_gp(vcpu, err);
6913                 case 4:
6914                         err = handle_set_cr4(vcpu, val);
6915                         return kvm_complete_insn_gp(vcpu, err);
6916                 case 8: {
6917                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6918                                 u8 cr8 = (u8)val;
6919                                 err = kvm_set_cr8(vcpu, cr8);
6920                                 ret = kvm_complete_insn_gp(vcpu, err);
6921                                 if (lapic_in_kernel(vcpu))
6922                                         return ret;
6923                                 if (cr8_prev <= cr8)
6924                                         return ret;
6925                                 /*
6926                                  * TODO: we might be squashing a
6927                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6928                                  * KVM_EXIT_DEBUG here.
6929                                  */
6930                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6931                                 return 0;
6932                         }
6933                 }
6934                 break;
6935         case 2: /* clts */
6936                 WARN_ONCE(1, "Guest should always own CR0.TS");
6937                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6938                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6939                 return kvm_skip_emulated_instruction(vcpu);
6940         case 1: /*mov from cr*/
6941                 switch (cr) {
6942                 case 3:
6943                         WARN_ON_ONCE(enable_unrestricted_guest);
6944                         val = kvm_read_cr3(vcpu);
6945                         kvm_register_write(vcpu, reg, val);
6946                         trace_kvm_cr_read(cr, val);
6947                         return kvm_skip_emulated_instruction(vcpu);
6948                 case 8:
6949                         val = kvm_get_cr8(vcpu);
6950                         kvm_register_write(vcpu, reg, val);
6951                         trace_kvm_cr_read(cr, val);
6952                         return kvm_skip_emulated_instruction(vcpu);
6953                 }
6954                 break;
6955         case 3: /* lmsw */
6956                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6957                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6958                 kvm_lmsw(vcpu, val);
6959 
6960                 return kvm_skip_emulated_instruction(vcpu);
6961         default:
6962                 break;
6963         }
6964         vcpu->run->exit_reason = 0;
6965         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6966                (int)(exit_qualification >> 4) & 3, cr);
6967         return 0;
6968 }
6969 
6970 static int handle_dr(struct kvm_vcpu *vcpu)
6971 {
6972         unsigned long exit_qualification;
6973         int dr, dr7, reg;
6974 
6975         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6976         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6977 
6978         /* First, if DR does not exist, trigger UD */
6979         if (!kvm_require_dr(vcpu, dr))
6980                 return 1;
6981 
6982         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6983         if (!kvm_require_cpl(vcpu, 0))
6984                 return 1;
6985         dr7 = vmcs_readl(GUEST_DR7);
6986         if (dr7 & DR7_GD) {
6987                 /*
6988                  * As the vm-exit takes precedence over the debug trap, we
6989                  * need to emulate the latter, either for the host or the
6990                  * guest debugging itself.
6991                  */
6992                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6993                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6994                         vcpu->run->debug.arch.dr7 = dr7;
6995                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6996                         vcpu->run->debug.arch.exception = DB_VECTOR;
6997                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6998                         return 0;
6999                 } else {
7000                         vcpu->arch.dr6 &= ~15;
7001                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7002                         kvm_queue_exception(vcpu, DB_VECTOR);
7003                         return 1;
7004                 }
7005         }
7006 
7007         if (vcpu->guest_debug == 0) {
7008                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7009                                 CPU_BASED_MOV_DR_EXITING);
7010 
7011                 /*
7012                  * No more DR vmexits; force a reload of the debug registers
7013                  * and reenter on this instruction.  The next vmexit will
7014                  * retrieve the full state of the debug registers.
7015                  */
7016                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7017                 return 1;
7018         }
7019 
7020         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7021         if (exit_qualification & TYPE_MOV_FROM_DR) {
7022                 unsigned long val;
7023 
7024                 if (kvm_get_dr(vcpu, dr, &val))
7025                         return 1;
7026                 kvm_register_write(vcpu, reg, val);
7027         } else
7028                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7029                         return 1;
7030 
7031         return kvm_skip_emulated_instruction(vcpu);
7032 }
7033 
7034 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7035 {
7036         return vcpu->arch.dr6;
7037 }
7038 
7039 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7040 {
7041 }
7042 
7043 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7044 {
7045         get_debugreg(vcpu->arch.db[0], 0);
7046         get_debugreg(vcpu->arch.db[1], 1);
7047         get_debugreg(vcpu->arch.db[2], 2);
7048         get_debugreg(vcpu->arch.db[3], 3);
7049         get_debugreg(vcpu->arch.dr6, 6);
7050         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7051 
7052         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7053         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7054 }
7055 
7056 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7057 {
7058         vmcs_writel(GUEST_DR7, val);
7059 }
7060 
7061 static int handle_cpuid(struct kvm_vcpu *vcpu)
7062 {
7063         return kvm_emulate_cpuid(vcpu);
7064 }
7065 
7066 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7067 {
7068         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7069         struct msr_data msr_info;
7070 
7071         msr_info.index = ecx;
7072         msr_info.host_initiated = false;
7073         if (vmx_get_msr(vcpu, &msr_info)) {
7074                 trace_kvm_msr_read_ex(ecx);
7075                 kvm_inject_gp(vcpu, 0);
7076                 return 1;
7077         }
7078 
7079         trace_kvm_msr_read(ecx, msr_info.data);
7080 
7081         /* FIXME: handling of bits 32:63 of rax, rdx */
7082         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7083         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7084         return kvm_skip_emulated_instruction(vcpu);
7085 }
7086 
7087 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7088 {
7089         struct msr_data msr;
7090         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7091         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7092                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7093 
7094         msr.data = data;
7095         msr.index = ecx;
7096         msr.host_initiated = false;
7097         if (kvm_set_msr(vcpu, &msr) != 0) {
7098                 trace_kvm_msr_write_ex(ecx, data);
7099                 kvm_inject_gp(vcpu, 0);
7100                 return 1;
7101         }
7102 
7103         trace_kvm_msr_write(ecx, data);
7104         return kvm_skip_emulated_instruction(vcpu);
7105 }
7106 
7107 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7108 {
7109         kvm_apic_update_ppr(vcpu);
7110         return 1;
7111 }
7112 
7113 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7114 {
7115         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7116                         CPU_BASED_VIRTUAL_INTR_PENDING);
7117 
7118         kvm_make_request(KVM_REQ_EVENT, vcpu);
7119 
7120         ++vcpu->stat.irq_window_exits;
7121         return 1;
7122 }
7123 
7124 static int handle_halt(struct kvm_vcpu *vcpu)
7125 {
7126         return kvm_emulate_halt(vcpu);
7127 }
7128 
7129 static int handle_vmcall(struct kvm_vcpu *vcpu)
7130 {
7131         return kvm_emulate_hypercall(vcpu);
7132 }
7133 
7134 static int handle_invd(struct kvm_vcpu *vcpu)
7135 {
7136         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7137 }
7138 
7139 static int handle_invlpg(struct kvm_vcpu *vcpu)
7140 {
7141         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7142 
7143         kvm_mmu_invlpg(vcpu, exit_qualification);
7144         return kvm_skip_emulated_instruction(vcpu);
7145 }
7146 
7147 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7148 {
7149         int err;
7150 
7151         err = kvm_rdpmc(vcpu);
7152         return kvm_complete_insn_gp(vcpu, err);
7153 }
7154 
7155 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7156 {
7157         return kvm_emulate_wbinvd(vcpu);
7158 }
7159 
7160 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7161 {
7162         u64 new_bv = kvm_read_edx_eax(vcpu);
7163         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7164 
7165         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7166                 return kvm_skip_emulated_instruction(vcpu);
7167         return 1;
7168 }
7169 
7170 static int handle_xsaves(struct kvm_vcpu *vcpu)
7171 {
7172         kvm_skip_emulated_instruction(vcpu);
7173         WARN(1, "this should never happen\n");
7174         return 1;
7175 }
7176 
7177 static int handle_xrstors(struct kvm_vcpu *vcpu)
7178 {
7179         kvm_skip_emulated_instruction(vcpu);
7180         WARN(1, "this should never happen\n");
7181         return 1;
7182 }
7183 
7184 static int handle_apic_access(struct kvm_vcpu *vcpu)
7185 {
7186         if (likely(fasteoi)) {
7187                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7188                 int access_type, offset;
7189 
7190                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7191                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7192                 /*
7193                  * Sane guest uses MOV to write EOI, with written value
7194                  * not cared. So make a short-circuit here by avoiding
7195                  * heavy instruction emulation.
7196                  */
7197                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7198                     (offset == APIC_EOI)) {
7199                         kvm_lapic_set_eoi(vcpu);
7200                         return kvm_skip_emulated_instruction(vcpu);
7201                 }
7202         }
7203         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7204 }
7205 
7206 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7207 {
7208         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7209         int vector = exit_qualification & 0xff;
7210 
7211         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7212         kvm_apic_set_eoi_accelerated(vcpu, vector);
7213         return 1;
7214 }
7215 
7216 static int handle_apic_write(struct kvm_vcpu *vcpu)
7217 {
7218         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7219         u32 offset = exit_qualification & 0xfff;
7220 
7221         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7222         kvm_apic_write_nodecode(vcpu, offset);
7223         return 1;
7224 }
7225 
7226 static int handle_task_switch(struct kvm_vcpu *vcpu)
7227 {
7228         struct vcpu_vmx *vmx = to_vmx(vcpu);
7229         unsigned long exit_qualification;
7230         bool has_error_code = false;
7231         u32 error_code = 0;
7232         u16 tss_selector;
7233         int reason, type, idt_v, idt_index;
7234 
7235         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7236         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7237         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7238 
7239         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7240 
7241         reason = (u32)exit_qualification >> 30;
7242         if (reason == TASK_SWITCH_GATE && idt_v) {
7243                 switch (type) {
7244                 case INTR_TYPE_NMI_INTR:
7245                         vcpu->arch.nmi_injected = false;
7246                         vmx_set_nmi_mask(vcpu, true);
7247                         break;
7248                 case INTR_TYPE_EXT_INTR:
7249                 case INTR_TYPE_SOFT_INTR:
7250                         kvm_clear_interrupt_queue(vcpu);
7251                         break;
7252                 case INTR_TYPE_HARD_EXCEPTION:
7253                         if (vmx->idt_vectoring_info &
7254                             VECTORING_INFO_DELIVER_CODE_MASK) {
7255                                 has_error_code = true;
7256                                 error_code =
7257                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7258                         }
7259                         /* fall through */
7260                 case INTR_TYPE_SOFT_EXCEPTION:
7261                         kvm_clear_exception_queue(vcpu);
7262                         break;
7263                 default:
7264                         break;
7265                 }
7266         }
7267         tss_selector = exit_qualification;
7268 
7269         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7270                        type != INTR_TYPE_EXT_INTR &&
7271                        type != INTR_TYPE_NMI_INTR))
7272                 skip_emulated_instruction(vcpu);
7273 
7274         if (kvm_task_switch(vcpu, tss_selector,
7275                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7276                             has_error_code, error_code) == EMULATE_FAIL) {
7277                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7278                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7279                 vcpu->run->internal.ndata = 0;
7280                 return 0;
7281         }
7282 
7283         /*
7284          * TODO: What about debug traps on tss switch?
7285          *       Are we supposed to inject them and update dr6?
7286          */
7287 
7288         return 1;
7289 }
7290 
7291 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7292 {
7293         unsigned long exit_qualification;
7294         gpa_t gpa;
7295         u64 error_code;
7296 
7297         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7298 
7299         /*
7300          * EPT violation happened while executing iret from NMI,
7301          * "blocked by NMI" bit has to be set before next VM entry.
7302          * There are errata that may cause this bit to not be set:
7303          * AAK134, BY25.
7304          */
7305         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7306                         enable_vnmi &&
7307                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7308                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7309 
7310         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7311         trace_kvm_page_fault(gpa, exit_qualification);
7312 
7313         /* Is it a read fault? */
7314         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7315                      ? PFERR_USER_MASK : 0;
7316         /* Is it a write fault? */
7317         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7318                       ? PFERR_WRITE_MASK : 0;
7319         /* Is it a fetch fault? */
7320         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7321                       ? PFERR_FETCH_MASK : 0;
7322         /* ept page table entry is present? */
7323         error_code |= (exit_qualification &
7324                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7325                         EPT_VIOLATION_EXECUTABLE))
7326                       ? PFERR_PRESENT_MASK : 0;
7327 
7328         error_code |= (exit_qualification & 0x100) != 0 ?
7329                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7330 
7331         vcpu->arch.exit_qualification = exit_qualification;
7332         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7333 }
7334 
7335 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7336 {
7337         gpa_t gpa;
7338 
7339         /*
7340          * A nested guest cannot optimize MMIO vmexits, because we have an
7341          * nGPA here instead of the required GPA.
7342          */
7343         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7344         if (!is_guest_mode(vcpu) &&
7345             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7346                 trace_kvm_fast_mmio(gpa);
7347                 /*
7348                  * Doing kvm_skip_emulated_instruction() depends on undefined
7349                  * behavior: Intel's manual doesn't mandate
7350                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7351                  * occurs and while on real hardware it was observed to be set,
7352                  * other hypervisors (namely Hyper-V) don't set it, we end up
7353                  * advancing IP with some random value. Disable fast mmio when
7354                  * running nested and keep it for real hardware in hope that
7355                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7356                  */
7357                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7358                         return kvm_skip_emulated_instruction(vcpu);
7359                 else
7360                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7361                                                        NULL, 0) == EMULATE_DONE;
7362         }
7363 
7364         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7365 }
7366 
7367 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7368 {
7369         WARN_ON_ONCE(!enable_vnmi);
7370         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7371                         CPU_BASED_VIRTUAL_NMI_PENDING);
7372         ++vcpu->stat.nmi_window_exits;
7373         kvm_make_request(KVM_REQ_EVENT, vcpu);
7374 
7375         return 1;
7376 }
7377 
7378 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7379 {
7380         struct vcpu_vmx *vmx = to_vmx(vcpu);
7381         enum emulation_result err = EMULATE_DONE;
7382         int ret = 1;
7383         u32 cpu_exec_ctrl;
7384         bool intr_window_requested;
7385         unsigned count = 130;
7386 
7387         /*
7388          * We should never reach the point where we are emulating L2
7389          * due to invalid guest state as that means we incorrectly
7390          * allowed a nested VMEntry with an invalid vmcs12.
7391          */
7392         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7393 
7394         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7395         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7396 
7397         while (vmx->emulation_required && count-- != 0) {
7398                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7399                         return handle_interrupt_window(&vmx->vcpu);
7400 
7401                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7402                         return 1;
7403 
7404                 err = emulate_instruction(vcpu, 0);
7405 
7406                 if (err == EMULATE_USER_EXIT) {
7407                         ++vcpu->stat.mmio_exits;
7408                         ret = 0;
7409                         goto out;
7410                 }
7411 
7412                 if (err != EMULATE_DONE)
7413                         goto emulation_error;
7414 
7415                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7416                     vcpu->arch.exception.pending)
7417                         goto emulation_error;
7418 
7419                 if (vcpu->arch.halt_request) {
7420                         vcpu->arch.halt_request = 0;
7421                         ret = kvm_vcpu_halt(vcpu);
7422                         goto out;
7423                 }
7424 
7425                 if (signal_pending(current))
7426                         goto out;
7427                 if (need_resched())
7428                         schedule();
7429         }
7430 
7431 out:
7432         return ret;
7433 
7434 emulation_error:
7435         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7436         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7437         vcpu->run->internal.ndata = 0;
7438         return 0;
7439 }
7440 
7441 static void grow_ple_window(struct kvm_vcpu *vcpu)
7442 {
7443         struct vcpu_vmx *vmx = to_vmx(vcpu);
7444         int old = vmx->ple_window;
7445 
7446         vmx->ple_window = __grow_ple_window(old, ple_window,
7447                                             ple_window_grow,
7448                                             ple_window_max);
7449 
7450         if (vmx->ple_window != old)
7451                 vmx->ple_window_dirty = true;
7452 
7453         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7454 }
7455 
7456 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7457 {
7458         struct vcpu_vmx *vmx = to_vmx(vcpu);
7459         int old = vmx->ple_window;
7460 
7461         vmx->ple_window = __shrink_ple_window(old, ple_window,
7462                                               ple_window_shrink,
7463                                               ple_window);
7464 
7465         if (vmx->ple_window != old)
7466                 vmx->ple_window_dirty = true;
7467 
7468         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7469 }
7470 
7471 /*
7472  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7473  */
7474 static void wakeup_handler(void)
7475 {
7476         struct kvm_vcpu *vcpu;
7477         int cpu = smp_processor_id();
7478 
7479         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7480         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7481                         blocked_vcpu_list) {
7482                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7483 
7484                 if (pi_test_on(pi_desc) == 1)
7485                         kvm_vcpu_kick(vcpu);
7486         }
7487         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7488 }
7489 
7490 static void vmx_enable_tdp(void)
7491 {
7492         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7493                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7494                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7495                 0ull, VMX_EPT_EXECUTABLE_MASK,
7496                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7497                 VMX_EPT_RWX_MASK, 0ull);
7498 
7499         ept_set_mmio_spte_mask();
7500         kvm_enable_tdp();
7501 }
7502 
7503 static __init int hardware_setup(void)
7504 {
7505         int r = -ENOMEM, i;
7506 
7507         rdmsrl_safe(MSR_EFER, &host_efer);
7508 
7509         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7510                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7511 
7512         for (i = 0; i < VMX_BITMAP_NR; i++) {
7513                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7514                 if (!vmx_bitmap[i])
7515                         goto out;
7516         }
7517 
7518         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7519         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7520 
7521         if (setup_vmcs_config(&vmcs_config) < 0) {
7522                 r = -EIO;
7523                 goto out;
7524         }
7525 
7526         if (boot_cpu_has(X86_FEATURE_NX))
7527                 kvm_enable_efer_bits(EFER_NX);
7528 
7529         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7530                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7531                 enable_vpid = 0;
7532 
7533         if (!cpu_has_vmx_ept() ||
7534             !cpu_has_vmx_ept_4levels() ||
7535             !cpu_has_vmx_ept_mt_wb() ||
7536             !cpu_has_vmx_invept_global())
7537                 enable_ept = 0;
7538 
7539         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7540                 enable_ept_ad_bits = 0;
7541 
7542         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7543                 enable_unrestricted_guest = 0;
7544 
7545         if (!cpu_has_vmx_flexpriority())
7546                 flexpriority_enabled = 0;
7547 
7548         if (!cpu_has_virtual_nmis())
7549                 enable_vnmi = 0;
7550 
7551         /*
7552          * set_apic_access_page_addr() is used to reload apic access
7553          * page upon invalidation.  No need to do anything if not
7554          * using the APIC_ACCESS_ADDR VMCS field.
7555          */
7556         if (!flexpriority_enabled)
7557                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7558 
7559         if (!cpu_has_vmx_tpr_shadow())
7560                 kvm_x86_ops->update_cr8_intercept = NULL;
7561 
7562         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7563                 kvm_disable_largepages();
7564 
7565         if (!cpu_has_vmx_ple()) {
7566                 ple_gap = 0;
7567                 ple_window = 0;
7568                 ple_window_grow = 0;
7569                 ple_window_max = 0;
7570                 ple_window_shrink = 0;
7571         }
7572 
7573         if (!cpu_has_vmx_apicv()) {
7574                 enable_apicv = 0;
7575                 kvm_x86_ops->sync_pir_to_irr = NULL;
7576         }
7577 
7578         if (cpu_has_vmx_tsc_scaling()) {
7579                 kvm_has_tsc_control = true;
7580                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7581                 kvm_tsc_scaling_ratio_frac_bits = 48;
7582         }
7583 
7584         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7585 
7586         if (enable_ept)
7587                 vmx_enable_tdp();
7588         else
7589                 kvm_disable_tdp();
7590 
7591         /*
7592          * Only enable PML when hardware supports PML feature, and both EPT
7593          * and EPT A/D bit features are enabled -- PML depends on them to work.
7594          */
7595         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7596                 enable_pml = 0;
7597 
7598         if (!enable_pml) {
7599                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7600                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7601                 kvm_x86_ops->flush_log_dirty = NULL;
7602                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7603         }
7604 
7605         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7606                 u64 vmx_msr;
7607 
7608                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7609                 cpu_preemption_timer_multi =
7610                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7611         } else {
7612                 kvm_x86_ops->set_hv_timer = NULL;
7613                 kvm_x86_ops->cancel_hv_timer = NULL;
7614         }
7615 
7616         if (!cpu_has_vmx_shadow_vmcs())
7617                 enable_shadow_vmcs = 0;
7618         if (enable_shadow_vmcs)
7619                 init_vmcs_shadow_fields();
7620 
7621         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7622         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7623 
7624         kvm_mce_cap_supported |= MCG_LMCE_P;
7625 
7626         return alloc_kvm_area();
7627 
7628 out:
7629         for (i = 0; i < VMX_BITMAP_NR; i++)
7630                 free_page((unsigned long)vmx_bitmap[i]);
7631 
7632     return r;
7633 }
7634 
7635 static __exit void hardware_unsetup(void)
7636 {
7637         int i;
7638 
7639         for (i = 0; i < VMX_BITMAP_NR; i++)
7640                 free_page((unsigned long)vmx_bitmap[i]);
7641 
7642         free_kvm_area();
7643 }
7644 
7645 /*
7646  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7647  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7648  */
7649 static int handle_pause(struct kvm_vcpu *vcpu)
7650 {
7651         if (!kvm_pause_in_guest(vcpu->kvm))
7652                 grow_ple_window(vcpu);
7653 
7654         /*
7655          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7656          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7657          * never set PAUSE_EXITING and just set PLE if supported,
7658          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7659          */
7660         kvm_vcpu_on_spin(vcpu, true);
7661         return kvm_skip_emulated_instruction(vcpu);
7662 }
7663 
7664 static int handle_nop(struct kvm_vcpu *vcpu)
7665 {
7666         return kvm_skip_emulated_instruction(vcpu);
7667 }
7668 
7669 static int handle_mwait(struct kvm_vcpu *vcpu)
7670 {
7671         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7672         return handle_nop(vcpu);
7673 }
7674 
7675 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7676 {
7677         kvm_queue_exception(vcpu, UD_VECTOR);
7678         return 1;
7679 }
7680 
7681 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7682 {
7683         return 1;
7684 }
7685 
7686 static int handle_monitor(struct kvm_vcpu *vcpu)
7687 {
7688         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7689         return handle_nop(vcpu);
7690 }
7691 
7692 /*
7693  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7694  * set the success or error code of an emulated VMX instruction, as specified
7695  * by Vol 2B, VMX Instruction Reference, "Conventions".
7696  */
7697 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7698 {
7699         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7700                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7701                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7702 }
7703 
7704 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7705 {
7706         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7707                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7708                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7709                         | X86_EFLAGS_CF);
7710 }
7711 
7712 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7713                                         u32 vm_instruction_error)
7714 {
7715         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7716                 /*
7717                  * failValid writes the error number to the current VMCS, which
7718                  * can't be done there isn't a current VMCS.
7719                  */
7720                 nested_vmx_failInvalid(vcpu);
7721                 return;
7722         }
7723         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7724                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7725                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7726                         | X86_EFLAGS_ZF);
7727         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7728         /*
7729          * We don't need to force a shadow sync because
7730          * VM_INSTRUCTION_ERROR is not shadowed
7731          */
7732 }
7733 
7734 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7735 {
7736         /* TODO: not to reset guest simply here. */
7737         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7738         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7739 }
7740 
7741 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7742 {
7743         struct vcpu_vmx *vmx =
7744                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7745 
7746         vmx->nested.preemption_timer_expired = true;
7747         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7748         kvm_vcpu_kick(&vmx->vcpu);
7749 
7750         return HRTIMER_NORESTART;
7751 }
7752 
7753 /*
7754  * Decode the memory-address operand of a vmx instruction, as recorded on an
7755  * exit caused by such an instruction (run by a guest hypervisor).
7756  * On success, returns 0. When the operand is invalid, returns 1 and throws
7757  * #UD or #GP.
7758  */
7759 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7760                                  unsigned long exit_qualification,
7761                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7762 {
7763         gva_t off;
7764         bool exn;
7765         struct kvm_segment s;
7766 
7767         /*
7768          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7769          * Execution", on an exit, vmx_instruction_info holds most of the
7770          * addressing components of the operand. Only the displacement part
7771          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7772          * For how an actual address is calculated from all these components,
7773          * refer to Vol. 1, "Operand Addressing".
7774          */
7775         int  scaling = vmx_instruction_info & 3;
7776         int  addr_size = (vmx_instruction_info >> 7) & 7;
7777         bool is_reg = vmx_instruction_info & (1u << 10);
7778         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7779         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7780         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7781         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7782         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7783 
7784         if (is_reg) {
7785                 kvm_queue_exception(vcpu, UD_VECTOR);
7786                 return 1;
7787         }
7788 
7789         /* Addr = segment_base + offset */
7790         /* offset = base + [index * scale] + displacement */
7791         off = exit_qualification; /* holds the displacement */
7792         if (base_is_valid)
7793                 off += kvm_register_read(vcpu, base_reg);
7794         if (index_is_valid)
7795                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7796         vmx_get_segment(vcpu, &s, seg_reg);
7797         *ret = s.base + off;
7798 
7799         if (addr_size == 1) /* 32 bit */
7800                 *ret &= 0xffffffff;
7801 
7802         /* Checks for #GP/#SS exceptions. */
7803         exn = false;
7804         if (is_long_mode(vcpu)) {
7805                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7806                  * non-canonical form. This is the only check on the memory
7807                  * destination for long mode!
7808                  */
7809                 exn = is_noncanonical_address(*ret, vcpu);
7810         } else if (is_protmode(vcpu)) {
7811                 /* Protected mode: apply checks for segment validity in the
7812                  * following order:
7813                  * - segment type check (#GP(0) may be thrown)
7814                  * - usability check (#GP(0)/#SS(0))
7815                  * - limit check (#GP(0)/#SS(0))
7816                  */
7817                 if (wr)
7818                         /* #GP(0) if the destination operand is located in a
7819                          * read-only data segment or any code segment.
7820                          */
7821                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7822                 else
7823                         /* #GP(0) if the source operand is located in an
7824                          * execute-only code segment
7825                          */
7826                         exn = ((s.type & 0xa) == 8);
7827                 if (exn) {
7828                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7829                         return 1;
7830                 }
7831                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7832                  */
7833                 exn = (s.unusable != 0);
7834                 /* Protected mode: #GP(0)/#SS(0) if the memory
7835                  * operand is outside the segment limit.
7836                  */
7837                 exn = exn || (off + sizeof(u64) > s.limit);
7838         }
7839         if (exn) {
7840                 kvm_queue_exception_e(vcpu,
7841                                       seg_reg == VCPU_SREG_SS ?
7842                                                 SS_VECTOR : GP_VECTOR,
7843                                       0);
7844                 return 1;
7845         }
7846 
7847         return 0;
7848 }
7849 
7850 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7851 {
7852         gva_t gva;
7853         struct x86_exception e;
7854 
7855         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7856                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7857                 return 1;
7858 
7859         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7860                 kvm_inject_page_fault(vcpu, &e);
7861                 return 1;
7862         }
7863 
7864         return 0;
7865 }
7866 
7867 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7868 {
7869         struct vcpu_vmx *vmx = to_vmx(vcpu);
7870         struct vmcs *shadow_vmcs;
7871         int r;
7872 
7873         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7874         if (r < 0)
7875                 goto out_vmcs02;
7876 
7877         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7878         if (!vmx->nested.cached_vmcs12)
7879                 goto out_cached_vmcs12;
7880 
7881         if (enable_shadow_vmcs) {
7882                 shadow_vmcs = alloc_vmcs();
7883                 if (!shadow_vmcs)
7884                         goto out_shadow_vmcs;
7885                 /* mark vmcs as shadow */
7886                 shadow_vmcs->revision_id |= (1u << 31);
7887                 /* init shadow vmcs */
7888                 vmcs_clear(shadow_vmcs);
7889                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7890         }
7891 
7892         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7893                      HRTIMER_MODE_REL_PINNED);
7894         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7895 
7896         vmx->nested.vpid02 = allocate_vpid();