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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/vmx.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * Copyright (C) 2006 Qumranet, Inc.
  8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  9  *
 10  * Authors:
 11  *   Avi Kivity   <avi@qumranet.com>
 12  *   Yaniv Kamay  <yaniv@qumranet.com>
 13  *
 14  * This work is licensed under the terms of the GNU GPL, version 2.  See
 15  * the COPYING file in the top-level directory.
 16  *
 17  */
 18 
 19 #include "irq.h"
 20 #include "mmu.h"
 21 #include "cpuid.h"
 22 #include "lapic.h"
 23 
 24 #include <linux/kvm_host.h>
 25 #include <linux/module.h>
 26 #include <linux/kernel.h>
 27 #include <linux/mm.h>
 28 #include <linux/highmem.h>
 29 #include <linux/sched.h>
 30 #include <linux/moduleparam.h>
 31 #include <linux/mod_devicetable.h>
 32 #include <linux/trace_events.h>
 33 #include <linux/slab.h>
 34 #include <linux/tboot.h>
 35 #include <linux/hrtimer.h>
 36 #include "kvm_cache_regs.h"
 37 #include "x86.h"
 38 
 39 #include <asm/cpu.h>
 40 #include <asm/io.h>
 41 #include <asm/desc.h>
 42 #include <asm/vmx.h>
 43 #include <asm/virtext.h>
 44 #include <asm/mce.h>
 45 #include <asm/fpu/internal.h>
 46 #include <asm/perf_event.h>
 47 #include <asm/debugreg.h>
 48 #include <asm/kexec.h>
 49 #include <asm/apic.h>
 50 #include <asm/irq_remapping.h>
 51 
 52 #include "trace.h"
 53 #include "pmu.h"
 54 
 55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 56 #define __ex_clear(x, reg) \
 57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
 58 
 59 MODULE_AUTHOR("Qumranet");
 60 MODULE_LICENSE("GPL");
 61 
 62 static const struct x86_cpu_id vmx_cpu_id[] = {
 63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
 64         {}
 65 };
 66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
 67 
 68 static bool __read_mostly enable_vpid = 1;
 69 module_param_named(vpid, enable_vpid, bool, 0444);
 70 
 71 static bool __read_mostly flexpriority_enabled = 1;
 72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
 73 
 74 static bool __read_mostly enable_ept = 1;
 75 module_param_named(ept, enable_ept, bool, S_IRUGO);
 76 
 77 static bool __read_mostly enable_unrestricted_guest = 1;
 78 module_param_named(unrestricted_guest,
 79                         enable_unrestricted_guest, bool, S_IRUGO);
 80 
 81 static bool __read_mostly enable_ept_ad_bits = 1;
 82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
 83 
 84 static bool __read_mostly emulate_invalid_guest_state = true;
 85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 86 
 87 static bool __read_mostly vmm_exclusive = 1;
 88 module_param(vmm_exclusive, bool, S_IRUGO);
 89 
 90 static bool __read_mostly fasteoi = 1;
 91 module_param(fasteoi, bool, S_IRUGO);
 92 
 93 static bool __read_mostly enable_apicv = 1;
 94 module_param(enable_apicv, bool, S_IRUGO);
 95 
 96 static bool __read_mostly enable_shadow_vmcs = 1;
 97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 98 /*
 99  * If nested=1, nested virtualization is supported, i.e., guests may use
100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101  * use VMX instructions.
102  */
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
105 
106 static u64 __read_mostly host_xss;
107 
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 
111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
112 
113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
115 #define KVM_VM_CR0_ALWAYS_ON                                            \
116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 
121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 
124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 
126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
127 
128 /*
129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
130  * ple_gap:    upper bound on the amount of time between two successive
131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
132  *             According to test, this time is usually smaller than 128 cycles.
133  * ple_window: upper bound on the amount of time a guest is allowed to execute
134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
135  *             less than 2^12 cycles
136  * Time is measured based on a counter that runs at the same rate as the TSC,
137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
138  */
139 #define KVM_VMX_DEFAULT_PLE_GAP           128
140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 
146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
147 module_param(ple_gap, int, S_IRUGO);
148 
149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
150 module_param(ple_window, int, S_IRUGO);
151 
152 /* Default doubles per-vcpu window every exit. */
153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
154 module_param(ple_window_grow, int, S_IRUGO);
155 
156 /* Default resets per-vcpu window every exit to ple_window. */
157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
158 module_param(ple_window_shrink, int, S_IRUGO);
159 
160 /* Default is to compute the maximum so we can never overflow. */
161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
163 module_param(ple_window_max, int, S_IRUGO);
164 
165 extern const ulong vmx_return;
166 
167 #define NR_AUTOLOAD_MSRS 8
168 #define VMCS02_POOL_SIZE 1
169 
170 struct vmcs {
171         u32 revision_id;
172         u32 abort;
173         char data[0];
174 };
175 
176 /*
177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
179  * loaded on this CPU (so we can clear them if the CPU goes down).
180  */
181 struct loaded_vmcs {
182         struct vmcs *vmcs;
183         int cpu;
184         int launched;
185         struct list_head loaded_vmcss_on_cpu_link;
186 };
187 
188 struct shared_msr_entry {
189         unsigned index;
190         u64 data;
191         u64 mask;
192 };
193 
194 /*
195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
202  * underlying hardware which will be used to run L2.
203  * This structure is packed to ensure that its layout is identical across
204  * machines (necessary for live migration).
205  * If there are changes in this struct, VMCS12_REVISION must be changed.
206  */
207 typedef u64 natural_width;
208 struct __packed vmcs12 {
209         /* According to the Intel spec, a VMCS region must start with the
210          * following two fields. Then follow implementation-specific data.
211          */
212         u32 revision_id;
213         u32 abort;
214 
215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
216         u32 padding[7]; /* room for future expansion */
217 
218         u64 io_bitmap_a;
219         u64 io_bitmap_b;
220         u64 msr_bitmap;
221         u64 vm_exit_msr_store_addr;
222         u64 vm_exit_msr_load_addr;
223         u64 vm_entry_msr_load_addr;
224         u64 tsc_offset;
225         u64 virtual_apic_page_addr;
226         u64 apic_access_addr;
227         u64 posted_intr_desc_addr;
228         u64 ept_pointer;
229         u64 eoi_exit_bitmap0;
230         u64 eoi_exit_bitmap1;
231         u64 eoi_exit_bitmap2;
232         u64 eoi_exit_bitmap3;
233         u64 xss_exit_bitmap;
234         u64 guest_physical_address;
235         u64 vmcs_link_pointer;
236         u64 guest_ia32_debugctl;
237         u64 guest_ia32_pat;
238         u64 guest_ia32_efer;
239         u64 guest_ia32_perf_global_ctrl;
240         u64 guest_pdptr0;
241         u64 guest_pdptr1;
242         u64 guest_pdptr2;
243         u64 guest_pdptr3;
244         u64 guest_bndcfgs;
245         u64 host_ia32_pat;
246         u64 host_ia32_efer;
247         u64 host_ia32_perf_global_ctrl;
248         u64 padding64[8]; /* room for future expansion */
249         /*
250          * To allow migration of L1 (complete with its L2 guests) between
251          * machines of different natural widths (32 or 64 bit), we cannot have
252          * unsigned long fields with no explict size. We use u64 (aliased
253          * natural_width) instead. Luckily, x86 is little-endian.
254          */
255         natural_width cr0_guest_host_mask;
256         natural_width cr4_guest_host_mask;
257         natural_width cr0_read_shadow;
258         natural_width cr4_read_shadow;
259         natural_width cr3_target_value0;
260         natural_width cr3_target_value1;
261         natural_width cr3_target_value2;
262         natural_width cr3_target_value3;
263         natural_width exit_qualification;
264         natural_width guest_linear_address;
265         natural_width guest_cr0;
266         natural_width guest_cr3;
267         natural_width guest_cr4;
268         natural_width guest_es_base;
269         natural_width guest_cs_base;
270         natural_width guest_ss_base;
271         natural_width guest_ds_base;
272         natural_width guest_fs_base;
273         natural_width guest_gs_base;
274         natural_width guest_ldtr_base;
275         natural_width guest_tr_base;
276         natural_width guest_gdtr_base;
277         natural_width guest_idtr_base;
278         natural_width guest_dr7;
279         natural_width guest_rsp;
280         natural_width guest_rip;
281         natural_width guest_rflags;
282         natural_width guest_pending_dbg_exceptions;
283         natural_width guest_sysenter_esp;
284         natural_width guest_sysenter_eip;
285         natural_width host_cr0;
286         natural_width host_cr3;
287         natural_width host_cr4;
288         natural_width host_fs_base;
289         natural_width host_gs_base;
290         natural_width host_tr_base;
291         natural_width host_gdtr_base;
292         natural_width host_idtr_base;
293         natural_width host_ia32_sysenter_esp;
294         natural_width host_ia32_sysenter_eip;
295         natural_width host_rsp;
296         natural_width host_rip;
297         natural_width paddingl[8]; /* room for future expansion */
298         u32 pin_based_vm_exec_control;
299         u32 cpu_based_vm_exec_control;
300         u32 exception_bitmap;
301         u32 page_fault_error_code_mask;
302         u32 page_fault_error_code_match;
303         u32 cr3_target_count;
304         u32 vm_exit_controls;
305         u32 vm_exit_msr_store_count;
306         u32 vm_exit_msr_load_count;
307         u32 vm_entry_controls;
308         u32 vm_entry_msr_load_count;
309         u32 vm_entry_intr_info_field;
310         u32 vm_entry_exception_error_code;
311         u32 vm_entry_instruction_len;
312         u32 tpr_threshold;
313         u32 secondary_vm_exec_control;
314         u32 vm_instruction_error;
315         u32 vm_exit_reason;
316         u32 vm_exit_intr_info;
317         u32 vm_exit_intr_error_code;
318         u32 idt_vectoring_info_field;
319         u32 idt_vectoring_error_code;
320         u32 vm_exit_instruction_len;
321         u32 vmx_instruction_info;
322         u32 guest_es_limit;
323         u32 guest_cs_limit;
324         u32 guest_ss_limit;
325         u32 guest_ds_limit;
326         u32 guest_fs_limit;
327         u32 guest_gs_limit;
328         u32 guest_ldtr_limit;
329         u32 guest_tr_limit;
330         u32 guest_gdtr_limit;
331         u32 guest_idtr_limit;
332         u32 guest_es_ar_bytes;
333         u32 guest_cs_ar_bytes;
334         u32 guest_ss_ar_bytes;
335         u32 guest_ds_ar_bytes;
336         u32 guest_fs_ar_bytes;
337         u32 guest_gs_ar_bytes;
338         u32 guest_ldtr_ar_bytes;
339         u32 guest_tr_ar_bytes;
340         u32 guest_interruptibility_info;
341         u32 guest_activity_state;
342         u32 guest_sysenter_cs;
343         u32 host_ia32_sysenter_cs;
344         u32 vmx_preemption_timer_value;
345         u32 padding32[7]; /* room for future expansion */
346         u16 virtual_processor_id;
347         u16 posted_intr_nv;
348         u16 guest_es_selector;
349         u16 guest_cs_selector;
350         u16 guest_ss_selector;
351         u16 guest_ds_selector;
352         u16 guest_fs_selector;
353         u16 guest_gs_selector;
354         u16 guest_ldtr_selector;
355         u16 guest_tr_selector;
356         u16 guest_intr_status;
357         u16 host_es_selector;
358         u16 host_cs_selector;
359         u16 host_ss_selector;
360         u16 host_ds_selector;
361         u16 host_fs_selector;
362         u16 host_gs_selector;
363         u16 host_tr_selector;
364 };
365 
366 /*
367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370  */
371 #define VMCS12_REVISION 0x11e57ed0
372 
373 /*
374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
376  * current implementation, 4K are reserved to avoid future complications.
377  */
378 #define VMCS12_SIZE 0x1000
379 
380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct vmcs02_list {
382         struct list_head list;
383         gpa_t vmptr;
384         struct loaded_vmcs vmcs02;
385 };
386 
387 /*
388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
390  */
391 struct nested_vmx {
392         /* Has the level1 guest done vmxon? */
393         bool vmxon;
394         gpa_t vmxon_ptr;
395 
396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
397         gpa_t current_vmptr;
398         /* The host-usable pointer to the above */
399         struct page *current_vmcs12_page;
400         struct vmcs12 *current_vmcs12;
401         struct vmcs *current_shadow_vmcs;
402         /*
403          * Indicates if the shadow vmcs must be updated with the
404          * data hold by vmcs12
405          */
406         bool sync_shadow_vmcs;
407 
408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
409         struct list_head vmcs02_pool;
410         int vmcs02_num;
411         u64 vmcs01_tsc_offset;
412         /* L2 must run next, and mustn't decide to exit to L1. */
413         bool nested_run_pending;
414         /*
415          * Guest pages referred to in vmcs02 with host-physical pointers, so
416          * we must keep them pinned while L2 runs.
417          */
418         struct page *apic_access_page;
419         struct page *virtual_apic_page;
420         struct page *pi_desc_page;
421         struct pi_desc *pi_desc;
422         bool pi_pending;
423         u16 posted_intr_nv;
424         u64 msr_ia32_feature_control;
425 
426         struct hrtimer preemption_timer;
427         bool preemption_timer_expired;
428 
429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
430         u64 vmcs01_debugctl;
431 
432         u16 vpid02;
433         u16 last_vpid;
434 
435         u32 nested_vmx_procbased_ctls_low;
436         u32 nested_vmx_procbased_ctls_high;
437         u32 nested_vmx_true_procbased_ctls_low;
438         u32 nested_vmx_secondary_ctls_low;
439         u32 nested_vmx_secondary_ctls_high;
440         u32 nested_vmx_pinbased_ctls_low;
441         u32 nested_vmx_pinbased_ctls_high;
442         u32 nested_vmx_exit_ctls_low;
443         u32 nested_vmx_exit_ctls_high;
444         u32 nested_vmx_true_exit_ctls_low;
445         u32 nested_vmx_entry_ctls_low;
446         u32 nested_vmx_entry_ctls_high;
447         u32 nested_vmx_true_entry_ctls_low;
448         u32 nested_vmx_misc_low;
449         u32 nested_vmx_misc_high;
450         u32 nested_vmx_ept_caps;
451         u32 nested_vmx_vpid_caps;
452 };
453 
454 #define POSTED_INTR_ON  0
455 #define POSTED_INTR_SN  1
456 
457 /* Posted-Interrupt Descriptor */
458 struct pi_desc {
459         u32 pir[8];     /* Posted interrupt requested */
460         union {
461                 struct {
462                                 /* bit 256 - Outstanding Notification */
463                         u16     on      : 1,
464                                 /* bit 257 - Suppress Notification */
465                                 sn      : 1,
466                                 /* bit 271:258 - Reserved */
467                                 rsvd_1  : 14;
468                                 /* bit 279:272 - Notification Vector */
469                         u8      nv;
470                                 /* bit 287:280 - Reserved */
471                         u8      rsvd_2;
472                                 /* bit 319:288 - Notification Destination */
473                         u32     ndst;
474                 };
475                 u64 control;
476         };
477         u32 rsvd[6];
478 } __aligned(64);
479 
480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
481 {
482         return test_and_set_bit(POSTED_INTR_ON,
483                         (unsigned long *)&pi_desc->control);
484 }
485 
486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
487 {
488         return test_and_clear_bit(POSTED_INTR_ON,
489                         (unsigned long *)&pi_desc->control);
490 }
491 
492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
493 {
494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
495 }
496 
497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
498 {
499         return clear_bit(POSTED_INTR_SN,
500                         (unsigned long *)&pi_desc->control);
501 }
502 
503 static inline void pi_set_sn(struct pi_desc *pi_desc)
504 {
505         return set_bit(POSTED_INTR_SN,
506                         (unsigned long *)&pi_desc->control);
507 }
508 
509 static inline int pi_test_on(struct pi_desc *pi_desc)
510 {
511         return test_bit(POSTED_INTR_ON,
512                         (unsigned long *)&pi_desc->control);
513 }
514 
515 static inline int pi_test_sn(struct pi_desc *pi_desc)
516 {
517         return test_bit(POSTED_INTR_SN,
518                         (unsigned long *)&pi_desc->control);
519 }
520 
521 struct vcpu_vmx {
522         struct kvm_vcpu       vcpu;
523         unsigned long         host_rsp;
524         u8                    fail;
525         bool                  nmi_known_unmasked;
526         u32                   exit_intr_info;
527         u32                   idt_vectoring_info;
528         ulong                 rflags;
529         struct shared_msr_entry *guest_msrs;
530         int                   nmsrs;
531         int                   save_nmsrs;
532         unsigned long         host_idt_base;
533 #ifdef CONFIG_X86_64
534         u64                   msr_host_kernel_gs_base;
535         u64                   msr_guest_kernel_gs_base;
536 #endif
537         u32 vm_entry_controls_shadow;
538         u32 vm_exit_controls_shadow;
539         /*
540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541          * non-nested (L1) guest, it always points to vmcs01. For a nested
542          * guest (L2), it points to a different VMCS.
543          */
544         struct loaded_vmcs    vmcs01;
545         struct loaded_vmcs   *loaded_vmcs;
546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
547         struct msr_autoload {
548                 unsigned nr;
549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
551         } msr_autoload;
552         struct {
553                 int           loaded;
554                 u16           fs_sel, gs_sel, ldt_sel;
555 #ifdef CONFIG_X86_64
556                 u16           ds_sel, es_sel;
557 #endif
558                 int           gs_ldt_reload_needed;
559                 int           fs_reload_needed;
560                 u64           msr_host_bndcfgs;
561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
562         } host_state;
563         struct {
564                 int vm86_active;
565                 ulong save_rflags;
566                 struct kvm_segment segs[8];
567         } rmode;
568         struct {
569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
570                 struct kvm_save_segment {
571                         u16 selector;
572                         unsigned long base;
573                         u32 limit;
574                         u32 ar;
575                 } seg[8];
576         } segment_cache;
577         int vpid;
578         bool emulation_required;
579 
580         /* Support for vnmi-less CPUs */
581         int soft_vnmi_blocked;
582         ktime_t entry_time;
583         s64 vnmi_blocked_time;
584         u32 exit_reason;
585 
586         /* Posted interrupt descriptor */
587         struct pi_desc pi_desc;
588 
589         /* Support for a guest hypervisor (nested VMX) */
590         struct nested_vmx nested;
591 
592         /* Dynamic PLE window. */
593         int ple_window;
594         bool ple_window_dirty;
595 
596         /* Support for PML */
597 #define PML_ENTITY_NUM          512
598         struct page *pml_pg;
599 
600         u64 current_tsc_ratio;
601 
602         bool guest_pkru_valid;
603         u32 guest_pkru;
604         u32 host_pkru;
605 };
606 
607 enum segment_cache_field {
608         SEG_FIELD_SEL = 0,
609         SEG_FIELD_BASE = 1,
610         SEG_FIELD_LIMIT = 2,
611         SEG_FIELD_AR = 3,
612 
613         SEG_FIELD_NR = 4
614 };
615 
616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
617 {
618         return container_of(vcpu, struct vcpu_vmx, vcpu);
619 }
620 
621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
622 {
623         return &(to_vmx(vcpu)->pi_desc);
624 }
625 
626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
627 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
628 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
629                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
630 
631 
632 static unsigned long shadow_read_only_fields[] = {
633         /*
634          * We do NOT shadow fields that are modified when L0
635          * traps and emulates any vmx instruction (e.g. VMPTRLD,
636          * VMXON...) executed by L1.
637          * For example, VM_INSTRUCTION_ERROR is read
638          * by L1 if a vmx instruction fails (part of the error path).
639          * Note the code assumes this logic. If for some reason
640          * we start shadowing these fields then we need to
641          * force a shadow sync when L0 emulates vmx instructions
642          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
643          * by nested_vmx_failValid)
644          */
645         VM_EXIT_REASON,
646         VM_EXIT_INTR_INFO,
647         VM_EXIT_INSTRUCTION_LEN,
648         IDT_VECTORING_INFO_FIELD,
649         IDT_VECTORING_ERROR_CODE,
650         VM_EXIT_INTR_ERROR_CODE,
651         EXIT_QUALIFICATION,
652         GUEST_LINEAR_ADDRESS,
653         GUEST_PHYSICAL_ADDRESS
654 };
655 static int max_shadow_read_only_fields =
656         ARRAY_SIZE(shadow_read_only_fields);
657 
658 static unsigned long shadow_read_write_fields[] = {
659         TPR_THRESHOLD,
660         GUEST_RIP,
661         GUEST_RSP,
662         GUEST_CR0,
663         GUEST_CR3,
664         GUEST_CR4,
665         GUEST_INTERRUPTIBILITY_INFO,
666         GUEST_RFLAGS,
667         GUEST_CS_SELECTOR,
668         GUEST_CS_AR_BYTES,
669         GUEST_CS_LIMIT,
670         GUEST_CS_BASE,
671         GUEST_ES_BASE,
672         GUEST_BNDCFGS,
673         CR0_GUEST_HOST_MASK,
674         CR0_READ_SHADOW,
675         CR4_READ_SHADOW,
676         TSC_OFFSET,
677         EXCEPTION_BITMAP,
678         CPU_BASED_VM_EXEC_CONTROL,
679         VM_ENTRY_EXCEPTION_ERROR_CODE,
680         VM_ENTRY_INTR_INFO_FIELD,
681         VM_ENTRY_INSTRUCTION_LEN,
682         VM_ENTRY_EXCEPTION_ERROR_CODE,
683         HOST_FS_BASE,
684         HOST_GS_BASE,
685         HOST_FS_SELECTOR,
686         HOST_GS_SELECTOR
687 };
688 static int max_shadow_read_write_fields =
689         ARRAY_SIZE(shadow_read_write_fields);
690 
691 static const unsigned short vmcs_field_to_offset_table[] = {
692         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
693         FIELD(POSTED_INTR_NV, posted_intr_nv),
694         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
695         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
696         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
697         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
698         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
699         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
700         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
701         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
702         FIELD(GUEST_INTR_STATUS, guest_intr_status),
703         FIELD(HOST_ES_SELECTOR, host_es_selector),
704         FIELD(HOST_CS_SELECTOR, host_cs_selector),
705         FIELD(HOST_SS_SELECTOR, host_ss_selector),
706         FIELD(HOST_DS_SELECTOR, host_ds_selector),
707         FIELD(HOST_FS_SELECTOR, host_fs_selector),
708         FIELD(HOST_GS_SELECTOR, host_gs_selector),
709         FIELD(HOST_TR_SELECTOR, host_tr_selector),
710         FIELD64(IO_BITMAP_A, io_bitmap_a),
711         FIELD64(IO_BITMAP_B, io_bitmap_b),
712         FIELD64(MSR_BITMAP, msr_bitmap),
713         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
714         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
715         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
716         FIELD64(TSC_OFFSET, tsc_offset),
717         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
718         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
719         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
720         FIELD64(EPT_POINTER, ept_pointer),
721         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
722         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
723         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
724         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
725         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
726         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
727         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
728         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
729         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
730         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
731         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
732         FIELD64(GUEST_PDPTR0, guest_pdptr0),
733         FIELD64(GUEST_PDPTR1, guest_pdptr1),
734         FIELD64(GUEST_PDPTR2, guest_pdptr2),
735         FIELD64(GUEST_PDPTR3, guest_pdptr3),
736         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
737         FIELD64(HOST_IA32_PAT, host_ia32_pat),
738         FIELD64(HOST_IA32_EFER, host_ia32_efer),
739         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
740         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
741         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
742         FIELD(EXCEPTION_BITMAP, exception_bitmap),
743         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
744         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
745         FIELD(CR3_TARGET_COUNT, cr3_target_count),
746         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
747         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
748         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
749         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
750         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
751         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
752         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
753         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
754         FIELD(TPR_THRESHOLD, tpr_threshold),
755         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
756         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
757         FIELD(VM_EXIT_REASON, vm_exit_reason),
758         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
759         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
760         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
761         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
762         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
763         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
764         FIELD(GUEST_ES_LIMIT, guest_es_limit),
765         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
766         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
767         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
768         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
769         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
770         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
771         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
772         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
773         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
774         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
775         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
776         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
777         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
778         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
779         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
780         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
781         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
782         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
783         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
784         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
785         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
786         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
787         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
788         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
789         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
790         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
791         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
792         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
793         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
794         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
795         FIELD(EXIT_QUALIFICATION, exit_qualification),
796         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
797         FIELD(GUEST_CR0, guest_cr0),
798         FIELD(GUEST_CR3, guest_cr3),
799         FIELD(GUEST_CR4, guest_cr4),
800         FIELD(GUEST_ES_BASE, guest_es_base),
801         FIELD(GUEST_CS_BASE, guest_cs_base),
802         FIELD(GUEST_SS_BASE, guest_ss_base),
803         FIELD(GUEST_DS_BASE, guest_ds_base),
804         FIELD(GUEST_FS_BASE, guest_fs_base),
805         FIELD(GUEST_GS_BASE, guest_gs_base),
806         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
807         FIELD(GUEST_TR_BASE, guest_tr_base),
808         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
809         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
810         FIELD(GUEST_DR7, guest_dr7),
811         FIELD(GUEST_RSP, guest_rsp),
812         FIELD(GUEST_RIP, guest_rip),
813         FIELD(GUEST_RFLAGS, guest_rflags),
814         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
815         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
816         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
817         FIELD(HOST_CR0, host_cr0),
818         FIELD(HOST_CR3, host_cr3),
819         FIELD(HOST_CR4, host_cr4),
820         FIELD(HOST_FS_BASE, host_fs_base),
821         FIELD(HOST_GS_BASE, host_gs_base),
822         FIELD(HOST_TR_BASE, host_tr_base),
823         FIELD(HOST_GDTR_BASE, host_gdtr_base),
824         FIELD(HOST_IDTR_BASE, host_idtr_base),
825         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
826         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
827         FIELD(HOST_RSP, host_rsp),
828         FIELD(HOST_RIP, host_rip),
829 };
830 
831 static inline short vmcs_field_to_offset(unsigned long field)
832 {
833         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
834 
835         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
836             vmcs_field_to_offset_table[field] == 0)
837                 return -ENOENT;
838 
839         return vmcs_field_to_offset_table[field];
840 }
841 
842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
843 {
844         return to_vmx(vcpu)->nested.current_vmcs12;
845 }
846 
847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
848 {
849         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
850         if (is_error_page(page))
851                 return NULL;
852 
853         return page;
854 }
855 
856 static void nested_release_page(struct page *page)
857 {
858         kvm_release_page_dirty(page);
859 }
860 
861 static void nested_release_page_clean(struct page *page)
862 {
863         kvm_release_page_clean(page);
864 }
865 
866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
867 static u64 construct_eptp(unsigned long root_hpa);
868 static void kvm_cpu_vmxon(u64 addr);
869 static void kvm_cpu_vmxoff(void);
870 static bool vmx_xsaves_supported(void);
871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
873                             struct kvm_segment *var, int seg);
874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
875                             struct kvm_segment *var, int seg);
876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
880 static int alloc_identity_pagetable(struct kvm *kvm);
881 
882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
884 /*
885  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
886  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
887  */
888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
890 
891 /*
892  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
893  * can find which vCPU should be waken up.
894  */
895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
897 
898 static unsigned long *vmx_io_bitmap_a;
899 static unsigned long *vmx_io_bitmap_b;
900 static unsigned long *vmx_msr_bitmap_legacy;
901 static unsigned long *vmx_msr_bitmap_longmode;
902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
904 static unsigned long *vmx_msr_bitmap_nested;
905 static unsigned long *vmx_vmread_bitmap;
906 static unsigned long *vmx_vmwrite_bitmap;
907 
908 static bool cpu_has_load_ia32_efer;
909 static bool cpu_has_load_perf_global_ctrl;
910 
911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
912 static DEFINE_SPINLOCK(vmx_vpid_lock);
913 
914 static struct vmcs_config {
915         int size;
916         int order;
917         u32 revision_id;
918         u32 pin_based_exec_ctrl;
919         u32 cpu_based_exec_ctrl;
920         u32 cpu_based_2nd_exec_ctrl;
921         u32 vmexit_ctrl;
922         u32 vmentry_ctrl;
923 } vmcs_config;
924 
925 static struct vmx_capability {
926         u32 ept;
927         u32 vpid;
928 } vmx_capability;
929 
930 #define VMX_SEGMENT_FIELD(seg)                                  \
931         [VCPU_SREG_##seg] = {                                   \
932                 .selector = GUEST_##seg##_SELECTOR,             \
933                 .base = GUEST_##seg##_BASE,                     \
934                 .limit = GUEST_##seg##_LIMIT,                   \
935                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
936         }
937 
938 static const struct kvm_vmx_segment_field {
939         unsigned selector;
940         unsigned base;
941         unsigned limit;
942         unsigned ar_bytes;
943 } kvm_vmx_segment_fields[] = {
944         VMX_SEGMENT_FIELD(CS),
945         VMX_SEGMENT_FIELD(DS),
946         VMX_SEGMENT_FIELD(ES),
947         VMX_SEGMENT_FIELD(FS),
948         VMX_SEGMENT_FIELD(GS),
949         VMX_SEGMENT_FIELD(SS),
950         VMX_SEGMENT_FIELD(TR),
951         VMX_SEGMENT_FIELD(LDTR),
952 };
953 
954 static u64 host_efer;
955 
956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
957 
958 /*
959  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
960  * away by decrementing the array size.
961  */
962 static const u32 vmx_msr_index[] = {
963 #ifdef CONFIG_X86_64
964         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
965 #endif
966         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
967 };
968 
969 static inline bool is_exception_n(u32 intr_info, u8 vector)
970 {
971         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
972                              INTR_INFO_VALID_MASK)) ==
973                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
974 }
975 
976 static inline bool is_debug(u32 intr_info)
977 {
978         return is_exception_n(intr_info, DB_VECTOR);
979 }
980 
981 static inline bool is_breakpoint(u32 intr_info)
982 {
983         return is_exception_n(intr_info, BP_VECTOR);
984 }
985 
986 static inline bool is_page_fault(u32 intr_info)
987 {
988         return is_exception_n(intr_info, PF_VECTOR);
989 }
990 
991 static inline bool is_no_device(u32 intr_info)
992 {
993         return is_exception_n(intr_info, NM_VECTOR);
994 }
995 
996 static inline bool is_invalid_opcode(u32 intr_info)
997 {
998         return is_exception_n(intr_info, UD_VECTOR);
999 }
1000 
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006 
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010                              INTR_INFO_VALID_MASK)) ==
1011                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013 
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018 
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023 
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028 
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031         return vmcs_config.cpu_based_exec_ctrl &
1032                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034 
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040 
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046 
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052 
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058 
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064 
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067         return cpu_has_vmx_apic_register_virt() &&
1068                 cpu_has_vmx_virtual_intr_delivery() &&
1069                 cpu_has_vmx_posted_intr();
1070 }
1071 
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074         return cpu_has_vmx_tpr_shadow() &&
1075                 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077 
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082 
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087 
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092 
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097 
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102 
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107 
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112 
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117 
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122 
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128 
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134 
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140 
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143         return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145 
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151 
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_RDTSCP;
1156 }
1157 
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160         return vmcs_config.cpu_based_2nd_exec_ctrl &
1161                 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163 
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168 
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174 
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177         u64 vmx_msr;
1178         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179         /* check if the cpu supports writing r/o exit information fields */
1180         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181                 return false;
1182 
1183         return vmcs_config.cpu_based_2nd_exec_ctrl &
1184                 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186 
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191 
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197 
1198 static inline bool report_flexpriority(void)
1199 {
1200         return flexpriority_enabled;
1201 }
1202 
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207 
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210         return (vmcs12->cpu_based_vm_exec_control &
1211                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212                 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214 
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219 
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222         return vmcs12->pin_based_vm_exec_control &
1223                 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225 
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230 
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234                 vmx_xsaves_supported();
1235 }
1236 
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241 
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246 
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251 
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256 
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261 
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267 
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269                               u32 exit_intr_info,
1270                               unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272                         struct vmcs12 *vmcs12,
1273                         u32 reason, unsigned long qualification);
1274 
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277         int i;
1278 
1279         for (i = 0; i < vmx->nmsrs; ++i)
1280                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281                         return i;
1282         return -1;
1283 }
1284 
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287     struct {
1288         u64 vpid : 16;
1289         u64 rsvd : 48;
1290         u64 gva;
1291     } operand = { vpid, 0, gva };
1292 
1293     asm volatile (__ex(ASM_VMX_INVVPID)
1294                   /* CF==1 or ZF==1 --> rc = -1 */
1295                   "; ja 1f ; ud2 ; 1:"
1296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298 
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301         struct {
1302                 u64 eptp, gpa;
1303         } operand = {eptp, gpa};
1304 
1305         asm volatile (__ex(ASM_VMX_INVEPT)
1306                         /* CF==1 or ZF==1 --> rc = -1 */
1307                         "; ja 1f ; ud2 ; 1:\n"
1308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310 
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313         int i;
1314 
1315         i = __find_msr_index(vmx, msr);
1316         if (i >= 0)
1317                 return &vmx->guest_msrs[i];
1318         return NULL;
1319 }
1320 
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323         u64 phys_addr = __pa(vmcs);
1324         u8 error;
1325 
1326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328                       : "cc", "memory");
1329         if (error)
1330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331                        vmcs, phys_addr);
1332 }
1333 
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336         vmcs_clear(loaded_vmcs->vmcs);
1337         loaded_vmcs->cpu = -1;
1338         loaded_vmcs->launched = 0;
1339 }
1340 
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343         u64 phys_addr = __pa(vmcs);
1344         u8 error;
1345 
1346         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348                         : "cc", "memory");
1349         if (error)
1350                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351                        vmcs, phys_addr);
1352 }
1353 
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356  * This bitmap is used to indicate whether the vmclear
1357  * operation is enabled on all cpus. All disabled by
1358  * default.
1359  */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361 
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366 
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371 
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376 
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379         int cpu = raw_smp_processor_id();
1380         struct loaded_vmcs *v;
1381 
1382         if (!crash_local_vmclear_enabled(cpu))
1383                 return;
1384 
1385         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386                             loaded_vmcss_on_cpu_link)
1387                 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393 
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396         struct loaded_vmcs *loaded_vmcs = arg;
1397         int cpu = raw_smp_processor_id();
1398 
1399         if (loaded_vmcs->cpu != cpu)
1400                 return; /* vcpu migration can race with cpu offline */
1401         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402                 per_cpu(current_vmcs, cpu) = NULL;
1403         crash_disable_local_vmclear(cpu);
1404         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405 
1406         /*
1407          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408          * is before setting loaded_vmcs->vcpu to -1 which is done in
1409          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410          * then adds the vmcs into percpu list before it is deleted.
1411          */
1412         smp_wmb();
1413 
1414         loaded_vmcs_init(loaded_vmcs);
1415         crash_enable_local_vmclear(cpu);
1416 }
1417 
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         int cpu = loaded_vmcs->cpu;
1421 
1422         if (cpu != -1)
1423                 smp_call_function_single(cpu,
1424                          __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426 
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429         if (vpid == 0)
1430                 return;
1431 
1432         if (cpu_has_vmx_invvpid_single())
1433                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435 
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438         if (cpu_has_vmx_invvpid_global())
1439                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441 
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444         if (cpu_has_vmx_invvpid_single())
1445                 vpid_sync_vcpu_single(vpid);
1446         else
1447                 vpid_sync_vcpu_global();
1448 }
1449 
1450 static inline void ept_sync_global(void)
1451 {
1452         if (cpu_has_vmx_invept_global())
1453                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455 
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458         if (enable_ept) {
1459                 if (cpu_has_vmx_invept_context())
1460                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461                 else
1462                         ept_sync_global();
1463         }
1464 }
1465 
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469                          "16-bit accessor invalid for 64-bit field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471                          "16-bit accessor invalid for 64-bit high field");
1472         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473                          "16-bit accessor invalid for 32-bit high field");
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475                          "16-bit accessor invalid for natural width field");
1476 }
1477 
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481                          "32-bit accessor invalid for 16-bit field");
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483                          "32-bit accessor invalid for natural width field");
1484 }
1485 
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489                          "64-bit accessor invalid for 16-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "64-bit accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "64-bit accessor invalid for 32-bit field");
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495                          "64-bit accessor invalid for natural width field");
1496 }
1497 
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501                          "Natural width accessor invalid for 16-bit field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503                          "Natural width accessor invalid for 64-bit field");
1504         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505                          "Natural width accessor invalid for 64-bit high field");
1506         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507                          "Natural width accessor invalid for 32-bit field");
1508 }
1509 
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512         unsigned long value;
1513 
1514         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515                       : "=a"(value) : "d"(field) : "cc");
1516         return value;
1517 }
1518 
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521         vmcs_check16(field);
1522         return __vmcs_readl(field);
1523 }
1524 
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527         vmcs_check32(field);
1528         return __vmcs_readl(field);
1529 }
1530 
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533         vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535         return __vmcs_readl(field);
1536 #else
1537         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540 
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543         vmcs_checkl(field);
1544         return __vmcs_readl(field);
1545 }
1546 
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551         dump_stack();
1552 }
1553 
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556         u8 error;
1557 
1558         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1560         if (unlikely(error))
1561                 vmwrite_error(field, value);
1562 }
1563 
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566         vmcs_check16(field);
1567         __vmcs_writel(field, value);
1568 }
1569 
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572         vmcs_check32(field);
1573         __vmcs_writel(field, value);
1574 }
1575 
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578         vmcs_check64(field);
1579         __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581         asm volatile ("");
1582         __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585 
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588         vmcs_checkl(field);
1589         __vmcs_writel(field, value);
1590 }
1591 
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595                          "vmcs_clear_bits does not support 64-bit fields");
1596         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598 
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602                          "vmcs_set_bits does not support 64-bit fields");
1603         __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605 
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         vmcs_write32(VM_ENTRY_CONTROLS, val);
1609         vmx->vm_entry_controls_shadow = val;
1610 }
1611 
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614         if (vmx->vm_entry_controls_shadow != val)
1615                 vm_entry_controls_init(vmx, val);
1616 }
1617 
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620         return vmx->vm_entry_controls_shadow;
1621 }
1622 
1623 
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628 
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633 
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         vmcs_write32(VM_EXIT_CONTROLS, val);
1637         vmx->vm_exit_controls_shadow = val;
1638 }
1639 
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642         if (vmx->vm_exit_controls_shadow != val)
1643                 vm_exit_controls_init(vmx, val);
1644 }
1645 
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648         return vmx->vm_exit_controls_shadow;
1649 }
1650 
1651 
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656 
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661 
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664         vmx->segment_cache.bitmask = 0;
1665 }
1666 
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668                                        unsigned field)
1669 {
1670         bool ret;
1671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672 
1673         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675                 vmx->segment_cache.bitmask = 0;
1676         }
1677         ret = vmx->segment_cache.bitmask & mask;
1678         vmx->segment_cache.bitmask |= mask;
1679         return ret;
1680 }
1681 
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684         u16 *p = &vmx->segment_cache.seg[seg].selector;
1685 
1686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688         return *p;
1689 }
1690 
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693         ulong *p = &vmx->segment_cache.seg[seg].base;
1694 
1695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697         return *p;
1698 }
1699 
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702         u32 *p = &vmx->segment_cache.seg[seg].limit;
1703 
1704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706         return *p;
1707 }
1708 
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711         u32 *p = &vmx->segment_cache.seg[seg].ar;
1712 
1713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715         return *p;
1716 }
1717 
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720         u32 eb;
1721 
1722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724         if ((vcpu->guest_debug &
1725              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727                 eb |= 1u << BP_VECTOR;
1728         if (to_vmx(vcpu)->rmode.vm86_active)
1729                 eb = ~0;
1730         if (enable_ept)
1731                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732         if (vcpu->fpu_active)
1733                 eb &= ~(1u << NM_VECTOR);
1734 
1735         /* When we are running a nested L2 guest and L1 specified for it a
1736          * certain exception bitmap, we must trap the same exceptions and pass
1737          * them to L1. When running L2, we will only handle the exceptions
1738          * specified above if L1 did not want them.
1739          */
1740         if (is_guest_mode(vcpu))
1741                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742 
1743         vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745 
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747                 unsigned long entry, unsigned long exit)
1748 {
1749         vm_entry_controls_clearbit(vmx, entry);
1750         vm_exit_controls_clearbit(vmx, exit);
1751 }
1752 
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755         unsigned i;
1756         struct msr_autoload *m = &vmx->msr_autoload;
1757 
1758         switch (msr) {
1759         case MSR_EFER:
1760                 if (cpu_has_load_ia32_efer) {
1761                         clear_atomic_switch_msr_special(vmx,
1762                                         VM_ENTRY_LOAD_IA32_EFER,
1763                                         VM_EXIT_LOAD_IA32_EFER);
1764                         return;
1765                 }
1766                 break;
1767         case MSR_CORE_PERF_GLOBAL_CTRL:
1768                 if (cpu_has_load_perf_global_ctrl) {
1769                         clear_atomic_switch_msr_special(vmx,
1770                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772                         return;
1773                 }
1774                 break;
1775         }
1776 
1777         for (i = 0; i < m->nr; ++i)
1778                 if (m->guest[i].index == msr)
1779                         break;
1780 
1781         if (i == m->nr)
1782                 return;
1783         --m->nr;
1784         m->guest[i] = m->guest[m->nr];
1785         m->host[i] = m->host[m->nr];
1786         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789 
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791                 unsigned long entry, unsigned long exit,
1792                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793                 u64 guest_val, u64 host_val)
1794 {
1795         vmcs_write64(guest_val_vmcs, guest_val);
1796         vmcs_write64(host_val_vmcs, host_val);
1797         vm_entry_controls_setbit(vmx, entry);
1798         vm_exit_controls_setbit(vmx, exit);
1799 }
1800 
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802                                   u64 guest_val, u64 host_val)
1803 {
1804         unsigned i;
1805         struct msr_autoload *m = &vmx->msr_autoload;
1806 
1807         switch (msr) {
1808         case MSR_EFER:
1809                 if (cpu_has_load_ia32_efer) {
1810                         add_atomic_switch_msr_special(vmx,
1811                                         VM_ENTRY_LOAD_IA32_EFER,
1812                                         VM_EXIT_LOAD_IA32_EFER,
1813                                         GUEST_IA32_EFER,
1814                                         HOST_IA32_EFER,
1815                                         guest_val, host_val);
1816                         return;
1817                 }
1818                 break;
1819         case MSR_CORE_PERF_GLOBAL_CTRL:
1820                 if (cpu_has_load_perf_global_ctrl) {
1821                         add_atomic_switch_msr_special(vmx,
1822                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1825                                         HOST_IA32_PERF_GLOBAL_CTRL,
1826                                         guest_val, host_val);
1827                         return;
1828                 }
1829                 break;
1830         case MSR_IA32_PEBS_ENABLE:
1831                 /* PEBS needs a quiescent period after being disabled (to write
1832                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1833                  * provide that period, so a CPU could write host's record into
1834                  * guest's memory.
1835                  */
1836                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837         }
1838 
1839         for (i = 0; i < m->nr; ++i)
1840                 if (m->guest[i].index == msr)
1841                         break;
1842 
1843         if (i == NR_AUTOLOAD_MSRS) {
1844                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845                                 "Can't add msr %x\n", msr);
1846                 return;
1847         } else if (i == m->nr) {
1848                 ++m->nr;
1849                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851         }
1852 
1853         m->guest[i].index = msr;
1854         m->guest[i].value = guest_val;
1855         m->host[i].index = msr;
1856         m->host[i].value = host_val;
1857 }
1858 
1859 static void reload_tss(void)
1860 {
1861         /*
1862          * VT restores TR but not its size.  Useless.
1863          */
1864         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865         struct desc_struct *descs;
1866 
1867         descs = (void *)gdt->address;
1868         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869         load_TR_desc();
1870 }
1871 
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874         u64 guest_efer = vmx->vcpu.arch.efer;
1875         u64 ignore_bits = 0;
1876 
1877         if (!enable_ept) {
1878                 /*
1879                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1880                  * host CPUID is more efficient than testing guest CPUID
1881                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1882                  */
1883                 if (boot_cpu_has(X86_FEATURE_SMEP))
1884                         guest_efer |= EFER_NX;
1885                 else if (!(guest_efer & EFER_NX))
1886                         ignore_bits |= EFER_NX;
1887         }
1888 
1889         /*
1890          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891          */
1892         ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894         ignore_bits |= EFER_LMA | EFER_LME;
1895         /* SCE is meaningful only in long mode on Intel */
1896         if (guest_efer & EFER_LMA)
1897                 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899 
1900         clear_atomic_switch_msr(vmx, MSR_EFER);
1901 
1902         /*
1903          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904          * On CPUs that support "load IA32_EFER", always switch EFER
1905          * atomically, since it's faster than switching it manually.
1906          */
1907         if (cpu_has_load_ia32_efer ||
1908             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909                 if (!(guest_efer & EFER_LMA))
1910                         guest_efer &= ~EFER_LME;
1911                 if (guest_efer != host_efer)
1912                         add_atomic_switch_msr(vmx, MSR_EFER,
1913                                               guest_efer, host_efer);
1914                 return false;
1915         } else {
1916                 guest_efer &= ~ignore_bits;
1917                 guest_efer |= host_efer & ignore_bits;
1918 
1919                 vmx->guest_msrs[efer_offset].data = guest_efer;
1920                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921 
1922                 return true;
1923         }
1924 }
1925 
1926 static unsigned long segment_base(u16 selector)
1927 {
1928         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929         struct desc_struct *d;
1930         unsigned long table_base;
1931         unsigned long v;
1932 
1933         if (!(selector & ~3))
1934                 return 0;
1935 
1936         table_base = gdt->address;
1937 
1938         if (selector & 4) {           /* from ldt */
1939                 u16 ldt_selector = kvm_read_ldt();
1940 
1941                 if (!(ldt_selector & ~3))
1942                         return 0;
1943 
1944                 table_base = segment_base(ldt_selector);
1945         }
1946         d = (struct desc_struct *)(table_base + (selector & ~7));
1947         v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952         return v;
1953 }
1954 
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957         u16 tr;
1958         asm("str %0" : "=g"(tr));
1959         return segment_base(tr);
1960 }
1961 
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964         struct vcpu_vmx *vmx = to_vmx(vcpu);
1965         int i;
1966 
1967         if (vmx->host_state.loaded)
1968                 return;
1969 
1970         vmx->host_state.loaded = 1;
1971         /*
1972          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1973          * allow segment selectors with cpl > 0 or ti == 1.
1974          */
1975         vmx->host_state.ldt_sel = kvm_read_ldt();
1976         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977         savesegment(fs, vmx->host_state.fs_sel);
1978         if (!(vmx->host_state.fs_sel & 7)) {
1979                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980                 vmx->host_state.fs_reload_needed = 0;
1981         } else {
1982                 vmcs_write16(HOST_FS_SELECTOR, 0);
1983                 vmx->host_state.fs_reload_needed = 1;
1984         }
1985         savesegment(gs, vmx->host_state.gs_sel);
1986         if (!(vmx->host_state.gs_sel & 7))
1987                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988         else {
1989                 vmcs_write16(HOST_GS_SELECTOR, 0);
1990                 vmx->host_state.gs_ldt_reload_needed = 1;
1991         }
1992 
1993 #ifdef CONFIG_X86_64
1994         savesegment(ds, vmx->host_state.ds_sel);
1995         savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997 
1998 #ifdef CONFIG_X86_64
1999         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005 
2006 #ifdef CONFIG_X86_64
2007         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008         if (is_long_mode(&vmx->vcpu))
2009                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011         if (boot_cpu_has(X86_FEATURE_MPX))
2012                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013         for (i = 0; i < vmx->save_nmsrs; ++i)
2014                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015                                    vmx->guest_msrs[i].data,
2016                                    vmx->guest_msrs[i].mask);
2017 }
2018 
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021         if (!vmx->host_state.loaded)
2022                 return;
2023 
2024         ++vmx->vcpu.stat.host_state_reload;
2025         vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027         if (is_long_mode(&vmx->vcpu))
2028                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.gs_ldt_reload_needed) {
2031                 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033                 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035                 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037         }
2038         if (vmx->host_state.fs_reload_needed)
2039                 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042                 loadsegment(ds, vmx->host_state.ds_sel);
2043                 loadsegment(es, vmx->host_state.es_sel);
2044         }
2045 #endif
2046         reload_tss();
2047 #ifdef CONFIG_X86_64
2048         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050         if (vmx->host_state.msr_host_bndcfgs)
2051                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052         /*
2053          * If the FPU is not active (through the host task or
2054          * the guest vcpu), then restore the cr0.TS bit.
2055          */
2056         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057                 stts();
2058         load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060 
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063         preempt_disable();
2064         __vmx_load_host_state(vmx);
2065         preempt_enable();
2066 }
2067 
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071         struct pi_desc old, new;
2072         unsigned int dest;
2073 
2074         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2076                 !kvm_vcpu_apicv_active(vcpu))
2077                 return;
2078 
2079         do {
2080                 old.control = new.control = pi_desc->control;
2081 
2082                 /*
2083                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2084                  * are two possible cases:
2085                  * 1. After running 'pre_block', context switch
2086                  *    happened. For this case, 'sn' was set in
2087                  *    vmx_vcpu_put(), so we need to clear it here.
2088                  * 2. After running 'pre_block', we were blocked,
2089                  *    and woken up by some other guy. For this case,
2090                  *    we don't need to do anything, 'pi_post_block'
2091                  *    will do everything for us. However, we cannot
2092                  *    check whether it is case #1 or case #2 here
2093                  *    (maybe, not needed), so we also clear sn here,
2094                  *    I think it is not a big deal.
2095                  */
2096                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2097                         if (vcpu->cpu != cpu) {
2098                                 dest = cpu_physical_id(cpu);
2099 
2100                                 if (x2apic_enabled())
2101                                         new.ndst = dest;
2102                                 else
2103                                         new.ndst = (dest << 8) & 0xFF00;
2104                         }
2105 
2106                         /* set 'NV' to 'notification vector' */
2107                         new.nv = POSTED_INTR_VECTOR;
2108                 }
2109 
2110                 /* Allow posting non-urgent interrupts */
2111                 new.sn = 0;
2112         } while (cmpxchg(&pi_desc->control, old.control,
2113                         new.control) != old.control);
2114 }
2115 
2116 /*
2117  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2118  * vcpu mutex is already taken.
2119  */
2120 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2121 {
2122         struct vcpu_vmx *vmx = to_vmx(vcpu);
2123         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2124 
2125         if (!vmm_exclusive)
2126                 kvm_cpu_vmxon(phys_addr);
2127         else if (vmx->loaded_vmcs->cpu != cpu)
2128                 loaded_vmcs_clear(vmx->loaded_vmcs);
2129 
2130         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2131                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2132                 vmcs_load(vmx->loaded_vmcs->vmcs);
2133         }
2134 
2135         if (vmx->loaded_vmcs->cpu != cpu) {
2136                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2137                 unsigned long sysenter_esp;
2138 
2139                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2140                 local_irq_disable();
2141                 crash_disable_local_vmclear(cpu);
2142 
2143                 /*
2144                  * Read loaded_vmcs->cpu should be before fetching
2145                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2146                  * See the comments in __loaded_vmcs_clear().
2147                  */
2148                 smp_rmb();
2149 
2150                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2151                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2152                 crash_enable_local_vmclear(cpu);
2153                 local_irq_enable();
2154 
2155                 /*
2156                  * Linux uses per-cpu TSS and GDT, so set these when switching
2157                  * processors.
2158                  */
2159                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2160                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2161 
2162                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2163                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2164 
2165                 vmx->loaded_vmcs->cpu = cpu;
2166         }
2167 
2168         /* Setup TSC multiplier */
2169         if (kvm_has_tsc_control &&
2170             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2171                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2172                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2173         }
2174 
2175         vmx_vcpu_pi_load(vcpu, cpu);
2176         vmx->host_pkru = read_pkru();
2177 }
2178 
2179 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2180 {
2181         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2182 
2183         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2184                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2185                 !kvm_vcpu_apicv_active(vcpu))
2186                 return;
2187 
2188         /* Set SN when the vCPU is preempted */
2189         if (vcpu->preempted)
2190                 pi_set_sn(pi_desc);
2191 }
2192 
2193 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2194 {
2195         vmx_vcpu_pi_put(vcpu);
2196 
2197         __vmx_load_host_state(to_vmx(vcpu));
2198         if (!vmm_exclusive) {
2199                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2200                 vcpu->cpu = -1;
2201                 kvm_cpu_vmxoff();
2202         }
2203 }
2204 
2205 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2206 {
2207         ulong cr0;
2208 
2209         if (vcpu->fpu_active)
2210                 return;
2211         vcpu->fpu_active = 1;
2212         cr0 = vmcs_readl(GUEST_CR0);
2213         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2214         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2215         vmcs_writel(GUEST_CR0, cr0);
2216         update_exception_bitmap(vcpu);
2217         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2218         if (is_guest_mode(vcpu))
2219                 vcpu->arch.cr0_guest_owned_bits &=
2220                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2221         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2222 }
2223 
2224 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2225 
2226 /*
2227  * Return the cr0 value that a nested guest would read. This is a combination
2228  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2229  * its hypervisor (cr0_read_shadow).
2230  */
2231 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2232 {
2233         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2234                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2235 }
2236 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2237 {
2238         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2239                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2240 }
2241 
2242 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2243 {
2244         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2245          * set this *before* calling this function.
2246          */
2247         vmx_decache_cr0_guest_bits(vcpu);
2248         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2249         update_exception_bitmap(vcpu);
2250         vcpu->arch.cr0_guest_owned_bits = 0;
2251         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2252         if (is_guest_mode(vcpu)) {
2253                 /*
2254                  * L1's specified read shadow might not contain the TS bit,
2255                  * so now that we turned on shadowing of this bit, we need to
2256                  * set this bit of the shadow. Like in nested_vmx_run we need
2257                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2258                  * up-to-date here because we just decached cr0.TS (and we'll
2259                  * only update vmcs12->guest_cr0 on nested exit).
2260                  */
2261                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2262                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2263                         (vcpu->arch.cr0 & X86_CR0_TS);
2264                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2265         } else
2266                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2267 }
2268 
2269 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2270 {
2271         unsigned long rflags, save_rflags;
2272 
2273         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2274                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2275                 rflags = vmcs_readl(GUEST_RFLAGS);
2276                 if (to_vmx(vcpu)->rmode.vm86_active) {
2277                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2278                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2279                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2280                 }
2281                 to_vmx(vcpu)->rflags = rflags;
2282         }
2283         return to_vmx(vcpu)->rflags;
2284 }
2285 
2286 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2287 {
2288         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2289         to_vmx(vcpu)->rflags = rflags;
2290         if (to_vmx(vcpu)->rmode.vm86_active) {
2291                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2292                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2293         }
2294         vmcs_writel(GUEST_RFLAGS, rflags);
2295 }
2296 
2297 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2298 {
2299         return to_vmx(vcpu)->guest_pkru;
2300 }
2301 
2302 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2303 {
2304         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2305         int ret = 0;
2306 
2307         if (interruptibility & GUEST_INTR_STATE_STI)
2308                 ret |= KVM_X86_SHADOW_INT_STI;
2309         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2310                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2311 
2312         return ret;
2313 }
2314 
2315 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2316 {
2317         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2318         u32 interruptibility = interruptibility_old;
2319 
2320         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2321 
2322         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2323                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2324         else if (mask & KVM_X86_SHADOW_INT_STI)
2325                 interruptibility |= GUEST_INTR_STATE_STI;
2326 
2327         if ((interruptibility != interruptibility_old))
2328                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2329 }
2330 
2331 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2332 {
2333         unsigned long rip;
2334 
2335         rip = kvm_rip_read(vcpu);
2336         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2337         kvm_rip_write(vcpu, rip);
2338 
2339         /* skipping an emulated instruction also counts */
2340         vmx_set_interrupt_shadow(vcpu, 0);
2341 }
2342 
2343 /*
2344  * KVM wants to inject page-faults which it got to the guest. This function
2345  * checks whether in a nested guest, we need to inject them to L1 or L2.
2346  */
2347 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2348 {
2349         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2350 
2351         if (!(vmcs12->exception_bitmap & (1u << nr)))
2352                 return 0;
2353 
2354         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2355                           vmcs_read32(VM_EXIT_INTR_INFO),
2356                           vmcs_readl(EXIT_QUALIFICATION));
2357         return 1;
2358 }
2359 
2360 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2361                                 bool has_error_code, u32 error_code,
2362                                 bool reinject)
2363 {
2364         struct vcpu_vmx *vmx = to_vmx(vcpu);
2365         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2366 
2367         if (!reinject && is_guest_mode(vcpu) &&
2368             nested_vmx_check_exception(vcpu, nr))
2369                 return;
2370 
2371         if (has_error_code) {
2372                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2373                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2374         }
2375 
2376         if (vmx->rmode.vm86_active) {
2377                 int inc_eip = 0;
2378                 if (kvm_exception_is_soft(nr))
2379                         inc_eip = vcpu->arch.event_exit_inst_len;
2380                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2381                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2382                 return;
2383         }
2384 
2385         if (kvm_exception_is_soft(nr)) {
2386                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2387                              vmx->vcpu.arch.event_exit_inst_len);
2388                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2389         } else
2390                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2391 
2392         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2393 }
2394 
2395 static bool vmx_rdtscp_supported(void)
2396 {
2397         return cpu_has_vmx_rdtscp();
2398 }
2399 
2400 static bool vmx_invpcid_supported(void)
2401 {
2402         return cpu_has_vmx_invpcid() && enable_ept;
2403 }
2404 
2405 /*
2406  * Swap MSR entry in host/guest MSR entry array.
2407  */
2408 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2409 {
2410         struct shared_msr_entry tmp;
2411 
2412         tmp = vmx->guest_msrs[to];
2413         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2414         vmx->guest_msrs[from] = tmp;
2415 }
2416 
2417 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2418 {
2419         unsigned long *msr_bitmap;
2420 
2421         if (is_guest_mode(vcpu))
2422                 msr_bitmap = vmx_msr_bitmap_nested;
2423         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2424                 if (is_long_mode(vcpu))
2425                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2426                 else
2427                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2428         } else {
2429                 if (is_long_mode(vcpu))
2430                         msr_bitmap = vmx_msr_bitmap_longmode;
2431                 else
2432                         msr_bitmap = vmx_msr_bitmap_legacy;
2433         }
2434 
2435         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2436 }
2437 
2438 /*
2439  * Set up the vmcs to automatically save and restore system
2440  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2441  * mode, as fiddling with msrs is very expensive.
2442  */
2443 static void setup_msrs(struct vcpu_vmx *vmx)
2444 {
2445         int save_nmsrs, index;
2446 
2447         save_nmsrs = 0;
2448 #ifdef CONFIG_X86_64
2449         if (is_long_mode(&vmx->vcpu)) {
2450                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2451                 if (index >= 0)
2452                         move_msr_up(vmx, index, save_nmsrs++);
2453                 index = __find_msr_index(vmx, MSR_LSTAR);
2454                 if (index >= 0)
2455                         move_msr_up(vmx, index, save_nmsrs++);
2456                 index = __find_msr_index(vmx, MSR_CSTAR);
2457                 if (index >= 0)
2458                         move_msr_up(vmx, index, save_nmsrs++);
2459                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2460                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2461                         move_msr_up(vmx, index, save_nmsrs++);
2462                 /*
2463                  * MSR_STAR is only needed on long mode guests, and only
2464                  * if efer.sce is enabled.
2465                  */
2466                 index = __find_msr_index(vmx, MSR_STAR);
2467                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2468                         move_msr_up(vmx, index, save_nmsrs++);
2469         }
2470 #endif
2471         index = __find_msr_index(vmx, MSR_EFER);
2472         if (index >= 0 && update_transition_efer(vmx, index))
2473                 move_msr_up(vmx, index, save_nmsrs++);
2474 
2475         vmx->save_nmsrs = save_nmsrs;
2476 
2477         if (cpu_has_vmx_msr_bitmap())
2478                 vmx_set_msr_bitmap(&vmx->vcpu);
2479 }
2480 
2481 /*
2482  * reads and returns guest's timestamp counter "register"
2483  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2484  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2485  */
2486 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2487 {
2488         u64 host_tsc, tsc_offset;
2489 
2490         host_tsc = rdtsc();
2491         tsc_offset = vmcs_read64(TSC_OFFSET);
2492         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2493 }
2494 
2495 /*
2496  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2497  * counter, even if a nested guest (L2) is currently running.
2498  */
2499 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2500 {
2501         u64 tsc_offset;
2502 
2503         tsc_offset = is_guest_mode(vcpu) ?
2504                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2505                 vmcs_read64(TSC_OFFSET);
2506         return host_tsc + tsc_offset;
2507 }
2508 
2509 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2510 {
2511         return vmcs_read64(TSC_OFFSET);
2512 }
2513 
2514 /*
2515  * writes 'offset' into guest's timestamp counter offset register
2516  */
2517 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2518 {
2519         if (is_guest_mode(vcpu)) {
2520                 /*
2521                  * We're here if L1 chose not to trap WRMSR to TSC. According
2522                  * to the spec, this should set L1's TSC; The offset that L1
2523                  * set for L2 remains unchanged, and still needs to be added
2524                  * to the newly set TSC to get L2's TSC.
2525                  */
2526                 struct vmcs12 *vmcs12;
2527                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2528                 /* recalculate vmcs02.TSC_OFFSET: */
2529                 vmcs12 = get_vmcs12(vcpu);
2530                 vmcs_write64(TSC_OFFSET, offset +
2531                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2532                          vmcs12->tsc_offset : 0));
2533         } else {
2534                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2535                                            vmcs_read64(TSC_OFFSET), offset);
2536                 vmcs_write64(TSC_OFFSET, offset);
2537         }
2538 }
2539 
2540 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2541 {
2542         u64 offset = vmcs_read64(TSC_OFFSET);
2543 
2544         vmcs_write64(TSC_OFFSET, offset + adjustment);
2545         if (is_guest_mode(vcpu)) {
2546                 /* Even when running L2, the adjustment needs to apply to L1 */
2547                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2548         } else
2549                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2550                                            offset + adjustment);
2551 }
2552 
2553 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2554 {
2555         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2556         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2557 }
2558 
2559 /*
2560  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2561  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2562  * all guests if the "nested" module option is off, and can also be disabled
2563  * for a single guest by disabling its VMX cpuid bit.
2564  */
2565 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2566 {
2567         return nested && guest_cpuid_has_vmx(vcpu);
2568 }
2569 
2570 /*
2571  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2572  * returned for the various VMX controls MSRs when nested VMX is enabled.
2573  * The same values should also be used to verify that vmcs12 control fields are
2574  * valid during nested entry from L1 to L2.
2575  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2576  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2577  * bit in the high half is on if the corresponding bit in the control field
2578  * may be on. See also vmx_control_verify().
2579  */
2580 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2581 {
2582         /*
2583          * Note that as a general rule, the high half of the MSRs (bits in
2584          * the control fields which may be 1) should be initialized by the
2585          * intersection of the underlying hardware's MSR (i.e., features which
2586          * can be supported) and the list of features we want to expose -
2587          * because they are known to be properly supported in our code.
2588          * Also, usually, the low half of the MSRs (bits which must be 1) can
2589          * be set to 0, meaning that L1 may turn off any of these bits. The
2590          * reason is that if one of these bits is necessary, it will appear
2591          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2592          * fields of vmcs01 and vmcs02, will turn these bits off - and
2593          * nested_vmx_exit_handled() will not pass related exits to L1.
2594          * These rules have exceptions below.
2595          */
2596 
2597         /* pin-based controls */
2598         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2599                 vmx->nested.nested_vmx_pinbased_ctls_low,
2600                 vmx->nested.nested_vmx_pinbased_ctls_high);
2601         vmx->nested.nested_vmx_pinbased_ctls_low |=
2602                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2603         vmx->nested.nested_vmx_pinbased_ctls_high &=
2604                 PIN_BASED_EXT_INTR_MASK |
2605                 PIN_BASED_NMI_EXITING |
2606                 PIN_BASED_VIRTUAL_NMIS;
2607         vmx->nested.nested_vmx_pinbased_ctls_high |=
2608                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2609                 PIN_BASED_VMX_PREEMPTION_TIMER;
2610         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2611                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2612                         PIN_BASED_POSTED_INTR;
2613 
2614         /* exit controls */
2615         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2616                 vmx->nested.nested_vmx_exit_ctls_low,
2617                 vmx->nested.nested_vmx_exit_ctls_high);
2618         vmx->nested.nested_vmx_exit_ctls_low =
2619                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2620 
2621         vmx->nested.nested_vmx_exit_ctls_high &=
2622 #ifdef CONFIG_X86_64
2623                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2624 #endif
2625                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2626         vmx->nested.nested_vmx_exit_ctls_high |=
2627                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2628                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2629                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2630 
2631         if (kvm_mpx_supported())
2632                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2633 
2634         /* We support free control of debug control saving. */
2635         vmx->nested.nested_vmx_true_exit_ctls_low =
2636                 vmx->nested.nested_vmx_exit_ctls_low &
2637                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2638 
2639         /* entry controls */
2640         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2641                 vmx->nested.nested_vmx_entry_ctls_low,
2642                 vmx->nested.nested_vmx_entry_ctls_high);
2643         vmx->nested.nested_vmx_entry_ctls_low =
2644                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2645         vmx->nested.nested_vmx_entry_ctls_high &=
2646 #ifdef CONFIG_X86_64
2647                 VM_ENTRY_IA32E_MODE |
2648 #endif
2649                 VM_ENTRY_LOAD_IA32_PAT;
2650         vmx->nested.nested_vmx_entry_ctls_high |=
2651                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2652         if (kvm_mpx_supported())
2653                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2654 
2655         /* We support free control of debug control loading. */
2656         vmx->nested.nested_vmx_true_entry_ctls_low =
2657                 vmx->nested.nested_vmx_entry_ctls_low &
2658                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2659 
2660         /* cpu-based controls */
2661         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2662                 vmx->nested.nested_vmx_procbased_ctls_low,
2663                 vmx->nested.nested_vmx_procbased_ctls_high);
2664         vmx->nested.nested_vmx_procbased_ctls_low =
2665                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2666         vmx->nested.nested_vmx_procbased_ctls_high &=
2667                 CPU_BASED_VIRTUAL_INTR_PENDING |
2668                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2669                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2670                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2671                 CPU_BASED_CR3_STORE_EXITING |
2672 #ifdef CONFIG_X86_64
2673                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2674 #endif
2675                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2676                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2677                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2678                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2679                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2680         /*
2681          * We can allow some features even when not supported by the
2682          * hardware. For example, L1 can specify an MSR bitmap - and we
2683          * can use it to avoid exits to L1 - even when L0 runs L2
2684          * without MSR bitmaps.
2685          */
2686         vmx->nested.nested_vmx_procbased_ctls_high |=
2687                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2688                 CPU_BASED_USE_MSR_BITMAPS;
2689 
2690         /* We support free control of CR3 access interception. */
2691         vmx->nested.nested_vmx_true_procbased_ctls_low =
2692                 vmx->nested.nested_vmx_procbased_ctls_low &
2693                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2694 
2695         /* secondary cpu-based controls */
2696         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2697                 vmx->nested.nested_vmx_secondary_ctls_low,
2698                 vmx->nested.nested_vmx_secondary_ctls_high);
2699         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2700         vmx->nested.nested_vmx_secondary_ctls_high &=
2701                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2702                 SECONDARY_EXEC_RDTSCP |
2703                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2704                 SECONDARY_EXEC_ENABLE_VPID |
2705                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2706                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2707                 SECONDARY_EXEC_WBINVD_EXITING |
2708                 SECONDARY_EXEC_XSAVES |
2709                 SECONDARY_EXEC_PCOMMIT;
2710 
2711         if (enable_ept) {
2712                 /* nested EPT: emulate EPT also to L1 */
2713                 vmx->nested.nested_vmx_secondary_ctls_high |=
2714                         SECONDARY_EXEC_ENABLE_EPT;
2715                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2716                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2717                          VMX_EPT_INVEPT_BIT;
2718                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2719                 /*
2720                  * For nested guests, we don't do anything specific
2721                  * for single context invalidation. Hence, only advertise
2722                  * support for global context invalidation.
2723                  */
2724                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2725         } else
2726                 vmx->nested.nested_vmx_ept_caps = 0;
2727 
2728         /*
2729          * Old versions of KVM use the single-context version without
2730          * checking for support, so declare that it is supported even
2731          * though it is treated as global context.  The alternative is
2732          * not failing the single-context invvpid, and it is worse.
2733          */
2734         if (enable_vpid)
2735                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2736                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2737                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2738         else
2739                 vmx->nested.nested_vmx_vpid_caps = 0;
2740 
2741         if (enable_unrestricted_guest)
2742                 vmx->nested.nested_vmx_secondary_ctls_high |=
2743                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2744 
2745         /* miscellaneous data */
2746         rdmsr(MSR_IA32_VMX_MISC,
2747                 vmx->nested.nested_vmx_misc_low,
2748                 vmx->nested.nested_vmx_misc_high);
2749         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2750         vmx->nested.nested_vmx_misc_low |=
2751                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2752                 VMX_MISC_ACTIVITY_HLT;
2753         vmx->nested.nested_vmx_misc_high = 0;
2754 }
2755 
2756 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2757 {
2758         /*
2759          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2760          */
2761         return ((control & high) | low) == control;
2762 }
2763 
2764 static inline u64 vmx_control_msr(u32 low, u32 high)
2765 {
2766         return low | ((u64)high << 32);
2767 }
2768 
2769 /* Returns 0 on success, non-0 otherwise. */
2770 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2771 {
2772         struct vcpu_vmx *vmx = to_vmx(vcpu);
2773 
2774         switch (msr_index) {
2775         case MSR_IA32_VMX_BASIC:
2776                 /*
2777                  * This MSR reports some information about VMX support. We
2778                  * should return information about the VMX we emulate for the
2779                  * guest, and the VMCS structure we give it - not about the
2780                  * VMX support of the underlying hardware.
2781                  */
2782                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2783                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2784                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2785                 break;
2786         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2787         case MSR_IA32_VMX_PINBASED_CTLS:
2788                 *pdata = vmx_control_msr(
2789                         vmx->nested.nested_vmx_pinbased_ctls_low,
2790                         vmx->nested.nested_vmx_pinbased_ctls_high);
2791                 break;
2792         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2793                 *pdata = vmx_control_msr(
2794                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2795                         vmx->nested.nested_vmx_procbased_ctls_high);
2796                 break;
2797         case MSR_IA32_VMX_PROCBASED_CTLS:
2798                 *pdata = vmx_control_msr(
2799                         vmx->nested.nested_vmx_procbased_ctls_low,
2800                         vmx->nested.nested_vmx_procbased_ctls_high);
2801                 break;
2802         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2803                 *pdata = vmx_control_msr(
2804                         vmx->nested.nested_vmx_true_exit_ctls_low,
2805                         vmx->nested.nested_vmx_exit_ctls_high);
2806                 break;
2807         case MSR_IA32_VMX_EXIT_CTLS:
2808                 *pdata = vmx_control_msr(
2809                         vmx->nested.nested_vmx_exit_ctls_low,
2810                         vmx->nested.nested_vmx_exit_ctls_high);
2811                 break;
2812         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2813                 *pdata = vmx_control_msr(
2814                         vmx->nested.nested_vmx_true_entry_ctls_low,
2815                         vmx->nested.nested_vmx_entry_ctls_high);
2816                 break;
2817         case MSR_IA32_VMX_ENTRY_CTLS:
2818                 *pdata = vmx_control_msr(
2819                         vmx->nested.nested_vmx_entry_ctls_low,
2820                         vmx->nested.nested_vmx_entry_ctls_high);
2821                 break;
2822         case MSR_IA32_VMX_MISC:
2823                 *pdata = vmx_control_msr(
2824                         vmx->nested.nested_vmx_misc_low,
2825                         vmx->nested.nested_vmx_misc_high);
2826                 break;
2827         /*
2828          * These MSRs specify bits which the guest must keep fixed (on or off)
2829          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2830          * We picked the standard core2 setting.
2831          */
2832 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2833 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2834         case MSR_IA32_VMX_CR0_FIXED0:
2835                 *pdata = VMXON_CR0_ALWAYSON;
2836                 break;
2837         case MSR_IA32_VMX_CR0_FIXED1:
2838                 *pdata = -1ULL;
2839                 break;
2840         case MSR_IA32_VMX_CR4_FIXED0:
2841                 *pdata = VMXON_CR4_ALWAYSON;
2842                 break;
2843         case MSR_IA32_VMX_CR4_FIXED1:
2844                 *pdata = -1ULL;
2845                 break;
2846         case MSR_IA32_VMX_VMCS_ENUM:
2847                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2848                 break;
2849         case MSR_IA32_VMX_PROCBASED_CTLS2:
2850                 *pdata = vmx_control_msr(
2851                         vmx->nested.nested_vmx_secondary_ctls_low,
2852                         vmx->nested.nested_vmx_secondary_ctls_high);
2853                 break;
2854         case MSR_IA32_VMX_EPT_VPID_CAP:
2855                 /* Currently, no nested vpid support */
2856                 *pdata = vmx->nested.nested_vmx_ept_caps |
2857                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2858                 break;
2859         default:
2860                 return 1;
2861         }
2862 
2863         return 0;
2864 }
2865 
2866 /*
2867  * Reads an msr value (of 'msr_index') into 'pdata'.
2868  * Returns 0 on success, non-0 otherwise.
2869  * Assumes vcpu_load() was already called.
2870  */
2871 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2872 {
2873         struct shared_msr_entry *msr;
2874 
2875         switch (msr_info->index) {
2876 #ifdef CONFIG_X86_64
2877         case MSR_FS_BASE:
2878                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2879                 break;
2880         case MSR_GS_BASE:
2881                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2882                 break;
2883         case MSR_KERNEL_GS_BASE:
2884                 vmx_load_host_state(to_vmx(vcpu));
2885                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2886                 break;
2887 #endif
2888         case MSR_EFER:
2889                 return kvm_get_msr_common(vcpu, msr_info);
2890         case MSR_IA32_TSC:
2891                 msr_info->data = guest_read_tsc(vcpu);
2892                 break;
2893         case MSR_IA32_SYSENTER_CS:
2894                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2895                 break;
2896         case MSR_IA32_SYSENTER_EIP:
2897                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2898                 break;
2899         case MSR_IA32_SYSENTER_ESP:
2900                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2901                 break;
2902         case MSR_IA32_BNDCFGS:
2903                 if (!kvm_mpx_supported())
2904                         return 1;
2905                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2906                 break;
2907         case MSR_IA32_FEATURE_CONTROL:
2908                 if (!nested_vmx_allowed(vcpu))
2909                         return 1;
2910                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2911                 break;
2912         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2913                 if (!nested_vmx_allowed(vcpu))
2914                         return 1;
2915                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2916         case MSR_IA32_XSS:
2917                 if (!vmx_xsaves_supported())
2918                         return 1;
2919                 msr_info->data = vcpu->arch.ia32_xss;
2920                 break;
2921         case MSR_TSC_AUX:
2922                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2923                         return 1;
2924                 /* Otherwise falls through */
2925         default:
2926                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2927                 if (msr) {
2928                         msr_info->data = msr->data;
2929                         break;
2930                 }
2931                 return kvm_get_msr_common(vcpu, msr_info);
2932         }
2933 
2934         return 0;
2935 }
2936 
2937 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2938 
2939 /*
2940  * Writes msr value into into the appropriate "register".
2941  * Returns 0 on success, non-0 otherwise.
2942  * Assumes vcpu_load() was already called.
2943  */
2944 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2945 {
2946         struct vcpu_vmx *vmx = to_vmx(vcpu);
2947         struct shared_msr_entry *msr;
2948         int ret = 0;
2949         u32 msr_index = msr_info->index;
2950         u64 data = msr_info->data;
2951 
2952         switch (msr_index) {
2953         case MSR_EFER:
2954                 ret = kvm_set_msr_common(vcpu, msr_info);
2955                 break;
2956 #ifdef CONFIG_X86_64
2957         case MSR_FS_BASE:
2958                 vmx_segment_cache_clear(vmx);
2959                 vmcs_writel(GUEST_FS_BASE, data);
2960                 break;
2961         case MSR_GS_BASE:
2962                 vmx_segment_cache_clear(vmx);
2963                 vmcs_writel(GUEST_GS_BASE, data);
2964                 break;
2965         case MSR_KERNEL_GS_BASE:
2966                 vmx_load_host_state(vmx);
2967                 vmx->msr_guest_kernel_gs_base = data;
2968                 break;
2969 #endif
2970         case MSR_IA32_SYSENTER_CS:
2971                 vmcs_write32(GUEST_SYSENTER_CS, data);
2972                 break;
2973         case MSR_IA32_SYSENTER_EIP:
2974                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2975                 break;
2976         case MSR_IA32_SYSENTER_ESP:
2977                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2978                 break;
2979         case MSR_IA32_BNDCFGS:
2980                 if (!kvm_mpx_supported())
2981                         return 1;
2982                 vmcs_write64(GUEST_BNDCFGS, data);
2983                 break;
2984         case MSR_IA32_TSC:
2985                 kvm_write_tsc(vcpu, msr_info);
2986                 break;
2987         case MSR_IA32_CR_PAT:
2988                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2989                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2990                                 return 1;
2991                         vmcs_write64(GUEST_IA32_PAT, data);
2992                         vcpu->arch.pat = data;
2993                         break;
2994                 }
2995                 ret = kvm_set_msr_common(vcpu, msr_info);
2996                 break;
2997         case MSR_IA32_TSC_ADJUST:
2998                 ret = kvm_set_msr_common(vcpu, msr_info);
2999                 break;
3000         case MSR_IA32_FEATURE_CONTROL:
3001                 if (!nested_vmx_allowed(vcpu) ||
3002                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
3003                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3004                         return 1;
3005                 vmx->nested.msr_ia32_feature_control = data;
3006                 if (msr_info->host_initiated && data == 0)
3007                         vmx_leave_nested(vcpu);
3008                 break;
3009         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3010                 return 1; /* they are read-only */
3011         case MSR_IA32_XSS:
3012                 if (!vmx_xsaves_supported())
3013                         return 1;
3014                 /*
3015                  * The only supported bit as of Skylake is bit 8, but
3016                  * it is not supported on KVM.
3017                  */
3018                 if (data != 0)
3019                         return 1;
3020                 vcpu->arch.ia32_xss = data;
3021                 if (vcpu->arch.ia32_xss != host_xss)
3022                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3023                                 vcpu->arch.ia32_xss, host_xss);
3024                 else
3025                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3026                 break;
3027         case MSR_TSC_AUX:
3028                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3029                         return 1;
3030                 /* Check reserved bit, higher 32 bits should be zero */
3031                 if ((data >> 32) != 0)
3032                         return 1;
3033                 /* Otherwise falls through */
3034         default:
3035                 msr = find_msr_entry(vmx, msr_index);
3036                 if (msr) {
3037                         u64 old_msr_data = msr->data;
3038                         msr->data = data;
3039                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3040                                 preempt_disable();
3041                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3042                                                          msr->mask);
3043                                 preempt_enable();
3044                                 if (ret)
3045                                         msr->data = old_msr_data;
3046                         }
3047                         break;
3048                 }
3049                 ret = kvm_set_msr_common(vcpu, msr_info);
3050         }
3051 
3052         return ret;
3053 }
3054 
3055 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3056 {
3057         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3058         switch (reg) {
3059         case VCPU_REGS_RSP:
3060                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3061                 break;
3062         case VCPU_REGS_RIP:
3063                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3064                 break;
3065         case VCPU_EXREG_PDPTR:
3066                 if (enable_ept)
3067                         ept_save_pdptrs(vcpu);
3068                 break;
3069         default:
3070                 break;
3071         }
3072 }
3073 
3074 static __init int cpu_has_kvm_support(void)
3075 {
3076         return cpu_has_vmx();
3077 }
3078 
3079 static __init int vmx_disabled_by_bios(void)
3080 {
3081         u64 msr;
3082 
3083         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3084         if (msr & FEATURE_CONTROL_LOCKED) {
3085                 /* launched w/ TXT and VMX disabled */
3086                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3087                         && tboot_enabled())
3088                         return 1;
3089                 /* launched w/o TXT and VMX only enabled w/ TXT */
3090                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3091                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3092                         && !tboot_enabled()) {
3093                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3094                                 "activate TXT before enabling KVM\n");
3095                         return 1;
3096                 }
3097                 /* launched w/o TXT and VMX disabled */
3098                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3099                         && !tboot_enabled())
3100                         return 1;
3101         }
3102 
3103         return 0;
3104 }
3105 
3106 static void kvm_cpu_vmxon(u64 addr)
3107 {
3108         intel_pt_handle_vmx(1);
3109 
3110         asm volatile (ASM_VMX_VMXON_RAX
3111                         : : "a"(&addr), "m"(addr)
3112                         : "memory", "cc");
3113 }
3114 
3115 static int hardware_enable(void)
3116 {
3117         int cpu = raw_smp_processor_id();
3118         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3119         u64 old, test_bits;
3120 
3121         if (cr4_read_shadow() & X86_CR4_VMXE)
3122                 return -EBUSY;
3123 
3124         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3125         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3126         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3127 
3128         /*
3129          * Now we can enable the vmclear operation in kdump
3130          * since the loaded_vmcss_on_cpu list on this cpu
3131          * has been initialized.
3132          *
3133          * Though the cpu is not in VMX operation now, there
3134          * is no problem to enable the vmclear operation
3135          * for the loaded_vmcss_on_cpu list is empty!
3136          */
3137         crash_enable_local_vmclear(cpu);
3138 
3139         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3140 
3141         test_bits = FEATURE_CONTROL_LOCKED;
3142         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3143         if (tboot_enabled())
3144                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3145 
3146         if ((old & test_bits) != test_bits) {
3147                 /* enable and lock */
3148                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3149         }
3150         cr4_set_bits(X86_CR4_VMXE);
3151 
3152         if (vmm_exclusive) {
3153                 kvm_cpu_vmxon(phys_addr);
3154                 ept_sync_global();
3155         }
3156 
3157         native_store_gdt(this_cpu_ptr(&host_gdt));
3158 
3159         return 0;
3160 }
3161 
3162 static void vmclear_local_loaded_vmcss(void)
3163 {
3164         int cpu = raw_smp_processor_id();
3165         struct loaded_vmcs *v, *n;
3166 
3167         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3168                                  loaded_vmcss_on_cpu_link)
3169                 __loaded_vmcs_clear(v);
3170 }
3171 
3172 
3173 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3174  * tricks.
3175  */
3176 static void kvm_cpu_vmxoff(void)
3177 {
3178         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3179 
3180         intel_pt_handle_vmx(0);
3181 }
3182 
3183 static void hardware_disable(void)
3184 {
3185         if (vmm_exclusive) {
3186                 vmclear_local_loaded_vmcss();
3187                 kvm_cpu_vmxoff();
3188         }
3189         cr4_clear_bits(X86_CR4_VMXE);
3190 }
3191 
3192 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3193                                       u32 msr, u32 *result)
3194 {
3195         u32 vmx_msr_low, vmx_msr_high;
3196         u32 ctl = ctl_min | ctl_opt;
3197 
3198         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3199 
3200         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3201         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3202 
3203         /* Ensure minimum (required) set of control bits are supported. */
3204         if (ctl_min & ~ctl)
3205                 return -EIO;
3206 
3207         *result = ctl;
3208         return 0;
3209 }
3210 
3211 static __init bool allow_1_setting(u32 msr, u32 ctl)
3212 {
3213         u32 vmx_msr_low, vmx_msr_high;
3214 
3215         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3216         return vmx_msr_high & ctl;
3217 }
3218 
3219 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3220 {
3221         u32 vmx_msr_low, vmx_msr_high;
3222         u32 min, opt, min2, opt2;
3223         u32 _pin_based_exec_control = 0;
3224         u32 _cpu_based_exec_control = 0;
3225         u32 _cpu_based_2nd_exec_control = 0;
3226         u32 _vmexit_control = 0;
3227         u32 _vmentry_control = 0;
3228 
3229         min = CPU_BASED_HLT_EXITING |
3230 #ifdef CONFIG_X86_64
3231               CPU_BASED_CR8_LOAD_EXITING |
3232               CPU_BASED_CR8_STORE_EXITING |
3233 #endif
3234               CPU_BASED_CR3_LOAD_EXITING |
3235               CPU_BASED_CR3_STORE_EXITING |
3236               CPU_BASED_USE_IO_BITMAPS |
3237               CPU_BASED_MOV_DR_EXITING |
3238               CPU_BASED_USE_TSC_OFFSETING |
3239               CPU_BASED_MWAIT_EXITING |
3240               CPU_BASED_MONITOR_EXITING |
3241               CPU_BASED_INVLPG_EXITING |
3242               CPU_BASED_RDPMC_EXITING;
3243 
3244         opt = CPU_BASED_TPR_SHADOW |
3245               CPU_BASED_USE_MSR_BITMAPS |
3246               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3247         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3248                                 &_cpu_based_exec_control) < 0)
3249                 return -EIO;
3250 #ifdef CONFIG_X86_64
3251         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3252                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3253                                            ~CPU_BASED_CR8_STORE_EXITING;
3254 #endif
3255         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3256                 min2 = 0;
3257                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3258                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3259                         SECONDARY_EXEC_WBINVD_EXITING |
3260                         SECONDARY_EXEC_ENABLE_VPID |
3261                         SECONDARY_EXEC_ENABLE_EPT |
3262                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3263                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3264                         SECONDARY_EXEC_RDTSCP |
3265                         SECONDARY_EXEC_ENABLE_INVPCID |
3266                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3267                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3268                         SECONDARY_EXEC_SHADOW_VMCS |
3269                         SECONDARY_EXEC_XSAVES |
3270                         SECONDARY_EXEC_ENABLE_PML |
3271                         SECONDARY_EXEC_PCOMMIT |
3272                         SECONDARY_EXEC_TSC_SCALING;
3273                 if (adjust_vmx_controls(min2, opt2,
3274                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3275                                         &_cpu_based_2nd_exec_control) < 0)
3276                         return -EIO;
3277         }
3278 #ifndef CONFIG_X86_64
3279         if (!(_cpu_based_2nd_exec_control &
3280                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3281                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3282 #endif
3283 
3284         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3285                 _cpu_based_2nd_exec_control &= ~(
3286                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3287                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3288                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3289 
3290         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3291                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3292                    enabled */
3293                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3294                                              CPU_BASED_CR3_STORE_EXITING |
3295                                              CPU_BASED_INVLPG_EXITING);
3296                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3297                       vmx_capability.ept, vmx_capability.vpid);
3298         }
3299 
3300         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3301 #ifdef CONFIG_X86_64
3302         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3303 #endif
3304         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3305                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3306         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3307                                 &_vmexit_control) < 0)
3308                 return -EIO;
3309 
3310         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3311         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3312         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3313                                 &_pin_based_exec_control) < 0)
3314                 return -EIO;
3315 
3316         if (!(_cpu_based_2nd_exec_control &
3317                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3318                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3319                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3320 
3321         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3322         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3323         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3324                                 &_vmentry_control) < 0)
3325                 return -EIO;
3326 
3327         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3328 
3329         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3330         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3331                 return -EIO;
3332 
3333 #ifdef CONFIG_X86_64
3334         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3335         if (vmx_msr_high & (1u<<16))
3336                 return -EIO;
3337 #endif
3338 
3339         /* Require Write-Back (WB) memory type for VMCS accesses. */
3340         if (((vmx_msr_high >> 18) & 15) != 6)
3341                 return -EIO;
3342 
3343         vmcs_conf->size = vmx_msr_high & 0x1fff;
3344         vmcs_conf->order = get_order(vmcs_config.size);
3345         vmcs_conf->revision_id = vmx_msr_low;
3346 
3347         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3348         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3349         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3350         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3351         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3352 
3353         cpu_has_load_ia32_efer =
3354                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3355                                 VM_ENTRY_LOAD_IA32_EFER)
3356                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3357                                    VM_EXIT_LOAD_IA32_EFER);
3358 
3359         cpu_has_load_perf_global_ctrl =
3360                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3361                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3362                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3363                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3364 
3365         /*
3366          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3367          * but due to arrata below it can't be used. Workaround is to use
3368          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3369          *
3370          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3371          *
3372          * AAK155             (model 26)
3373          * AAP115             (model 30)
3374          * AAT100             (model 37)
3375          * BC86,AAY89,BD102   (model 44)
3376          * BA97               (model 46)
3377          *
3378          */
3379         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3380                 switch (boot_cpu_data.x86_model) {
3381                 case 26:
3382                 case 30:
3383                 case 37:
3384                 case 44:
3385                 case 46:
3386                         cpu_has_load_perf_global_ctrl = false;
3387                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3388                                         "does not work properly. Using workaround\n");
3389                         break;
3390                 default:
3391                         break;
3392                 }
3393         }
3394 
3395         if (cpu_has_xsaves)
3396                 rdmsrl(MSR_IA32_XSS, host_xss);
3397 
3398         return 0;
3399 }
3400 
3401 static struct vmcs *alloc_vmcs_cpu(int cpu)
3402 {
3403         int node = cpu_to_node(cpu);
3404         struct page *pages;
3405         struct vmcs *vmcs;
3406 
3407         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3408         if (!pages)
3409                 return NULL;
3410         vmcs = page_address(pages);
3411         memset(vmcs, 0, vmcs_config.size);
3412         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3413         return vmcs;
3414 }
3415 
3416 static struct vmcs *alloc_vmcs(void)
3417 {
3418         return alloc_vmcs_cpu(raw_smp_processor_id());
3419 }
3420 
3421 static void free_vmcs(struct vmcs *vmcs)
3422 {
3423         free_pages((unsigned long)vmcs, vmcs_config.order);
3424 }
3425 
3426 /*
3427  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3428  */
3429 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3430 {
3431         if (!loaded_vmcs->vmcs)
3432                 return;
3433         loaded_vmcs_clear(loaded_vmcs);
3434         free_vmcs(loaded_vmcs->vmcs);
3435         loaded_vmcs->vmcs = NULL;
3436 }
3437 
3438 static void free_kvm_area(void)
3439 {
3440         int cpu;
3441 
3442         for_each_possible_cpu(cpu) {
3443                 free_vmcs(per_cpu(vmxarea, cpu));
3444                 per_cpu(vmxarea, cpu) = NULL;
3445         }
3446 }
3447 
3448 static void init_vmcs_shadow_fields(void)
3449 {
3450         int i, j;
3451 
3452         /* No checks for read only fields yet */
3453 
3454         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3455                 switch (shadow_read_write_fields[i]) {
3456                 case GUEST_BNDCFGS:
3457                         if (!kvm_mpx_supported())
3458                                 continue;
3459                         break;
3460                 default:
3461                         break;
3462                 }
3463 
3464                 if (j < i)
3465                         shadow_read_write_fields[j] =
3466                                 shadow_read_write_fields[i];
3467                 j++;
3468         }
3469         max_shadow_read_write_fields = j;
3470 
3471         /* shadowed fields guest access without vmexit */
3472         for (i = 0; i < max_shadow_read_write_fields; i++) {
3473                 clear_bit(shadow_read_write_fields[i],
3474                           vmx_vmwrite_bitmap);
3475                 clear_bit(shadow_read_write_fields[i],
3476                           vmx_vmread_bitmap);
3477         }
3478         for (i = 0; i < max_shadow_read_only_fields; i++)
3479                 clear_bit(shadow_read_only_fields[i],
3480                           vmx_vmread_bitmap);
3481 }
3482 
3483 static __init int alloc_kvm_area(void)
3484 {
3485         int cpu;
3486 
3487         for_each_possible_cpu(cpu) {
3488                 struct vmcs *vmcs;
3489 
3490                 vmcs = alloc_vmcs_cpu(cpu);
3491                 if (!vmcs) {
3492                         free_kvm_area();
3493                         return -ENOMEM;
3494                 }
3495 
3496                 per_cpu(vmxarea, cpu) = vmcs;
3497         }
3498         return 0;
3499 }
3500 
3501 static bool emulation_required(struct kvm_vcpu *vcpu)
3502 {
3503         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3504 }
3505 
3506 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3507                 struct kvm_segment *save)
3508 {
3509         if (!emulate_invalid_guest_state) {
3510                 /*
3511                  * CS and SS RPL should be equal during guest entry according
3512                  * to VMX spec, but in reality it is not always so. Since vcpu
3513                  * is in the middle of the transition from real mode to
3514                  * protected mode it is safe to assume that RPL 0 is a good
3515                  * default value.
3516                  */
3517                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3518                         save->selector &= ~SEGMENT_RPL_MASK;
3519                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3520                 save->s = 1;
3521         }
3522         vmx_set_segment(vcpu, save, seg);
3523 }
3524 
3525 static void enter_pmode(struct kvm_vcpu *vcpu)
3526 {
3527         unsigned long flags;
3528         struct vcpu_vmx *vmx = to_vmx(vcpu);
3529 
3530         /*
3531          * Update real mode segment cache. It may be not up-to-date if sement
3532          * register was written while vcpu was in a guest mode.
3533          */
3534         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3535         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3536         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3537         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3538         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3539         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3540 
3541         vmx->rmode.vm86_active = 0;
3542 
3543         vmx_segment_cache_clear(vmx);
3544 
3545         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3546 
3547         flags = vmcs_readl(GUEST_RFLAGS);
3548         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3549         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3550         vmcs_writel(GUEST_RFLAGS, flags);
3551 
3552         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3553                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3554 
3555         update_exception_bitmap(vcpu);
3556 
3557         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3558         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3559         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3560         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3561         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3562         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3563 }
3564 
3565 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3566 {
3567         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3568         struct kvm_segment var = *save;
3569 
3570         var.dpl = 0x3;
3571         if (seg == VCPU_SREG_CS)
3572                 var.type = 0x3;
3573 
3574         if (!emulate_invalid_guest_state) {
3575                 var.selector = var.base >> 4;
3576                 var.base = var.base & 0xffff0;
3577                 var.limit = 0xffff;
3578                 var.g = 0;
3579                 var.db = 0;
3580                 var.present = 1;
3581                 var.s = 1;
3582                 var.l = 0;
3583                 var.unusable = 0;
3584                 var.type = 0x3;
3585                 var.avl = 0;
3586                 if (save->base & 0xf)
3587                         printk_once(KERN_WARNING "kvm: segment base is not "
3588                                         "paragraph aligned when entering "
3589                                         "protected mode (seg=%d)", seg);
3590         }
3591 
3592         vmcs_write16(sf->selector, var.selector);
3593         vmcs_write32(sf->base, var.base);
3594         vmcs_write32(sf->limit, var.limit);
3595         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3596 }
3597 
3598 static void enter_rmode(struct kvm_vcpu *vcpu)
3599 {
3600         unsigned long flags;
3601         struct vcpu_vmx *vmx = to_vmx(vcpu);
3602 
3603         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3604         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3605         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3606         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3607         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3608         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3609         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3610 
3611         vmx->rmode.vm86_active = 1;
3612 
3613         /*
3614          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3615          * vcpu. Warn the user that an update is overdue.
3616          */
3617         if (!vcpu->kvm->arch.tss_addr)
3618                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3619                              "called before entering vcpu\n");
3620 
3621         vmx_segment_cache_clear(vmx);
3622 
3623         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3624         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3625         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3626 
3627         flags = vmcs_readl(GUEST_RFLAGS);
3628         vmx->rmode.save_rflags = flags;
3629 
3630         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3631 
3632         vmcs_writel(GUEST_RFLAGS, flags);
3633         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3634         update_exception_bitmap(vcpu);
3635 
3636         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3637         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3638         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3639         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3640         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3641         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3642 
3643         kvm_mmu_reset_context(vcpu);
3644 }
3645 
3646 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3647 {
3648         struct vcpu_vmx *vmx = to_vmx(vcpu);
3649         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3650 
3651         if (!msr)
3652                 return;
3653 
3654         /*
3655          * Force kernel_gs_base reloading before EFER changes, as control
3656          * of this msr depends on is_long_mode().
3657          */
3658         vmx_load_host_state(to_vmx(vcpu));
3659         vcpu->arch.efer = efer;
3660         if (efer & EFER_LMA) {
3661                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3662                 msr->data = efer;
3663         } else {
3664                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3665 
3666                 msr->data = efer & ~EFER_LME;
3667         }
3668         setup_msrs(vmx);
3669 }
3670 
3671 #ifdef CONFIG_X86_64
3672 
3673 static void enter_lmode(struct kvm_vcpu *vcpu)
3674 {
3675         u32 guest_tr_ar;
3676 
3677         vmx_segment_cache_clear(to_vmx(vcpu));
3678 
3679         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3680         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3681                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3682                                      __func__);
3683                 vmcs_write32(GUEST_TR_AR_BYTES,
3684                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3685                              | VMX_AR_TYPE_BUSY_64_TSS);
3686         }
3687         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3688 }
3689 
3690 static void exit_lmode(struct kvm_vcpu *vcpu)
3691 {
3692         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3693         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3694 }
3695 
3696 #endif
3697 
3698 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3699 {
3700         vpid_sync_context(vpid);
3701         if (enable_ept) {
3702                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3703                         return;
3704                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3705         }
3706 }
3707 
3708 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3709 {
3710         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3711 }
3712 
3713 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3714 {
3715         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3716 
3717         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3718         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3719 }
3720 
3721 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3722 {
3723         if (enable_ept && is_paging(vcpu))
3724                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3725         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3726 }
3727 
3728 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3729 {
3730         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3731 
3732         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3733         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3734 }
3735 
3736 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3737 {
3738         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3739 
3740         if (!test_bit(VCPU_EXREG_PDPTR,
3741                       (unsigned long *)&vcpu->arch.regs_dirty))
3742                 return;
3743 
3744         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3745                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3746                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3747                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3748                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3749         }
3750 }
3751 
3752 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3753 {
3754         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3755 
3756         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3757                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3758                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3759                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3760                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3761         }
3762 
3763         __set_bit(VCPU_EXREG_PDPTR,
3764                   (unsigned long *)&vcpu->arch.regs_avail);
3765         __set_bit(VCPU_EXREG_PDPTR,
3766                   (unsigned long *)&vcpu->arch.regs_dirty);
3767 }
3768 
3769 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3770 
3771 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3772                                         unsigned long cr0,
3773                                         struct kvm_vcpu *vcpu)
3774 {
3775         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3776                 vmx_decache_cr3(vcpu);
3777         if (!(cr0 & X86_CR0_PG)) {
3778                 /* From paging/starting to nonpaging */
3779                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3780                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3781                              (CPU_BASED_CR3_LOAD_EXITING |
3782                               CPU_BASED_CR3_STORE_EXITING));
3783                 vcpu->arch.cr0 = cr0;
3784                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3785         } else if (!is_paging(vcpu)) {
3786                 /* From nonpaging to paging */
3787                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3788                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3789                              ~(CPU_BASED_CR3_LOAD_EXITING |
3790                                CPU_BASED_CR3_STORE_EXITING));
3791                 vcpu->arch.cr0 = cr0;
3792                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3793         }
3794 
3795         if (!(cr0 & X86_CR0_WP))
3796                 *hw_cr0 &= ~X86_CR0_WP;
3797 }
3798 
3799 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3800 {
3801         struct vcpu_vmx *vmx = to_vmx(vcpu);
3802         unsigned long hw_cr0;
3803 
3804         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3805         if (enable_unrestricted_guest)
3806                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3807         else {
3808                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3809 
3810                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3811                         enter_pmode(vcpu);
3812 
3813                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3814                         enter_rmode(vcpu);
3815         }
3816 
3817 #ifdef CONFIG_X86_64
3818         if (vcpu->arch.efer & EFER_LME) {
3819                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3820                         enter_lmode(vcpu);
3821                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3822                         exit_lmode(vcpu);
3823         }
3824 #endif
3825 
3826         if (enable_ept)
3827                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3828 
3829         if (!vcpu->fpu_active)
3830                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3831 
3832         vmcs_writel(CR0_READ_SHADOW, cr0);
3833         vmcs_writel(GUEST_CR0, hw_cr0);
3834         vcpu->arch.cr0 = cr0;
3835 
3836         /* depends on vcpu->arch.cr0 to be set to a new value */
3837         vmx->emulation_required = emulation_required(vcpu);
3838 }
3839 
3840 static u64 construct_eptp(unsigned long root_hpa)
3841 {
3842         u64 eptp;
3843 
3844         /* TODO write the value reading from MSR */
3845         eptp = VMX_EPT_DEFAULT_MT |
3846                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3847         if (enable_ept_ad_bits)
3848                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3849         eptp |= (root_hpa & PAGE_MASK);
3850 
3851         return eptp;
3852 }
3853 
3854 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3855 {
3856         unsigned long guest_cr3;
3857         u64 eptp;
3858 
3859         guest_cr3 = cr3;
3860         if (enable_ept) {
3861                 eptp = construct_eptp(cr3);
3862                 vmcs_write64(EPT_POINTER, eptp);
3863                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3864                         guest_cr3 = kvm_read_cr3(vcpu);
3865                 else
3866                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3867                 ept_load_pdptrs(vcpu);
3868         }
3869 
3870         vmx_flush_tlb(vcpu);
3871         vmcs_writel(GUEST_CR3, guest_cr3);
3872 }
3873 
3874 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3875 {
3876         /*
3877          * Pass through host's Machine Check Enable value to hw_cr4, which
3878          * is in force while we are in guest mode.  Do not let guests control
3879          * this bit, even if host CR4.MCE == 0.
3880          */
3881         unsigned long hw_cr4 =
3882                 (cr4_read_shadow() & X86_CR4_MCE) |
3883                 (cr4 & ~X86_CR4_MCE) |
3884                 (to_vmx(vcpu)->rmode.vm86_active ?
3885                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3886 
3887         if (cr4 & X86_CR4_VMXE) {
3888                 /*
3889                  * To use VMXON (and later other VMX instructions), a guest
3890                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3891                  * So basically the check on whether to allow nested VMX
3892                  * is here.
3893                  */
3894                 if (!nested_vmx_allowed(vcpu))
3895                         return 1;
3896         }
3897         if (to_vmx(vcpu)->nested.vmxon &&
3898             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3899                 return 1;
3900 
3901         vcpu->arch.cr4 = cr4;
3902         if (enable_ept) {
3903                 if (!is_paging(vcpu)) {
3904                         hw_cr4 &= ~X86_CR4_PAE;
3905                         hw_cr4 |= X86_CR4_PSE;
3906                 } else if (!(cr4 & X86_CR4_PAE)) {
3907                         hw_cr4 &= ~X86_CR4_PAE;
3908                 }
3909         }
3910 
3911         if (!enable_unrestricted_guest && !is_paging(vcpu))
3912                 /*
3913                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3914                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3915                  * to be manually disabled when guest switches to non-paging
3916                  * mode.
3917                  *
3918                  * If !enable_unrestricted_guest, the CPU is always running
3919                  * with CR0.PG=1 and CR4 needs to be modified.
3920                  * If enable_unrestricted_guest, the CPU automatically
3921                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3922                  */
3923                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3924 
3925         vmcs_writel(CR4_READ_SHADOW, cr4);
3926         vmcs_writel(GUEST_CR4, hw_cr4);
3927         return 0;
3928 }
3929 
3930 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3931                             struct kvm_segment *var, int seg)
3932 {
3933         struct vcpu_vmx *vmx = to_vmx(vcpu);
3934         u32 ar;
3935 
3936         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3937                 *var = vmx->rmode.segs[seg];
3938                 if (seg == VCPU_SREG_TR
3939                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3940                         return;
3941                 var->base = vmx_read_guest_seg_base(vmx, seg);
3942                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3943                 return;
3944         }
3945         var->base = vmx_read_guest_seg_base(vmx, seg);
3946         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3947         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3948         ar = vmx_read_guest_seg_ar(vmx, seg);
3949         var->unusable = (ar >> 16) & 1;
3950         var->type = ar & 15;
3951         var->s = (ar >> 4) & 1;
3952         var->dpl = (ar >> 5) & 3;
3953         /*
3954          * Some userspaces do not preserve unusable property. Since usable
3955          * segment has to be present according to VMX spec we can use present
3956          * property to amend userspace bug by making unusable segment always
3957          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3958          * segment as unusable.
3959          */
3960         var->present = !var->unusable;
3961         var->avl = (ar >> 12) & 1;
3962         var->l = (ar >> 13) & 1;
3963         var->db = (ar >> 14) & 1;
3964         var->g = (ar >> 15) & 1;
3965 }
3966 
3967 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3968 {
3969         struct kvm_segment s;
3970 
3971         if (to_vmx(vcpu)->rmode.vm86_active) {
3972                 vmx_get_segment(vcpu, &s, seg);
3973                 return s.base;
3974         }
3975         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3976 }
3977 
3978 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3979 {
3980         struct vcpu_vmx *vmx = to_vmx(vcpu);
3981 
3982         if (unlikely(vmx->rmode.vm86_active))
3983                 return 0;
3984         else {
3985                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3986                 return VMX_AR_DPL(ar);
3987         }
3988 }
3989 
3990 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3991 {
3992         u32 ar;
3993 
3994         if (var->unusable || !var->present)
3995                 ar = 1 << 16;
3996         else {
3997                 ar = var->type & 15;
3998                 ar |= (var->s & 1) << 4;
3999                 ar |= (var->dpl & 3) << 5;
4000                 ar |= (var->present & 1) << 7;
4001                 ar |= (var->avl & 1) << 12;
4002                 ar |= (var->l & 1) << 13;
4003                 ar |= (var->db & 1) << 14;
4004                 ar |= (var->g & 1) << 15;
4005         }
4006 
4007         return ar;
4008 }
4009 
4010 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4011                             struct kvm_segment *var, int seg)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4015 
4016         vmx_segment_cache_clear(vmx);
4017 
4018         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4019                 vmx->rmode.segs[seg] = *var;
4020                 if (seg == VCPU_SREG_TR)
4021                         vmcs_write16(sf->selector, var->selector);
4022                 else if (var->s)
4023                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4024                 goto out;
4025         }
4026 
4027         vmcs_writel(sf->base, var->base);
4028         vmcs_write32(sf->limit, var->limit);
4029         vmcs_write16(sf->selector, var->selector);
4030 
4031         /*
4032          *   Fix the "Accessed" bit in AR field of segment registers for older
4033          * qemu binaries.
4034          *   IA32 arch specifies that at the time of processor reset the
4035          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4036          * is setting it to 0 in the userland code. This causes invalid guest
4037          * state vmexit when "unrestricted guest" mode is turned on.
4038          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4039          * tree. Newer qemu binaries with that qemu fix would not need this
4040          * kvm hack.
4041          */
4042         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4043                 var->type |= 0x1; /* Accessed */
4044 
4045         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4046 
4047 out:
4048         vmx->emulation_required = emulation_required(vcpu);
4049 }
4050 
4051 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4052 {
4053         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4054 
4055         *db = (ar >> 14) & 1;
4056         *l = (ar >> 13) & 1;
4057 }
4058 
4059 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4060 {
4061         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4062         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4063 }
4064 
4065 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4066 {
4067         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4068         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4069 }
4070 
4071 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4072 {
4073         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4074         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4075 }
4076 
4077 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4078 {
4079         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4080         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4081 }
4082 
4083 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4084 {
4085         struct kvm_segment var;
4086         u32 ar;
4087 
4088         vmx_get_segment(vcpu, &var, seg);
4089         var.dpl = 0x3;
4090         if (seg == VCPU_SREG_CS)
4091                 var.type = 0x3;
4092         ar = vmx_segment_access_rights(&var);
4093 
4094         if (var.base != (var.selector << 4))
4095                 return false;
4096         if (var.limit != 0xffff)
4097                 return false;
4098         if (ar != 0xf3)
4099                 return false;
4100 
4101         return true;
4102 }
4103 
4104 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4105 {
4106         struct kvm_segment cs;
4107         unsigned int cs_rpl;
4108 
4109         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4110         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4111 
4112         if (cs.unusable)
4113                 return false;
4114         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4115                 return false;
4116         if (!cs.s)
4117                 return false;
4118         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4119                 if (cs.dpl > cs_rpl)
4120                         return false;
4121         } else {
4122                 if (cs.dpl != cs_rpl)
4123                         return false;
4124         }
4125         if (!cs.present)
4126                 return false;
4127 
4128         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4129         return true;
4130 }
4131 
4132 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4133 {
4134         struct kvm_segment ss;
4135         unsigned int ss_rpl;
4136 
4137         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4138         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4139 
4140         if (ss.unusable)
4141                 return true;
4142         if (ss.type != 3 && ss.type != 7)
4143                 return false;
4144         if (!ss.s)
4145                 return false;
4146         if (ss.dpl != ss_rpl) /* DPL != RPL */
4147                 return false;
4148         if (!ss.present)
4149                 return false;
4150 
4151         return true;
4152 }
4153 
4154 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4155 {
4156         struct kvm_segment var;
4157         unsigned int rpl;
4158 
4159         vmx_get_segment(vcpu, &var, seg);
4160         rpl = var.selector & SEGMENT_RPL_MASK;
4161 
4162         if (var.unusable)
4163                 return true;
4164         if (!var.s)
4165                 return false;
4166         if (!var.present)
4167                 return false;
4168         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4169                 if (var.dpl < rpl) /* DPL < RPL */
4170                         return false;
4171         }
4172 
4173         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4174          * rights flags
4175          */
4176         return true;
4177 }
4178 
4179 static bool tr_valid(struct kvm_vcpu *vcpu)
4180 {
4181         struct kvm_segment tr;
4182 
4183         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4184 
4185         if (tr.unusable)
4186                 return false;
4187         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4188                 return false;
4189         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4190                 return false;
4191         if (!tr.present)
4192                 return false;
4193 
4194         return true;
4195 }
4196 
4197 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4198 {
4199         struct kvm_segment ldtr;
4200 
4201         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4202 
4203         if (ldtr.unusable)
4204                 return true;
4205         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4206                 return false;
4207         if (ldtr.type != 2)
4208                 return false;
4209         if (!ldtr.present)
4210                 return false;
4211 
4212         return true;
4213 }
4214 
4215 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4216 {
4217         struct kvm_segment cs, ss;
4218 
4219         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4220         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4221 
4222         return ((cs.selector & SEGMENT_RPL_MASK) ==
4223                  (ss.selector & SEGMENT_RPL_MASK));
4224 }
4225 
4226 /*
4227  * Check if guest state is valid. Returns true if valid, false if
4228  * not.
4229  * We assume that registers are always usable
4230  */
4231 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4232 {
4233         if (enable_unrestricted_guest)
4234                 return true;
4235 
4236         /* real mode guest state checks */
4237         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4238                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4239                         return false;
4240                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4241                         return false;
4242                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4243                         return false;
4244                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4245                         return false;
4246                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4247                         return false;
4248                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4249                         return false;
4250         } else {
4251         /* protected mode guest state checks */
4252                 if (!cs_ss_rpl_check(vcpu))
4253                         return false;
4254                 if (!code_segment_valid(vcpu))
4255                         return false;
4256                 if (!stack_segment_valid(vcpu))
4257                         return false;
4258                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4259                         return false;
4260                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4261                         return false;
4262                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4263                         return false;
4264                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4265                         return false;
4266                 if (!tr_valid(vcpu))
4267                         return false;
4268                 if (!ldtr_valid(vcpu))
4269                         return false;
4270         }
4271         /* TODO:
4272          * - Add checks on RIP
4273          * - Add checks on RFLAGS
4274          */
4275 
4276         return true;
4277 }
4278 
4279 static int init_rmode_tss(struct kvm *kvm)
4280 {
4281         gfn_t fn;
4282         u16 data = 0;
4283         int idx, r;
4284 
4285         idx = srcu_read_lock(&kvm->srcu);
4286         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4287         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4288         if (r < 0)
4289                 goto out;
4290         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4291         r = kvm_write_guest_page(kvm, fn++, &data,
4292                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4293         if (r < 0)
4294                 goto out;
4295         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4296         if (r < 0)
4297                 goto out;
4298         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4299         if (r < 0)
4300                 goto out;
4301         data = ~0;
4302         r = kvm_write_guest_page(kvm, fn, &data,
4303                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4304                                  sizeof(u8));
4305 out:
4306         srcu_read_unlock(&kvm->srcu, idx);
4307         return r;
4308 }
4309 
4310 static int init_rmode_identity_map(struct kvm *kvm)
4311 {
4312         int i, idx, r = 0;
4313         kvm_pfn_t identity_map_pfn;
4314         u32 tmp;
4315 
4316         if (!enable_ept)
4317                 return 0;
4318 
4319         /* Protect kvm->arch.ept_identity_pagetable_done. */
4320         mutex_lock(&kvm->slots_lock);
4321 
4322         if (likely(kvm->arch.ept_identity_pagetable_done))
4323                 goto out2;
4324 
4325         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4326 
4327         r = alloc_identity_pagetable(kvm);
4328         if (r < 0)
4329                 goto out2;
4330 
4331         idx = srcu_read_lock(&kvm->srcu);
4332         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4333         if (r < 0)
4334                 goto out;
4335         /* Set up identity-mapping pagetable for EPT in real mode */
4336         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4337                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4338                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4339                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4340                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4341                 if (r < 0)
4342                         goto out;
4343         }
4344         kvm->arch.ept_identity_pagetable_done = true;
4345 
4346 out:
4347         srcu_read_unlock(&kvm->srcu, idx);
4348 
4349 out2:
4350         mutex_unlock(&kvm->slots_lock);
4351         return r;
4352 }
4353 
4354 static void seg_setup(int seg)
4355 {
4356         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4357         unsigned int ar;
4358 
4359         vmcs_write16(sf->selector, 0);
4360         vmcs_writel(sf->base, 0);
4361         vmcs_write32(sf->limit, 0xffff);
4362         ar = 0x93;
4363         if (seg == VCPU_SREG_CS)
4364                 ar |= 0x08; /* code segment */
4365 
4366         vmcs_write32(sf->ar_bytes, ar);
4367 }
4368 
4369 static int alloc_apic_access_page(struct kvm *kvm)
4370 {
4371         struct page *page;
4372         int r = 0;
4373 
4374         mutex_lock(&kvm->slots_lock);
4375         if (kvm->arch.apic_access_page_done)
4376                 goto out;
4377         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4378                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4379         if (r)
4380                 goto out;
4381 
4382         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4383         if (is_error_page(page)) {
4384                 r = -EFAULT;
4385                 goto out;
4386         }
4387 
4388         /*
4389          * Do not pin the page in memory, so that memory hot-unplug
4390          * is able to migrate it.
4391          */
4392         put_page(page);
4393         kvm->arch.apic_access_page_done = true;
4394 out:
4395         mutex_unlock(&kvm->slots_lock);
4396         return r;
4397 }
4398 
4399 static int alloc_identity_pagetable(struct kvm *kvm)
4400 {
4401         /* Called with kvm->slots_lock held. */
4402 
4403         int r = 0;
4404 
4405         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4406 
4407         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4408                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4409 
4410         return r;
4411 }
4412 
4413 static int allocate_vpid(void)
4414 {
4415         int vpid;
4416 
4417         if (!enable_vpid)
4418                 return 0;
4419         spin_lock(&vmx_vpid_lock);
4420         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4421         if (vpid < VMX_NR_VPIDS)
4422                 __set_bit(vpid, vmx_vpid_bitmap);
4423         else
4424                 vpid = 0;
4425         spin_unlock(&vmx_vpid_lock);
4426         return vpid;
4427 }
4428 
4429 static void free_vpid(int vpid)
4430 {
4431         if (!enable_vpid || vpid == 0)
4432                 return;
4433         spin_lock(&vmx_vpid_lock);
4434         __clear_bit(vpid, vmx_vpid_bitmap);
4435         spin_unlock(&vmx_vpid_lock);
4436 }
4437 
4438 #define MSR_TYPE_R      1
4439 #define MSR_TYPE_W      2
4440 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4441                                                 u32 msr, int type)
4442 {
4443         int f = sizeof(unsigned long);
4444 
4445         if (!cpu_has_vmx_msr_bitmap())
4446                 return;
4447 
4448         /*
4449          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4450          * have the write-low and read-high bitmap offsets the wrong way round.
4451          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4452          */
4453         if (msr <= 0x1fff) {
4454                 if (type & MSR_TYPE_R)
4455                         /* read-low */
4456                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4457 
4458                 if (type & MSR_TYPE_W)
4459                         /* write-low */
4460                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4461 
4462         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4463                 msr &= 0x1fff;
4464                 if (type & MSR_TYPE_R)
4465                         /* read-high */
4466                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4467 
4468                 if (type & MSR_TYPE_W)
4469                         /* write-high */
4470                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4471 
4472         }
4473 }
4474 
4475 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4476                                                 u32 msr, int type)
4477 {
4478         int f = sizeof(unsigned long);
4479 
4480         if (!cpu_has_vmx_msr_bitmap())
4481                 return;
4482 
4483         /*
4484          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4485          * have the write-low and read-high bitmap offsets the wrong way round.
4486          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4487          */
4488         if (msr <= 0x1fff) {
4489                 if (type & MSR_TYPE_R)
4490                         /* read-low */
4491                         __set_bit(msr, msr_bitmap + 0x000 / f);
4492 
4493                 if (type & MSR_TYPE_W)
4494                         /* write-low */
4495                         __set_bit(msr, msr_bitmap + 0x800 / f);
4496 
4497         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4498                 msr &= 0x1fff;
4499                 if (type & MSR_TYPE_R)
4500                         /* read-high */
4501                         __set_bit(msr, msr_bitmap + 0x400 / f);
4502 
4503                 if (type & MSR_TYPE_W)
4504                         /* write-high */
4505                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4506 
4507         }
4508 }
4509 
4510 /*
4511  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4512  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4513  */
4514 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4515                                                unsigned long *msr_bitmap_nested,
4516                                                u32 msr, int type)
4517 {
4518         int f = sizeof(unsigned long);
4519 
4520         if (!cpu_has_vmx_msr_bitmap()) {
4521                 WARN_ON(1);
4522                 return;
4523         }
4524 
4525         /*
4526          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4527          * have the write-low and read-high bitmap offsets the wrong way round.
4528          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4529          */
4530         if (msr <= 0x1fff) {
4531                 if (type & MSR_TYPE_R &&
4532                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4533                         /* read-low */
4534                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4535 
4536                 if (type & MSR_TYPE_W &&
4537                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4538                         /* write-low */
4539                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4540 
4541         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4542                 msr &= 0x1fff;
4543                 if (type & MSR_TYPE_R &&
4544                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4545                         /* read-high */
4546                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4547 
4548                 if (type & MSR_TYPE_W &&
4549                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4550                         /* write-high */
4551                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4552 
4553         }
4554 }
4555 
4556 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4557 {
4558         if (!longmode_only)
4559                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4560                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4561         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4562                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4563 }
4564 
4565 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4566 {
4567         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4568                         msr, MSR_TYPE_R);
4569         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4570                         msr, MSR_TYPE_R);
4571 }
4572 
4573 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4574 {
4575         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4576                         msr, MSR_TYPE_R);
4577         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4578                         msr, MSR_TYPE_R);
4579 }
4580 
4581 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4582 {
4583         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4584                         msr, MSR_TYPE_W);
4585         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4586                         msr, MSR_TYPE_W);
4587 }
4588 
4589 static bool vmx_get_enable_apicv(void)
4590 {
4591         return enable_apicv;
4592 }
4593 
4594 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4595 {
4596         struct vcpu_vmx *vmx = to_vmx(vcpu);
4597         int max_irr;
4598         void *vapic_page;
4599         u16 status;
4600 
4601         if (vmx->nested.pi_desc &&
4602             vmx->nested.pi_pending) {
4603                 vmx->nested.pi_pending = false;
4604                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4605                         return 0;
4606 
4607                 max_irr = find_last_bit(
4608                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4609 
4610                 if (max_irr == 256)
4611                         return 0;
4612 
4613                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4614                 if (!vapic_page) {
4615                         WARN_ON(1);
4616                         return -ENOMEM;
4617                 }
4618                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4619                 kunmap(vmx->nested.virtual_apic_page);
4620 
4621                 status = vmcs_read16(GUEST_INTR_STATUS);
4622                 if ((u8)max_irr > ((u8)status & 0xff)) {
4623                         status &= ~0xff;
4624                         status |= (u8)max_irr;
4625                         vmcs_write16(GUEST_INTR_STATUS, status);
4626                 }
4627         }
4628         return 0;
4629 }
4630 
4631 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4632 {
4633 #ifdef CONFIG_SMP
4634         if (vcpu->mode == IN_GUEST_MODE) {
4635                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4636 
4637                 /*
4638                  * Currently, we don't support urgent interrupt,
4639                  * all interrupts are recognized as non-urgent
4640                  * interrupt, so we cannot post interrupts when
4641                  * 'SN' is set.
4642                  *
4643                  * If the vcpu is in guest mode, it means it is
4644                  * running instead of being scheduled out and
4645                  * waiting in the run queue, and that's the only
4646                  * case when 'SN' is set currently, warning if
4647                  * 'SN' is set.
4648                  */
4649                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4650 
4651                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4652                                 POSTED_INTR_VECTOR);
4653                 return true;
4654         }
4655 #endif
4656         return false;
4657 }
4658 
4659 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4660                                                 int vector)
4661 {
4662         struct vcpu_vmx *vmx = to_vmx(vcpu);
4663 
4664         if (is_guest_mode(vcpu) &&
4665             vector == vmx->nested.posted_intr_nv) {
4666                 /* the PIR and ON have been set by L1. */
4667                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4668                 /*
4669                  * If a posted intr is not recognized by hardware,
4670                  * we will accomplish it in the next vmentry.
4671                  */
4672                 vmx->nested.pi_pending = true;
4673                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4674                 return 0;
4675         }
4676         return -1;
4677 }
4678 /*
4679  * Send interrupt to vcpu via posted interrupt way.
4680  * 1. If target vcpu is running(non-root mode), send posted interrupt
4681  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4682  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4683  * interrupt from PIR in next vmentry.
4684  */
4685 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4686 {
4687         struct vcpu_vmx *vmx = to_vmx(vcpu);
4688         int r;
4689 
4690         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4691         if (!r)
4692                 return;
4693 
4694         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4695                 return;
4696 
4697         r = pi_test_and_set_on(&vmx->pi_desc);
4698         kvm_make_request(KVM_REQ_EVENT, vcpu);
4699         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4700                 kvm_vcpu_kick(vcpu);
4701 }
4702 
4703 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4704 {
4705         struct vcpu_vmx *vmx = to_vmx(vcpu);
4706 
4707         if (!pi_test_and_clear_on(&vmx->pi_desc))
4708                 return;
4709 
4710         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4711 }
4712 
4713 /*
4714  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4715  * will not change in the lifetime of the guest.
4716  * Note that host-state that does change is set elsewhere. E.g., host-state
4717  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4718  */
4719 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4720 {
4721         u32 low32, high32;
4722         unsigned long tmpl;
4723         struct desc_ptr dt;
4724         unsigned long cr4;
4725 
4726         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4727         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4728 
4729         /* Save the most likely value for this task's CR4 in the VMCS. */
4730         cr4 = cr4_read_shadow();
4731         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4732         vmx->host_state.vmcs_host_cr4 = cr4;
4733 
4734         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4735 #ifdef CONFIG_X86_64
4736         /*
4737          * Load null selectors, so we can avoid reloading them in
4738          * __vmx_load_host_state(), in case userspace uses the null selectors
4739          * too (the expected case).
4740          */
4741         vmcs_write16(HOST_DS_SELECTOR, 0);
4742         vmcs_write16(HOST_ES_SELECTOR, 0);
4743 #else
4744         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4745         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4746 #endif
4747         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4748         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4749 
4750         native_store_idt(&dt);
4751         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4752         vmx->host_idt_base = dt.address;
4753 
4754         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4755 
4756         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4757         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4758         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4759         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4760 
4761         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4762                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4763                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4764         }
4765 }
4766 
4767 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4768 {
4769         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4770         if (enable_ept)
4771                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4772         if (is_guest_mode(&vmx->vcpu))
4773                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4774                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4775         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4776 }
4777 
4778 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4779 {
4780         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4781 
4782         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4783                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4784         return pin_based_exec_ctrl;
4785 }
4786 
4787 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4788 {
4789         struct vcpu_vmx *vmx = to_vmx(vcpu);
4790 
4791         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792 }
4793 
4794 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4795 {
4796         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4797 
4798         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4799                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4800 
4801         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4802                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4803 #ifdef CONFIG_X86_64
4804                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4805                                 CPU_BASED_CR8_LOAD_EXITING;
4806 #endif
4807         }
4808         if (!enable_ept)
4809                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4810                                 CPU_BASED_CR3_LOAD_EXITING  |
4811                                 CPU_BASED_INVLPG_EXITING;
4812         return exec_control;
4813 }
4814 
4815 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4816 {
4817         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4818         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4819                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4820         if (vmx->vpid == 0)
4821                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4822         if (!enable_ept) {
4823                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4824                 enable_unrestricted_guest = 0;
4825                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4826                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4827         }
4828         if (!enable_unrestricted_guest)
4829                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4830         if (!ple_gap)
4831                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4832         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4833                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4834                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4835         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4836         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4837            (handle_vmptrld).
4838            We can NOT enable shadow_vmcs here because we don't have yet
4839            a current VMCS12
4840         */
4841         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4842 
4843         if (!enable_pml)
4844                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4845 
4846         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4847         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4848 
4849         return exec_control;
4850 }
4851 
4852 static void ept_set_mmio_spte_mask(void)
4853 {
4854         /*
4855          * EPT Misconfigurations can be generated if the value of bits 2:0
4856          * of an EPT paging-structure entry is 110b (write/execute).
4857          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4858          * spte.
4859          */
4860         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4861 }
4862 
4863 #define VMX_XSS_EXIT_BITMAP 0
4864 /*
4865  * Sets up the vmcs for emulated real mode.
4866  */
4867 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4868 {
4869 #ifdef CONFIG_X86_64
4870         unsigned long a;
4871 #endif
4872         int i;
4873 
4874         /* I/O */
4875         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4876         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4877 
4878         if (enable_shadow_vmcs) {
4879                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4880                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4881         }
4882         if (cpu_has_vmx_msr_bitmap())
4883                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4884 
4885         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4886 
4887         /* Control */
4888         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4889 
4890         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4891 
4892         if (cpu_has_secondary_exec_ctrls())
4893                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4894                                 vmx_secondary_exec_control(vmx));
4895 
4896         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4897                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4898                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4899                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4900                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4901 
4902                 vmcs_write16(GUEST_INTR_STATUS, 0);
4903 
4904                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4905                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4906         }
4907 
4908         if (ple_gap) {
4909                 vmcs_write32(PLE_GAP, ple_gap);
4910                 vmx->ple_window = ple_window;
4911                 vmx->ple_window_dirty = true;
4912         }
4913 
4914         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4915         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4916         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4917 
4918         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4919         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4920         vmx_set_constant_host_state(vmx);
4921 #ifdef CONFIG_X86_64
4922         rdmsrl(MSR_FS_BASE, a);
4923         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4924         rdmsrl(MSR_GS_BASE, a);
4925         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4926 #else
4927         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4928         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4929 #endif
4930 
4931         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4932         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4933         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4934         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4935         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4936 
4937         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4938                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4939 
4940         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4941                 u32 index = vmx_msr_index[i];
4942                 u32 data_low, data_high;
4943                 int j = vmx->nmsrs;
4944 
4945                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4946                         continue;
4947                 if (wrmsr_safe(index, data_low, data_high) < 0)
4948                         continue;
4949                 vmx->guest_msrs[j].index = i;
4950                 vmx->guest_msrs[j].data = 0;
4951                 vmx->guest_msrs[j].mask = -1ull;
4952                 ++vmx->nmsrs;
4953         }
4954 
4955 
4956         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4957 
4958         /* 22.2.1, 20.8.1 */
4959         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4960 
4961         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4962         set_cr4_guest_host_mask(vmx);
4963 
4964         if (vmx_xsaves_supported())
4965                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4966 
4967         return 0;
4968 }
4969 
4970 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4971 {
4972         struct vcpu_vmx *vmx = to_vmx(vcpu);
4973         struct msr_data apic_base_msr;
4974         u64 cr0;
4975 
4976         vmx->rmode.vm86_active = 0;
4977 
4978         vmx->soft_vnmi_blocked = 0;
4979 
4980         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4981         kvm_set_cr8(vcpu, 0);
4982 
4983         if (!init_event) {
4984                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4985                                      MSR_IA32_APICBASE_ENABLE;
4986                 if (kvm_vcpu_is_reset_bsp(vcpu))
4987                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4988                 apic_base_msr.host_initiated = true;
4989                 kvm_set_apic_base(vcpu, &apic_base_msr);
4990         }
4991 
4992         vmx_segment_cache_clear(vmx);
4993 
4994         seg_setup(VCPU_SREG_CS);
4995         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4996         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4997 
4998         seg_setup(VCPU_SREG_DS);
4999         seg_setup(VCPU_SREG_ES);
5000         seg_setup(VCPU_SREG_FS);
5001         seg_setup(VCPU_SREG_GS);
5002         seg_setup(VCPU_SREG_SS);
5003 
5004         vmcs_write16(GUEST_TR_SELECTOR, 0);
5005         vmcs_writel(GUEST_TR_BASE, 0);
5006         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5007         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5008 
5009         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5010         vmcs_writel(GUEST_LDTR_BASE, 0);
5011         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5012         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5013 
5014         if (!init_event) {
5015                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5016                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5017                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5018                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5019         }
5020 
5021         vmcs_writel(GUEST_RFLAGS, 0x02);
5022         kvm_rip_write(vcpu, 0xfff0);
5023 
5024         vmcs_writel(GUEST_GDTR_BASE, 0);
5025         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5026 
5027         vmcs_writel(GUEST_IDTR_BASE, 0);
5028         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5029 
5030         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5031         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5032         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5033 
5034         setup_msrs(vmx);
5035 
5036         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5037 
5038         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5039                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5040                 if (cpu_need_tpr_shadow(vcpu))
5041                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5042                                      __pa(vcpu->arch.apic->regs));
5043                 vmcs_write32(TPR_THRESHOLD, 0);
5044         }
5045 
5046         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5047 
5048         if (kvm_vcpu_apicv_active(vcpu))
5049                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5050 
5051         if (vmx->vpid != 0)
5052                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5053 
5054         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5055         vmx->vcpu.arch.cr0 = cr0;
5056         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5057         vmx_set_cr4(vcpu, 0);
5058         vmx_set_efer(vcpu, 0);
5059         vmx_fpu_activate(vcpu);
5060         update_exception_bitmap(vcpu);
5061 
5062         vpid_sync_context(vmx->vpid);
5063 }
5064 
5065 /*
5066  * In nested virtualization, check if L1 asked to exit on external interrupts.
5067  * For most existing hypervisors, this will always return true.
5068  */
5069 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5070 {
5071         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5072                 PIN_BASED_EXT_INTR_MASK;
5073 }
5074 
5075 /*
5076  * In nested virtualization, check if L1 has set
5077  * VM_EXIT_ACK_INTR_ON_EXIT
5078  */
5079 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5080 {
5081         return get_vmcs12(vcpu)->vm_exit_controls &
5082                 VM_EXIT_ACK_INTR_ON_EXIT;
5083 }
5084 
5085 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5086 {
5087         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5088                 PIN_BASED_NMI_EXITING;
5089 }
5090 
5091 static void enable_irq_window(struct kvm_vcpu *vcpu)
5092 {
5093         u32 cpu_based_vm_exec_control;
5094 
5095         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5096         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5097         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5098 }
5099 
5100 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5101 {
5102         u32 cpu_based_vm_exec_control;
5103 
5104         if (!cpu_has_virtual_nmis() ||
5105             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5106                 enable_irq_window(vcpu);
5107                 return;
5108         }
5109 
5110         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5111         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5112         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5113 }
5114 
5115 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5116 {
5117         struct vcpu_vmx *vmx = to_vmx(vcpu);
5118         uint32_t intr;
5119         int irq = vcpu->arch.interrupt.nr;
5120 
5121         trace_kvm_inj_virq(irq);
5122 
5123         ++vcpu->stat.irq_injections;
5124         if (vmx->rmode.vm86_active) {
5125                 int inc_eip = 0;
5126                 if (vcpu->arch.interrupt.soft)
5127                         inc_eip = vcpu->arch.event_exit_inst_len;
5128                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5129                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5130                 return;
5131         }
5132         intr = irq | INTR_INFO_VALID_MASK;
5133         if (vcpu->arch.interrupt.soft) {
5134                 intr |= INTR_TYPE_SOFT_INTR;
5135                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5136                              vmx->vcpu.arch.event_exit_inst_len);
5137         } else
5138                 intr |= INTR_TYPE_EXT_INTR;
5139         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5140 }
5141 
5142 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5143 {
5144         struct vcpu_vmx *vmx = to_vmx(vcpu);
5145 
5146         if (is_guest_mode(vcpu))
5147                 return;
5148 
5149         if (!cpu_has_virtual_nmis()) {
5150                 /*
5151                  * Tracking the NMI-blocked state in software is built upon
5152                  * finding the next open IRQ window. This, in turn, depends on
5153                  * well-behaving guests: They have to keep IRQs disabled at
5154                  * least as long as the NMI handler runs. Otherwise we may
5155                  * cause NMI nesting, maybe breaking the guest. But as this is
5156                  * highly unlikely, we can live with the residual risk.
5157                  */
5158                 vmx->soft_vnmi_blocked = 1;
5159                 vmx->vnmi_blocked_time = 0;
5160         }
5161 
5162         ++vcpu->stat.nmi_injections;
5163         vmx->nmi_known_unmasked = false;
5164         if (vmx->rmode.vm86_active) {
5165                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5166                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5167                 return;
5168         }
5169         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5170                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5171 }
5172 
5173 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5174 {
5175         if (!cpu_has_virtual_nmis())
5176                 return to_vmx(vcpu)->soft_vnmi_blocked;
5177         if (to_vmx(vcpu)->nmi_known_unmasked)
5178                 return false;
5179         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5180 }
5181 
5182 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5183 {
5184         struct vcpu_vmx *vmx = to_vmx(vcpu);
5185 
5186         if (!cpu_has_virtual_nmis()) {
5187                 if (vmx->soft_vnmi_blocked != masked) {
5188                         vmx->soft_vnmi_blocked = masked;
5189                         vmx->vnmi_blocked_time = 0;
5190                 }
5191         } else {
5192                 vmx->nmi_known_unmasked = !masked;
5193                 if (masked)
5194                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5195                                       GUEST_INTR_STATE_NMI);
5196                 else
5197                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5198                                         GUEST_INTR_STATE_NMI);
5199         }
5200 }
5201 
5202 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5203 {
5204         if (to_vmx(vcpu)->nested.nested_run_pending)
5205                 return 0;
5206 
5207         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5208                 return 0;
5209 
5210         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5211                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5212                    | GUEST_INTR_STATE_NMI));
5213 }
5214 
5215 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5216 {
5217         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5218                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5219                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5220                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5221 }
5222 
5223 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5224 {
5225         int ret;
5226 
5227         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5228                                     PAGE_SIZE * 3);
5229         if (ret)
5230                 return ret;
5231         kvm->arch.tss_addr = addr;
5232         return init_rmode_tss(kvm);
5233 }
5234 
5235 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5236 {
5237         switch (vec) {
5238         case BP_VECTOR:
5239                 /*
5240                  * Update instruction length as we may reinject the exception
5241                  * from user space while in guest debugging mode.
5242                  */
5243                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5244                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5245                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5246                         return false;
5247                 /* fall through */
5248         case DB_VECTOR:
5249                 if (vcpu->guest_debug &
5250                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5251                         return false;
5252                 /* fall through */
5253         case DE_VECTOR:
5254         case OF_VECTOR:
5255         case BR_VECTOR:
5256         case UD_VECTOR:
5257         case DF_VECTOR:
5258         case SS_VECTOR:
5259         case GP_VECTOR:
5260         case MF_VECTOR:
5261                 return true;
5262         break;
5263         }
5264         return false;
5265 }
5266 
5267 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5268                                   int vec, u32 err_code)
5269 {
5270         /*
5271          * Instruction with address size override prefix opcode 0x67
5272          * Cause the #SS fault with 0 error code in VM86 mode.
5273          */
5274         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5275                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5276                         if (vcpu->arch.halt_request) {
5277                                 vcpu->arch.halt_request = 0;
5278                                 return kvm_vcpu_halt(vcpu);
5279                         }
5280                         return 1;
5281                 }
5282                 return 0;
5283         }
5284 
5285         /*
5286          * Forward all other exceptions that are valid in real mode.
5287          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5288          *        the required debugging infrastructure rework.
5289          */
5290         kvm_queue_exception(vcpu, vec);
5291         return 1;
5292 }
5293 
5294 /*
5295  * Trigger machine check on the host. We assume all the MSRs are already set up
5296  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5297  * We pass a fake environment to the machine check handler because we want
5298  * the guest to be always treated like user space, no matter what context
5299  * it used internally.
5300  */
5301 static void kvm_machine_check(void)
5302 {
5303 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5304         struct pt_regs regs = {
5305                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5306                 .flags = X86_EFLAGS_IF,
5307         };
5308 
5309         do_machine_check(&regs, 0);
5310 #endif
5311 }
5312 
5313 static int handle_machine_check(struct kvm_vcpu *vcpu)
5314 {
5315         /* already handled by vcpu_run */
5316         return 1;
5317 }
5318 
5319 static int handle_exception(struct kvm_vcpu *vcpu)
5320 {
5321         struct vcpu_vmx *vmx = to_vmx(vcpu);
5322         struct kvm_run *kvm_run = vcpu->run;
5323         u32 intr_info, ex_no, error_code;
5324         unsigned long cr2, rip, dr6;
5325         u32 vect_info;
5326         enum emulation_result er;
5327 
5328         vect_info = vmx->idt_vectoring_info;
5329         intr_info = vmx->exit_intr_info;
5330 
5331         if (is_machine_check(intr_info))
5332                 return handle_machine_check(vcpu);
5333 
5334         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5335                 return 1;  /* already handled by vmx_vcpu_run() */
5336 
5337         if (is_no_device(intr_info)) {
5338                 vmx_fpu_activate(vcpu);
5339                 return 1;
5340         }
5341 
5342         if (is_invalid_opcode(intr_info)) {
5343                 if (is_guest_mode(vcpu)) {
5344                         kvm_queue_exception(vcpu, UD_VECTOR);
5345                         return 1;
5346                 }
5347                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5348                 if (er != EMULATE_DONE)
5349                         kvm_queue_exception(vcpu, UD_VECTOR);
5350                 return 1;
5351         }
5352 
5353         error_code = 0;
5354         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5355                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5356 
5357         /*
5358          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5359          * MMIO, it is better to report an internal error.
5360          * See the comments in vmx_handle_exit.
5361          */
5362         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5363             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5364                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5365                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5366                 vcpu->run->internal.ndata = 3;
5367                 vcpu->run->internal.data[0] = vect_info;
5368                 vcpu->run->internal.data[1] = intr_info;
5369                 vcpu->run->internal.data[2] = error_code;
5370                 return 0;
5371         }
5372 
5373         if (is_page_fault(intr_info)) {
5374                 /* EPT won't cause page fault directly */
5375                 BUG_ON(enable_ept);
5376                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5377                 trace_kvm_page_fault(cr2, error_code);
5378 
5379                 if (kvm_event_needs_reinjection(vcpu))
5380                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5381                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5382         }
5383 
5384         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5385 
5386         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5387                 return handle_rmode_exception(vcpu, ex_no, error_code);
5388 
5389         switch (ex_no) {
5390         case AC_VECTOR:
5391                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5392                 return 1;
5393         case DB_VECTOR:
5394                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5395                 if (!(vcpu->guest_debug &
5396                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5397                         vcpu->arch.dr6 &= ~15;
5398                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5399                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5400                                 skip_emulated_instruction(vcpu);
5401 
5402                         kvm_queue_exception(vcpu, DB_VECTOR);
5403                         return 1;
5404                 }
5405                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5406                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5407                 /* fall through */
5408         case BP_VECTOR:
5409                 /*
5410                  * Update instruction length as we may reinject #BP from
5411                  * user space while in guest debugging mode. Reading it for
5412                  * #DB as well causes no harm, it is not used in that case.
5413                  */
5414                 vmx->vcpu.arch.event_exit_inst_len =
5415                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5416                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5417                 rip = kvm_rip_read(vcpu);
5418                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5419                 kvm_run->debug.arch.exception = ex_no;
5420                 break;
5421         default:
5422                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5423                 kvm_run->ex.exception = ex_no;
5424                 kvm_run->ex.error_code = error_code;
5425                 break;
5426         }
5427         return 0;
5428 }
5429 
5430 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5431 {
5432         ++vcpu->stat.irq_exits;
5433         return 1;
5434 }
5435 
5436 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5437 {
5438         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5439         return 0;
5440 }
5441 
5442 static int handle_io(struct kvm_vcpu *vcpu)
5443 {
5444         unsigned long exit_qualification;
5445         int size, in, string;
5446         unsigned port;
5447 
5448         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5449         string = (exit_qualification & 16) != 0;
5450         in = (exit_qualification & 8) != 0;
5451 
5452         ++vcpu->stat.io_exits;
5453 
5454         if (string || in)
5455                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5456 
5457         port = exit_qualification >> 16;
5458         size = (exit_qualification & 7) + 1;
5459         skip_emulated_instruction(vcpu);
5460 
5461         return kvm_fast_pio_out(vcpu, size, port);
5462 }
5463 
5464 static void
5465 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5466 {
5467         /*
5468          * Patch in the VMCALL instruction:
5469          */
5470         hypercall[0] = 0x0f;
5471         hypercall[1] = 0x01;
5472         hypercall[2] = 0xc1;
5473 }
5474 
5475 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5476 {
5477         unsigned long always_on = VMXON_CR0_ALWAYSON;
5478         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5479 
5480         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5481                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5482             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5483                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5484         return (val & always_on) == always_on;
5485 }
5486 
5487 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5488 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5489 {
5490         if (is_guest_mode(vcpu)) {
5491                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5492                 unsigned long orig_val = val;
5493 
5494                 /*
5495                  * We get here when L2 changed cr0 in a way that did not change
5496                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5497                  * but did change L0 shadowed bits. So we first calculate the
5498                  * effective cr0 value that L1 would like to write into the
5499                  * hardware. It consists of the L2-owned bits from the new
5500                  * value combined with the L1-owned bits from L1's guest_cr0.
5501                  */
5502                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5503                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5504 
5505                 if (!nested_cr0_valid(vcpu, val))
5506                         return 1;
5507 
5508                 if (kvm_set_cr0(vcpu, val))
5509                         return 1;
5510                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5511                 return 0;
5512         } else {
5513                 if (to_vmx(vcpu)->nested.vmxon &&
5514                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5515                         return 1;
5516                 return kvm_set_cr0(vcpu, val);
5517         }
5518 }
5519 
5520 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5521 {
5522         if (is_guest_mode(vcpu)) {
5523                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5524                 unsigned long orig_val = val;
5525 
5526                 /* analogously to handle_set_cr0 */
5527                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5528                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5529                 if (kvm_set_cr4(vcpu, val))
5530                         return 1;
5531                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5532                 return 0;
5533         } else
5534                 return kvm_set_cr4(vcpu, val);
5535 }
5536 
5537 /* called to set cr0 as appropriate for clts instruction exit. */
5538 static void handle_clts(struct kvm_vcpu *vcpu)
5539 {
5540         if (is_guest_mode(vcpu)) {
5541                 /*
5542                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5543                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5544                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5545                  */
5546                 vmcs_writel(CR0_READ_SHADOW,
5547                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5548                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5549         } else
5550                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5551 }
5552 
5553 static int handle_cr(struct kvm_vcpu *vcpu)
5554 {
5555         unsigned long exit_qualification, val;
5556         int cr;
5557         int reg;
5558         int err;
5559 
5560         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5561         cr = exit_qualification & 15;
5562         reg = (exit_qualification >> 8) & 15;
5563         switch ((exit_qualification >> 4) & 3) {
5564         case 0: /* mov to cr */
5565                 val = kvm_register_readl(vcpu, reg);
5566                 trace_kvm_cr_write(cr, val);
5567                 switch (cr) {
5568                 case 0:
5569                         err = handle_set_cr0(vcpu, val);
5570                         kvm_complete_insn_gp(vcpu, err);
5571                         return 1;
5572                 case 3:
5573                         err = kvm_set_cr3(vcpu, val);
5574                         kvm_complete_insn_gp(vcpu, err);
5575                         return 1;
5576                 case 4:
5577                         err = handle_set_cr4(vcpu, val);
5578                         kvm_complete_insn_gp(vcpu, err);
5579                         return 1;
5580                 case 8: {
5581                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5582                                 u8 cr8 = (u8)val;
5583                                 err = kvm_set_cr8(vcpu, cr8);
5584                                 kvm_complete_insn_gp(vcpu, err);
5585                                 if (lapic_in_kernel(vcpu))
5586                                         return 1;
5587                                 if (cr8_prev <= cr8)
5588                                         return 1;
5589                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5590                                 return 0;
5591                         }
5592                 }
5593                 break;
5594         case 2: /* clts */
5595                 handle_clts(vcpu);
5596                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5597                 skip_emulated_instruction(vcpu);
5598                 vmx_fpu_activate(vcpu);
5599                 return 1;
5600         case 1: /*mov from cr*/
5601                 switch (cr) {
5602                 case 3:
5603                         val = kvm_read_cr3(vcpu);
5604                         kvm_register_write(vcpu, reg, val);
5605                         trace_kvm_cr_read(cr, val);
5606                         skip_emulated_instruction(vcpu);
5607                         return 1;
5608                 case 8:
5609                         val = kvm_get_cr8(vcpu);
5610                         kvm_register_write(vcpu, reg, val);
5611                         trace_kvm_cr_read(cr, val);
5612                         skip_emulated_instruction(vcpu);
5613                         return 1;
5614                 }
5615                 break;
5616         case 3: /* lmsw */
5617                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5618                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5619                 kvm_lmsw(vcpu, val);
5620 
5621                 skip_emulated_instruction(vcpu);
5622                 return 1;
5623         default:
5624                 break;
5625         }
5626         vcpu->run->exit_reason = 0;
5627         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5628                (int)(exit_qualification >> 4) & 3, cr);
5629         return 0;
5630 }
5631 
5632 static int handle_dr(struct kvm_vcpu *vcpu)
5633 {
5634         unsigned long exit_qualification;
5635         int dr, dr7, reg;
5636 
5637         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5639 
5640         /* First, if DR does not exist, trigger UD */
5641         if (!kvm_require_dr(vcpu, dr))
5642                 return 1;
5643 
5644         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5645         if (!kvm_require_cpl(vcpu, 0))
5646                 return 1;
5647         dr7 = vmcs_readl(GUEST_DR7);
5648         if (dr7 & DR7_GD) {
5649                 /*
5650                  * As the vm-exit takes precedence over the debug trap, we
5651                  * need to emulate the latter, either for the host or the
5652                  * guest debugging itself.
5653                  */
5654                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5655                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5656                         vcpu->run->debug.arch.dr7 = dr7;
5657                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5658                         vcpu->run->debug.arch.exception = DB_VECTOR;
5659                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5660                         return 0;
5661                 } else {
5662                         vcpu->arch.dr6 &= ~15;
5663                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5664                         kvm_queue_exception(vcpu, DB_VECTOR);
5665                         return 1;
5666                 }
5667         }
5668 
5669         if (vcpu->guest_debug == 0) {
5670                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5671                                 CPU_BASED_MOV_DR_EXITING);
5672 
5673                 /*
5674                  * No more DR vmexits; force a reload of the debug registers
5675                  * and reenter on this instruction.  The next vmexit will
5676                  * retrieve the full state of the debug registers.
5677                  */
5678                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5679                 return 1;
5680         }
5681 
5682         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5683         if (exit_qualification & TYPE_MOV_FROM_DR) {
5684                 unsigned long val;
5685 
5686                 if (kvm_get_dr(vcpu, dr, &val))
5687                         return 1;
5688                 kvm_register_write(vcpu, reg, val);
5689         } else
5690                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5691                         return 1;
5692 
5693         skip_emulated_instruction(vcpu);
5694         return 1;
5695 }
5696 
5697 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5698 {
5699         return vcpu->arch.dr6;
5700 }
5701 
5702 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5703 {
5704 }
5705 
5706 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5707 {
5708         get_debugreg(vcpu->arch.db[0], 0);
5709         get_debugreg(vcpu->arch.db[1], 1);
5710         get_debugreg(vcpu->arch.db[2], 2);
5711         get_debugreg(vcpu->arch.db[3], 3);
5712         get_debugreg(vcpu->arch.dr6, 6);
5713         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5714 
5715         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5716         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5717 }
5718 
5719 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5720 {
5721         vmcs_writel(GUEST_DR7, val);
5722 }
5723 
5724 static int handle_cpuid(struct kvm_vcpu *vcpu)
5725 {
5726         kvm_emulate_cpuid(vcpu);
5727         return 1;
5728 }
5729 
5730 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5731 {
5732         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5733         struct msr_data msr_info;
5734 
5735         msr_info.index = ecx;
5736         msr_info.host_initiated = false;
5737         if (vmx_get_msr(vcpu, &msr_info)) {
5738                 trace_kvm_msr_read_ex(ecx);
5739                 kvm_inject_gp(vcpu, 0);
5740                 return 1;
5741         }
5742 
5743         trace_kvm_msr_read(ecx, msr_info.data);
5744 
5745         /* FIXME: handling of bits 32:63 of rax, rdx */
5746         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5747         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5748         skip_emulated_instruction(vcpu);
5749         return 1;
5750 }
5751 
5752 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5753 {
5754         struct msr_data msr;
5755         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5756         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5757                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5758 
5759         msr.data = data;
5760         msr.index = ecx;
5761         msr.host_initiated = false;
5762         if (kvm_set_msr(vcpu, &msr) != 0) {
5763                 trace_kvm_msr_write_ex(ecx, data);
5764                 kvm_inject_gp(vcpu, 0);
5765                 return 1;
5766         }
5767 
5768         trace_kvm_msr_write(ecx, data);
5769         skip_emulated_instruction(vcpu);
5770         return 1;
5771 }
5772 
5773 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5774 {
5775         kvm_make_request(KVM_REQ_EVENT, vcpu);
5776         return 1;
5777 }
5778 
5779 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5780 {
5781         u32 cpu_based_vm_exec_control;
5782 
5783         /* clear pending irq */
5784         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5785         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5786         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5787 
5788         kvm_make_request(KVM_REQ_EVENT, vcpu);
5789 
5790         ++vcpu->stat.irq_window_exits;
5791         return 1;
5792 }
5793 
5794 static int handle_halt(struct kvm_vcpu *vcpu)
5795 {
5796         return kvm_emulate_halt(vcpu);
5797 }
5798 
5799 static int handle_vmcall(struct kvm_vcpu *vcpu)
5800 {
5801         return kvm_emulate_hypercall(vcpu);
5802 }
5803 
5804 static int handle_invd(struct kvm_vcpu *vcpu)
5805 {
5806         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5807 }
5808 
5809 static int handle_invlpg(struct kvm_vcpu *vcpu)
5810 {
5811         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5812 
5813         kvm_mmu_invlpg(vcpu, exit_qualification);
5814         skip_emulated_instruction(vcpu);
5815         return 1;
5816 }
5817 
5818 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5819 {
5820         int err;
5821 
5822         err = kvm_rdpmc(vcpu);
5823         kvm_complete_insn_gp(vcpu, err);
5824 
5825         return 1;
5826 }
5827 
5828 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5829 {
5830         kvm_emulate_wbinvd(vcpu);
5831         return 1;
5832 }
5833 
5834 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5835 {
5836         u64 new_bv = kvm_read_edx_eax(vcpu);
5837         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5838 
5839         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5840                 skip_emulated_instruction(vcpu);
5841         return 1;
5842 }
5843 
5844 static int handle_xsaves(struct kvm_vcpu *vcpu)
5845 {
5846         skip_emulated_instruction(vcpu);
5847         WARN(1, "this should never happen\n");
5848         return 1;
5849 }
5850 
5851 static int handle_xrstors(struct kvm_vcpu *vcpu)
5852 {
5853         skip_emulated_instruction(vcpu);
5854         WARN(1, "this should never happen\n");
5855         return 1;
5856 }
5857 
5858 static int handle_apic_access(struct kvm_vcpu *vcpu)
5859 {
5860         if (likely(fasteoi)) {
5861                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5862                 int access_type, offset;
5863 
5864                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5865                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5866                 /*
5867                  * Sane guest uses MOV to write EOI, with written value
5868                  * not cared. So make a short-circuit here by avoiding
5869                  * heavy instruction emulation.
5870                  */
5871                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5872                     (offset == APIC_EOI)) {
5873                         kvm_lapic_set_eoi(vcpu);
5874                         skip_emulated_instruction(vcpu);
5875                         return 1;
5876                 }
5877         }
5878         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5879 }
5880 
5881 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5882 {
5883         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5884         int vector = exit_qualification & 0xff;
5885 
5886         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5887         kvm_apic_set_eoi_accelerated(vcpu, vector);
5888         return 1;
5889 }
5890 
5891 static int handle_apic_write(struct kvm_vcpu *vcpu)
5892 {
5893         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5894         u32 offset = exit_qualification & 0xfff;
5895 
5896         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5897         kvm_apic_write_nodecode(vcpu, offset);
5898         return 1;
5899 }
5900 
5901 static int handle_task_switch(struct kvm_vcpu *vcpu)
5902 {
5903         struct vcpu_vmx *vmx = to_vmx(vcpu);
5904         unsigned long exit_qualification;
5905         bool has_error_code = false;
5906         u32 error_code = 0;
5907         u16 tss_selector;
5908         int reason, type, idt_v, idt_index;
5909 
5910         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5911         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5912         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5913 
5914         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5915 
5916         reason = (u32)exit_qualification >> 30;
5917         if (reason == TASK_SWITCH_GATE && idt_v) {
5918                 switch (type) {
5919                 case INTR_TYPE_NMI_INTR:
5920                         vcpu->arch.nmi_injected = false;
5921                         vmx_set_nmi_mask(vcpu, true);
5922                         break;
5923                 case INTR_TYPE_EXT_INTR:
5924                 case INTR_TYPE_SOFT_INTR:
5925                         kvm_clear_interrupt_queue(vcpu);
5926                         break;
5927                 case INTR_TYPE_HARD_EXCEPTION:
5928                         if (vmx->idt_vectoring_info &
5929                             VECTORING_INFO_DELIVER_CODE_MASK) {
5930                                 has_error_code = true;
5931                                 error_code =
5932                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5933                         }
5934                         /* fall through */
5935                 case INTR_TYPE_SOFT_EXCEPTION:
5936                         kvm_clear_exception_queue(vcpu);
5937                         break;
5938                 default:
5939                         break;
5940                 }
5941         }
5942         tss_selector = exit_qualification;
5943 
5944         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5945                        type != INTR_TYPE_EXT_INTR &&
5946                        type != INTR_TYPE_NMI_INTR))
5947                 skip_emulated_instruction(vcpu);
5948 
5949         if (kvm_task_switch(vcpu, tss_selector,
5950                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5951                             has_error_code, error_code) == EMULATE_FAIL) {
5952                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5953                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5954                 vcpu->run->internal.ndata = 0;
5955                 return 0;
5956         }
5957 
5958         /*
5959          * TODO: What about debug traps on tss switch?
5960          *       Are we supposed to inject them and update dr6?
5961          */
5962 
5963         return 1;
5964 }
5965 
5966 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5967 {
5968         unsigned long exit_qualification;
5969         gpa_t gpa;
5970         u32 error_code;
5971         int gla_validity;
5972 
5973         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5974 
5975         gla_validity = (exit_qualification >> 7) & 0x3;
5976         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5977                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5978                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5979                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5980                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5981                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5982                         (long unsigned int)exit_qualification);
5983                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5984                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5985                 return 0;
5986         }
5987 
5988         /*
5989          * EPT violation happened while executing iret from NMI,
5990          * "blocked by NMI" bit has to be set before next VM entry.
5991          * There are errata that may cause this bit to not be set:
5992          * AAK134, BY25.
5993          */
5994         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5995                         cpu_has_virtual_nmis() &&
5996                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5997                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5998 
5999         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6000         trace_kvm_page_fault(gpa, exit_qualification);
6001 
6002         /* It is a write fault? */
6003         error_code = exit_qualification & PFERR_WRITE_MASK;
6004         /* It is a fetch fault? */
6005         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6006         /* ept page table is present? */
6007         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6008 
6009         vcpu->arch.exit_qualification = exit_qualification;
6010 
6011         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6012 }
6013 
6014 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6015 {
6016         int ret;
6017         gpa_t gpa;
6018 
6019         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6020         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6021                 skip_emulated_instruction(vcpu);
6022                 trace_kvm_fast_mmio(gpa);
6023                 return 1;
6024         }
6025 
6026         ret = handle_mmio_page_fault(vcpu, gpa, true);
6027         if (likely(ret == RET_MMIO_PF_EMULATE))
6028                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6029                                               EMULATE_DONE;
6030 
6031         if (unlikely(ret == RET_MMIO_PF_INVALID))
6032                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6033 
6034         if (unlikely(ret == RET_MMIO_PF_RETRY))
6035                 return 1;
6036 
6037         /* It is the real ept misconfig */
6038         WARN_ON(1);
6039 
6040         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6041         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6042 
6043         return 0;
6044 }
6045 
6046 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6047 {
6048         u32 cpu_based_vm_exec_control;
6049 
6050         /* clear pending NMI */
6051         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6052         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6053         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6054         ++vcpu->stat.nmi_window_exits;
6055         kvm_make_request(KVM_REQ_EVENT, vcpu);
6056 
6057         return 1;
6058 }
6059 
6060 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6061 {
6062         struct vcpu_vmx *vmx = to_vmx(vcpu);
6063         enum emulation_result err = EMULATE_DONE;
6064         int ret = 1;
6065         u32 cpu_exec_ctrl;
6066         bool intr_window_requested;
6067         unsigned count = 130;
6068 
6069         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6070         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6071 
6072         while (vmx->emulation_required && count-- != 0) {
6073                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6074                         return handle_interrupt_window(&vmx->vcpu);
6075 
6076                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6077                         return 1;
6078 
6079                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6080 
6081                 if (err == EMULATE_USER_EXIT) {
6082                         ++vcpu->stat.mmio_exits;
6083                         ret = 0;
6084                         goto out;
6085                 }
6086 
6087                 if (err != EMULATE_DONE) {
6088                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6089                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6090                         vcpu->run->internal.ndata = 0;
6091                         return 0;
6092                 }
6093 
6094                 if (vcpu->arch.halt_request) {
6095                         vcpu->arch.halt_request = 0;
6096                         ret = kvm_vcpu_halt(vcpu);
6097                         goto out;
6098                 }
6099 
6100                 if (signal_pending(current))
6101                         goto out;
6102                 if (need_resched())
6103                         schedule();
6104         }
6105 
6106 out:
6107         return ret;
6108 }
6109 
6110 static int __grow_ple_window(int val)
6111 {
6112         if (ple_window_grow < 1)
6113                 return ple_window;
6114 
6115         val = min(val, ple_window_actual_max);
6116 
6117         if (ple_window_grow < ple_window)
6118                 val *= ple_window_grow;
6119         else
6120                 val += ple_window_grow;
6121 
6122         return val;
6123 }
6124 
6125 static int __shrink_ple_window(int val, int modifier, int minimum)
6126 {
6127         if (modifier < 1)
6128                 return ple_window;
6129 
6130         if (modifier < ple_window)
6131                 val /= modifier;
6132         else
6133                 val -= modifier;
6134 
6135         return max(val, minimum);
6136 }
6137 
6138 static void grow_ple_window(struct kvm_vcpu *vcpu)
6139 {
6140         struct vcpu_vmx *vmx = to_vmx(vcpu);
6141         int old = vmx->ple_window;
6142 
6143         vmx->ple_window = __grow_ple_window(old);
6144 
6145         if (vmx->ple_window != old)
6146                 vmx->ple_window_dirty = true;
6147 
6148         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6149 }
6150 
6151 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6152 {
6153         struct vcpu_vmx *vmx = to_vmx(vcpu);
6154         int old = vmx->ple_window;
6155 
6156         vmx->ple_window = __shrink_ple_window(old,
6157                                               ple_window_shrink, ple_window);
6158 
6159         if (vmx->ple_window != old)
6160                 vmx->ple_window_dirty = true;
6161 
6162         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6163 }
6164 
6165 /*
6166  * ple_window_actual_max is computed to be one grow_ple_window() below
6167  * ple_window_max. (See __grow_ple_window for the reason.)
6168  * This prevents overflows, because ple_window_max is int.
6169  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6170  * this process.
6171  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6172  */
6173 static void update_ple_window_actual_max(void)
6174 {
6175         ple_window_actual_max =
6176                         __shrink_ple_window(max(ple_window_max, ple_window),
6177                                             ple_window_grow, INT_MIN);
6178 }
6179 
6180 /*
6181  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6182  */
6183 static void wakeup_handler(void)
6184 {
6185         struct kvm_vcpu *vcpu;
6186         int cpu = smp_processor_id();
6187 
6188         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6189         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6190                         blocked_vcpu_list) {
6191                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6192 
6193                 if (pi_test_on(pi_desc) == 1)
6194                         kvm_vcpu_kick(vcpu);
6195         }
6196         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6197 }
6198 
6199 static __init int hardware_setup(void)
6200 {
6201         int r = -ENOMEM, i, msr;
6202 
6203         rdmsrl_safe(MSR_EFER, &host_efer);
6204 
6205         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6206                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6207 
6208         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6209         if (!vmx_io_bitmap_a)
6210                 return r;
6211 
6212         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6213         if (!vmx_io_bitmap_b)
6214                 goto out;
6215 
6216         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6217         if (!vmx_msr_bitmap_legacy)
6218                 goto out1;
6219 
6220         vmx_msr_bitmap_legacy_x2apic =
6221                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6222         if (!vmx_msr_bitmap_legacy_x2apic)
6223                 goto out2;
6224 
6225         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6226         if (!vmx_msr_bitmap_longmode)
6227                 goto out3;
6228 
6229         vmx_msr_bitmap_longmode_x2apic =
6230                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6231         if (!vmx_msr_bitmap_longmode_x2apic)
6232                 goto out4;
6233 
6234         if (nested) {
6235                 vmx_msr_bitmap_nested =
6236                         (unsigned long *)__get_free_page(GFP_KERNEL);
6237                 if (!vmx_msr_bitmap_nested)
6238                         goto out5;
6239         }
6240 
6241         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6242         if (!vmx_vmread_bitmap)
6243                 goto out6;
6244 
6245         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6246         if (!vmx_vmwrite_bitmap)
6247                 goto out7;
6248 
6249         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6250         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6251 
6252         /*
6253          * Allow direct access to the PC debug port (it is often used for I/O
6254          * delays, but the vmexits simply slow things down).
6255          */
6256         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6257         clear_bit(0x80, vmx_io_bitmap_a);
6258 
6259         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6260 
6261         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6262         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6263         if (nested)
6264                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6265 
6266         if (setup_vmcs_config(&vmcs_config) < 0) {
6267                 r = -EIO;
6268                 goto out8;
6269         }
6270 
6271         if (boot_cpu_has(X86_FEATURE_NX))
6272                 kvm_enable_efer_bits(EFER_NX);
6273 
6274         if (!cpu_has_vmx_vpid())
6275                 enable_vpid = 0;
6276         if (!cpu_has_vmx_shadow_vmcs())
6277                 enable_shadow_vmcs = 0;
6278         if (enable_shadow_vmcs)
6279                 init_vmcs_shadow_fields();
6280 
6281         if (!cpu_has_vmx_ept() ||
6282             !cpu_has_vmx_ept_4levels()) {
6283                 enable_ept = 0;
6284                 enable_unrestricted_guest = 0;
6285                 enable_ept_ad_bits = 0;
6286         }
6287 
6288         if (!cpu_has_vmx_ept_ad_bits())
6289                 enable_ept_ad_bits = 0;
6290 
6291         if (!cpu_has_vmx_unrestricted_guest())
6292                 enable_unrestricted_guest = 0;
6293 
6294         if (!cpu_has_vmx_flexpriority())
6295                 flexpriority_enabled = 0;
6296 
6297         /*
6298          * set_apic_access_page_addr() is used to reload apic access
6299          * page upon invalidation.  No need to do anything if not
6300          * using the APIC_ACCESS_ADDR VMCS field.
6301          */
6302         if (!flexpriority_enabled)
6303                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6304 
6305         if (!cpu_has_vmx_tpr_shadow())
6306                 kvm_x86_ops->update_cr8_intercept = NULL;
6307 
6308         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6309                 kvm_disable_largepages();
6310 
6311         if (!cpu_has_vmx_ple())
6312                 ple_gap = 0;
6313 
6314         if (!cpu_has_vmx_apicv())
6315                 enable_apicv = 0;
6316 
6317         if (cpu_has_vmx_tsc_scaling()) {
6318                 kvm_has_tsc_control = true;
6319                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6320                 kvm_tsc_scaling_ratio_frac_bits = 48;
6321         }
6322 
6323         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6324         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6325         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6326         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6327         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6328         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6329         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6330 
6331         memcpy(vmx_msr_bitmap_legacy_x2apic,
6332                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6333         memcpy(vmx_msr_bitmap_longmode_x2apic,
6334                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6335 
6336         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6337 
6338         if (enable_apicv) {
6339                 for (msr = 0x800; msr <= 0x8ff; msr++)
6340                         vmx_disable_intercept_msr_read_x2apic(msr);
6341 
6342                 /* According SDM, in x2apic mode, the whole id reg is used.
6343                  * But in KVM, it only use the highest eight bits. Need to
6344                  * intercept it */
6345                 vmx_enable_intercept_msr_read_x2apic(0x802);
6346                 /* TMCCT */
6347                 vmx_enable_intercept_msr_read_x2apic(0x839);
6348                 /* TPR */
6349                 vmx_disable_intercept_msr_write_x2apic(0x808);
6350                 /* EOI */
6351                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6352                 /* SELF-IPI */
6353                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6354         }
6355 
6356         if (enable_ept) {
6357                 kvm_mmu_set_mask_ptes(0ull,
6358                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6359                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6360                         0ull, VMX_EPT_EXECUTABLE_MASK);
6361                 ept_set_mmio_spte_mask();
6362                 kvm_enable_tdp();
6363         } else
6364                 kvm_disable_tdp();
6365 
6366         update_ple_window_actual_max();
6367 
6368         /*
6369          * Only enable PML when hardware supports PML feature, and both EPT
6370          * and EPT A/D bit features are enabled -- PML depends on them to work.
6371          */
6372         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6373                 enable_pml = 0;
6374 
6375         if (!enable_pml) {
6376                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6377                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6378                 kvm_x86_ops->flush_log_dirty = NULL;
6379                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6380         }
6381 
6382         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6383 
6384         return alloc_kvm_area();
6385 
6386 out8:
6387         free_page((unsigned long)vmx_vmwrite_bitmap);
6388 out7:
6389         free_page((unsigned long)vmx_vmread_bitmap);
6390 out6:
6391         if (nested)
6392                 free_page((unsigned long)vmx_msr_bitmap_nested);
6393 out5:
6394         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6395 out4:
6396         free_page((unsigned long)vmx_msr_bitmap_longmode);
6397 out3:
6398         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6399 out2:
6400         free_page((unsigned long)vmx_msr_bitmap_legacy);
6401 out1:
6402         free_page((unsigned long)vmx_io_bitmap_b);
6403 out:
6404         free_page((unsigned long)vmx_io_bitmap_a);
6405 
6406     return r;
6407 }
6408 
6409 static __exit void hardware_unsetup(void)
6410 {
6411         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6412         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6413         free_page((unsigned long)vmx_msr_bitmap_legacy);
6414         free_page((unsigned long)vmx_msr_bitmap_longmode);
6415         free_page((unsigned long)vmx_io_bitmap_b);
6416         free_page((unsigned long)vmx_io_bitmap_a);
6417         free_page((unsigned long)vmx_vmwrite_bitmap);
6418         free_page((unsigned long)vmx_vmread_bitmap);
6419         if (nested)
6420                 free_page((unsigned long)vmx_msr_bitmap_nested);
6421 
6422         free_kvm_area();
6423 }
6424 
6425 /*
6426  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6427  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6428  */
6429 static int handle_pause(struct kvm_vcpu *vcpu)
6430 {
6431         if (ple_gap)
6432                 grow_ple_window(vcpu);
6433 
6434         skip_emulated_instruction(vcpu);
6435         kvm_vcpu_on_spin(vcpu);
6436 
6437         return 1;
6438 }
6439 
6440 static int handle_nop(struct kvm_vcpu *vcpu)
6441 {
6442         skip_emulated_instruction(vcpu);
6443         return 1;
6444 }
6445 
6446 static int handle_mwait(struct kvm_vcpu *vcpu)
6447 {
6448         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6449         return handle_nop(vcpu);
6450 }
6451 
6452 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6453 {
6454         return 1;
6455 }
6456 
6457 static int handle_monitor(struct kvm_vcpu *vcpu)
6458 {
6459         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6460         return handle_nop(vcpu);
6461 }
6462 
6463 /*
6464  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6465  * We could reuse a single VMCS for all the L2 guests, but we also want the
6466  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6467  * allows keeping them loaded on the processor, and in the future will allow
6468  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6469  * every entry if they never change.
6470  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6471  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6472  *
6473  * The following functions allocate and free a vmcs02 in this pool.
6474  */
6475 
6476 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6477 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6478 {
6479         struct vmcs02_list *item;
6480         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6481                 if (item->vmptr == vmx->nested.current_vmptr) {
6482                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6483                         return &item->vmcs02;
6484                 }
6485 
6486         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6487                 /* Recycle the least recently used VMCS. */
6488                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6489                                        struct vmcs02_list, list);
6490                 item->vmptr = vmx->nested.current_vmptr;
6491                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6492                 return &item->vmcs02;
6493         }
6494 
6495         /* Create a new VMCS */
6496         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6497         if (!item)
6498                 return NULL;
6499         item->vmcs02.vmcs = alloc_vmcs();
6500         if (!item->vmcs02.vmcs) {
6501                 kfree(item);
6502                 return NULL;
6503         }
6504         loaded_vmcs_init(&item->vmcs02);
6505         item->vmptr = vmx->nested.current_vmptr;
6506         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6507         vmx->nested.vmcs02_num++;
6508         return &item->vmcs02;
6509 }
6510 
6511 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6512 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6513 {
6514         struct vmcs02_list *item;
6515         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6516                 if (item->vmptr == vmptr) {
6517                         free_loaded_vmcs(&item->vmcs02);
6518                         list_del(&item->list);
6519                         kfree(item);
6520                         vmx->nested.vmcs02_num--;
6521                         return;
6522                 }
6523 }
6524 
6525 /*
6526  * Free all VMCSs saved for this vcpu, except the one pointed by
6527  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6528  * must be &vmx->vmcs01.
6529  */
6530 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6531 {
6532         struct vmcs02_list *item, *n;
6533 
6534         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6535         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6536                 /*
6537                  * Something will leak if the above WARN triggers.  Better than
6538                  * a use-after-free.
6539                  */
6540                 if (vmx->loaded_vmcs == &item->vmcs02)
6541                         continue;
6542 
6543                 free_loaded_vmcs(&item->vmcs02);
6544                 list_del(&item->list);
6545                 kfree(item);
6546                 vmx->nested.vmcs02_num--;
6547         }
6548 }
6549 
6550 /*
6551  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6552  * set the success or error code of an emulated VMX instruction, as specified
6553  * by Vol 2B, VMX Instruction Reference, "Conventions".
6554  */
6555 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6556 {
6557         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6558                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6559                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6560 }
6561 
6562 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6563 {
6564         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6565                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6566                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6567                         | X86_EFLAGS_CF);
6568 }
6569 
6570 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6571                                         u32 vm_instruction_error)
6572 {
6573         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6574                 /*
6575                  * failValid writes the error number to the current VMCS, which
6576                  * can't be done there isn't a current VMCS.
6577                  */
6578                 nested_vmx_failInvalid(vcpu);
6579                 return;
6580         }
6581         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6582                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6583                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6584                         | X86_EFLAGS_ZF);
6585         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6586         /*
6587          * We don't need to force a shadow sync because
6588          * VM_INSTRUCTION_ERROR is not shadowed
6589          */
6590 }
6591 
6592 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6593 {
6594         /* TODO: not to reset guest simply here. */
6595         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6596         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6597 }
6598 
6599 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6600 {
6601         struct vcpu_vmx *vmx =
6602                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6603 
6604         vmx->nested.preemption_timer_expired = true;
6605         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6606         kvm_vcpu_kick(&vmx->vcpu);
6607 
6608         return HRTIMER_NORESTART;
6609 }
6610 
6611 /*
6612  * Decode the memory-address operand of a vmx instruction, as recorded on an
6613  * exit caused by such an instruction (run by a guest hypervisor).
6614  * On success, returns 0. When the operand is invalid, returns 1 and throws
6615  * #UD or #GP.
6616  */
6617 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6618                                  unsigned long exit_qualification,
6619                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6620 {
6621         gva_t off;
6622         bool exn;
6623         struct kvm_segment s;
6624 
6625         /*
6626          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6627          * Execution", on an exit, vmx_instruction_info holds most of the
6628          * addressing components of the operand. Only the displacement part
6629          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6630          * For how an actual address is calculated from all these components,
6631          * refer to Vol. 1, "Operand Addressing".
6632          */
6633         int  scaling = vmx_instruction_info & 3;
6634         int  addr_size = (vmx_instruction_info >> 7) & 7;
6635         bool is_reg = vmx_instruction_info & (1u << 10);
6636         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6637         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6638         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6639         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6640         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6641 
6642         if (is_reg) {
6643                 kvm_queue_exception(vcpu, UD_VECTOR);
6644                 return 1;
6645         }
6646 
6647         /* Addr = segment_base + offset */
6648         /* offset = base + [index * scale] + displacement */
6649         off = exit_qualification; /* holds the displacement */
6650         if (base_is_valid)
6651                 off += kvm_register_read(vcpu, base_reg);
6652         if (index_is_valid)
6653                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6654         vmx_get_segment(vcpu, &s, seg_reg);
6655         *ret = s.base + off;
6656 
6657         if (addr_size == 1) /* 32 bit */
6658                 *ret &= 0xffffffff;
6659 
6660         /* Checks for #GP/#SS exceptions. */
6661         exn = false;
6662         if (is_long_mode(vcpu)) {
6663                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6664                  * non-canonical form. This is the only check on the memory
6665                  * destination for long mode!
6666                  */
6667                 exn = is_noncanonical_address(*ret);
6668         } else if (is_protmode(vcpu)) {
6669                 /* Protected mode: apply checks for segment validity in the
6670                  * following order:
6671                  * - segment type check (#GP(0) may be thrown)
6672                  * - usability check (#GP(0)/#SS(0))
6673                  * - limit check (#GP(0)/#SS(0))
6674                  */
6675                 if (wr)
6676                         /* #GP(0) if the destination operand is located in a
6677                          * read-only data segment or any code segment.
6678                          */
6679                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6680                 else
6681                         /* #GP(0) if the source operand is located in an
6682                          * execute-only code segment
6683                          */
6684                         exn = ((s.type & 0xa) == 8);
6685                 if (exn) {
6686                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6687                         return 1;
6688                 }
6689                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6690                  */
6691                 exn = (s.unusable != 0);
6692                 /* Protected mode: #GP(0)/#SS(0) if the memory
6693                  * operand is outside the segment limit.
6694                  */
6695                 exn = exn || (off + sizeof(u64) > s.limit);
6696         }
6697         if (exn) {
6698                 kvm_queue_exception_e(vcpu,
6699                                       seg_reg == VCPU_SREG_SS ?
6700                                                 SS_VECTOR : GP_VECTOR,
6701                                       0);
6702                 return 1;
6703         }
6704 
6705         return 0;
6706 }
6707 
6708 /*
6709  * This function performs the various checks including
6710  * - if it's 4KB aligned
6711  * - No bits beyond the physical address width are set
6712  * - Returns 0 on success or else 1
6713  * (Intel SDM Section 30.3)
6714  */
6715 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6716                                   gpa_t *vmpointer)
6717 {
6718         gva_t gva;
6719         gpa_t vmptr;
6720         struct x86_exception e;
6721         struct page *page;
6722         struct vcpu_vmx *vmx = to_vmx(vcpu);
6723         int maxphyaddr = cpuid_maxphyaddr(vcpu);