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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/x86.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * derived from drivers/kvm/kvm_main.c
  5  *
  6  * Copyright (C) 2006 Qumranet, Inc.
  7  * Copyright (C) 2008 Qumranet, Inc.
  8  * Copyright IBM Corporation, 2008
  9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 10  *
 11  * Authors:
 12  *   Avi Kivity   <avi@qumranet.com>
 13  *   Yaniv Kamay  <yaniv@qumranet.com>
 14  *   Amit Shah    <amit.shah@qumranet.com>
 15  *   Ben-Ami Yassour <benami@il.ibm.com>
 16  *
 17  * This work is licensed under the terms of the GNU GPL, version 2.  See
 18  * the COPYING file in the top-level directory.
 19  *
 20  */
 21 
 22 #include <linux/kvm_host.h>
 23 #include "irq.h"
 24 #include "mmu.h"
 25 #include "i8254.h"
 26 #include "tss.h"
 27 #include "kvm_cache_regs.h"
 28 #include "x86.h"
 29 #include "cpuid.h"
 30 #include "pmu.h"
 31 #include "hyperv.h"
 32 
 33 #include <linux/clocksource.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/kvm.h>
 36 #include <linux/fs.h>
 37 #include <linux/vmalloc.h>
 38 #include <linux/export.h>
 39 #include <linux/moduleparam.h>
 40 #include <linux/mman.h>
 41 #include <linux/highmem.h>
 42 #include <linux/iommu.h>
 43 #include <linux/intel-iommu.h>
 44 #include <linux/cpufreq.h>
 45 #include <linux/user-return-notifier.h>
 46 #include <linux/srcu.h>
 47 #include <linux/slab.h>
 48 #include <linux/perf_event.h>
 49 #include <linux/uaccess.h>
 50 #include <linux/hash.h>
 51 #include <linux/pci.h>
 52 #include <linux/timekeeper_internal.h>
 53 #include <linux/pvclock_gtod.h>
 54 #include <linux/kvm_irqfd.h>
 55 #include <linux/irqbypass.h>
 56 #include <linux/sched/stat.h>
 57 #include <linux/mem_encrypt.h>
 58 
 59 #include <trace/events/kvm.h>
 60 
 61 #include <asm/debugreg.h>
 62 #include <asm/msr.h>
 63 #include <asm/desc.h>
 64 #include <asm/mce.h>
 65 #include <linux/kernel_stat.h>
 66 #include <asm/fpu/internal.h> /* Ugh! */
 67 #include <asm/pvclock.h>
 68 #include <asm/div64.h>
 69 #include <asm/irq_remapping.h>
 70 #include <asm/mshyperv.h>
 71 #include <asm/hypervisor.h>
 72 #include <asm/intel_pt.h>
 73 
 74 #define CREATE_TRACE_POINTS
 75 #include "trace.h"
 76 
 77 #define MAX_IO_MSRS 256
 78 #define KVM_MAX_MCE_BANKS 32
 79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
 80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
 81 
 82 #define emul_to_vcpu(ctxt) \
 83         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
 84 
 85 /* EFER defaults:
 86  * - enable syscall per default because its emulated by KVM
 87  * - enable LME and LMA per default on 64 bit KVM
 88  */
 89 #ifdef CONFIG_X86_64
 90 static
 91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
 92 #else
 93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
 94 #endif
 95 
 96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
 97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
 98 
 99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
108 
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32  __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64  __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138 
139 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
140 unsigned int __read_mostly lapic_timer_advance_ns = 1000;
141 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
143 
144 static bool __read_mostly vector_hashing = true;
145 module_param(vector_hashing, bool, S_IRUGO);
146 
147 bool __read_mostly enable_vmware_backdoor = false;
148 module_param(enable_vmware_backdoor, bool, S_IRUGO);
149 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150 
151 static bool __read_mostly force_emulation_prefix = false;
152 module_param(force_emulation_prefix, bool, S_IRUGO);
153 
154 #define KVM_NR_SHARED_MSRS 16
155 
156 struct kvm_shared_msrs_global {
157         int nr;
158         u32 msrs[KVM_NR_SHARED_MSRS];
159 };
160 
161 struct kvm_shared_msrs {
162         struct user_return_notifier urn;
163         bool registered;
164         struct kvm_shared_msr_values {
165                 u64 host;
166                 u64 curr;
167         } values[KVM_NR_SHARED_MSRS];
168 };
169 
170 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
171 static struct kvm_shared_msrs __percpu *shared_msrs;
172 
173 struct kvm_stats_debugfs_item debugfs_entries[] = {
174         { "pf_fixed", VCPU_STAT(pf_fixed) },
175         { "pf_guest", VCPU_STAT(pf_guest) },
176         { "tlb_flush", VCPU_STAT(tlb_flush) },
177         { "invlpg", VCPU_STAT(invlpg) },
178         { "exits", VCPU_STAT(exits) },
179         { "io_exits", VCPU_STAT(io_exits) },
180         { "mmio_exits", VCPU_STAT(mmio_exits) },
181         { "signal_exits", VCPU_STAT(signal_exits) },
182         { "irq_window", VCPU_STAT(irq_window_exits) },
183         { "nmi_window", VCPU_STAT(nmi_window_exits) },
184         { "halt_exits", VCPU_STAT(halt_exits) },
185         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
186         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
187         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
188         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
189         { "hypercalls", VCPU_STAT(hypercalls) },
190         { "request_irq", VCPU_STAT(request_irq_exits) },
191         { "irq_exits", VCPU_STAT(irq_exits) },
192         { "host_state_reload", VCPU_STAT(host_state_reload) },
193         { "fpu_reload", VCPU_STAT(fpu_reload) },
194         { "insn_emulation", VCPU_STAT(insn_emulation) },
195         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
196         { "irq_injections", VCPU_STAT(irq_injections) },
197         { "nmi_injections", VCPU_STAT(nmi_injections) },
198         { "req_event", VCPU_STAT(req_event) },
199         { "l1d_flush", VCPU_STAT(l1d_flush) },
200         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204         { "mmu_flooded", VM_STAT(mmu_flooded) },
205         { "mmu_recycled", VM_STAT(mmu_recycled) },
206         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
207         { "mmu_unsync", VM_STAT(mmu_unsync) },
208         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
209         { "largepages", VM_STAT(lpages) },
210         { "max_mmu_page_hash_collisions",
211                 VM_STAT(max_mmu_page_hash_collisions) },
212         { NULL }
213 };
214 
215 u64 __read_mostly host_xcr0;
216 
217 struct kmem_cache *x86_fpu_cache;
218 EXPORT_SYMBOL_GPL(x86_fpu_cache);
219 
220 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
221 
222 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
223 {
224         int i;
225         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226                 vcpu->arch.apf.gfns[i] = ~0;
227 }
228 
229 static void kvm_on_user_return(struct user_return_notifier *urn)
230 {
231         unsigned slot;
232         struct kvm_shared_msrs *locals
233                 = container_of(urn, struct kvm_shared_msrs, urn);
234         struct kvm_shared_msr_values *values;
235         unsigned long flags;
236 
237         /*
238          * Disabling irqs at this point since the following code could be
239          * interrupted and executed through kvm_arch_hardware_disable()
240          */
241         local_irq_save(flags);
242         if (locals->registered) {
243                 locals->registered = false;
244                 user_return_notifier_unregister(urn);
245         }
246         local_irq_restore(flags);
247         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
248                 values = &locals->values[slot];
249                 if (values->host != values->curr) {
250                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
251                         values->curr = values->host;
252                 }
253         }
254 }
255 
256 static void shared_msr_update(unsigned slot, u32 msr)
257 {
258         u64 value;
259         unsigned int cpu = smp_processor_id();
260         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
261 
262         /* only read, and nobody should modify it at this time,
263          * so don't need lock */
264         if (slot >= shared_msrs_global.nr) {
265                 printk(KERN_ERR "kvm: invalid MSR slot!");
266                 return;
267         }
268         rdmsrl_safe(msr, &value);
269         smsr->values[slot].host = value;
270         smsr->values[slot].curr = value;
271 }
272 
273 void kvm_define_shared_msr(unsigned slot, u32 msr)
274 {
275         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
276         shared_msrs_global.msrs[slot] = msr;
277         if (slot >= shared_msrs_global.nr)
278                 shared_msrs_global.nr = slot + 1;
279 }
280 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
281 
282 static void kvm_shared_msr_cpu_online(void)
283 {
284         unsigned i;
285 
286         for (i = 0; i < shared_msrs_global.nr; ++i)
287                 shared_msr_update(i, shared_msrs_global.msrs[i]);
288 }
289 
290 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
291 {
292         unsigned int cpu = smp_processor_id();
293         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
294         int err;
295 
296         if (((value ^ smsr->values[slot].curr) & mask) == 0)
297                 return 0;
298         smsr->values[slot].curr = value;
299         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
300         if (err)
301                 return 1;
302 
303         if (!smsr->registered) {
304                 smsr->urn.on_user_return = kvm_on_user_return;
305                 user_return_notifier_register(&smsr->urn);
306                 smsr->registered = true;
307         }
308         return 0;
309 }
310 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
311 
312 static void drop_user_return_notifiers(void)
313 {
314         unsigned int cpu = smp_processor_id();
315         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
316 
317         if (smsr->registered)
318                 kvm_on_user_return(&smsr->urn);
319 }
320 
321 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
322 {
323         return vcpu->arch.apic_base;
324 }
325 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
326 
327 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
328 {
329         return kvm_apic_mode(kvm_get_apic_base(vcpu));
330 }
331 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
332 
333 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
334 {
335         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
337         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
339 
340         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
341                 return 1;
342         if (!msr_info->host_initiated) {
343                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
344                         return 1;
345                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
346                         return 1;
347         }
348 
349         kvm_lapic_set_base(vcpu, msr_info->data);
350         return 0;
351 }
352 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
353 
354 asmlinkage __visible void kvm_spurious_fault(void)
355 {
356         /* Fault while not rebooting.  We want the trace. */
357         BUG();
358 }
359 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
360 
361 #define EXCPT_BENIGN            0
362 #define EXCPT_CONTRIBUTORY      1
363 #define EXCPT_PF                2
364 
365 static int exception_class(int vector)
366 {
367         switch (vector) {
368         case PF_VECTOR:
369                 return EXCPT_PF;
370         case DE_VECTOR:
371         case TS_VECTOR:
372         case NP_VECTOR:
373         case SS_VECTOR:
374         case GP_VECTOR:
375                 return EXCPT_CONTRIBUTORY;
376         default:
377                 break;
378         }
379         return EXCPT_BENIGN;
380 }
381 
382 #define EXCPT_FAULT             0
383 #define EXCPT_TRAP              1
384 #define EXCPT_ABORT             2
385 #define EXCPT_INTERRUPT         3
386 
387 static int exception_type(int vector)
388 {
389         unsigned int mask;
390 
391         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392                 return EXCPT_INTERRUPT;
393 
394         mask = 1 << vector;
395 
396         /* #DB is trap, as instruction watchpoints are handled elsewhere */
397         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
398                 return EXCPT_TRAP;
399 
400         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
401                 return EXCPT_ABORT;
402 
403         /* Reserved exceptions will result in fault */
404         return EXCPT_FAULT;
405 }
406 
407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
408 {
409         unsigned nr = vcpu->arch.exception.nr;
410         bool has_payload = vcpu->arch.exception.has_payload;
411         unsigned long payload = vcpu->arch.exception.payload;
412 
413         if (!has_payload)
414                 return;
415 
416         switch (nr) {
417         case DB_VECTOR:
418                 /*
419                  * "Certain debug exceptions may clear bit 0-3.  The
420                  * remaining contents of the DR6 register are never
421                  * cleared by the processor".
422                  */
423                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
424                 /*
425                  * DR6.RTM is set by all #DB exceptions that don't clear it.
426                  */
427                 vcpu->arch.dr6 |= DR6_RTM;
428                 vcpu->arch.dr6 |= payload;
429                 /*
430                  * Bit 16 should be set in the payload whenever the #DB
431                  * exception should clear DR6.RTM. This makes the payload
432                  * compatible with the pending debug exceptions under VMX.
433                  * Though not currently documented in the SDM, this also
434                  * makes the payload compatible with the exit qualification
435                  * for #DB exceptions under VMX.
436                  */
437                 vcpu->arch.dr6 ^= payload & DR6_RTM;
438                 break;
439         case PF_VECTOR:
440                 vcpu->arch.cr2 = payload;
441                 break;
442         }
443 
444         vcpu->arch.exception.has_payload = false;
445         vcpu->arch.exception.payload = 0;
446 }
447 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
448 
449 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
450                 unsigned nr, bool has_error, u32 error_code,
451                 bool has_payload, unsigned long payload, bool reinject)
452 {
453         u32 prev_nr;
454         int class1, class2;
455 
456         kvm_make_request(KVM_REQ_EVENT, vcpu);
457 
458         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
459         queue:
460                 if (has_error && !is_protmode(vcpu))
461                         has_error = false;
462                 if (reinject) {
463                         /*
464                          * On vmentry, vcpu->arch.exception.pending is only
465                          * true if an event injection was blocked by
466                          * nested_run_pending.  In that case, however,
467                          * vcpu_enter_guest requests an immediate exit,
468                          * and the guest shouldn't proceed far enough to
469                          * need reinjection.
470                          */
471                         WARN_ON_ONCE(vcpu->arch.exception.pending);
472                         vcpu->arch.exception.injected = true;
473                         if (WARN_ON_ONCE(has_payload)) {
474                                 /*
475                                  * A reinjected event has already
476                                  * delivered its payload.
477                                  */
478                                 has_payload = false;
479                                 payload = 0;
480                         }
481                 } else {
482                         vcpu->arch.exception.pending = true;
483                         vcpu->arch.exception.injected = false;
484                 }
485                 vcpu->arch.exception.has_error_code = has_error;
486                 vcpu->arch.exception.nr = nr;
487                 vcpu->arch.exception.error_code = error_code;
488                 vcpu->arch.exception.has_payload = has_payload;
489                 vcpu->arch.exception.payload = payload;
490                 /*
491                  * In guest mode, payload delivery should be deferred,
492                  * so that the L1 hypervisor can intercept #PF before
493                  * CR2 is modified (or intercept #DB before DR6 is
494                  * modified under nVMX).  However, for ABI
495                  * compatibility with KVM_GET_VCPU_EVENTS and
496                  * KVM_SET_VCPU_EVENTS, we can't delay payload
497                  * delivery unless userspace has enabled this
498                  * functionality via the per-VM capability,
499                  * KVM_CAP_EXCEPTION_PAYLOAD.
500                  */
501                 if (!vcpu->kvm->arch.exception_payload_enabled ||
502                     !is_guest_mode(vcpu))
503                         kvm_deliver_exception_payload(vcpu);
504                 return;
505         }
506 
507         /* to check exception */
508         prev_nr = vcpu->arch.exception.nr;
509         if (prev_nr == DF_VECTOR) {
510                 /* triple fault -> shutdown */
511                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
512                 return;
513         }
514         class1 = exception_class(prev_nr);
515         class2 = exception_class(nr);
516         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
518                 /*
519                  * Generate double fault per SDM Table 5-5.  Set
520                  * exception.pending = true so that the double fault
521                  * can trigger a nested vmexit.
522                  */
523                 vcpu->arch.exception.pending = true;
524                 vcpu->arch.exception.injected = false;
525                 vcpu->arch.exception.has_error_code = true;
526                 vcpu->arch.exception.nr = DF_VECTOR;
527                 vcpu->arch.exception.error_code = 0;
528                 vcpu->arch.exception.has_payload = false;
529                 vcpu->arch.exception.payload = 0;
530         } else
531                 /* replace previous exception with a new one in a hope
532                    that instruction re-execution will regenerate lost
533                    exception */
534                 goto queue;
535 }
536 
537 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538 {
539         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
540 }
541 EXPORT_SYMBOL_GPL(kvm_queue_exception);
542 
543 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544 {
545         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
546 }
547 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548 
549 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550                                   unsigned long payload)
551 {
552         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
553 }
554 
555 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556                                     u32 error_code, unsigned long payload)
557 {
558         kvm_multiple_exception(vcpu, nr, true, error_code,
559                                true, payload, false);
560 }
561 
562 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
563 {
564         if (err)
565                 kvm_inject_gp(vcpu, 0);
566         else
567                 return kvm_skip_emulated_instruction(vcpu);
568 
569         return 1;
570 }
571 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
572 
573 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
574 {
575         ++vcpu->stat.pf_guest;
576         vcpu->arch.exception.nested_apf =
577                 is_guest_mode(vcpu) && fault->async_page_fault;
578         if (vcpu->arch.exception.nested_apf) {
579                 vcpu->arch.apf.nested_apf_token = fault->address;
580                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581         } else {
582                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
583                                         fault->address);
584         }
585 }
586 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
587 
588 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
589 {
590         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
592         else
593                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
594 
595         return fault->nested_page_fault;
596 }
597 
598 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599 {
600         atomic_inc(&vcpu->arch.nmi_queued);
601         kvm_make_request(KVM_REQ_NMI, vcpu);
602 }
603 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604 
605 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606 {
607         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
608 }
609 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610 
611 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612 {
613         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
614 }
615 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
616 
617 /*
618  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
619  * a #GP and return false.
620  */
621 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
622 {
623         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624                 return true;
625         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
626         return false;
627 }
628 EXPORT_SYMBOL_GPL(kvm_require_cpl);
629 
630 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631 {
632         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
633                 return true;
634 
635         kvm_queue_exception(vcpu, UD_VECTOR);
636         return false;
637 }
638 EXPORT_SYMBOL_GPL(kvm_require_dr);
639 
640 /*
641  * This function will be used to read from the physical memory of the currently
642  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
643  * can read from guest physical or from the guest's guest physical memory.
644  */
645 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646                             gfn_t ngfn, void *data, int offset, int len,
647                             u32 access)
648 {
649         struct x86_exception exception;
650         gfn_t real_gfn;
651         gpa_t ngpa;
652 
653         ngpa     = gfn_to_gpa(ngfn);
654         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
655         if (real_gfn == UNMAPPED_GVA)
656                 return -EFAULT;
657 
658         real_gfn = gpa_to_gfn(real_gfn);
659 
660         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
661 }
662 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663 
664 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
665                                void *data, int offset, int len, u32 access)
666 {
667         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668                                        data, offset, len, access);
669 }
670 
671 /*
672  * Load the pae pdptrs.  Return true is they are all valid.
673  */
674 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
675 {
676         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
678         int i;
679         int ret;
680         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
681 
682         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683                                       offset * sizeof(u64), sizeof(pdpte),
684                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
685         if (ret < 0) {
686                 ret = 0;
687                 goto out;
688         }
689         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
690                 if ((pdpte[i] & PT_PRESENT_MASK) &&
691                     (pdpte[i] &
692                      vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
693                         ret = 0;
694                         goto out;
695                 }
696         }
697         ret = 1;
698 
699         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
700         __set_bit(VCPU_EXREG_PDPTR,
701                   (unsigned long *)&vcpu->arch.regs_avail);
702         __set_bit(VCPU_EXREG_PDPTR,
703                   (unsigned long *)&vcpu->arch.regs_dirty);
704 out:
705 
706         return ret;
707 }
708 EXPORT_SYMBOL_GPL(load_pdptrs);
709 
710 bool pdptrs_changed(struct kvm_vcpu *vcpu)
711 {
712         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
713         bool changed = true;
714         int offset;
715         gfn_t gfn;
716         int r;
717 
718         if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
719                 return false;
720 
721         if (!test_bit(VCPU_EXREG_PDPTR,
722                       (unsigned long *)&vcpu->arch.regs_avail))
723                 return true;
724 
725         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
729         if (r < 0)
730                 goto out;
731         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
732 out:
733 
734         return changed;
735 }
736 EXPORT_SYMBOL_GPL(pdptrs_changed);
737 
738 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
739 {
740         unsigned long old_cr0 = kvm_read_cr0(vcpu);
741         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
742 
743         cr0 |= X86_CR0_ET;
744 
745 #ifdef CONFIG_X86_64
746         if (cr0 & 0xffffffff00000000UL)
747                 return 1;
748 #endif
749 
750         cr0 &= ~CR0_RESERVED_BITS;
751 
752         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753                 return 1;
754 
755         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756                 return 1;
757 
758         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
759 #ifdef CONFIG_X86_64
760                 if ((vcpu->arch.efer & EFER_LME)) {
761                         int cs_db, cs_l;
762 
763                         if (!is_pae(vcpu))
764                                 return 1;
765                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
766                         if (cs_l)
767                                 return 1;
768                 } else
769 #endif
770                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
771                                                  kvm_read_cr3(vcpu)))
772                         return 1;
773         }
774 
775         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776                 return 1;
777 
778         kvm_x86_ops->set_cr0(vcpu, cr0);
779 
780         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
781                 kvm_clear_async_pf_completion_queue(vcpu);
782                 kvm_async_pf_hash_reset(vcpu);
783         }
784 
785         if ((cr0 ^ old_cr0) & update_bits)
786                 kvm_mmu_reset_context(vcpu);
787 
788         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
791                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
792 
793         return 0;
794 }
795 EXPORT_SYMBOL_GPL(kvm_set_cr0);
796 
797 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
798 {
799         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
800 }
801 EXPORT_SYMBOL_GPL(kvm_lmsw);
802 
803 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
804 {
805         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806                         !vcpu->guest_xcr0_loaded) {
807                 /* kvm_set_xcr() also depends on this */
808                 if (vcpu->arch.xcr0 != host_xcr0)
809                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810                 vcpu->guest_xcr0_loaded = 1;
811         }
812 }
813 
814 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
815 {
816         if (vcpu->guest_xcr0_loaded) {
817                 if (vcpu->arch.xcr0 != host_xcr0)
818                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819                 vcpu->guest_xcr0_loaded = 0;
820         }
821 }
822 
823 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
824 {
825         u64 xcr0 = xcr;
826         u64 old_xcr0 = vcpu->arch.xcr0;
827         u64 valid_bits;
828 
829         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
830         if (index != XCR_XFEATURE_ENABLED_MASK)
831                 return 1;
832         if (!(xcr0 & XFEATURE_MASK_FP))
833                 return 1;
834         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
835                 return 1;
836 
837         /*
838          * Do not allow the guest to set bits that we do not support
839          * saving.  However, xcr0 bit 0 is always set, even if the
840          * emulated CPU does not support XSAVE (see fx_init).
841          */
842         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
843         if (xcr0 & ~valid_bits)
844                 return 1;
845 
846         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
847             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
848                 return 1;
849 
850         if (xcr0 & XFEATURE_MASK_AVX512) {
851                 if (!(xcr0 & XFEATURE_MASK_YMM))
852                         return 1;
853                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
854                         return 1;
855         }
856         vcpu->arch.xcr0 = xcr0;
857 
858         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
859                 kvm_update_cpuid(vcpu);
860         return 0;
861 }
862 
863 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
864 {
865         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
866             __kvm_set_xcr(vcpu, index, xcr)) {
867                 kvm_inject_gp(vcpu, 0);
868                 return 1;
869         }
870         return 0;
871 }
872 EXPORT_SYMBOL_GPL(kvm_set_xcr);
873 
874 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
875 {
876         unsigned long old_cr4 = kvm_read_cr4(vcpu);
877         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
878                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
879 
880         if (cr4 & CR4_RESERVED_BITS)
881                 return 1;
882 
883         if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
884                 return 1;
885 
886         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
887                 return 1;
888 
889         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
890                 return 1;
891 
892         if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
893                 return 1;
894 
895         if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
896                 return 1;
897 
898         if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
899                 return 1;
900 
901         if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
902                 return 1;
903 
904         if (is_long_mode(vcpu)) {
905                 if (!(cr4 & X86_CR4_PAE))
906                         return 1;
907         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
908                    && ((cr4 ^ old_cr4) & pdptr_bits)
909                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
910                                    kvm_read_cr3(vcpu)))
911                 return 1;
912 
913         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
914                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
915                         return 1;
916 
917                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
918                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
919                         return 1;
920         }
921 
922         if (kvm_x86_ops->set_cr4(vcpu, cr4))
923                 return 1;
924 
925         if (((cr4 ^ old_cr4) & pdptr_bits) ||
926             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
927                 kvm_mmu_reset_context(vcpu);
928 
929         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
930                 kvm_update_cpuid(vcpu);
931 
932         return 0;
933 }
934 EXPORT_SYMBOL_GPL(kvm_set_cr4);
935 
936 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
937 {
938         bool skip_tlb_flush = false;
939 #ifdef CONFIG_X86_64
940         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
941 
942         if (pcid_enabled) {
943                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
944                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
945         }
946 #endif
947 
948         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
949                 if (!skip_tlb_flush) {
950                         kvm_mmu_sync_roots(vcpu);
951                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
952                 }
953                 return 0;
954         }
955 
956         if (is_long_mode(vcpu) &&
957             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
958                 return 1;
959         else if (is_pae(vcpu) && is_paging(vcpu) &&
960                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
961                 return 1;
962 
963         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
964         vcpu->arch.cr3 = cr3;
965         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
966 
967         return 0;
968 }
969 EXPORT_SYMBOL_GPL(kvm_set_cr3);
970 
971 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
972 {
973         if (cr8 & CR8_RESERVED_BITS)
974                 return 1;
975         if (lapic_in_kernel(vcpu))
976                 kvm_lapic_set_tpr(vcpu, cr8);
977         else
978                 vcpu->arch.cr8 = cr8;
979         return 0;
980 }
981 EXPORT_SYMBOL_GPL(kvm_set_cr8);
982 
983 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
984 {
985         if (lapic_in_kernel(vcpu))
986                 return kvm_lapic_get_cr8(vcpu);
987         else
988                 return vcpu->arch.cr8;
989 }
990 EXPORT_SYMBOL_GPL(kvm_get_cr8);
991 
992 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
993 {
994         int i;
995 
996         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
997                 for (i = 0; i < KVM_NR_DB_REGS; i++)
998                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
999                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1000         }
1001 }
1002 
1003 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1004 {
1005         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1006                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1007 }
1008 
1009 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1010 {
1011         unsigned long dr7;
1012 
1013         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014                 dr7 = vcpu->arch.guest_debug_dr7;
1015         else
1016                 dr7 = vcpu->arch.dr7;
1017         kvm_x86_ops->set_dr7(vcpu, dr7);
1018         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1019         if (dr7 & DR7_BP_EN_MASK)
1020                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1021 }
1022 
1023 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1024 {
1025         u64 fixed = DR6_FIXED_1;
1026 
1027         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1028                 fixed |= DR6_RTM;
1029         return fixed;
1030 }
1031 
1032 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1033 {
1034         switch (dr) {
1035         case 0 ... 3:
1036                 vcpu->arch.db[dr] = val;
1037                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038                         vcpu->arch.eff_db[dr] = val;
1039                 break;
1040         case 4:
1041                 /* fall through */
1042         case 6:
1043                 if (val & 0xffffffff00000000ULL)
1044                         return -1; /* #GP */
1045                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1046                 kvm_update_dr6(vcpu);
1047                 break;
1048         case 5:
1049                 /* fall through */
1050         default: /* 7 */
1051                 if (val & 0xffffffff00000000ULL)
1052                         return -1; /* #GP */
1053                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1054                 kvm_update_dr7(vcpu);
1055                 break;
1056         }
1057 
1058         return 0;
1059 }
1060 
1061 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1062 {
1063         if (__kvm_set_dr(vcpu, dr, val)) {
1064                 kvm_inject_gp(vcpu, 0);
1065                 return 1;
1066         }
1067         return 0;
1068 }
1069 EXPORT_SYMBOL_GPL(kvm_set_dr);
1070 
1071 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1072 {
1073         switch (dr) {
1074         case 0 ... 3:
1075                 *val = vcpu->arch.db[dr];
1076                 break;
1077         case 4:
1078                 /* fall through */
1079         case 6:
1080                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081                         *val = vcpu->arch.dr6;
1082                 else
1083                         *val = kvm_x86_ops->get_dr6(vcpu);
1084                 break;
1085         case 5:
1086                 /* fall through */
1087         default: /* 7 */
1088                 *val = vcpu->arch.dr7;
1089                 break;
1090         }
1091         return 0;
1092 }
1093 EXPORT_SYMBOL_GPL(kvm_get_dr);
1094 
1095 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1096 {
1097         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1098         u64 data;
1099         int err;
1100 
1101         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1102         if (err)
1103                 return err;
1104         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1105         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1106         return err;
1107 }
1108 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1109 
1110 /*
1111  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1112  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1113  *
1114  * This list is modified at module load time to reflect the
1115  * capabilities of the host cpu. This capabilities test skips MSRs that are
1116  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1117  * may depend on host virtualization features rather than host cpu features.
1118  */
1119 
1120 static u32 msrs_to_save[] = {
1121         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1122         MSR_STAR,
1123 #ifdef CONFIG_X86_64
1124         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1125 #endif
1126         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1127         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1128         MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES,
1129         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1130         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1131         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1132         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1133         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1134         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1135 };
1136 
1137 static unsigned num_msrs_to_save;
1138 
1139 static u32 emulated_msrs[] = {
1140         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1141         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1142         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1143         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1144         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1145         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1146         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1147         HV_X64_MSR_RESET,
1148         HV_X64_MSR_VP_INDEX,
1149         HV_X64_MSR_VP_RUNTIME,
1150         HV_X64_MSR_SCONTROL,
1151         HV_X64_MSR_STIMER0_CONFIG,
1152         HV_X64_MSR_VP_ASSIST_PAGE,
1153         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1154         HV_X64_MSR_TSC_EMULATION_STATUS,
1155 
1156         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1157         MSR_KVM_PV_EOI_EN,
1158 
1159         MSR_IA32_TSC_ADJUST,
1160         MSR_IA32_TSCDEADLINE,
1161         MSR_IA32_MISC_ENABLE,
1162         MSR_IA32_MCG_STATUS,
1163         MSR_IA32_MCG_CTL,
1164         MSR_IA32_MCG_EXT_CTL,
1165         MSR_IA32_SMBASE,
1166         MSR_SMI_COUNT,
1167         MSR_PLATFORM_INFO,
1168         MSR_MISC_FEATURES_ENABLES,
1169         MSR_AMD64_VIRT_SPEC_CTRL,
1170 };
1171 
1172 static unsigned num_emulated_msrs;
1173 
1174 /*
1175  * List of msr numbers which are used to expose MSR-based features that
1176  * can be used by a hypervisor to validate requested CPU features.
1177  */
1178 static u32 msr_based_features[] = {
1179         MSR_IA32_VMX_BASIC,
1180         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1181         MSR_IA32_VMX_PINBASED_CTLS,
1182         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1183         MSR_IA32_VMX_PROCBASED_CTLS,
1184         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1185         MSR_IA32_VMX_EXIT_CTLS,
1186         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1187         MSR_IA32_VMX_ENTRY_CTLS,
1188         MSR_IA32_VMX_MISC,
1189         MSR_IA32_VMX_CR0_FIXED0,
1190         MSR_IA32_VMX_CR0_FIXED1,
1191         MSR_IA32_VMX_CR4_FIXED0,
1192         MSR_IA32_VMX_CR4_FIXED1,
1193         MSR_IA32_VMX_VMCS_ENUM,
1194         MSR_IA32_VMX_PROCBASED_CTLS2,
1195         MSR_IA32_VMX_EPT_VPID_CAP,
1196         MSR_IA32_VMX_VMFUNC,
1197 
1198         MSR_F10H_DECFG,
1199         MSR_IA32_UCODE_REV,
1200         MSR_IA32_ARCH_CAPABILITIES,
1201 };
1202 
1203 static unsigned int num_msr_based_features;
1204 
1205 u64 kvm_get_arch_capabilities(void)
1206 {
1207         u64 data;
1208 
1209         rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1210 
1211         /*
1212          * If we're doing cache flushes (either "always" or "cond")
1213          * we will do one whenever the guest does a vmlaunch/vmresume.
1214          * If an outer hypervisor is doing the cache flush for us
1215          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1216          * capability to the guest too, and if EPT is disabled we're not
1217          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1218          * require a nested hypervisor to do a flush of its own.
1219          */
1220         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1221                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1222 
1223         return data;
1224 }
1225 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1226 
1227 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1228 {
1229         switch (msr->index) {
1230         case MSR_IA32_ARCH_CAPABILITIES:
1231                 msr->data = kvm_get_arch_capabilities();
1232                 break;
1233         case MSR_IA32_UCODE_REV:
1234                 rdmsrl_safe(msr->index, &msr->data);
1235                 break;
1236         default:
1237                 if (kvm_x86_ops->get_msr_feature(msr))
1238                         return 1;
1239         }
1240         return 0;
1241 }
1242 
1243 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1244 {
1245         struct kvm_msr_entry msr;
1246         int r;
1247 
1248         msr.index = index;
1249         r = kvm_get_msr_feature(&msr);
1250         if (r)
1251                 return r;
1252 
1253         *data = msr.data;
1254 
1255         return 0;
1256 }
1257 
1258 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1259 {
1260         if (efer & efer_reserved_bits)
1261                 return false;
1262 
1263         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1264                         return false;
1265 
1266         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1267                         return false;
1268 
1269         return true;
1270 }
1271 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1272 
1273 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1274 {
1275         u64 old_efer = vcpu->arch.efer;
1276 
1277         if (!kvm_valid_efer(vcpu, efer))
1278                 return 1;
1279 
1280         if (is_paging(vcpu)
1281             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1282                 return 1;
1283 
1284         efer &= ~EFER_LMA;
1285         efer |= vcpu->arch.efer & EFER_LMA;
1286 
1287         kvm_x86_ops->set_efer(vcpu, efer);
1288 
1289         /* Update reserved bits */
1290         if ((efer ^ old_efer) & EFER_NX)
1291                 kvm_mmu_reset_context(vcpu);
1292 
1293         return 0;
1294 }
1295 
1296 void kvm_enable_efer_bits(u64 mask)
1297 {
1298        efer_reserved_bits &= ~mask;
1299 }
1300 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1301 
1302 /*
1303  * Writes msr value into into the appropriate "register".
1304  * Returns 0 on success, non-0 otherwise.
1305  * Assumes vcpu_load() was already called.
1306  */
1307 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1308 {
1309         switch (msr->index) {
1310         case MSR_FS_BASE:
1311         case MSR_GS_BASE:
1312         case MSR_KERNEL_GS_BASE:
1313         case MSR_CSTAR:
1314         case MSR_LSTAR:
1315                 if (is_noncanonical_address(msr->data, vcpu))
1316                         return 1;
1317                 break;
1318         case MSR_IA32_SYSENTER_EIP:
1319         case MSR_IA32_SYSENTER_ESP:
1320                 /*
1321                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1322                  * non-canonical address is written on Intel but not on
1323                  * AMD (which ignores the top 32-bits, because it does
1324                  * not implement 64-bit SYSENTER).
1325                  *
1326                  * 64-bit code should hence be able to write a non-canonical
1327                  * value on AMD.  Making the address canonical ensures that
1328                  * vmentry does not fail on Intel after writing a non-canonical
1329                  * value, and that something deterministic happens if the guest
1330                  * invokes 64-bit SYSENTER.
1331                  */
1332                 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1333         }
1334         return kvm_x86_ops->set_msr(vcpu, msr);
1335 }
1336 EXPORT_SYMBOL_GPL(kvm_set_msr);
1337 
1338 /*
1339  * Adapt set_msr() to msr_io()'s calling convention
1340  */
1341 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1342 {
1343         struct msr_data msr;
1344         int r;
1345 
1346         msr.index = index;
1347         msr.host_initiated = true;
1348         r = kvm_get_msr(vcpu, &msr);
1349         if (r)
1350                 return r;
1351 
1352         *data = msr.data;
1353         return 0;
1354 }
1355 
1356 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1357 {
1358         struct msr_data msr;
1359 
1360         msr.data = *data;
1361         msr.index = index;
1362         msr.host_initiated = true;
1363         return kvm_set_msr(vcpu, &msr);
1364 }
1365 
1366 #ifdef CONFIG_X86_64
1367 struct pvclock_gtod_data {
1368         seqcount_t      seq;
1369 
1370         struct { /* extract of a clocksource struct */
1371                 int vclock_mode;
1372                 u64     cycle_last;
1373                 u64     mask;
1374                 u32     mult;
1375                 u32     shift;
1376         } clock;
1377 
1378         u64             boot_ns;
1379         u64             nsec_base;
1380         u64             wall_time_sec;
1381 };
1382 
1383 static struct pvclock_gtod_data pvclock_gtod_data;
1384 
1385 static void update_pvclock_gtod(struct timekeeper *tk)
1386 {
1387         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1388         u64 boot_ns;
1389 
1390         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1391 
1392         write_seqcount_begin(&vdata->seq);
1393 
1394         /* copy pvclock gtod data */
1395         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1396         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1397         vdata->clock.mask               = tk->tkr_mono.mask;
1398         vdata->clock.mult               = tk->tkr_mono.mult;
1399         vdata->clock.shift              = tk->tkr_mono.shift;
1400 
1401         vdata->boot_ns                  = boot_ns;
1402         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1403 
1404         vdata->wall_time_sec            = tk->xtime_sec;
1405 
1406         write_seqcount_end(&vdata->seq);
1407 }
1408 #endif
1409 
1410 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1411 {
1412         /*
1413          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1414          * vcpu_enter_guest.  This function is only called from
1415          * the physical CPU that is running vcpu.
1416          */
1417         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1418 }
1419 
1420 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1421 {
1422         int version;
1423         int r;
1424         struct pvclock_wall_clock wc;
1425         struct timespec64 boot;
1426 
1427         if (!wall_clock)
1428                 return;
1429 
1430         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1431         if (r)
1432                 return;
1433 
1434         if (version & 1)
1435                 ++version;  /* first time write, random junk */
1436 
1437         ++version;
1438 
1439         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1440                 return;
1441 
1442         /*
1443          * The guest calculates current wall clock time by adding
1444          * system time (updated by kvm_guest_time_update below) to the
1445          * wall clock specified here.  guest system time equals host
1446          * system time for us, thus we must fill in host boot time here.
1447          */
1448         getboottime64(&boot);
1449 
1450         if (kvm->arch.kvmclock_offset) {
1451                 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1452                 boot = timespec64_sub(boot, ts);
1453         }
1454         wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1455         wc.nsec = boot.tv_nsec;
1456         wc.version = version;
1457 
1458         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1459 
1460         version++;
1461         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1462 }
1463 
1464 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1465 {
1466         do_shl32_div32(dividend, divisor);
1467         return dividend;
1468 }
1469 
1470 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1471                                s8 *pshift, u32 *pmultiplier)
1472 {
1473         uint64_t scaled64;
1474         int32_t  shift = 0;
1475         uint64_t tps64;
1476         uint32_t tps32;
1477 
1478         tps64 = base_hz;
1479         scaled64 = scaled_hz;
1480         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1481                 tps64 >>= 1;
1482                 shift--;
1483         }
1484 
1485         tps32 = (uint32_t)tps64;
1486         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1487                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1488                         scaled64 >>= 1;
1489                 else
1490                         tps32 <<= 1;
1491                 shift++;
1492         }
1493 
1494         *pshift = shift;
1495         *pmultiplier = div_frac(scaled64, tps32);
1496 
1497         pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1498                  __func__, base_hz, scaled_hz, shift, *pmultiplier);
1499 }
1500 
1501 #ifdef CONFIG_X86_64
1502 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1503 #endif
1504 
1505 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1506 static unsigned long max_tsc_khz;
1507 
1508 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1509 {
1510         u64 v = (u64)khz * (1000000 + ppm);
1511         do_div(v, 1000000);
1512         return v;
1513 }
1514 
1515 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1516 {
1517         u64 ratio;
1518 
1519         /* Guest TSC same frequency as host TSC? */
1520         if (!scale) {
1521                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1522                 return 0;
1523         }
1524 
1525         /* TSC scaling supported? */
1526         if (!kvm_has_tsc_control) {
1527                 if (user_tsc_khz > tsc_khz) {
1528                         vcpu->arch.tsc_catchup = 1;
1529                         vcpu->arch.tsc_always_catchup = 1;
1530                         return 0;
1531                 } else {
1532                         WARN(1, "user requested TSC rate below hardware speed\n");
1533                         return -1;
1534                 }
1535         }
1536 
1537         /* TSC scaling required  - calculate ratio */
1538         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1539                                 user_tsc_khz, tsc_khz);
1540 
1541         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1542                 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1543                           user_tsc_khz);
1544                 return -1;
1545         }
1546 
1547         vcpu->arch.tsc_scaling_ratio = ratio;
1548         return 0;
1549 }
1550 
1551 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1552 {
1553         u32 thresh_lo, thresh_hi;
1554         int use_scaling = 0;
1555 
1556         /* tsc_khz can be zero if TSC calibration fails */
1557         if (user_tsc_khz == 0) {
1558                 /* set tsc_scaling_ratio to a safe value */
1559                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1560                 return -1;
1561         }
1562 
1563         /* Compute a scale to convert nanoseconds in TSC cycles */
1564         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1565                            &vcpu->arch.virtual_tsc_shift,
1566                            &vcpu->arch.virtual_tsc_mult);
1567         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1568 
1569         /*
1570          * Compute the variation in TSC rate which is acceptable
1571          * within the range of tolerance and decide if the
1572          * rate being applied is within that bounds of the hardware
1573          * rate.  If so, no scaling or compensation need be done.
1574          */
1575         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1576         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1577         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1578                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1579                 use_scaling = 1;
1580         }
1581         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1582 }
1583 
1584 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1585 {
1586         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1587                                       vcpu->arch.virtual_tsc_mult,
1588                                       vcpu->arch.virtual_tsc_shift);
1589         tsc += vcpu->arch.this_tsc_write;
1590         return tsc;
1591 }
1592 
1593 static inline int gtod_is_based_on_tsc(int mode)
1594 {
1595         return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1596 }
1597 
1598 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1599 {
1600 #ifdef CONFIG_X86_64
1601         bool vcpus_matched;
1602         struct kvm_arch *ka = &vcpu->kvm->arch;
1603         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1604 
1605         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1606                          atomic_read(&vcpu->kvm->online_vcpus));
1607 
1608         /*
1609          * Once the masterclock is enabled, always perform request in
1610          * order to update it.
1611          *
1612          * In order to enable masterclock, the host clocksource must be TSC
1613          * and the vcpus need to have matched TSCs.  When that happens,
1614          * perform request to enable masterclock.
1615          */
1616         if (ka->use_master_clock ||
1617             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1618                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1619 
1620         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1621                             atomic_read(&vcpu->kvm->online_vcpus),
1622                             ka->use_master_clock, gtod->clock.vclock_mode);
1623 #endif
1624 }
1625 
1626 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1627 {
1628         u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1629         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1630 }
1631 
1632 /*
1633  * Multiply tsc by a fixed point number represented by ratio.
1634  *
1635  * The most significant 64-N bits (mult) of ratio represent the
1636  * integral part of the fixed point number; the remaining N bits
1637  * (frac) represent the fractional part, ie. ratio represents a fixed
1638  * point number (mult + frac * 2^(-N)).
1639  *
1640  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1641  */
1642 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1643 {
1644         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1645 }
1646 
1647 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1648 {
1649         u64 _tsc = tsc;
1650         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1651 
1652         if (ratio != kvm_default_tsc_scaling_ratio)
1653                 _tsc = __scale_tsc(ratio, tsc);
1654 
1655         return _tsc;
1656 }
1657 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1658 
1659 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1660 {
1661         u64 tsc;
1662 
1663         tsc = kvm_scale_tsc(vcpu, rdtsc());
1664 
1665         return target_tsc - tsc;
1666 }
1667 
1668 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1669 {
1670         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1671 
1672         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1673 }
1674 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1675 
1676 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1677 {
1678         vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1679 }
1680 
1681 static inline bool kvm_check_tsc_unstable(void)
1682 {
1683 #ifdef CONFIG_X86_64
1684         /*
1685          * TSC is marked unstable when we're running on Hyper-V,
1686          * 'TSC page' clocksource is good.
1687          */
1688         if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1689                 return false;
1690 #endif
1691         return check_tsc_unstable();
1692 }
1693 
1694 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1695 {
1696         struct kvm *kvm = vcpu->kvm;
1697         u64 offset, ns, elapsed;
1698         unsigned long flags;
1699         bool matched;
1700         bool already_matched;
1701         u64 data = msr->data;
1702         bool synchronizing = false;
1703 
1704         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1705         offset = kvm_compute_tsc_offset(vcpu, data);
1706         ns = ktime_get_boot_ns();
1707         elapsed = ns - kvm->arch.last_tsc_nsec;
1708 
1709         if (vcpu->arch.virtual_tsc_khz) {
1710                 if (data == 0 && msr->host_initiated) {
1711                         /*
1712                          * detection of vcpu initialization -- need to sync
1713                          * with other vCPUs. This particularly helps to keep
1714                          * kvm_clock stable after CPU hotplug
1715                          */
1716                         synchronizing = true;
1717                 } else {
1718                         u64 tsc_exp = kvm->arch.last_tsc_write +
1719                                                 nsec_to_cycles(vcpu, elapsed);
1720                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1721                         /*
1722                          * Special case: TSC write with a small delta (1 second)
1723                          * of virtual cycle time against real time is
1724                          * interpreted as an attempt to synchronize the CPU.
1725                          */
1726                         synchronizing = data < tsc_exp + tsc_hz &&
1727                                         data + tsc_hz > tsc_exp;
1728                 }
1729         }
1730 
1731         /*
1732          * For a reliable TSC, we can match TSC offsets, and for an unstable
1733          * TSC, we add elapsed time in this computation.  We could let the
1734          * compensation code attempt to catch up if we fall behind, but
1735          * it's better to try to match offsets from the beginning.
1736          */
1737         if (synchronizing &&
1738             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1739                 if (!kvm_check_tsc_unstable()) {
1740                         offset = kvm->arch.cur_tsc_offset;
1741                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1742                 } else {
1743                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1744                         data += delta;
1745                         offset = kvm_compute_tsc_offset(vcpu, data);
1746                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1747                 }
1748                 matched = true;
1749                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1750         } else {
1751                 /*
1752                  * We split periods of matched TSC writes into generations.
1753                  * For each generation, we track the original measured
1754                  * nanosecond time, offset, and write, so if TSCs are in
1755                  * sync, we can match exact offset, and if not, we can match
1756                  * exact software computation in compute_guest_tsc()
1757                  *
1758                  * These values are tracked in kvm->arch.cur_xxx variables.
1759                  */
1760                 kvm->arch.cur_tsc_generation++;
1761                 kvm->arch.cur_tsc_nsec = ns;
1762                 kvm->arch.cur_tsc_write = data;
1763                 kvm->arch.cur_tsc_offset = offset;
1764                 matched = false;
1765                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1766                          kvm->arch.cur_tsc_generation, data);
1767         }
1768 
1769         /*
1770          * We also track th most recent recorded KHZ, write and time to
1771          * allow the matching interval to be extended at each write.
1772          */
1773         kvm->arch.last_tsc_nsec = ns;
1774         kvm->arch.last_tsc_write = data;
1775         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1776 
1777         vcpu->arch.last_guest_tsc = data;
1778 
1779         /* Keep track of which generation this VCPU has synchronized to */
1780         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1781         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1782         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1783 
1784         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1785                 update_ia32_tsc_adjust_msr(vcpu, offset);
1786 
1787         kvm_vcpu_write_tsc_offset(vcpu, offset);
1788         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1789 
1790         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1791         if (!matched) {
1792                 kvm->arch.nr_vcpus_matched_tsc = 0;
1793         } else if (!already_matched) {
1794                 kvm->arch.nr_vcpus_matched_tsc++;
1795         }
1796 
1797         kvm_track_tsc_matching(vcpu);
1798         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1799 }
1800 
1801 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1802 
1803 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1804                                            s64 adjustment)
1805 {
1806         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1807         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1808 }
1809 
1810 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1811 {
1812         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1813                 WARN_ON(adjustment < 0);
1814         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1815         adjust_tsc_offset_guest(vcpu, adjustment);
1816 }
1817 
1818 #ifdef CONFIG_X86_64
1819 
1820 static u64 read_tsc(void)
1821 {
1822         u64 ret = (u64)rdtsc_ordered();
1823         u64 last = pvclock_gtod_data.clock.cycle_last;
1824 
1825         if (likely(ret >= last))
1826                 return ret;
1827 
1828         /*
1829          * GCC likes to generate cmov here, but this branch is extremely
1830          * predictable (it's just a function of time and the likely is
1831          * very likely) and there's a data dependence, so force GCC
1832          * to generate a branch instead.  I don't barrier() because
1833          * we don't actually need a barrier, and if this function
1834          * ever gets inlined it will generate worse code.
1835          */
1836         asm volatile ("");
1837         return last;
1838 }
1839 
1840 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1841 {
1842         long v;
1843         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1844         u64 tsc_pg_val;
1845 
1846         switch (gtod->clock.vclock_mode) {
1847         case VCLOCK_HVCLOCK:
1848                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1849                                                   tsc_timestamp);
1850                 if (tsc_pg_val != U64_MAX) {
1851                         /* TSC page valid */
1852                         *mode = VCLOCK_HVCLOCK;
1853                         v = (tsc_pg_val - gtod->clock.cycle_last) &
1854                                 gtod->clock.mask;
1855                 } else {
1856                         /* TSC page invalid */
1857                         *mode = VCLOCK_NONE;
1858                 }
1859                 break;
1860         case VCLOCK_TSC:
1861                 *mode = VCLOCK_TSC;
1862                 *tsc_timestamp = read_tsc();
1863                 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1864                         gtod->clock.mask;
1865                 break;
1866         default:
1867                 *mode = VCLOCK_NONE;
1868         }
1869 
1870         if (*mode == VCLOCK_NONE)
1871                 *tsc_timestamp = v = 0;
1872 
1873         return v * gtod->clock.mult;
1874 }
1875 
1876 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1877 {
1878         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1879         unsigned long seq;
1880         int mode;
1881         u64 ns;
1882 
1883         do {
1884                 seq = read_seqcount_begin(&gtod->seq);
1885                 ns = gtod->nsec_base;
1886                 ns += vgettsc(tsc_timestamp, &mode);
1887                 ns >>= gtod->clock.shift;
1888                 ns += gtod->boot_ns;
1889         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1890         *t = ns;
1891 
1892         return mode;
1893 }
1894 
1895 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1896 {
1897         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1898         unsigned long seq;
1899         int mode;
1900         u64 ns;
1901 
1902         do {
1903                 seq = read_seqcount_begin(&gtod->seq);
1904                 ts->tv_sec = gtod->wall_time_sec;
1905                 ns = gtod->nsec_base;
1906                 ns += vgettsc(tsc_timestamp, &mode);
1907                 ns >>= gtod->clock.shift;
1908         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1909 
1910         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1911         ts->tv_nsec = ns;
1912 
1913         return mode;
1914 }
1915 
1916 /* returns true if host is using TSC based clocksource */
1917 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1918 {
1919         /* checked again under seqlock below */
1920         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1921                 return false;
1922 
1923         return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1924                                                       tsc_timestamp));
1925 }
1926 
1927 /* returns true if host is using TSC based clocksource */
1928 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1929                                            u64 *tsc_timestamp)
1930 {
1931         /* checked again under seqlock below */
1932         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1933                 return false;
1934 
1935         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1936 }
1937 #endif
1938 
1939 /*
1940  *
1941  * Assuming a stable TSC across physical CPUS, and a stable TSC
1942  * across virtual CPUs, the following condition is possible.
1943  * Each numbered line represents an event visible to both
1944  * CPUs at the next numbered event.
1945  *
1946  * "timespecX" represents host monotonic time. "tscX" represents
1947  * RDTSC value.
1948  *
1949  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1950  *
1951  * 1.  read timespec0,tsc0
1952  * 2.                                   | timespec1 = timespec0 + N
1953  *                                      | tsc1 = tsc0 + M
1954  * 3. transition to guest               | transition to guest
1955  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1956  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1957  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1958  *
1959  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1960  *
1961  *      - ret0 < ret1
1962  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1963  *              ...
1964  *      - 0 < N - M => M < N
1965  *
1966  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1967  * always the case (the difference between two distinct xtime instances
1968  * might be smaller then the difference between corresponding TSC reads,
1969  * when updating guest vcpus pvclock areas).
1970  *
1971  * To avoid that problem, do not allow visibility of distinct
1972  * system_timestamp/tsc_timestamp values simultaneously: use a master
1973  * copy of host monotonic time values. Update that master copy
1974  * in lockstep.
1975  *
1976  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1977  *
1978  */
1979 
1980 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1981 {
1982 #ifdef CONFIG_X86_64
1983         struct kvm_arch *ka = &kvm->arch;
1984         int vclock_mode;
1985         bool host_tsc_clocksource, vcpus_matched;
1986 
1987         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1988                         atomic_read(&kvm->online_vcpus));
1989 
1990         /*
1991          * If the host uses TSC clock, then passthrough TSC as stable
1992          * to the guest.
1993          */
1994         host_tsc_clocksource = kvm_get_time_and_clockread(
1995                                         &ka->master_kernel_ns,
1996                                         &ka->master_cycle_now);
1997 
1998         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1999                                 && !ka->backwards_tsc_observed
2000                                 && !ka->boot_vcpu_runs_old_kvmclock;
2001 
2002         if (ka->use_master_clock)
2003                 atomic_set(&kvm_guest_has_master_clock, 1);
2004 
2005         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2006         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2007                                         vcpus_matched);
2008 #endif
2009 }
2010 
2011 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2012 {
2013         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2014 }
2015 
2016 static void kvm_gen_update_masterclock(struct kvm *kvm)
2017 {
2018 #ifdef CONFIG_X86_64
2019         int i;
2020         struct kvm_vcpu *vcpu;
2021         struct kvm_arch *ka = &kvm->arch;
2022 
2023         spin_lock(&ka->pvclock_gtod_sync_lock);
2024         kvm_make_mclock_inprogress_request(kvm);
2025         /* no guest entries from this point */
2026         pvclock_update_vm_gtod_copy(kvm);
2027 
2028         kvm_for_each_vcpu(i, vcpu, kvm)
2029                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2030 
2031         /* guest entries allowed */
2032         kvm_for_each_vcpu(i, vcpu, kvm)
2033                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2034 
2035         spin_unlock(&ka->pvclock_gtod_sync_lock);
2036 #endif
2037 }
2038 
2039 u64 get_kvmclock_ns(struct kvm *kvm)
2040 {
2041         struct kvm_arch *ka = &kvm->arch;
2042         struct pvclock_vcpu_time_info hv_clock;
2043         u64 ret;
2044 
2045         spin_lock(&ka->pvclock_gtod_sync_lock);
2046         if (!ka->use_master_clock) {
2047                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2048                 return ktime_get_boot_ns() + ka->kvmclock_offset;
2049         }
2050 
2051         hv_clock.tsc_timestamp = ka->master_cycle_now;
2052         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2053         spin_unlock(&ka->pvclock_gtod_sync_lock);
2054 
2055         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2056         get_cpu();
2057 
2058         if (__this_cpu_read(cpu_tsc_khz)) {
2059                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2060                                    &hv_clock.tsc_shift,
2061                                    &hv_clock.tsc_to_system_mul);
2062                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2063         } else
2064                 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2065 
2066         put_cpu();
2067 
2068         return ret;
2069 }
2070 
2071 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2072 {
2073         struct kvm_vcpu_arch *vcpu = &v->arch;
2074         struct pvclock_vcpu_time_info guest_hv_clock;
2075 
2076         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2077                 &guest_hv_clock, sizeof(guest_hv_clock))))
2078                 return;
2079 
2080         /* This VCPU is paused, but it's legal for a guest to read another
2081          * VCPU's kvmclock, so we really have to follow the specification where
2082          * it says that version is odd if data is being modified, and even after
2083          * it is consistent.
2084          *
2085          * Version field updates must be kept separate.  This is because
2086          * kvm_write_guest_cached might use a "rep movs" instruction, and
2087          * writes within a string instruction are weakly ordered.  So there
2088          * are three writes overall.
2089          *
2090          * As a small optimization, only write the version field in the first
2091          * and third write.  The vcpu->pv_time cache is still valid, because the
2092          * version field is the first in the struct.
2093          */
2094         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2095 
2096         if (guest_hv_clock.version & 1)
2097                 ++guest_hv_clock.version;  /* first time write, random junk */
2098 
2099         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2100         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2101                                 &vcpu->hv_clock,
2102                                 sizeof(vcpu->hv_clock.version));
2103 
2104         smp_wmb();
2105 
2106         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2107         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2108 
2109         if (vcpu->pvclock_set_guest_stopped_request) {
2110                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2111                 vcpu->pvclock_set_guest_stopped_request = false;
2112         }
2113 
2114         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2115 
2116         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2117                                 &vcpu->hv_clock,
2118                                 sizeof(vcpu->hv_clock));
2119 
2120         smp_wmb();
2121 
2122         vcpu->hv_clock.version++;
2123         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2124                                 &vcpu->hv_clock,
2125                                 sizeof(vcpu->hv_clock.version));
2126 }
2127 
2128 static int kvm_guest_time_update(struct kvm_vcpu *v)
2129 {
2130         unsigned long flags, tgt_tsc_khz;
2131         struct kvm_vcpu_arch *vcpu = &v->arch;
2132         struct kvm_arch *ka = &v->kvm->arch;
2133         s64 kernel_ns;
2134         u64 tsc_timestamp, host_tsc;
2135         u8 pvclock_flags;
2136         bool use_master_clock;
2137 
2138         kernel_ns = 0;
2139         host_tsc = 0;
2140 
2141         /*
2142          * If the host uses TSC clock, then passthrough TSC as stable
2143          * to the guest.
2144          */
2145         spin_lock(&ka->pvclock_gtod_sync_lock);
2146         use_master_clock = ka->use_master_clock;
2147         if (use_master_clock) {
2148                 host_tsc = ka->master_cycle_now;
2149                 kernel_ns = ka->master_kernel_ns;
2150         }
2151         spin_unlock(&ka->pvclock_gtod_sync_lock);
2152 
2153         /* Keep irq disabled to prevent changes to the clock */
2154         local_irq_save(flags);
2155         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2156         if (unlikely(tgt_tsc_khz == 0)) {
2157                 local_irq_restore(flags);
2158                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2159                 return 1;
2160         }
2161         if (!use_master_clock) {
2162                 host_tsc = rdtsc();
2163                 kernel_ns = ktime_get_boot_ns();
2164         }
2165 
2166         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2167 
2168         /*
2169          * We may have to catch up the TSC to match elapsed wall clock
2170          * time for two reasons, even if kvmclock is used.
2171          *   1) CPU could have been running below the maximum TSC rate
2172          *   2) Broken TSC compensation resets the base at each VCPU
2173          *      entry to avoid unknown leaps of TSC even when running
2174          *      again on the same CPU.  This may cause apparent elapsed
2175          *      time to disappear, and the guest to stand still or run
2176          *      very slowly.
2177          */
2178         if (vcpu->tsc_catchup) {
2179                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2180                 if (tsc > tsc_timestamp) {
2181                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2182                         tsc_timestamp = tsc;
2183                 }
2184         }
2185 
2186         local_irq_restore(flags);
2187 
2188         /* With all the info we got, fill in the values */
2189 
2190         if (kvm_has_tsc_control)
2191                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2192 
2193         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2194                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2195                                    &vcpu->hv_clock.tsc_shift,
2196                                    &vcpu->hv_clock.tsc_to_system_mul);
2197                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2198         }
2199 
2200         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2201         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2202         vcpu->last_guest_tsc = tsc_timestamp;
2203 
2204         /* If the host uses TSC clocksource, then it is stable */
2205         pvclock_flags = 0;
2206         if (use_master_clock)
2207                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2208 
2209         vcpu->hv_clock.flags = pvclock_flags;
2210 
2211         if (vcpu->pv_time_enabled)
2212                 kvm_setup_pvclock_page(v);
2213         if (v == kvm_get_vcpu(v->kvm, 0))
2214                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2215         return 0;
2216 }
2217 
2218 /*
2219  * kvmclock updates which are isolated to a given vcpu, such as
2220  * vcpu->cpu migration, should not allow system_timestamp from
2221  * the rest of the vcpus to remain static. Otherwise ntp frequency
2222  * correction applies to one vcpu's system_timestamp but not
2223  * the others.
2224  *
2225  * So in those cases, request a kvmclock update for all vcpus.
2226  * We need to rate-limit these requests though, as they can
2227  * considerably slow guests that have a large number of vcpus.
2228  * The time for a remote vcpu to update its kvmclock is bound
2229  * by the delay we use to rate-limit the updates.
2230  */
2231 
2232 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2233 
2234 static void kvmclock_update_fn(struct work_struct *work)
2235 {
2236         int i;
2237         struct delayed_work *dwork = to_delayed_work(work);
2238         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2239                                            kvmclock_update_work);
2240         struct kvm *kvm = container_of(ka, struct kvm, arch);
2241         struct kvm_vcpu *vcpu;
2242 
2243         kvm_for_each_vcpu(i, vcpu, kvm) {
2244                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2245                 kvm_vcpu_kick(vcpu);
2246         }
2247 }
2248 
2249 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2250 {
2251         struct kvm *kvm = v->kvm;
2252 
2253         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2254         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2255                                         KVMCLOCK_UPDATE_DELAY);
2256 }
2257 
2258 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2259 
2260 static void kvmclock_sync_fn(struct work_struct *work)
2261 {
2262         struct delayed_work *dwork = to_delayed_work(work);
2263         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2264                                            kvmclock_sync_work);
2265         struct kvm *kvm = container_of(ka, struct kvm, arch);
2266 
2267         if (!kvmclock_periodic_sync)
2268                 return;
2269 
2270         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2271         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2272                                         KVMCLOCK_SYNC_PERIOD);
2273 }
2274 
2275 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2276 {
2277         u64 mcg_cap = vcpu->arch.mcg_cap;
2278         unsigned bank_num = mcg_cap & 0xff;
2279         u32 msr = msr_info->index;
2280         u64 data = msr_info->data;
2281 
2282         switch (msr) {
2283         case MSR_IA32_MCG_STATUS:
2284                 vcpu->arch.mcg_status = data;
2285                 break;
2286         case MSR_IA32_MCG_CTL:
2287                 if (!(mcg_cap & MCG_CTL_P) &&
2288                     (data || !msr_info->host_initiated))
2289                         return 1;
2290                 if (data != 0 && data != ~(u64)0)
2291                         return 1;
2292                 vcpu->arch.mcg_ctl = data;
2293                 break;
2294         default:
2295                 if (msr >= MSR_IA32_MC0_CTL &&
2296                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2297                         u32 offset = msr - MSR_IA32_MC0_CTL;
2298                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2299                          * some Linux kernels though clear bit 10 in bank 4 to
2300                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2301                          * this to avoid an uncatched #GP in the guest
2302                          */
2303                         if ((offset & 0x3) == 0 &&
2304                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2305                                 return -1;
2306                         if (!msr_info->host_initiated &&
2307                                 (offset & 0x3) == 1 && data != 0)
2308                                 return -1;
2309                         vcpu->arch.mce_banks[offset] = data;
2310                         break;
2311                 }
2312                 return 1;
2313         }
2314         return 0;
2315 }
2316 
2317 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2318 {
2319         struct kvm *kvm = vcpu->kvm;
2320         int lm = is_long_mode(vcpu);
2321         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2322                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2323         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2324                 : kvm->arch.xen_hvm_config.blob_size_32;
2325         u32 page_num = data & ~PAGE_MASK;
2326         u64 page_addr = data & PAGE_MASK;
2327         u8 *page;
2328         int r;
2329 
2330         r = -E2BIG;
2331         if (page_num >= blob_size)
2332                 goto out;
2333         r = -ENOMEM;
2334         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2335         if (IS_ERR(page)) {
2336                 r = PTR_ERR(page);
2337                 goto out;
2338         }
2339         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2340                 goto out_free;
2341         r = 0;
2342 out_free:
2343         kfree(page);
2344 out:
2345         return r;
2346 }
2347 
2348 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2349 {
2350         gpa_t gpa = data & ~0x3f;
2351 
2352         /* Bits 3:5 are reserved, Should be zero */
2353         if (data & 0x38)
2354                 return 1;
2355 
2356         vcpu->arch.apf.msr_val = data;
2357 
2358         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2359                 kvm_clear_async_pf_completion_queue(vcpu);
2360                 kvm_async_pf_hash_reset(vcpu);
2361                 return 0;
2362         }
2363 
2364         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2365                                         sizeof(u32)))
2366                 return 1;
2367 
2368         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2369         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2370         kvm_async_pf_wakeup_all(vcpu);
2371         return 0;
2372 }
2373 
2374 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2375 {
2376         vcpu->arch.pv_time_enabled = false;
2377 }
2378 
2379 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2380 {
2381         ++vcpu->stat.tlb_flush;
2382         kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2383 }
2384 
2385 static void record_steal_time(struct kvm_vcpu *vcpu)
2386 {
2387         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2388                 return;
2389 
2390         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2391                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2392                 return;
2393 
2394         /*
2395          * Doing a TLB flush here, on the guest's behalf, can avoid
2396          * expensive IPIs.
2397          */
2398         if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2399                 kvm_vcpu_flush_tlb(vcpu, false);
2400 
2401         if (vcpu->arch.st.steal.version & 1)
2402                 vcpu->arch.st.steal.version += 1;  /* first time write, random junk */
2403 
2404         vcpu->arch.st.steal.version += 1;
2405 
2406         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2407                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2408 
2409         smp_wmb();
2410 
2411         vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2412                 vcpu->arch.st.last_steal;
2413         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2414 
2415         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2416                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2417 
2418         smp_wmb();
2419 
2420         vcpu->arch.st.steal.version += 1;
2421 
2422         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2423                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2424 }
2425 
2426 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2427 {
2428         bool pr = false;
2429         u32 msr = msr_info->index;
2430         u64 data = msr_info->data;
2431 
2432         switch (msr) {
2433         case MSR_AMD64_NB_CFG:
2434         case MSR_IA32_UCODE_WRITE:
2435         case MSR_VM_HSAVE_PA:
2436         case MSR_AMD64_PATCH_LOADER:
2437         case MSR_AMD64_BU_CFG2:
2438         case MSR_AMD64_DC_CFG:
2439         case MSR_F15H_EX_CFG:
2440                 break;
2441 
2442         case MSR_IA32_UCODE_REV:
2443                 if (msr_info->host_initiated)
2444                         vcpu->arch.microcode_version = data;
2445                 break;
2446         case MSR_EFER:
2447                 return set_efer(vcpu, data);
2448         case MSR_K7_HWCR:
2449                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2450                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2451                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2452                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2453                 if (data != 0) {
2454                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2455                                     data);
2456                         return 1;
2457                 }
2458                 break;
2459         case MSR_FAM10H_MMIO_CONF_BASE:
2460                 if (data != 0) {
2461                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2462                                     "0x%llx\n", data);
2463                         return 1;
2464                 }
2465                 break;
2466         case MSR_IA32_DEBUGCTLMSR:
2467                 if (!data) {
2468                         /* We support the non-activated case already */
2469                         break;
2470                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2471                         /* Values other than LBR and BTF are vendor-specific,
2472                            thus reserved and should throw a #GP */
2473                         return 1;
2474                 }
2475                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2476                             __func__, data);
2477                 break;
2478         case 0x200 ... 0x2ff:
2479                 return kvm_mtrr_set_msr(vcpu, msr, data);
2480         case MSR_IA32_APICBASE:
2481                 return kvm_set_apic_base(vcpu, msr_info);
2482         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2483                 return kvm_x2apic_msr_write(vcpu, msr, data);
2484         case MSR_IA32_TSCDEADLINE:
2485                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2486                 break;
2487         case MSR_IA32_TSC_ADJUST:
2488                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2489                         if (!msr_info->host_initiated) {
2490                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2491                                 adjust_tsc_offset_guest(vcpu, adj);
2492                         }
2493                         vcpu->arch.ia32_tsc_adjust_msr = data;
2494                 }
2495                 break;
2496         case MSR_IA32_MISC_ENABLE:
2497                 vcpu->arch.ia32_misc_enable_msr = data;
2498                 break;
2499         case MSR_IA32_SMBASE:
2500                 if (!msr_info->host_initiated)
2501                         return 1;
2502                 vcpu->arch.smbase = data;
2503                 break;
2504         case MSR_IA32_TSC:
2505                 kvm_write_tsc(vcpu, msr_info);
2506                 break;
2507         case MSR_SMI_COUNT:
2508                 if (!msr_info->host_initiated)
2509                         return 1;
2510                 vcpu->arch.smi_count = data;
2511                 break;
2512         case MSR_KVM_WALL_CLOCK_NEW:
2513         case MSR_KVM_WALL_CLOCK:
2514                 vcpu->kvm->arch.wall_clock = data;
2515                 kvm_write_wall_clock(vcpu->kvm, data);
2516                 break;
2517         case MSR_KVM_SYSTEM_TIME_NEW:
2518         case MSR_KVM_SYSTEM_TIME: {
2519                 struct kvm_arch *ka = &vcpu->kvm->arch;
2520 
2521                 kvmclock_reset(vcpu);
2522 
2523                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2524                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2525 
2526                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2527                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2528 
2529                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2530                 }
2531 
2532                 vcpu->arch.time = data;
2533                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2534 
2535                 /* we verify if the enable bit is set... */
2536                 if (!(data & 1))
2537                         break;
2538 
2539                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2540                      &vcpu->arch.pv_time, data & ~1ULL,
2541                      sizeof(struct pvclock_vcpu_time_info)))
2542                         vcpu->arch.pv_time_enabled = false;
2543                 else
2544                         vcpu->arch.pv_time_enabled = true;
2545 
2546                 break;
2547         }
2548         case MSR_KVM_ASYNC_PF_EN:
2549                 if (kvm_pv_enable_async_pf(vcpu, data))
2550                         return 1;
2551                 break;
2552         case MSR_KVM_STEAL_TIME:
2553 
2554                 if (unlikely(!sched_info_on()))
2555                         return 1;
2556 
2557                 if (data & KVM_STEAL_RESERVED_MASK)
2558                         return 1;
2559 
2560                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2561                                                 data & KVM_STEAL_VALID_BITS,
2562                                                 sizeof(struct kvm_steal_time)))
2563                         return 1;
2564 
2565                 vcpu->arch.st.msr_val = data;
2566 
2567                 if (!(data & KVM_MSR_ENABLED))
2568                         break;
2569 
2570                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2571 
2572                 break;
2573         case MSR_KVM_PV_EOI_EN:
2574                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2575                         return 1;
2576                 break;
2577 
2578         case MSR_IA32_MCG_CTL:
2579         case MSR_IA32_MCG_STATUS:
2580         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2581                 return set_msr_mce(vcpu, msr_info);
2582 
2583         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2584         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2585                 pr = true; /* fall through */
2586         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2587         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2588                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2589                         return kvm_pmu_set_msr(vcpu, msr_info);
2590 
2591                 if (pr || data != 0)
2592                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2593                                     "0x%x data 0x%llx\n", msr, data);
2594                 break;
2595         case MSR_K7_CLK_CTL:
2596                 /*
2597                  * Ignore all writes to this no longer documented MSR.
2598                  * Writes are only relevant for old K7 processors,
2599                  * all pre-dating SVM, but a recommended workaround from
2600                  * AMD for these chips. It is possible to specify the
2601                  * affected processor models on the command line, hence
2602                  * the need to ignore the workaround.
2603                  */
2604                 break;
2605         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2606         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2607         case HV_X64_MSR_CRASH_CTL:
2608         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2609         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2610         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2611         case HV_X64_MSR_TSC_EMULATION_STATUS:
2612                 return kvm_hv_set_msr_common(vcpu, msr, data,
2613                                              msr_info->host_initiated);
2614         case MSR_IA32_BBL_CR_CTL3:
2615                 /* Drop writes to this legacy MSR -- see rdmsr
2616                  * counterpart for further detail.
2617                  */
2618                 if (report_ignored_msrs)
2619                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2620                                 msr, data);
2621                 break;
2622         case MSR_AMD64_OSVW_ID_LENGTH:
2623                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2624                         return 1;
2625                 vcpu->arch.osvw.length = data;
2626                 break;
2627         case MSR_AMD64_OSVW_STATUS:
2628                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2629                         return 1;
2630                 vcpu->arch.osvw.status = data;
2631                 break;
2632         case MSR_PLATFORM_INFO:
2633                 if (!msr_info->host_initiated ||
2634                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2635                      cpuid_fault_enabled(vcpu)))
2636                         return 1;
2637                 vcpu->arch.msr_platform_info = data;
2638                 break;
2639         case MSR_MISC_FEATURES_ENABLES:
2640                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2641                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2642                      !supports_cpuid_fault(vcpu)))
2643                         return 1;
2644                 vcpu->arch.msr_misc_features_enables = data;
2645                 break;
2646         default:
2647                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2648                         return xen_hvm_config(vcpu, data);
2649                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2650                         return kvm_pmu_set_msr(vcpu, msr_info);
2651                 if (!ignore_msrs) {
2652                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2653                                     msr, data);
2654                         return 1;
2655                 } else {
2656                         if (report_ignored_msrs)
2657                                 vcpu_unimpl(vcpu,
2658                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2659                                         msr, data);
2660                         break;
2661                 }
2662         }
2663         return 0;
2664 }
2665 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2666 
2667 
2668 /*
2669  * Reads an msr value (of 'msr_index') into 'pdata'.
2670  * Returns 0 on success, non-0 otherwise.
2671  * Assumes vcpu_load() was already called.
2672  */
2673 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2674 {
2675         return kvm_x86_ops->get_msr(vcpu, msr);
2676 }
2677 EXPORT_SYMBOL_GPL(kvm_get_msr);
2678 
2679 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2680 {
2681         u64 data;
2682         u64 mcg_cap = vcpu->arch.mcg_cap;
2683         unsigned bank_num = mcg_cap & 0xff;
2684 
2685         switch (msr) {
2686         case MSR_IA32_P5_MC_ADDR:
2687         case MSR_IA32_P5_MC_TYPE:
2688                 data = 0;
2689                 break;
2690         case MSR_IA32_MCG_CAP:
2691                 data = vcpu->arch.mcg_cap;
2692                 break;
2693         case MSR_IA32_MCG_CTL:
2694                 if (!(mcg_cap & MCG_CTL_P) && !host)
2695                         return 1;
2696                 data = vcpu->arch.mcg_ctl;
2697                 break;
2698         case MSR_IA32_MCG_STATUS:
2699                 data = vcpu->arch.mcg_status;
2700                 break;
2701         default:
2702                 if (msr >= MSR_IA32_MC0_CTL &&
2703                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2704                         u32 offset = msr - MSR_IA32_MC0_CTL;
2705                         data = vcpu->arch.mce_banks[offset];
2706                         break;
2707                 }
2708                 return 1;
2709         }
2710         *pdata = data;
2711         return 0;
2712 }
2713 
2714 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2715 {
2716         switch (msr_info->index) {
2717         case MSR_IA32_PLATFORM_ID:
2718         case MSR_IA32_EBL_CR_POWERON:
2719         case MSR_IA32_DEBUGCTLMSR:
2720         case MSR_IA32_LASTBRANCHFROMIP:
2721         case MSR_IA32_LASTBRANCHTOIP:
2722         case MSR_IA32_LASTINTFROMIP:
2723         case MSR_IA32_LASTINTTOIP:
2724         case MSR_K8_SYSCFG:
2725         case MSR_K8_TSEG_ADDR:
2726         case MSR_K8_TSEG_MASK:
2727         case MSR_K7_HWCR:
2728         case MSR_VM_HSAVE_PA:
2729         case MSR_K8_INT_PENDING_MSG:
2730         case MSR_AMD64_NB_CFG:
2731         case MSR_FAM10H_MMIO_CONF_BASE:
2732         case MSR_AMD64_BU_CFG2:
2733         case MSR_IA32_PERF_CTL:
2734         case MSR_AMD64_DC_CFG:
2735         case MSR_F15H_EX_CFG:
2736                 msr_info->data = 0;
2737                 break;
2738         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2739         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2740         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2741         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2742         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2743                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2744                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2745                 msr_info->data = 0;
2746                 break;
2747         case MSR_IA32_UCODE_REV:
2748                 msr_info->data = vcpu->arch.microcode_version;
2749                 break;
2750         case MSR_IA32_TSC:
2751                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2752                 break;
2753         case MSR_MTRRcap:
2754         case 0x200 ... 0x2ff:
2755                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2756         case 0xcd: /* fsb frequency */
2757                 msr_info->data = 3;
2758                 break;
2759                 /*
2760                  * MSR_EBC_FREQUENCY_ID
2761                  * Conservative value valid for even the basic CPU models.
2762                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2763                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2764                  * and 266MHz for model 3, or 4. Set Core Clock
2765                  * Frequency to System Bus Frequency Ratio to 1 (bits
2766                  * 31:24) even though these are only valid for CPU
2767                  * models > 2, however guests may end up dividing or
2768                  * multiplying by zero otherwise.
2769                  */
2770         case MSR_EBC_FREQUENCY_ID:
2771                 msr_info->data = 1 << 24;
2772                 break;
2773         case MSR_IA32_APICBASE:
2774                 msr_info->data = kvm_get_apic_base(vcpu);
2775                 break;
2776         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2777                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2778                 break;
2779         case MSR_IA32_TSCDEADLINE:
2780                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2781                 break;
2782         case MSR_IA32_TSC_ADJUST:
2783                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2784                 break;
2785         case MSR_IA32_MISC_ENABLE:
2786                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2787                 break;
2788         case MSR_IA32_SMBASE:
2789                 if (!msr_info->host_initiated)
2790                         return 1;
2791                 msr_info->data = vcpu->arch.smbase;
2792                 break;
2793         case MSR_SMI_COUNT:
2794                 msr_info->data = vcpu->arch.smi_count;
2795                 break;
2796         case MSR_IA32_PERF_STATUS:
2797                 /* TSC increment by tick */
2798                 msr_info->data = 1000ULL;
2799                 /* CPU multiplier */
2800                 msr_info->data |= (((uint64_t)4ULL) << 40);
2801                 break;
2802         case MSR_EFER:
2803                 msr_info->data = vcpu->arch.efer;
2804                 break;
2805         case MSR_KVM_WALL_CLOCK:
2806         case MSR_KVM_WALL_CLOCK_NEW:
2807                 msr_info->data = vcpu->kvm->arch.wall_clock;
2808                 break;
2809         case MSR_KVM_SYSTEM_TIME:
2810         case MSR_KVM_SYSTEM_TIME_NEW:
2811                 msr_info->data = vcpu->arch.time;
2812                 break;
2813         case MSR_KVM_ASYNC_PF_EN:
2814                 msr_info->data = vcpu->arch.apf.msr_val;
2815                 break;
2816         case MSR_KVM_STEAL_TIME:
2817                 msr_info->data = vcpu->arch.st.msr_val;
2818                 break;
2819         case MSR_KVM_PV_EOI_EN:
2820                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2821                 break;
2822         case MSR_IA32_P5_MC_ADDR:
2823         case MSR_IA32_P5_MC_TYPE:
2824         case MSR_IA32_MCG_CAP:
2825         case MSR_IA32_MCG_CTL:
2826         case MSR_IA32_MCG_STATUS:
2827         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2828                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2829                                    msr_info->host_initiated);
2830         case MSR_K7_CLK_CTL:
2831                 /*
2832                  * Provide expected ramp-up count for K7. All other
2833                  * are set to zero, indicating minimum divisors for
2834                  * every field.
2835                  *
2836                  * This prevents guest kernels on AMD host with CPU
2837                  * type 6, model 8 and higher from exploding due to
2838                  * the rdmsr failing.
2839                  */
2840                 msr_info->data = 0x20000000;
2841                 break;
2842         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2843         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2844         case HV_X64_MSR_CRASH_CTL:
2845         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2846         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2847         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2848         case HV_X64_MSR_TSC_EMULATION_STATUS:
2849                 return kvm_hv_get_msr_common(vcpu,
2850                                              msr_info->index, &msr_info->data,
2851                                              msr_info->host_initiated);
2852                 break;
2853         case MSR_IA32_BBL_CR_CTL3:
2854                 /* This legacy MSR exists but isn't fully documented in current
2855                  * silicon.  It is however accessed by winxp in very narrow
2856                  * scenarios where it sets bit #19, itself documented as
2857                  * a "reserved" bit.  Best effort attempt to source coherent
2858                  * read data here should the balance of the register be
2859                  * interpreted by the guest:
2860                  *
2861                  * L2 cache control register 3: 64GB range, 256KB size,
2862                  * enabled, latency 0x1, configured
2863                  */
2864                 msr_info->data = 0xbe702111;
2865                 break;
2866         case MSR_AMD64_OSVW_ID_LENGTH:
2867                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2868                         return 1;
2869                 msr_info->data = vcpu->arch.osvw.length;
2870                 break;
2871         case MSR_AMD64_OSVW_STATUS:
2872                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2873                         return 1;
2874                 msr_info->data = vcpu->arch.osvw.status;
2875                 break;
2876         case MSR_PLATFORM_INFO:
2877                 if (!msr_info->host_initiated &&
2878                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2879                         return 1;
2880                 msr_info->data = vcpu->arch.msr_platform_info;
2881                 break;
2882         case MSR_MISC_FEATURES_ENABLES:
2883                 msr_info->data = vcpu->arch.msr_misc_features_enables;
2884                 break;
2885         default:
2886                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2887                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2888                 if (!ignore_msrs) {
2889                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2890                                                msr_info->index);
2891                         return 1;
2892                 } else {
2893                         if (report_ignored_msrs)
2894                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2895                                         msr_info->index);
2896                         msr_info->data = 0;
2897                 }
2898                 break;
2899         }
2900         return 0;
2901 }
2902 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2903 
2904 /*
2905  * Read or write a bunch of msrs. All parameters are kernel addresses.
2906  *
2907  * @return number of msrs set successfully.
2908  */
2909 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2910                     struct kvm_msr_entry *entries,
2911                     int (*do_msr)(struct kvm_vcpu *vcpu,
2912                                   unsigned index, u64 *data))
2913 {
2914         int i;
2915 
2916         for (i = 0; i < msrs->nmsrs; ++i)
2917                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2918                         break;
2919 
2920         return i;
2921 }
2922 
2923 /*
2924  * Read or write a bunch of msrs. Parameters are user addresses.
2925  *
2926  * @return number of msrs set successfully.
2927  */
2928 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2929                   int (*do_msr)(struct kvm_vcpu *vcpu,
2930                                 unsigned index, u64 *data),
2931                   int writeback)
2932 {
2933         struct kvm_msrs msrs;
2934         struct kvm_msr_entry *entries;
2935         int r, n;
2936         unsigned size;
2937 
2938         r = -EFAULT;
2939         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
2940                 goto out;
2941 
2942         r = -E2BIG;
2943         if (msrs.nmsrs >= MAX_IO_MSRS)
2944                 goto out;
2945 
2946         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2947         entries = memdup_user(user_msrs->entries, size);
2948         if (IS_ERR(entries)) {
2949                 r = PTR_ERR(entries);
2950                 goto out;
2951         }
2952 
2953         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2954         if (r < 0)
2955                 goto out_free;
2956 
2957         r = -EFAULT;
2958         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2959                 goto out_free;
2960 
2961         r = n;
2962 
2963 out_free:
2964         kfree(entries);
2965 out:
2966         return r;
2967 }
2968 
2969 static inline bool kvm_can_mwait_in_guest(void)
2970 {
2971         return boot_cpu_has(X86_FEATURE_MWAIT) &&
2972                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2973                 boot_cpu_has(X86_FEATURE_ARAT);
2974 }
2975 
2976 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2977 {
2978         int r = 0;
2979 
2980         switch (ext) {
2981         case KVM_CAP_IRQCHIP:
2982         case KVM_CAP_HLT:
2983         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2984         case KVM_CAP_SET_TSS_ADDR:
2985         case KVM_CAP_EXT_CPUID:
2986         case KVM_CAP_EXT_EMUL_CPUID:
2987         case KVM_CAP_CLOCKSOURCE:
2988         case KVM_CAP_PIT:
2989         case KVM_CAP_NOP_IO_DELAY:
2990         case KVM_CAP_MP_STATE:
2991         case KVM_CAP_SYNC_MMU:
2992         case KVM_CAP_USER_NMI:
2993         case KVM_CAP_REINJECT_CONTROL:
2994         case KVM_CAP_IRQ_INJECT_STATUS:
2995         case KVM_CAP_IOEVENTFD:
2996         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2997         case KVM_CAP_PIT2:
2998         case KVM_CAP_PIT_STATE2:
2999         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3000         case KVM_CAP_XEN_HVM:
3001         case KVM_CAP_VCPU_EVENTS:
3002         case KVM_CAP_HYPERV:
3003         case KVM_CAP_HYPERV_VAPIC:
3004         case KVM_CAP_HYPERV_SPIN:
3005         case KVM_CAP_HYPERV_SYNIC:
3006         case KVM_CAP_HYPERV_SYNIC2:
3007         case KVM_CAP_HYPERV_VP_INDEX:
3008         case KVM_CAP_HYPERV_EVENTFD:
3009         case KVM_CAP_HYPERV_TLBFLUSH:
3010         case KVM_CAP_HYPERV_SEND_IPI:
3011         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3012         case KVM_CAP_HYPERV_CPUID:
3013         case KVM_CAP_PCI_SEGMENT:
3014         case KVM_CAP_DEBUGREGS:
3015         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3016         case KVM_CAP_XSAVE:
3017         case KVM_CAP_ASYNC_PF:
3018         case KVM_CAP_GET_TSC_KHZ:
3019         case KVM_CAP_KVMCLOCK_CTRL:
3020         case KVM_CAP_READONLY_MEM:
3021         case KVM_CAP_HYPERV_TIME:
3022         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3023         case KVM_CAP_TSC_DEADLINE_TIMER:
3024         case KVM_CAP_DISABLE_QUIRKS:
3025         case KVM_CAP_SET_BOOT_CPU_ID:
3026         case KVM_CAP_SPLIT_IRQCHIP:
3027         case KVM_CAP_IMMEDIATE_EXIT:
3028         case KVM_CAP_GET_MSR_FEATURES:
3029         case KVM_CAP_MSR_PLATFORM_INFO:
3030         case KVM_CAP_EXCEPTION_PAYLOAD:
3031                 r = 1;
3032                 break;
3033         case KVM_CAP_SYNC_REGS:
3034                 r = KVM_SYNC_X86_VALID_FIELDS;
3035                 break;
3036         case KVM_CAP_ADJUST_CLOCK:
3037                 r = KVM_CLOCK_TSC_STABLE;
3038                 break;
3039         case KVM_CAP_X86_DISABLE_EXITS:
3040                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
3041                 if(kvm_can_mwait_in_guest())
3042                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3043                 break;
3044         case KVM_CAP_X86_SMM:
3045                 /* SMBASE is usually relocated above 1M on modern chipsets,
3046                  * and SMM handlers might indeed rely on 4G segment limits,
3047                  * so do not report SMM to be available if real mode is
3048                  * emulated via vm86 mode.  Still, do not go to great lengths
3049                  * to avoid userspace's usage of the feature, because it is a
3050                  * fringe case that is not enabled except via specific settings
3051                  * of the module parameters.
3052                  */
3053                 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3054                 break;
3055         case KVM_CAP_VAPIC:
3056                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3057                 break;
3058         case KVM_CAP_NR_VCPUS:
3059                 r = KVM_SOFT_MAX_VCPUS;
3060                 break;
3061         case KVM_CAP_MAX_VCPUS:
3062                 r = KVM_MAX_VCPUS;
3063                 break;
3064         case KVM_CAP_NR_MEMSLOTS:
3065                 r = KVM_USER_MEM_SLOTS;
3066                 break;
3067         case KVM_CAP_PV_MMU:    /* obsolete */
3068                 r = 0;
3069                 break;
3070         case KVM_CAP_MCE:
3071                 r = KVM_MAX_MCE_BANKS;
3072                 break;
3073         case KVM_CAP_XCRS:
3074                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3075                 break;
3076         case KVM_CAP_TSC_CONTROL:
3077                 r = kvm_has_tsc_control;
3078                 break;
3079         case KVM_CAP_X2APIC_API:
3080                 r = KVM_X2APIC_API_VALID_FLAGS;
3081                 break;
3082         case KVM_CAP_NESTED_STATE:
3083                 r = kvm_x86_ops->get_nested_state ?
3084                         kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3085                 break;
3086         default:
3087                 break;
3088         }
3089         return r;
3090 
3091 }
3092 
3093 long kvm_arch_dev_ioctl(struct file *filp,
3094                         unsigned int ioctl, unsigned long arg)
3095 {
3096         void __user *argp = (void __user *)arg;
3097         long r;
3098 
3099         switch (ioctl) {
3100         case KVM_GET_MSR_INDEX_LIST: {
3101                 struct kvm_msr_list __user *user_msr_list = argp;
3102                 struct kvm_msr_list msr_list;
3103                 unsigned n;
3104 
3105                 r = -EFAULT;
3106                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3107                         goto out;
3108                 n = msr_list.nmsrs;
3109                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3110                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3111                         goto out;
3112                 r = -E2BIG;
3113                 if (n < msr_list.nmsrs)
3114                         goto out;
3115                 r = -EFAULT;
3116                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3117                                  num_msrs_to_save * sizeof(u32)))
3118                         goto out;
3119                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3120                                  &emulated_msrs,
3121                                  num_emulated_msrs * sizeof(u32)))
3122                         goto out;
3123                 r = 0;
3124                 break;
3125         }
3126         case KVM_GET_SUPPORTED_CPUID:
3127         case KVM_GET_EMULATED_CPUID: {
3128                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3129                 struct kvm_cpuid2 cpuid;
3130 
3131                 r = -EFAULT;
3132                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3133                         goto out;
3134 
3135                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3136                                             ioctl);
3137                 if (r)
3138                         goto out;
3139 
3140                 r = -EFAULT;
3141                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3142                         goto out;
3143                 r = 0;
3144                 break;
3145         }
3146         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3147                 r = -EFAULT;
3148                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3149                                  sizeof(kvm_mce_cap_supported)))
3150                         goto out;
3151                 r = 0;
3152                 break;
3153         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3154                 struct kvm_msr_list __user *user_msr_list = argp;
3155                 struct kvm_msr_list msr_list;
3156                 unsigned int n;
3157 
3158                 r = -EFAULT;
3159                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3160                         goto out;
3161                 n = msr_list.nmsrs;
3162                 msr_list.nmsrs = num_msr_based_features;
3163                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3164                         goto out;
3165                 r = -E2BIG;
3166                 if (n < msr_list.nmsrs)
3167                         goto out;
3168                 r = -EFAULT;
3169                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3170                                  num_msr_based_features * sizeof(u32)))
3171                         goto out;
3172                 r = 0;
3173                 break;
3174         }
3175         case KVM_GET_MSRS:
3176                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3177                 break;
3178         }
3179         default:
3180                 r = -EINVAL;
3181         }
3182 out:
3183         return r;
3184 }
3185 
3186 static void wbinvd_ipi(void *garbage)
3187 {
3188         wbinvd();
3189 }
3190 
3191 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3192 {
3193         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3194 }
3195 
3196 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3197 {
3198         /* Address WBINVD may be executed by guest */
3199         if (need_emulate_wbinvd(vcpu)) {
3200                 if (kvm_x86_ops->has_wbinvd_exit())
3201                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3202                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3203                         smp_call_function_single(vcpu->cpu,
3204                                         wbinvd_ipi, NULL, 1);
3205         }
3206 
3207         kvm_x86_ops->vcpu_load(vcpu, cpu);
3208 
3209         /* Apply any externally detected TSC adjustments (due to suspend) */
3210         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3211                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3212                 vcpu->arch.tsc_offset_adjustment = 0;
3213                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3214         }
3215 
3216         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3217                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3218                                 rdtsc() - vcpu->arch.last_host_tsc;
3219                 if (tsc_delta < 0)
3220                         mark_tsc_unstable("KVM discovered backwards TSC");
3221 
3222                 if (kvm_check_tsc_unstable()) {
3223                         u64 offset = kvm_compute_tsc_offset(vcpu,
3224                                                 vcpu->arch.last_guest_tsc);
3225                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3226                         vcpu->arch.tsc_catchup = 1;
3227                 }
3228 
3229                 if (kvm_lapic_hv_timer_in_use(vcpu))
3230                         kvm_lapic_restart_hv_timer(vcpu);
3231 
3232                 /*
3233                  * On a host with synchronized TSC, there is no need to update
3234                  * kvmclock on vcpu->cpu migration
3235                  */
3236                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3237                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3238                 if (vcpu->cpu != cpu)
3239                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3240                 vcpu->cpu = cpu;
3241         }
3242 
3243         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3244 }
3245 
3246 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3247 {
3248         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3249                 return;
3250 
3251         vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3252 
3253         kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3254                         &vcpu->arch.st.steal.preempted,
3255                         offsetof(struct kvm_steal_time, preempted),
3256                         sizeof(vcpu->arch.st.steal.preempted));
3257 }
3258 
3259 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3260 {
3261         int idx;
3262 
3263         if (vcpu->preempted)
3264                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3265 
3266         /*
3267          * Disable page faults because we're in atomic context here.
3268          * kvm_write_guest_offset_cached() would call might_fault()
3269          * that relies on pagefault_disable() to tell if there's a
3270          * bug. NOTE: the write to guest memory may not go through if
3271          * during postcopy live migration or if there's heavy guest
3272          * paging.
3273          */
3274         pagefault_disable();
3275         /*
3276          * kvm_memslots() will be called by
3277          * kvm_write_guest_offset_cached() so take the srcu lock.
3278          */
3279         idx = srcu_read_lock(&vcpu->kvm->srcu);
3280         kvm_steal_time_set_preempted(vcpu);
3281         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3282         pagefault_enable();
3283         kvm_x86_ops->vcpu_put(vcpu);
3284         vcpu->arch.last_host_tsc = rdtsc();
3285         /*
3286          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3287          * on every vmexit, but if not, we might have a stale dr6 from the
3288          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3289          */
3290         set_debugreg(0, 6);
3291 }
3292 
3293 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3294                                     struct kvm_lapic_state *s)
3295 {
3296         if (vcpu->arch.apicv_active)
3297                 kvm_x86_ops->sync_pir_to_irr(vcpu);
3298 
3299         return kvm_apic_get_state(vcpu, s);
3300 }
3301 
3302 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3303                                     struct kvm_lapic_state *s)
3304 {
3305         int r;
3306 
3307         r = kvm_apic_set_state(vcpu, s);
3308         if (r)
3309                 return r;
3310         update_cr8_intercept(vcpu);
3311 
3312         return 0;
3313 }
3314 
3315 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3316 {
3317         return (!lapic_in_kernel(vcpu) ||
3318                 kvm_apic_accept_pic_intr(vcpu));
3319 }
3320 
3321 /*
3322  * if userspace requested an interrupt window, check that the
3323  * interrupt window is open.
3324  *
3325  * No need to exit to userspace if we already have an interrupt queued.
3326  */
3327 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3328 {
3329         return kvm_arch_interrupt_allowed(vcpu) &&
3330                 !kvm_cpu_has_interrupt(vcpu) &&
3331                 !kvm_event_needs_reinjection(vcpu) &&
3332                 kvm_cpu_accept_dm_intr(vcpu);
3333 }
3334 
3335 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3336                                     struct kvm_interrupt *irq)
3337 {
3338         if (irq->irq >= KVM_NR_INTERRUPTS)
3339                 return -EINVAL;
3340 
3341         if (!irqchip_in_kernel(vcpu->kvm)) {
3342                 kvm_queue_interrupt(vcpu, irq->irq, false);
3343                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3344                 return 0;
3345         }
3346 
3347         /*
3348          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3349          * fail for in-kernel 8259.
3350          */
3351         if (pic_in_kernel(vcpu->kvm))
3352                 return -ENXIO;
3353 
3354         if (vcpu->arch.pending_external_vector != -1)
3355                 return -EEXIST;
3356 
3357         vcpu->arch.pending_external_vector = irq->irq;
3358         kvm_make_request(KVM_REQ_EVENT, vcpu);
3359         return 0;
3360 }
3361 
3362 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3363 {
3364         kvm_inject_nmi(vcpu);
3365 
3366         return 0;
3367 }
3368 
3369 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3370 {
3371         kvm_make_request(KVM_REQ_SMI, vcpu);
3372 
3373         return 0;
3374 }
3375 
3376 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3377                                            struct kvm_tpr_access_ctl *tac)
3378 {
3379         if (tac->flags)
3380                 return -EINVAL;
3381         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3382         return 0;
3383 }
3384 
3385 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3386                                         u64 mcg_cap)
3387 {
3388         int r;
3389         unsigned bank_num = mcg_cap & 0xff, bank;
3390 
3391         r = -EINVAL;
3392         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3393                 goto out;
3394         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3395                 goto out;
3396         r = 0;
3397         vcpu->arch.mcg_cap = mcg_cap;
3398         /* Init IA32_MCG_CTL to all 1s */
3399         if (mcg_cap & MCG_CTL_P)
3400                 vcpu->arch.mcg_ctl = ~(u64)0;
3401         /* Init IA32_MCi_CTL to all 1s */
3402         for (bank = 0; bank < bank_num; bank++)
3403                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3404 
3405         if (kvm_x86_ops->setup_mce)
3406                 kvm_x86_ops->setup_mce(vcpu);
3407 out:
3408         return r;
3409 }
3410 
3411 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3412                                       struct kvm_x86_mce *mce)
3413 {
3414         u64 mcg_cap = vcpu->arch.mcg_cap;
3415         unsigned bank_num = mcg_cap & 0xff;
3416         u64 *banks = vcpu->arch.mce_banks;
3417 
3418         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3419                 return -EINVAL;
3420         /*
3421          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3422          * reporting is disabled
3423          */
3424         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3425             vcpu->arch.mcg_ctl != ~(u64)0)
3426                 return 0;
3427         banks += 4 * mce->bank;
3428         /*
3429          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3430          * reporting is disabled for the bank
3431          */
3432         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3433                 return 0;
3434         if (mce->status & MCI_STATUS_UC) {
3435                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3436                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3437                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3438                         return 0;
3439                 }
3440                 if (banks[1] & MCI_STATUS_VAL)
3441                         mce->status |= MCI_STATUS_OVER;
3442                 banks[2] = mce->addr;
3443                 banks[3] = mce->misc;
3444                 vcpu->arch.mcg_status = mce->mcg_status;
3445                 banks[1] = mce->status;
3446                 kvm_queue_exception(vcpu, MC_VECTOR);
3447         } else if (!(banks[1] & MCI_STATUS_VAL)
3448                    || !(banks[1] & MCI_STATUS_UC)) {
3449                 if (banks[1] & MCI_STATUS_VAL)
3450                         mce->status |= MCI_STATUS_OVER;
3451                 banks[2] = mce->addr;
3452                 banks[3] = mce->misc;
3453                 banks[1] = mce->status;
3454         } else
3455                 banks[1] |= MCI_STATUS_OVER;
3456         return 0;
3457 }
3458 
3459 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3460                                                struct kvm_vcpu_events *events)
3461 {
3462         process_nmi(vcpu);
3463 
3464         /*
3465          * The API doesn't provide the instruction length for software
3466          * exceptions, so don't report them. As long as the guest RIP
3467          * isn't advanced, we should expect to encounter the exception
3468          * again.
3469          */
3470         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3471                 events->exception.injected = 0;
3472                 events->exception.pending = 0;
3473         } else {
3474                 events->exception.injected = vcpu->arch.exception.injected;
3475                 events->exception.pending = vcpu->arch.exception.pending;
3476                 /*
3477                  * For ABI compatibility, deliberately conflate
3478                  * pending and injected exceptions when
3479                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3480                  */
3481                 if (!vcpu->kvm->arch.exception_payload_enabled)
3482                         events->exception.injected |=
3483                                 vcpu->arch.exception.pending;
3484         }
3485         events->exception.nr = vcpu->arch.exception.nr;
3486         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3487         events->exception.error_code = vcpu->arch.exception.error_code;
3488         events->exception_has_payload = vcpu->arch.exception.has_payload;
3489         events->exception_payload = vcpu->arch.exception.payload;
3490 
3491         events->interrupt.injected =
3492                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3493         events->interrupt.nr = vcpu->arch.interrupt.nr;
3494         events->interrupt.soft = 0;
3495         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3496 
3497         events->nmi.injected = vcpu->arch.nmi_injected;
3498         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3499         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3500         events->nmi.pad = 0;
3501 
3502         events->sipi_vector = 0; /* never valid when reporting to user space */
3503 
3504         events->smi.smm = is_smm(vcpu);
3505         events->smi.pending = vcpu->arch.smi_pending;
3506         events->smi.smm_inside_nmi =
3507                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3508         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3509 
3510         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3511                          | KVM_VCPUEVENT_VALID_SHADOW
3512                          | KVM_VCPUEVENT_VALID_SMM);
3513         if (vcpu->kvm->arch.exception_payload_enabled)
3514                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3515 
3516         memset(&events->reserved, 0, sizeof(events->reserved));
3517 }
3518 
3519 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3520 
3521 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3522                                               struct kvm_vcpu_events *events)
3523 {
3524         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3525                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3526                               | KVM_VCPUEVENT_VALID_SHADOW
3527                               | KVM_VCPUEVENT_VALID_SMM
3528                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3529                 return -EINVAL;
3530 
3531         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3532                 if (!vcpu->kvm->arch.exception_payload_enabled)
3533                         return -EINVAL;
3534                 if (events->exception.pending)
3535                         events->exception.injected = 0;
3536                 else
3537                         events->exception_has_payload = 0;
3538         } else {
3539                 events->exception.pending = 0;
3540                 events->exception_has_payload = 0;
3541         }
3542 
3543         if ((events->exception.injected || events->exception.pending) &&
3544             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3545                 return -EINVAL;
3546 
3547         /* INITs are latched while in SMM */
3548         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3549             (events->smi.smm || events->smi.pending) &&
3550             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3551                 return -EINVAL;
3552 
3553         process_nmi(vcpu);
3554         vcpu->arch.exception.injected = events->exception.injected;
3555         vcpu->arch.exception.pending = events->exception.pending;
3556         vcpu->arch.exception.nr = events->exception.nr;
3557         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3558         vcpu->arch.exception.error_code = events->exception.error_code;
3559         vcpu->arch.exception.has_payload = events->exception_has_payload;
3560         vcpu->arch.exception.payload = events->exception_payload;
3561 
3562         vcpu->arch.interrupt.injected = events->interrupt.injected;
3563         vcpu->arch.interrupt.nr = events->interrupt.nr;
3564         vcpu->arch.interrupt.soft = events->interrupt.soft;
3565         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3566                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3567                                                   events->interrupt.shadow);
3568 
3569         vcpu->arch.nmi_injected = events->nmi.injected;
3570         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3571                 vcpu->arch.nmi_pending = events->nmi.pending;
3572         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3573 
3574         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3575             lapic_in_kernel(vcpu))
3576                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3577 
3578         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3579                 u32 hflags = vcpu->arch.hflags;
3580                 if (events->smi.smm)
3581                         hflags |= HF_SMM_MASK;
3582                 else
3583                         hflags &= ~HF_SMM_MASK;
3584                 kvm_set_hflags(vcpu, hflags);
3585 
3586                 vcpu->arch.smi_pending = events->smi.pending;
3587 
3588                 if (events->smi.smm) {
3589                         if (events->smi.smm_inside_nmi)
3590                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3591                         else
3592                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3593                         if (lapic_in_kernel(vcpu)) {
3594                                 if (events->smi.latched_init)
3595                                         set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3596                                 else
3597                                         clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3598                         }
3599                 }
3600         }
3601 
3602         kvm_make_request(KVM_REQ_EVENT, vcpu);
3603 
3604         return 0;
3605 }
3606 
3607 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3608                                              struct kvm_debugregs *dbgregs)
3609 {
3610         unsigned long val;
3611 
3612         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3613         kvm_get_dr(vcpu, 6, &val);
3614         dbgregs->dr6 = val;
3615         dbgregs->dr7 = vcpu->arch.dr7;
3616         dbgregs->flags = 0;
3617         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3618 }
3619 
3620 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3621                                             struct kvm_debugregs *dbgregs)
3622 {
3623         if (dbgregs->flags)
3624                 return -EINVAL;
3625 
3626         if (dbgregs->dr6 & ~0xffffffffull)
3627                 return -EINVAL;
3628         if (dbgregs->dr7 & ~0xffffffffull)
3629                 return -EINVAL;
3630 
3631         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3632         kvm_update_dr0123(vcpu);
3633         vcpu->arch.dr6 = dbgregs->dr6;
3634         kvm_update_dr6(vcpu);
3635         vcpu->arch.dr7 = dbgregs->dr7;
3636         kvm_update_dr7(vcpu);
3637 
3638         return 0;
3639 }
3640 
3641 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3642 
3643 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3644 {
3645         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3646         u64 xstate_bv = xsave->header.xfeatures;
3647         u64 valid;
3648 
3649         /*
3650          * Copy legacy XSAVE area, to avoid complications with CPUID
3651          * leaves 0 and 1 in the loop below.
3652          */
3653         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3654 
3655         /* Set XSTATE_BV */
3656         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3657         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3658 
3659         /*
3660          * Copy each region from the possibly compacted offset to the
3661          * non-compacted offset.
3662          */
3663         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3664         while (valid) {
3665                 u64 feature = valid & -valid;
3666                 int index = fls64(feature) - 1;
3667                 void *src = get_xsave_addr(xsave, feature);
3668 
3669                 if (src) {
3670                         u32 size, offset, ecx, edx;
3671                         cpuid_count(XSTATE_CPUID, index,
3672                                     &size, &offset, &ecx, &edx);
3673                         if (feature == XFEATURE_MASK_PKRU)
3674                                 memcpy(dest + offset, &vcpu->arch.pkru,
3675                                        sizeof(vcpu->arch.pkru));
3676                         else
3677                                 memcpy(dest + offset, src, size);
3678 
3679                 }
3680 
3681                 valid -= feature;
3682         }
3683 }
3684 
3685 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3686 {
3687         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3688         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3689         u64 valid;
3690 
3691         /*
3692          * Copy legacy XSAVE area, to avoid complications with CPUID
3693          * leaves 0 and 1 in the loop below.
3694          */
3695         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3696 
3697         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3698         xsave->header.xfeatures = xstate_bv;
3699         if (boot_cpu_has(X86_FEATURE_XSAVES))
3700                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3701 
3702         /*
3703          * Copy each region from the non-compacted offset to the
3704          * possibly compacted offset.
3705          */
3706         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3707         while (valid) {
3708                 u64 feature = valid & -valid;
3709                 int index = fls64(feature) - 1;
3710                 void *dest = get_xsave_addr(xsave, feature);
3711 
3712                 if (dest) {
3713                         u32 size, offset, ecx, edx;
3714                         cpuid_count(XSTATE_CPUID, index,
3715                                     &size, &offset, &ecx, &edx);
3716                         if (feature == XFEATURE_MASK_PKRU)
3717                                 memcpy(&vcpu->arch.pkru, src + offset,
3718                                        sizeof(vcpu->arch.pkru));
3719                         else
3720                                 memcpy(dest, src + offset, size);
3721                 }
3722 
3723                 valid -= feature;
3724         }
3725 }
3726 
3727 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3728                                          struct kvm_xsave *guest_xsave)
3729 {
3730         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3731                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3732                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3733         } else {
3734                 memcpy(guest_xsave->region,
3735                         &vcpu->arch.guest_fpu->state.fxsave,
3736                         sizeof(struct fxregs_state));
3737                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3738                         XFEATURE_MASK_FPSSE;
3739         }
3740 }
3741 
3742 #define XSAVE_MXCSR_OFFSET 24
3743 
3744 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3745                                         struct kvm_xsave *guest_xsave)
3746 {
3747         u64 xstate_bv =
3748                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3749         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3750 
3751         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3752                 /*
3753                  * Here we allow setting states that are not present in
3754                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3755                  * with old userspace.
3756                  */
3757                 if (xstate_bv & ~kvm_supported_xcr0() ||
3758                         mxcsr & ~mxcsr_feature_mask)
3759                         return -EINVAL;
3760                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3761         } else {
3762                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3763                         mxcsr & ~mxcsr_feature_mask)
3764                         return -EINVAL;
3765                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3766                         guest_xsave->region, sizeof(struct fxregs_state));
3767         }
3768         return 0;
3769 }
3770 
3771 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3772                                         struct kvm_xcrs *guest_xcrs)
3773 {
3774         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3775                 guest_xcrs->nr_xcrs = 0;
3776                 return;
3777         }
3778 
3779         guest_xcrs->nr_xcrs = 1;
3780         guest_xcrs->flags = 0;
3781         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3782         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3783 }
3784 
3785 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3786                                        struct kvm_xcrs *guest_xcrs)
3787 {
3788         int i, r = 0;
3789 
3790         if (!boot_cpu_has(X86_FEATURE_XSAVE))
3791                 return -EINVAL;
3792 
3793         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3794                 return -EINVAL;
3795 
3796         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3797                 /* Only support XCR0 currently */
3798                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3799                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3800                                 guest_xcrs->xcrs[i].value);
3801                         break;
3802                 }
3803         if (r)
3804                 r = -EINVAL;
3805         return r;
3806 }
3807 
3808 /*
3809  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3810  * stopped by the hypervisor.  This function will be called from the host only.
3811  * EINVAL is returned when the host attempts to set the flag for a guest that
3812  * does not support pv clocks.
3813  */
3814 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3815 {
3816         if (!vcpu->arch.pv_time_enabled)
3817                 return -EINVAL;
3818         vcpu->arch.pvclock_set_guest_stopped_request = true;
3819         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3820         return 0;
3821 }
3822 
3823 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3824                                      struct kvm_enable_cap *cap)
3825 {
3826         int r;
3827         uint16_t vmcs_version;
3828         void __user *user_ptr;
3829 
3830         if (cap->flags)
3831                 return -EINVAL;
3832 
3833         switch (cap->cap) {
3834         case KVM_CAP_HYPERV_SYNIC2:
3835                 if (cap->args[0])
3836                         return -EINVAL;
3837                 /* fall through */
3838 
3839         case KVM_CAP_HYPERV_SYNIC:
3840                 if (!irqchip_in_kernel(vcpu->kvm))
3841                         return -EINVAL;
3842                 return kvm_hv_activate_synic(vcpu, cap->cap ==
3843                                              KVM_CAP_HYPERV_SYNIC2);
3844         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3845                 if (!kvm_x86_ops->nested_enable_evmcs)
3846                         return -ENOTTY;
3847                 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3848                 if (!r) {
3849                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
3850                         if (copy_to_user(user_ptr, &vmcs_version,
3851                                          sizeof(vmcs_version)))
3852                                 r = -EFAULT;
3853                 }
3854                 return r;
3855 
3856         default:
3857                 return -EINVAL;
3858         }
3859 }
3860 
3861 long kvm_arch_vcpu_ioctl(struct file *filp,
3862                          unsigned int ioctl, unsigned long arg)
3863 {
3864         struct kvm_vcpu *vcpu = filp->private_data;
3865         void __user *argp = (void __user *)arg;
3866         int r;
3867         union {
3868                 struct kvm_lapic_state *lapic;
3869                 struct kvm_xsave *xsave;
3870                 struct kvm_xcrs *xcrs;
3871                 void *buffer;
3872         } u;
3873 
3874         vcpu_load(vcpu);
3875 
3876         u.buffer = NULL;
3877         switch (ioctl) {
3878         case KVM_GET_LAPIC: {
3879                 r = -EINVAL;
3880                 if (!lapic_in_kernel(vcpu))
3881                         goto out;
3882                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3883                                 GFP_KERNEL_ACCOUNT);
3884 
3885                 r = -ENOMEM;
3886                 if (!u.lapic)
3887                         goto out;
3888                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3889                 if (r)
3890                         goto out;
3891                 r = -EFAULT;
3892                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3893                         goto out;
3894                 r = 0;
3895                 break;
3896         }
3897         case KVM_SET_LAPIC: {
3898                 r = -EINVAL;
3899                 if (!lapic_in_kernel(vcpu))
3900                         goto out;
3901                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3902                 if (IS_ERR(u.lapic)) {
3903                         r = PTR_ERR(u.lapic);
3904                         goto out_nofree;
3905                 }
3906 
3907                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3908                 break;
3909         }
3910         case KVM_INTERRUPT: {
3911                 struct kvm_interrupt irq;
3912 
3913                 r = -EFAULT;
3914                 if (copy_from_user(&irq, argp, sizeof(irq)))
3915                         goto out;
3916                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3917                 break;
3918         }
3919         case KVM_NMI: {
3920                 r = kvm_vcpu_ioctl_nmi(vcpu);
3921                 break;
3922         }
3923         case KVM_SMI: {
3924                 r = kvm_vcpu_ioctl_smi(vcpu);
3925                 break;
3926         }
3927         case KVM_SET_CPUID: {
3928                 struct kvm_cpuid __user *cpuid_arg = argp;
3929                 struct kvm_cpuid cpuid;
3930 
3931                 r = -EFAULT;
3932                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3933                         goto out;
3934                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3935                 break;
3936         }
3937         case KVM_SET_CPUID2: {
3938                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3939                 struct kvm_cpuid2 cpuid;
3940 
3941                 r = -EFAULT;
3942                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3943                         goto out;
3944                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3945                                               cpuid_arg->entries);
3946                 break;
3947         }
3948         case KVM_GET_CPUID2: {
3949                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3950                 struct kvm_cpuid2 cpuid;
3951 
3952                 r = -EFAULT;
3953                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3954                         goto out;
3955                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3956                                               cpuid_arg->entries);
3957                 if (r)
3958                         goto out;
3959                 r = -EFAULT;
3960                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3961                         goto out;
3962                 r = 0;
3963                 break;
3964         }
3965         case KVM_GET_MSRS: {
3966                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3967                 r = msr_io(vcpu, argp, do_get_msr, 1);
3968                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3969                 break;
3970         }
3971         case KVM_SET_MSRS: {
3972                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3973                 r = msr_io(vcpu, argp, do_set_msr, 0);
3974                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3975                 break;
3976         }
3977         case KVM_TPR_ACCESS_REPORTING: {
3978                 struct kvm_tpr_access_ctl tac;
3979 
3980                 r = -EFAULT;
3981                 if (copy_from_user(&tac, argp, sizeof(tac)))
3982                         goto out;
3983                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3984                 if (r)
3985                         goto out;
3986                 r = -EFAULT;
3987                 if (copy_to_user(argp, &tac, sizeof(tac)))
3988                         goto out;
3989                 r = 0;
3990                 break;
3991         };
3992         case KVM_SET_VAPIC_ADDR: {
3993                 struct kvm_vapic_addr va;
3994                 int idx;
3995 
3996                 r = -EINVAL;
3997                 if (!lapic_in_kernel(vcpu))
3998                         goto out;
3999                 r = -EFAULT;
4000                 if (copy_from_user(&va, argp, sizeof(va)))
4001                         goto out;
4002                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4003                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4004                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4005                 break;
4006         }
4007         case KVM_X86_SETUP_MCE: {
4008                 u64 mcg_cap;
4009 
4010                 r = -EFAULT;
4011                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4012                         goto out;
4013                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4014                 break;
4015         }
4016         case KVM_X86_SET_MCE: {
4017                 struct kvm_x86_mce mce;
4018 
4019                 r = -EFAULT;
4020                 if (copy_from_user(&mce, argp, sizeof(mce)))
4021                         goto out;
4022                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4023                 break;
4024         }
4025         case KVM_GET_VCPU_EVENTS: {
4026                 struct kvm_vcpu_events events;
4027 
4028                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4029 
4030                 r = -EFAULT;
4031                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4032                         break;
4033                 r = 0;
4034                 break;
4035         }
4036         case KVM_SET_VCPU_EVENTS: {
4037                 struct kvm_vcpu_events events;
4038 
4039                 r = -EFAULT;
4040                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4041                         break;
4042 
4043                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4044                 break;
4045         }
4046         case KVM_GET_DEBUGREGS: {
4047                 struct kvm_debugregs dbgregs;
4048 
4049                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4050 
4051                 r = -EFAULT;
4052                 if (copy_to_user(argp, &dbgregs,
4053                                  sizeof(struct kvm_debugregs)))
4054                         break;
4055                 r = 0;
4056                 break;
4057         }
4058         case KVM_SET_DEBUGREGS: {
4059                 struct kvm_debugregs dbgregs;
4060 
4061                 r = -EFAULT;
4062                 if (copy_from_user(&dbgregs, argp,
4063                                    sizeof(struct kvm_debugregs)))
4064                         break;
4065 
4066                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4067                 break;
4068         }
4069         case KVM_GET_XSAVE: {
4070                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4071                 r = -ENOMEM;
4072                 if (!u.xsave)
4073                         break;
4074 
4075                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4076 
4077                 r = -EFAULT;
4078                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4079                         break;
4080                 r = 0;
4081                 break;
4082         }
4083         case KVM_SET_XSAVE: {
4084                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4085                 if (IS_ERR(u.xsave)) {
4086                         r = PTR_ERR(u.xsave);
4087                         goto out_nofree;
4088                 }
4089 
4090                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4091                 break;
4092         }
4093         case KVM_GET_XCRS: {
4094                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4095                 r = -ENOMEM;
4096                 if (!u.xcrs)
4097                         break;
4098 
4099                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4100 
4101                 r = -EFAULT;
4102                 if (copy_to_user(argp, u.xcrs,
4103                                  sizeof(struct kvm_xcrs)))
4104                         break;
4105                 r = 0;
4106                 break;
4107         }
4108         case KVM_SET_XCRS: {
4109                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4110                 if (IS_ERR(u.xcrs)) {
4111                         r = PTR_ERR(u.xcrs);
4112                         goto out_nofree;
4113                 }
4114 
4115                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4116                 break;
4117         }
4118         case KVM_SET_TSC_KHZ: {
4119                 u32 user_tsc_khz;
4120 
4121                 r = -EINVAL;
4122                 user_tsc_khz = (u32)arg;
4123 
4124                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4125                         goto out;
4126 
4127                 if (user_tsc_khz == 0)
4128                         user_tsc_khz = tsc_khz;
4129 
4130                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4131                         r = 0;
4132 
4133                 goto out;
4134         }
4135         case KVM_GET_TSC_KHZ: {
4136                 r = vcpu->arch.virtual_tsc_khz;
4137                 goto out;
4138         }
4139         case KVM_KVMCLOCK_CTRL: {
4140                 r = kvm_set_guest_paused(vcpu);
4141                 goto out;
4142         }
4143         case KVM_ENABLE_CAP: {
4144                 struct kvm_enable_cap cap;
4145 
4146                 r = -EFAULT;
4147                 if (copy_from_user(&cap, argp, sizeof(cap)))
4148                         goto out;
4149                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4150                 break;
4151         }
4152         case KVM_GET_NESTED_STATE: {
4153                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4154                 u32 user_data_size;
4155 
4156                 r = -EINVAL;
4157                 if (!kvm_x86_ops->get_nested_state)
4158                         break;
4159 
4160                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4161                 r = -EFAULT;
4162                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4163                         break;
4164 
4165                 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4166                                                   user_data_size);
4167                 if (r < 0)
4168                         break;
4169 
4170                 if (r > user_data_size) {
4171                         if (put_user(r, &user_kvm_nested_state->size))
4172                                 r = -EFAULT;
4173                         else
4174                                 r = -E2BIG;
4175                         break;
4176                 }
4177 
4178                 r = 0;
4179                 break;
4180         }
4181         case KVM_SET_NESTED_STATE: {
4182                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4183                 struct kvm_nested_state kvm_state;
4184 
4185                 r = -EINVAL;
4186                 if (!kvm_x86_ops->set_nested_state)
4187                         break;
4188 
4189                 r = -EFAULT;
4190                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4191                         break;
4192 
4193                 r = -EINVAL;
4194                 if (kvm_state.size < sizeof(kvm_state))
4195                         break;
4196 
4197                 if (kvm_state.flags &
4198                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4199                       | KVM_STATE_NESTED_EVMCS))
4200                         break;
4201 
4202                 /* nested_run_pending implies guest_mode.  */
4203                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4204                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4205                         break;
4206 
4207                 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4208                 break;
4209         }
4210         case KVM_GET_SUPPORTED_HV_CPUID: {
4211                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4212                 struct kvm_cpuid2 cpuid;
4213 
4214                 r = -EFAULT;
4215                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4216                         goto out;
4217 
4218                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4219                                                 cpuid_arg->entries);
4220                 if (r)
4221                         goto out;
4222 
4223                 r = -EFAULT;
4224                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4225                         goto out;
4226                 r = 0;
4227                 break;
4228         }
4229         default:
4230                 r = -EINVAL;
4231         }
4232 out:
4233         kfree(u.buffer);
4234 out_nofree:
4235         vcpu_put(vcpu);
4236         return r;
4237 }
4238 
4239 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4240 {
4241         return VM_FAULT_SIGBUS;
4242 }
4243 
4244 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4245 {
4246         int ret;
4247 
4248         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4249                 return -EINVAL;
4250         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4251         return ret;
4252 }
4253 
4254 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4255                                               u64 ident_addr)
4256 {
4257         return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4258 }
4259 
4260 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4261                                           u32 kvm_nr_mmu_pages)
4262 {
4263         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4264                 return -EINVAL;
4265 
4266         mutex_lock(&kvm->slots_lock);
4267 
4268         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4269         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4270 
4271         mutex_unlock(&kvm->slots_lock);
4272         return 0;
4273 }
4274 
4275 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4276 {
4277         return kvm->arch.n_max_mmu_pages;
4278 }
4279 
4280 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4281 {
4282         struct kvm_pic *pic = kvm->arch.vpic;
4283         int r;
4284 
4285         r = 0;
4286         switch (chip->chip_id) {
4287         case KVM_IRQCHIP_PIC_MASTER:
4288                 memcpy(&chip->chip.pic, &pic->pics[0],
4289                         sizeof(struct kvm_pic_state));
4290                 break;
4291         case KVM_IRQCHIP_PIC_SLAVE:
4292                 memcpy(&chip->chip.pic, &pic->pics[1],
4293                         sizeof(struct kvm_pic_state));
4294                 break;
4295         case KVM_IRQCHIP_IOAPIC:
4296                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4297                 break;
4298         default:
4299                 r = -EINVAL;
4300                 break;
4301         }
4302         return r;
4303 }
4304 
4305 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4306 {
4307         struct kvm_pic *pic = kvm->arch.vpic;
4308         int r;
4309 
4310         r = 0;
4311         switch (chip->chip_id) {
4312         case KVM_IRQCHIP_PIC_MASTER:
4313                 spin_lock(&pic->lock);
4314                 memcpy(&pic->pics[0], &chip->chip.pic,
4315                         sizeof(struct kvm_pic_state));
4316                 spin_unlock(&pic->lock);
4317                 break;
4318         case KVM_IRQCHIP_PIC_SLAVE:
4319                 spin_lock(&pic->lock);
4320                 memcpy(&pic->pics[1], &chip->chip.pic,
4321                         sizeof(struct kvm_pic_state));
4322                 spin_unlock(&pic->lock);
4323                 break;
4324         case KVM_IRQCHIP_IOAPIC:
4325                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4326                 break;
4327         default:
4328                 r = -EINVAL;
4329                 break;
4330         }
4331         kvm_pic_update_irq(pic);
4332         return r;
4333 }
4334 
4335 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4336 {
4337         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4338 
4339         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4340 
4341         mutex_lock(&kps->lock);
4342         memcpy(ps, &kps->channels, sizeof(*ps));
4343         mutex_unlock(&kps->lock);
4344         return 0;
4345 }
4346 
4347 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4348 {
4349         int i;
4350         struct kvm_pit *pit = kvm->arch.vpit;
4351 
4352         mutex_lock(&pit->pit_state.lock);
4353         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4354         for (i = 0; i < 3; i++)
4355                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4356         mutex_unlock(&pit->pit_state.lock);
4357         return 0;
4358 }
4359 
4360 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4361 {
4362         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4363         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4364                 sizeof(ps->channels));
4365         ps->flags = kvm->arch.vpit->pit_state.flags;
4366         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4367         memset(&ps->reserved, 0, sizeof(ps->reserved));
4368         return 0;
4369 }
4370 
4371 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4372 {
4373         int start = 0;
4374         int i;
4375         u32 prev_legacy, cur_legacy;
4376         struct kvm_pit *pit = kvm->arch.vpit;
4377 
4378         mutex_lock(&pit->pit_state.lock);
4379         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4380         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4381         if (!prev_legacy && cur_legacy)
4382                 start = 1;
4383         memcpy(&pit->pit_state.channels, &ps->channels,
4384                sizeof(pit->pit_state.channels));
4385         pit->pit_state.flags = ps->flags;
4386         for (i = 0; i < 3; i++)
4387                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4388                                    start && i == 0);
4389         mutex_unlock(&pit->pit_state.lock);
4390         return 0;
4391 }
4392 
4393 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4394                                  struct kvm_reinject_control *control)
4395 {
4396         struct kvm_pit *pit = kvm->arch.vpit;
4397 
4398         if (!pit)
4399                 return -ENXIO;
4400 
4401         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4402          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4403          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4404          */
4405         mutex_lock(&pit->pit_state.lock);
4406         kvm_pit_set_reinject(pit, control->pit_reinject);
4407         mutex_unlock(&pit->pit_state.lock);
4408 
4409         return 0;
4410 }
4411 
4412 /**
4413  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4414  * @kvm: kvm instance
4415  * @log: slot id and address to which we copy the log
4416  *
4417  * Steps 1-4 below provide general overview of dirty page logging. See
4418  * kvm_get_dirty_log_protect() function description for additional details.
4419  *
4420  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4421  * always flush the TLB (step 4) even if previous step failed  and the dirty
4422  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4423  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4424  * writes will be marked dirty for next log read.
4425  *
4426  *   1. Take a snapshot of the bit and clear it if needed.
4427  *   2. Write protect the corresponding page.
4428  *   3. Copy the snapshot to the userspace.
4429  *   4. Flush TLB's if needed.
4430  */
4431 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4432 {
4433         bool flush = false;
4434         int r;
4435 
4436         mutex_lock(&kvm->slots_lock);
4437 
4438         /*
4439          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4440          */
4441         if (kvm_x86_ops->flush_log_dirty)
4442                 kvm_x86_ops->flush_log_dirty(kvm);
4443 
4444         r = kvm_get_dirty_log_protect(kvm, log, &flush);
4445 
4446         /*
4447          * All the TLBs can be flushed out of mmu lock, see the comments in
4448          * kvm_mmu_slot_remove_write_access().
4449          */
4450         lockdep_assert_held(&kvm->slots_lock);
4451         if (flush)
4452                 kvm_flush_remote_tlbs(kvm);
4453 
4454         mutex_unlock(&kvm->slots_lock);
4455         return r;
4456 }
4457 
4458 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4459 {
4460         bool flush = false;
4461         int r;
4462 
4463         mutex_lock(&kvm->slots_lock);
4464 
4465         /*
4466          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4467          */
4468         if (kvm_x86_ops->flush_log_dirty)
4469                 kvm_x86_ops->flush_log_dirty(kvm);
4470 
4471         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4472 
4473         /*
4474          * All the TLBs can be flushed out of mmu lock, see the comments in
4475          * kvm_mmu_slot_remove_write_access().
4476          */
4477         lockdep_assert_held(&kvm->slots_lock);
4478         if (flush)
4479                 kvm_flush_remote_tlbs(kvm);
4480 
4481         mutex_unlock(&kvm->slots_lock);
4482         return r;
4483 }
4484 
4485 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4486                         bool line_status)
4487 {
4488         if (!irqchip_in_kernel(kvm))
4489                 return -ENXIO;
4490 
4491         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4492                                         irq_event->irq, irq_event->level,
4493                                         line_status);
4494         return 0;
4495 }
4496 
4497 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4498                             struct kvm_enable_cap *cap)
4499 {
4500         int r;
4501 
4502         if (cap->flags)
4503                 return -EINVAL;
4504 
4505         switch (cap->cap) {
4506         case KVM_CAP_DISABLE_QUIRKS:
4507                 kvm->arch.disabled_quirks = cap->args[0];
4508                 r = 0;
4509                 break;
4510         case KVM_CAP_SPLIT_IRQCHIP: {
4511                 mutex_lock(&kvm->lock);
4512                 r = -EINVAL;
4513                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4514                         goto split_irqchip_unlock;
4515                 r = -EEXIST;
4516                 if (irqchip_in_kernel(kvm))
4517                         goto split_irqchip_unlock;
4518                 if (kvm->created_vcpus)
4519                         goto split_irqchip_unlock;
4520                 r = kvm_setup_empty_irq_routing(kvm);
4521                 if (r)
4522                         goto split_irqchip_unlock;
4523                 /* Pairs with irqchip_in_kernel. */
4524                 smp_wmb();
4525                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4526                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4527                 r = 0;
4528 split_irqchip_unlock:
4529                 mutex_unlock(&kvm->lock);
4530                 break;
4531         }
4532         case KVM_CAP_X2APIC_API:
4533                 r = -EINVAL;
4534                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4535                         break;
4536 
4537                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4538                         kvm->arch.x2apic_format = true;
4539                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4540                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4541 
4542                 r = 0;
4543                 break;
4544         case KVM_CAP_X86_DISABLE_EXITS:
4545                 r = -EINVAL;
4546                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4547                         break;
4548 
4549                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4550                         kvm_can_mwait_in_guest())
4551                         kvm->arch.mwait_in_guest = true;
4552                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4553                         kvm->arch.hlt_in_guest = true;
4554                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4555                         kvm->arch.pause_in_guest = true;
4556                 r = 0;
4557                 break;
4558         case KVM_CAP_MSR_PLATFORM_INFO:
4559                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4560                 r = 0;
4561                 break;
4562         case KVM_CAP_EXCEPTION_PAYLOAD:
4563                 kvm->arch.exception_payload_enabled = cap->args[0];
4564                 r = 0;
4565                 break;
4566         default:
4567                 r = -EINVAL;
4568                 break;
4569         }
4570         return r;
4571 }
4572 
4573 long kvm_arch_vm_ioctl(struct file *filp,
4574                        unsigned int ioctl, unsigned long arg)
4575 {
4576         struct kvm *kvm = filp->private_data;
4577         void __user *argp = (void __user *)arg;
4578         int r = -ENOTTY;
4579         /*
4580          * This union makes it completely explicit to gcc-3.x
4581          * that these two variables' stack usage should be
4582          * combined, not added together.
4583          */
4584         union {
4585                 struct kvm_pit_state ps;
4586                 struct kvm_pit_state2 ps2;
4587                 struct kvm_pit_config pit_config;
4588         } u;
4589 
4590         switch (ioctl) {
4591         case KVM_SET_TSS_ADDR:
4592                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4593                 break;
4594         case KVM_SET_IDENTITY_MAP_ADDR: {
4595                 u64 ident_addr;
4596 
4597                 mutex_lock(&kvm->lock);
4598                 r = -EINVAL;
4599                 if (kvm->created_vcpus)
4600                         goto set_identity_unlock;
4601                 r = -EFAULT;
4602                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4603                         goto set_identity_unlock;
4604                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4605 set_identity_unlock:
4606                 mutex_unlock(&kvm->lock);
4607                 break;
4608         }
4609         case KVM_SET_NR_MMU_PAGES:
4610                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4611                 break;
4612         case KVM_GET_NR_MMU_PAGES:
4613                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4614                 break;
4615         case KVM_CREATE_IRQCHIP: {
4616                 mutex_lock(&kvm->lock);
4617 
4618                 r = -EEXIST;
4619                 if (irqchip_in_kernel(kvm))
4620                         goto create_irqchip_unlock;
4621 
4622                 r = -EINVAL;
4623                 if (kvm->created_vcpus)
4624                         goto create_irqchip_unlock;
4625 
4626                 r = kvm_pic_init(kvm);
4627                 if (r)
4628                         goto create_irqchip_unlock;
4629 
4630                 r = kvm_ioapic_init(kvm);
4631                 if (r) {
4632                         kvm_pic_destroy(kvm);
4633                         goto create_irqchip_unlock;
4634                 }
4635 
4636                 r = kvm_setup_default_irq_routing(kvm);
4637                 if (r) {
4638                         kvm_ioapic_destroy(kvm);
4639                         kvm_pic_destroy(kvm);
4640                         goto create_irqchip_unlock;
4641                 }
4642                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4643                 smp_wmb();
4644                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4645         create_irqchip_unlock:
4646                 mutex_unlock(&kvm->lock);
4647                 break;
4648         }
4649         case KVM_CREATE_PIT:
4650                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4651                 goto create_pit;
4652         case KVM_CREATE_PIT2:
4653                 r = -EFAULT;
4654                 if (copy_from_user(&u.pit_config, argp,
4655                                    sizeof(struct kvm_pit_config)))
4656                         goto out;
4657         create_pit:
4658                 mutex_lock(&kvm->lock);
4659                 r = -EEXIST;
4660                 if (kvm->arch.vpit)
4661                         goto create_pit_unlock;
4662                 r = -ENOMEM;
4663                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4664                 if (kvm->arch.vpit)
4665                         r = 0;
4666         create_pit_unlock:
4667                 mutex_unlock(&kvm->lock);
4668                 break;
4669         case KVM_GET_IRQCHIP: {
4670                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4671                 struct kvm_irqchip *chip;
4672 
4673                 chip = memdup_user(argp, sizeof(*chip));
4674                 if (IS_ERR(chip)) {
4675                         r = PTR_ERR(chip);
4676                         goto out;
4677                 }
4678 
4679                 r = -ENXIO;
4680                 if (!irqchip_kernel(kvm))
4681                         goto get_irqchip_out;
4682                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4683                 if (r)
4684                         goto get_irqchip_out;
4685                 r = -EFAULT;
4686                 if (copy_to_user(argp, chip, sizeof(*chip)))
4687                         goto get_irqchip_out;
4688                 r = 0;
4689         get_irqchip_out:
4690                 kfree(chip);
4691                 break;
4692         }
4693         case KVM_SET_IRQCHIP: {
4694                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4695                 struct kvm_irqchip *chip;
4696 
4697                 chip = memdup_user(argp, sizeof(*chip));
4698                 if (IS_ERR(chip)) {
4699                         r = PTR_ERR(chip);
4700                         goto out;
4701                 }
4702 
4703                 r = -ENXIO;
4704                 if (!irqchip_kernel(kvm))
4705                         goto set_irqchip_out;
4706                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4707                 if (r)
4708                         goto set_irqchip_out;
4709                 r = 0;
4710         set_irqchip_out:
4711                 kfree(chip);
4712                 break;
4713         }
4714         case KVM_GET_PIT: {
4715                 r = -EFAULT;
4716                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4717                         goto out;
4718                 r = -ENXIO;
4719                 if (!kvm->arch.vpit)
4720                         goto out;
4721                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4722                 if (r)
4723                         goto out;
4724                 r = -EFAULT;
4725                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4726                         goto out;
4727                 r = 0;
4728                 break;
4729         }
4730         case KVM_SET_PIT: {
4731                 r = -EFAULT;
4732                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4733                         goto out;
4734                 r = -ENXIO;
4735                 if (!kvm->arch.vpit)
4736                         goto out;
4737                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4738                 break;
4739         }
4740         case KVM_GET_PIT2: {
4741                 r = -ENXIO;
4742                 if (!kvm->arch.vpit)
4743                         goto out;
4744                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4745                 if (r)
4746                         goto out;
4747                 r = -EFAULT;
4748                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4749                         goto out;
4750                 r = 0;
4751                 break;
4752         }
4753         case KVM_SET_PIT2: {
4754                 r = -EFAULT;
4755                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4756                         goto out;
4757                 r = -ENXIO;
4758                 if (!kvm->arch.vpit)
4759                         goto out;
4760                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4761                 break;
4762         }
4763         case KVM_REINJECT_CONTROL: {
4764                 struct kvm_reinject_control control;
4765                 r =  -EFAULT;
4766                 if (copy_from_user(&control, argp, sizeof(control)))
4767                         goto out;
4768                 r = kvm_vm_ioctl_reinject(kvm, &control);
4769                 break;
4770         }
4771         case KVM_SET_BOOT_CPU_ID:
4772                 r = 0;
4773                 mutex_lock(&kvm->lock);
4774                 if (kvm->created_vcpus)
4775                         r = -EBUSY;
4776                 else
4777                         kvm->arch.bsp_vcpu_id = arg;
4778                 mutex_unlock(&kvm->lock);
4779                 break;
4780         case KVM_XEN_HVM_CONFIG: {
4781                 struct kvm_xen_hvm_config xhc;
4782                 r = -EFAULT;
4783                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4784                         goto out;
4785                 r = -EINVAL;
4786                 if (xhc.flags)
4787                         goto out;
4788                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4789                 r = 0;
4790                 break;
4791         }
4792         case KVM_SET_CLOCK: {
4793                 struct kvm_clock_data user_ns;
4794                 u64 now_ns;
4795 
4796                 r = -EFAULT;
4797                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4798                         goto out;
4799 
4800                 r = -EINVAL;
4801                 if (user_ns.flags)
4802                         goto out;
4803 
4804                 r = 0;
4805                 /*
4806                  * TODO: userspace has to take care of races with VCPU_RUN, so
4807                  * kvm_gen_update_masterclock() can be cut down to locked
4808                  * pvclock_update_vm_gtod_copy().
4809                  */
4810                 kvm_gen_update_masterclock(kvm);
4811                 now_ns = get_kvmclock_ns(kvm);
4812                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4813                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4814                 break;
4815         }
4816         case KVM_GET_CLOCK: {
4817                 struct kvm_clock_data user_ns;
4818                 u64 now_ns;
4819 
4820                 now_ns = get_kvmclock_ns(kvm);
4821                 user_ns.clock = now_ns;
4822                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4823                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4824 
4825                 r = -EFAULT;
4826                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4827                         goto out;
4828                 r = 0;
4829                 break;
4830         }
4831         case KVM_MEMORY_ENCRYPT_OP: {
4832                 r = -ENOTTY;
4833                 if (kvm_x86_ops->mem_enc_op)
4834                         r = kvm_x86_ops->mem_enc_op(kvm, argp);
4835                 break;
4836         }
4837         case KVM_MEMORY_ENCRYPT_REG_REGION: {
4838                 struct kvm_enc_region region;
4839 
4840                 r = -EFAULT;
4841                 if (copy_from_user(&region, argp, sizeof(region)))
4842                         goto out;
4843 
4844                 r = -ENOTTY;
4845                 if (kvm_x86_ops->mem_enc_reg_region)
4846                         r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4847                 break;
4848         }
4849         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4850                 struct kvm_enc_region region;
4851 
4852                 r = -EFAULT;
4853                 if (copy_from_user(&region, argp, sizeof(region)))
4854                         goto out;
4855 
4856                 r = -ENOTTY;
4857                 if (kvm_x86_ops->mem_enc_unreg_region)
4858                         r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4859                 break;
4860         }
4861         case KVM_HYPERV_EVENTFD: {
4862                 struct kvm_hyperv_eventfd hvevfd;
4863 
4864                 r = -EFAULT;
4865                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4866                         goto out;
4867                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4868                 break;
4869         }
4870         default:
4871                 r = -ENOTTY;
4872         }
4873 out:
4874         return r;
4875 }
4876 
4877 static void kvm_init_msr_list(void)
4878 {
4879         u32 dummy[2];
4880         unsigned i, j;
4881 
4882         for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4883                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4884                         continue;
4885 
4886                 /*
4887                  * Even MSRs that are valid in the host may not be exposed
4888                  * to the guests in some cases.
4889                  */
4890                 switch (msrs_to_save[i]) {
4891                 case MSR_IA32_BNDCFGS:
4892                         if (!kvm_mpx_supported())
4893                                 continue;
4894                         break;
4895                 case MSR_TSC_AUX:
4896                         if (!kvm_x86_ops->rdtscp_supported())
4897                                 continue;
4898                         break;
4899                 case MSR_IA32_RTIT_CTL:
4900                 case MSR_IA32_RTIT_STATUS:
4901                         if (!kvm_x86_ops->pt_supported())
4902                                 continue;
4903                         break;
4904                 case MSR_IA32_RTIT_CR3_MATCH:
4905                         if (!kvm_x86_ops->pt_supported() ||
4906                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4907                                 continue;
4908                         break;
4909                 case MSR_IA32_RTIT_OUTPUT_BASE:
4910                 case MSR_IA32_RTIT_OUTPUT_MASK:
4911                         if (!kvm_x86_ops->pt_supported() ||
4912                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4913                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4914                                 continue;
4915                         break;
4916                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4917                         if (!kvm_x86_ops->pt_supported() ||
4918                                 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4919                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4920                                 continue;
4921                         break;
4922                 }
4923                 default:
4924                         break;
4925                 }
4926 
4927                 if (j < i)
4928                         msrs_to_save[j] = msrs_to_save[i];
4929                 j++;
4930         }
4931         num_msrs_to_save = j;
4932 
4933         for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4934                 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4935                         continue;
4936 
4937                 if (j < i)
4938                         emulated_msrs[j] = emulated_msrs[i];
4939                 j++;
4940         }
4941         num_emulated_msrs = j;
4942 
4943         for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4944                 struct kvm_msr_entry msr;
4945 
4946                 msr.index = msr_based_features[i];
4947                 if (kvm_get_msr_feature(&msr))
4948                         continue;
4949 
4950                 if (j < i)
4951                         msr_based_features[j] = msr_based_features[i];
4952                 j++;
4953         }
4954         num_msr_based_features = j;
4955 }
4956 
4957 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4958                            const void *v)
4959 {
4960         int handled = 0;
4961         int n;
4962 
4963         do {
4964                 n = min(len, 8);
4965                 if (!(lapic_in_kernel(vcpu) &&
4966                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4967                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4968                         break;
4969                 handled += n;
4970                 addr += n;
4971                 len -= n;
4972                 v += n;
4973         } while (len);
4974 
4975         return handled;
4976 }
4977 
4978 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4979 {
4980         int handled = 0;
4981         int n;
4982 
4983         do {
4984                 n = min(len, 8);
4985                 if (!(lapic_in_kernel(vcpu) &&
4986                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4987                                          addr, n, v))
4988                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4989                         break;
4990                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4991                 handled += n;
4992                 addr += n;
4993                 len -= n;
4994                 v += n;
4995         } while (len);
4996 
4997         return handled;
4998 }
4999 
5000 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5001                         struct kvm_segment *var, int seg)
5002 {
5003         kvm_x86_ops->set_segment(vcpu, var, seg);
5004 }
5005 
5006 void kvm_get_segment(struct kvm_vcpu *vcpu,
5007                      struct kvm_segment *var, int seg)
5008 {
5009         kvm_x86_ops->get_segment(vcpu, var, seg);
5010 }
5011 
5012 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5013                            struct x86_exception *exception)
5014 {
5015         gpa_t t_gpa;
5016 
5017         BUG_ON(!mmu_is_nested(vcpu));
5018 
5019         /* NPT walks are always user-walks */
5020         access |= PFERR_USER_MASK;
5021         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5022 
5023         return t_gpa;
5024 }
5025 
5026 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5027                               struct x86_exception *exception)
5028 {
5029         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5030         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5031 }
5032 
5033  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5034                                 struct x86_exception *exception)
5035 {
5036         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5037         access |= PFERR_FETCH_MASK;
5038         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5039 }
5040 
5041 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5042                                struct x86_exception *exception)
5043 {
5044         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5045         access |= PFERR_WRITE_MASK;
5046         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5047 }
5048 
5049 /* uses this to access any guest's mapped memory without checking CPL */
5050 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5051                                 struct x86_exception *exception)
5052 {
5053         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5054 }
5055 
5056 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5057                                       struct kvm_vcpu *vcpu, u32 access,
5058                                       struct x86_exception *exception)
5059 {
5060         void *data = val;
5061         int r = X86EMUL_CONTINUE;
5062 
5063         while (bytes) {
5064                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5065                                                             exception);
5066                 unsigned offset = addr & (PAGE_SIZE-1);
5067                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5068                 int ret;
5069 
5070                 if (gpa == UNMAPPED_GVA)
5071                         return X86EMUL_PROPAGATE_FAULT;
5072                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5073                                                offset, toread);
5074                 if (ret < 0) {
5075                         r = X86EMUL_IO_NEEDED;
5076                         goto out;
5077                 }
5078 
5079                 bytes -= toread;
5080                 data += toread;
5081                 addr += toread;
5082         }
5083 out:
5084         return r;
5085 }
5086 
5087 /* used for instruction fetching */
5088 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5089                                 gva_t addr, void *val, unsigned int bytes,
5090                                 struct x86_exception *exception)
5091 {
5092         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5093         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5094         unsigned offset;
5095         int ret;
5096 
5097         /* Inline kvm_read_guest_virt_helper for speed.  */
5098         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5099                                                     exception);
5100         if (unlikely(gpa == UNMAPPED_GVA))
5101                 return X86EMUL_PROPAGATE_FAULT;
5102 
5103         offset = addr & (PAGE_SIZE-1);
5104         if (WARN_ON(offset + bytes > PAGE_SIZE))
5105                 bytes = (unsigned)PAGE_SIZE - offset;
5106         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5107                                        offset, bytes);
5108         if (unlikely(ret < 0))
5109                 return X86EMUL_IO_NEEDED;
5110 
5111         return X86EMUL_CONTINUE;
5112 }
5113 
5114 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5115                                gva_t addr, void *val, unsigned int bytes,
5116                                struct x86_exception *exception)
5117 {
5118         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5119 
5120         /*
5121          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5122          * is returned, but our callers are not ready for that and they blindly
5123          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5124          * uninitialized kernel stack memory into cr2 and error code.
5125          */
5126         memset(exception, 0, sizeof(*exception));
5127         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5128                                           exception);
5129 }
5130 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5131 
5132 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5133                              gva_t addr, void *val, unsigned int bytes,
5134                              struct x86_exception *exception, bool system)
5135 {
5136         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5137         u32 access = 0;
5138 
5139         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5140                 access |= PFERR_USER_MASK;
5141 
5142         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5143 }
5144 
5145 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5146                 unsigned long addr, void *val, unsigned int bytes)
5147 {
5148         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5149         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5150 
5151         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5152 }
5153 
5154 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5155                                       struct kvm_vcpu *vcpu, u32 access,
5156                                       struct x86_exception *exception)
5157 {
5158         void *data = val;
5159         int r = X86EMUL_CONTINUE;
5160 
5161         while (bytes) {
5162                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5163                                                              access,
5164                                                              exception);
5165                 unsigned offset = addr & (PAGE_SIZE-1);
5166                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5167                 int ret;
5168 
5169                 if (gpa == UNMAPPED_GVA)
5170                         return X86EMUL_PROPAGATE_FAULT;
5171                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5172                 if (ret < 0) {
5173                         r = X86EMUL_IO_NEEDED;
5174                         goto out;
5175                 }
5176 
5177                 bytes -= towrite;
5178                 data += towrite;
5179                 addr += towrite;
5180         }
5181 out:
5182         return r;
5183 }
5184 
5185 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5186                               unsigned int bytes, struct x86_exception *exception,
5187                               bool system)
5188 {
5189         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5190         u32 access = PFERR_WRITE_MASK;
5191 
5192         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5193                 access |= PFERR_USER_MASK;
5194 
5195         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5196                                            access, exception);
5197 }
5198 
5199 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5200                                 unsigned int bytes, struct x86_exception *exception)
5201 {
5202         /* kvm_write_guest_virt_system can pull in tons of pages. */
5203         vcpu->arch.l1tf_flush_l1d = true;
5204 
5205         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5206                                            PFERR_WRITE_MASK, exception);
5207 }
5208 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5209 
5210 int handle_ud(struct kvm_vcpu *vcpu)
5211 {
5212         int emul_type = EMULTYPE_TRAP_UD;
5213         enum emulation_result er;
5214         char sig[5]; /* ud2; .ascii "kvm" */
5215         struct x86_exception e;
5216 
5217         if (force_emulation_prefix &&
5218             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5219                                 sig, sizeof(sig), &e) == 0 &&
5220             memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5221                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5222                 emul_type = 0;
5223         }
5224 
5225         er = kvm_emulate_instruction(vcpu, emul_type);
5226         if (er == EMULATE_USER_EXIT)
5227                 return 0;
5228         if (er != EMULATE_DONE)
5229                 kvm_queue_exception(vcpu, UD_VECTOR);
5230         return 1;
5231 }
5232 EXPORT_SYMBOL_GPL(handle_ud);
5233 
5234 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5235                             gpa_t gpa, bool write)
5236 {
5237         /* For APIC access vmexit */
5238         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5239                 return 1;
5240 
5241         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5242                 trace_vcpu_match_mmio(gva, gpa, write, true);
5243                 return 1;
5244         }
5245 
5246         return 0;
5247 }
5248 
5249 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5250                                 gpa_t *gpa, struct x86_exception *exception,
5251                                 bool write)
5252 {
5253         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5254                 | (write ? PFERR_WRITE_MASK : 0);
5255 
5256         /*
5257          * currently PKRU is only applied to ept enabled guest so
5258          * there is no pkey in EPT page table for L1 guest or EPT
5259          * shadow page table for L2 guest.
5260          */
5261         if (vcpu_match_mmio_gva(vcpu, gva)
5262             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5263                                  vcpu->arch.access, 0, access)) {
5264                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5265                                         (gva & (PAGE_SIZE - 1));
5266                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5267                 return 1;
5268         }
5269 
5270         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5271 
5272         if (*gpa == UNMAPPED_GVA)
5273                 return -1;
5274 
5275         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5276 }
5277 
5278 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5279                         const void *val, int bytes)
5280 {
5281         int ret;
5282 
5283         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5284         if (ret < 0)
5285                 return 0;
5286         kvm_page_track_write(vcpu, gpa, val, bytes);
5287         return 1;
5288 }
5289 
5290 struct read_write_emulator_ops {
5291         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5292                                   int bytes);
5293         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5294                                   void *val, int bytes);
5295         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5296                                int bytes, void *val);
5297         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5298                                     void *val, int bytes);
5299         bool write;
5300 };
5301 
5302 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5303 {
5304         if (vcpu->mmio_read_completed) {
5305                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5306                                vcpu->mmio_fragments[0].gpa, val);
5307                 vcpu->mmio_read_completed = 0;
5308                 return 1;
5309         }
5310 
5311         return 0;
5312 }
5313 
5314 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5315                         void *val, int bytes)
5316 {
5317         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5318 }
5319 
5320 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5321                          void *val, int bytes)
5322 {
5323         return emulator_write_phys(vcpu, gpa, val, bytes);
5324 }
5325 
5326 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5327 {
5328         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5329         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5330 }
5331 
5332 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5333                           void *val, int bytes)
5334 {
5335         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5336         return X86EMUL_IO_NEEDED;
5337 }
5338 
5339 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5340                            void *val, int bytes)
5341 {
5342         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5343 
5344         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5345         return X86EMUL_CONTINUE;
5346 }
5347 
5348 static const struct read_write_emulator_ops read_emultor = {
5349         .read_write_prepare = read_prepare,
5350         .read_write_emulate = read_emulate,
5351         .read_write_mmio = vcpu_mmio_read,
5352         .read_write_exit_mmio = read_exit_mmio,
5353 };
5354 
5355 static const struct read_write_emulator_ops write_emultor = {
5356         .read_write_emulate = write_emulate,
5357         .read_write_mmio = write_mmio,
5358         .read_write_exit_mmio = write_exit_mmio,
5359         .write = true,
5360 };
5361 
5362 static int emulator_read_write_onepage(unsigned long addr, void *val,
5363                                        unsigned int bytes,
5364                                        struct x86_exception *exception,
5365                                        struct kvm_vcpu *vcpu,
5366                                        const struct read_write_emulator_ops *ops)
5367 {
5368         gpa_t gpa;
5369         int handled, ret;
5370         bool write = ops->write;
5371         struct kvm_mmio_fragment *frag;
5372         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5373 
5374         /*
5375          * If the exit was due to a NPF we may already have a GPA.
5376          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5377          * Note, this cannot be used on string operations since string
5378          * operation using rep will only have the initial GPA from the NPF
5379          * occurred.
5380          */
5381         if (vcpu->arch.gpa_available &&
5382             emulator_can_use_gpa(ctxt) &&
5383             (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5384                 gpa = vcpu->arch.gpa_val;
5385                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5386         } else {
5387                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5388                 if (ret < 0)
5389                         return X86EMUL_PROPAGATE_FAULT;
5390         }
5391 
5392         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5393                 return X86EMUL_CONTINUE;
5394 
5395         /*
5396          * Is this MMIO handled locally?
5397          */
5398         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5399         if (handled == bytes)
5400                 return X86EMUL_CONTINUE;
5401 
5402         gpa += handled;
5403         bytes -= handled;
5404         val += handled;
5405 
5406         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5407         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5408         frag->gpa = gpa;
5409         frag->data = val;
5410         frag->len = bytes;
5411         return X86EMUL_CONTINUE;
5412 }
5413 
5414 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5415                         unsigned long addr,
5416                         void *val, unsigned int bytes,
5417                         struct x86_exception *exception,
5418                         const struct read_write_emulator_ops *ops)
5419 {
5420         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5421         gpa_t gpa;
5422         int rc;
5423 
5424         if (ops->read_write_prepare &&
5425                   ops->read_write_prepare(vcpu, val, bytes))
5426                 return X86EMUL_CONTINUE;
5427 
5428         vcpu->mmio_nr_fragments = 0;
5429 
5430         /* Crossing a page boundary? */
5431         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5432                 int now;
5433 
5434                 now = -addr & ~PAGE_MASK;
5435                 rc = emulator_read_write_onepage(addr, val, now, exception,
5436                                                  vcpu, ops);
5437 
5438                 if (rc != X86EMUL_CONTINUE)
5439                         return rc;
5440                 addr += now;
5441                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5442                         addr = (u32)addr;
5443                 val += now;
5444                 bytes -= now;
5445         }
5446 
5447         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5448                                          vcpu, ops);
5449         if (rc != X86EMUL_CONTINUE)
5450                 return rc;
5451 
5452         if (!vcpu->mmio_nr_fragments)
5453                 return rc;
5454 
5455         gpa = vcpu->mmio_fragments[0].gpa;
5456 
5457         vcpu->mmio_needed = 1;
5458         vcpu->mmio_cur_fragment = 0;
5459 
5460         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5461         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5462         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5463         vcpu->run->mmio.phys_addr = gpa;
5464 
5465         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5466 }
5467 
5468 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5469                                   unsigned long addr,
5470                                   void *val,
5471                                   unsigned int bytes,
5472                                   struct x86_exception *exception)
5473 {
5474         return emulator_read_write(ctxt, addr, val, bytes,
5475                                    exception, &read_emultor);
5476 }
5477 
5478 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5479                             unsigned long addr,
5480                             const void *val,
5481                             unsigned int bytes,
5482                             struct x86_exception *exception)
5483 {
5484         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5485                                    exception, &write_emultor);
5486 }
5487 
5488 #define CMPXCHG_TYPE(t, ptr, old, new) \
5489         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5490 
5491 #ifdef CONFIG_X86_64
5492 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5493 #else
5494 #  define CMPXCHG64(ptr, old, new) \
5495         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5496 #endif
5497 
5498 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5499                                      unsigned long addr,
5500                                      const void *old,
5501                                      const void *new,
5502                                      unsigned int bytes,
5503                                      struct x86_exception *exception)
5504 {
5505         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5506         gpa_t gpa;
5507         struct page *page;
5508         char *kaddr;
5509         bool exchanged;
5510 
5511         /* guests cmpxchg8b have to be emulated atomically */
5512         if (bytes > 8 || (bytes & (bytes - 1)))
5513                 goto emul_write;
5514 
5515         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5516 
5517         if (gpa == UNMAPPED_GVA ||
5518             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5519                 goto emul_write;
5520 
5521         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5522                 goto emul_write;
5523 
5524         page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5525         if (is_error_page(page))
5526                 goto emul_write;
5527 
5528         kaddr = kmap_atomic(page);
5529         kaddr += offset_in_page(gpa);
5530         switch (bytes) {
5531         case 1:
5532                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5533                 break;
5534         case 2:
5535                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5536                 break;
5537         case 4:
5538                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5539                 break;
5540         case 8:
5541                 exchanged = CMPXCHG64(kaddr, old, new);
5542                 break;
5543         default:
5544                 BUG();
5545         }
5546         kunmap_atomic(kaddr);
5547         kvm_release_page_dirty(page);
5548 
5549         if (!exchanged)
5550                 return X86EMUL_CMPXCHG_FAILED;
5551 
5552         kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5553         kvm_page_track_write(vcpu, gpa, new, bytes);
5554 
5555         return X86EMUL_CONTINUE;
5556 
5557 emul_write:
5558         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5559 
5560         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5561 }
5562 
5563 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5564 {
5565         int r = 0, i;
5566 
5567         for (i = 0; i < vcpu->arch.pio.count; i++) {
5568                 if (vcpu->arch.pio.in)
5569                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5570                                             vcpu->arch.pio.size, pd);
5571                 else
5572                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5573                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5574                                              pd);
5575                 if (r)
5576                         break;
5577                 pd += vcpu->arch.pio.size;
5578         }
5579         return r;
5580 }
5581 
5582 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5583                                unsigned short port, void *val,
5584                                unsigned int count, bool in)
5585 {
5586         vcpu->arch.pio.port = port;
5587         vcpu->arch.pio.in = in;
5588         vcpu->arch.pio.count  = count;
5589         vcpu->arch.pio.size = size;
5590 
5591         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5592                 vcpu->arch.pio.count = 0;
5593                 return 1;
5594         }
5595 
5596         vcpu->run->exit_reason = KVM_EXIT_IO;
5597         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5598         vcpu->run->io.size = size;
5599         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5600         vcpu->run->io.count = count;
5601         vcpu->run->io.port = port;
5602 
5603         return 0;
5604 }
5605 
5606 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5607                                     int size, unsigned short port, void *val,
5608                                     unsigned int count)
5609 {
5610         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5611         int ret;
5612 
5613         if (vcpu->arch.pio.count)
5614                 goto data_avail;
5615 
5616         memset(vcpu->arch.pio_data, 0, size * count);
5617 
5618         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5619         if (ret) {
5620 data_avail:
5621                 memcpy(val, vcpu->arch.pio_data, size * count);
5622                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5623                 vcpu->arch.pio.count = 0;
5624                 return 1;
5625         }
5626 
5627         return 0;
5628 }
5629 
5630 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5631                                      int size, unsigned short port,
5632                                      const void *val, unsigned int count)
5633 {
5634         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5635 
5636         memcpy(vcpu->arch.pio_data, val, size * count);
5637         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5638         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5639 }
5640 
5641 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5642 {
5643         return kvm_x86_ops->get_segment_base(vcpu, seg);
5644 }
5645 
5646 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5647 {
5648         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5649 }
5650 
5651 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5652 {
5653         if (!need_emulate_wbinvd(vcpu))
5654                 return X86EMUL_CONTINUE;
5655 
5656         if (kvm_x86_ops->has_wbinvd_exit()) {
5657                 int cpu = get_cpu();
5658 
5659                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5660                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5661                                 wbinvd_ipi, NULL, 1);
5662                 put_cpu();
5663                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5664         } else
5665                 wbinvd();
5666         return X86EMUL_CONTINUE;
5667 }
5668 
5669 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5670 {
5671         kvm_emulate_wbinvd_noskip(vcpu);
5672         return kvm_skip_emulated_instruction(vcpu);
5673 }
5674 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5675 
5676 
5677 
5678 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5679 {
5680         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5681 }
5682 
5683 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5684                            unsigned long *dest)
5685 {
5686         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5687 }
5688 
5689 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5690                            unsigned long value)
5691 {
5692 
5693         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5694 }
5695 
5696 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5697 {
5698         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5699 }
5700 
5701 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5702 {
5703         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5704         unsigned long value;
5705 
5706         switch (cr) {
5707         case 0:
5708                 value = kvm_read_cr0(vcpu);
5709                 break;
5710         case 2:
5711                 value = vcpu->arch.cr2;
5712                 break;
5713         case 3:
5714                 value = kvm_read_cr3(vcpu);
5715                 break;
5716         case 4:
5717                 value = kvm_read_cr4(vcpu);
5718                 break;
5719         case 8:
5720                 value = kvm_get_cr8(vcpu);
5721                 break;
5722         default:
5723                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5724                 return 0;
5725         }
5726 
5727         return value;
5728 }
5729 
5730 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5731 {
5732         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5733         int res = 0;
5734 
5735         switch (cr) {
5736         case 0:
5737                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5738                 break;
5739         case 2:
5740                 vcpu->arch.cr2 = val;
5741                 break;
5742         case 3:
5743                 res = kvm_set_cr3(vcpu, val);
5744                 break;
5745         case 4:
5746                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5747                 break;
5748         case 8:
5749                 res = kvm_set_cr8(vcpu, val);
5750                 break;
5751         default:
5752                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5753                 res = -1;
5754         }
5755 
5756         return res;
5757 }
5758 
5759 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5760 {
5761         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5762 }
5763 
5764 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5765 {
5766         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5767 }
5768 
5769 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5770 {
5771         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5772 }
5773 
5774 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5775 {
5776         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5777 }
5778 
5779 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5780 {
5781         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5782 }
5783 
5784 static unsigned long emulator_get_cached_segment_base(
5785         struct x86_emulate_ctxt *ctxt, int seg)
5786 {
5787         return get_segment_base(emul_to_vcpu(ctxt), seg);
5788 }
5789 
5790 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5791                                  struct desc_struct *desc, u32 *base3,
5792                                  int seg)
5793 {
5794         struct kvm_segment var;
5795 
5796         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5797         *selector = var.selector;
5798 
5799         if (var.unusable) {
5800                 memset(desc, 0, sizeof(*desc));
5801                 if (base3)
5802                         *base3 = 0;
5803                 return false;
5804         }
5805 
5806         if (var.g)
5807                 var.limit >>= 12;
5808         set_desc_limit(desc, var.limit);
5809         set_desc_base(desc, (unsigned long)var.base);
5810 #ifdef CONFIG_X86_64
5811         if (base3)
5812                 *base3 = var.base >> 32;
5813 #endif
5814         desc->type = var.type;
5815         desc->s = var.s;
5816         desc->dpl = var.dpl;
5817         desc->p = var.present;
5818         desc->avl = var.avl;
5819         desc->l = var.l;
5820         desc->d = var.db;
5821         desc->g = var.g;
5822 
5823         return true;
5824 }
5825 
5826 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5827                                  struct desc_struct *desc, u32 base3,
5828                                  int seg)
5829 {
5830         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5831         struct kvm_segment var;
5832 
5833         var.selector = selector;
5834         var.base = get_desc_base(desc);
5835 #ifdef CONFIG_X86_64
5836         var.base |= ((u64)base3) << 32;
5837 #endif
5838         var.limit = get_desc_limit(desc);
5839         if (desc->g)
5840                 var.limit = (var.limit << 12) | 0xfff;
5841         var.type = desc->type;
5842         var.dpl = desc->dpl;
5843         var.db = desc->d;
5844         var.s = desc->s;
5845         var.l = desc->l;
5846         var.g = desc->g;
5847         var.avl = desc->avl;
5848         var.present = desc->p;
5849         var.unusable = !var.present;
5850         var.padding = 0;
5851 
5852         kvm_set_segment(vcpu, &var, seg);
5853         return;
5854 }
5855 
5856 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5857                             u32 msr_index, u64 *pdata)
5858 {
5859         struct msr_data msr;
5860         int r;
5861 
5862         msr.index = msr_index;
5863         msr.host_initiated = false;
5864         r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5865         if (r)
5866                 return r;
5867 
5868         *pdata = msr.data;
5869         return 0;
5870 }
5871 
5872 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5873                             u32 msr_index, u64 data)
5874 {
5875         struct msr_data msr;
5876 
5877         msr.data = data;
5878         msr.index = msr_index;
5879         msr.host_initiated = false;
5880         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5881 }
5882 
5883 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5884 {
5885         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5886 
5887         return vcpu->arch.smbase;
5888 }
5889 
5890 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5891 {
5892         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5893 
5894         vcpu->arch.smbase = smbase;
5895 }
5896 
5897 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5898                               u32 pmc)
5899 {
5900         return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5901 }
5902 
5903 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5904                              u32 pmc, u64 *pdata)
5905 {
5906         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5907 }
5908 
5909 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5910 {
5911         emul_to_vcpu(ctxt)->arch.halt_request = 1;
5912 }
5913 
5914 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5915                               struct x86_instruction_info *info,
5916                               enum x86_intercept_stage stage)
5917 {
5918         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5919 }
5920 
5921 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5922                         u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5923 {
5924         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5925 }
5926 
5927 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5928 {
5929         return kvm_register_read(emul_to_vcpu(ctxt), reg);
5930 }
5931 
5932 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5933 {
5934         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5935 }
5936 
5937 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5938 {
5939         kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5940 }
5941 
5942 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5943 {
5944         return emul_to_vcpu(ctxt)->arch.hflags;
5945 }
5946 
5947 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5948 {
5949         kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5950 }
5951 
5952 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5953 {
5954         return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5955 }
5956 
5957 static const struct x86_emulate_ops emulate_ops = {
5958         .read_gpr            = emulator_read_gpr,
5959         .write_gpr           = emulator_write_gpr,
5960         .read_std            = emulator_read_std,
5961         .write_std           = emulator_write_std,
5962         .read_phys           = kvm_read_guest_phys_system,
5963         .fetch               = kvm_fetch_guest_virt,
5964         .read_emulated       = emulator_read_emulated,
5965         .write_emulated      = emulator_write_emulated,
5966         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
5967         .invlpg              = emulator_invlpg,
5968         .pio_in_emulated     = emulator_pio_in_emulated,
5969         .pio_out_emulated    = emulator_pio_out_emulated,
5970         .get_segment         = emulator_get_segment,
5971         .set_segment         = emulator_set_segment,
5972         .get_cached_segment_base = emulator_get_cached_segment_base,
5973         .get_gdt             = emulator_get_gdt,
5974         .get_idt             = emulator_get_idt,
5975         .set_gdt             = emulator_set_gdt,
5976         .set_idt             = emulator_set_idt,
5977         .get_cr              = emulator_get_cr,
5978         .set_cr              = emulator_set_cr,
5979         .cpl                 = emulator_get_cpl,
5980         .get_dr              = emulator_get_dr,
5981         .set_dr              = emulator_set_dr,
5982         .get_smbase          = emulator_get_smbase,
5983         .set_smbase          = emulator_set_smbase,
5984         .set_msr             = emulator_set_msr,
5985         .get_msr             = emulator_get_msr,
5986         .check_pmc           = emulator_check_pmc,
5987         .read_pmc            = emulator_read_pmc,
5988         .halt                = emulator_halt,
5989         .wbinvd              = emulator_wbinvd,
5990         .fix_hypercall       = emulator_fix_hypercall,
5991         .intercept           = emulator_intercept,
5992         .get_cpuid           = emulator_get_cpuid,
5993         .set_nmi_mask        = emulator_set_nmi_mask,
5994         .get_hflags          = emulator_get_hflags,
5995         .set_hflags          = emulator_set_hflags,
5996         .pre_leave_smm       = emulator_pre_leave_smm,
5997 };
5998 
5999 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6000 {
6001         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6002         /*
6003          * an sti; sti; sequence only disable interrupts for the first
6004          * instruction. So, if the last instruction, be it emulated or
6005          * not, left the system with the INT_STI flag enabled, it
6006          * means that the last instruction is an sti. We should not
6007          * leave the flag on in this case. The same goes for mov ss
6008          */
6009         if (int_shadow & mask)
6010                 mask = 0;
6011         if (unlikely(int_shadow || mask)) {
6012                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6013                 if (!mask)
6014                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6015         }
6016 }
6017 
6018 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6019 {
6020         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6021         if (ctxt->exception.vector == PF_VECTOR)
6022                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6023 
6024         if (ctxt->exception.error_code_valid)
6025                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6026                                       ctxt->exception.error_code);
6027         else
6028                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6029         return false;
6030 }
6031 
6032 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6033 {
6034         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6035         int cs_db, cs_l;
6036 
6037         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6038 
6039         ctxt->eflags = kvm_get_rflags(vcpu);
6040         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6041 
6042         ctxt->eip = kvm_rip_read(vcpu);
6043         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6044                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6045                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6046                      cs_db                              ? X86EMUL_MODE_PROT32 :
6047                                                           X86EMUL_MODE_PROT16;
6048         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6049         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6050         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6051 
6052         init_decode_cache(ctxt);
6053         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6054 }
6055 
6056 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6057 {
6058         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6059         int ret;
6060 
6061         init_emulate_ctxt(vcpu);
6062 
6063         ctxt->op_bytes = 2;
6064         ctxt->ad_bytes = 2;
6065         ctxt->_eip = ctxt->eip + inc_eip;
6066         ret = emulate_int_real(ctxt, irq);
6067 
6068         if (ret != X86EMUL_CONTINUE)
6069                 return EMULATE_FAIL;
6070 
6071         ctxt->eip = ctxt->_eip;
6072         kvm_rip_write(vcpu, ctxt->eip);
6073         kvm_set_rflags(vcpu, ctxt->eflags);
6074 
6075         return EMULATE_DONE;
6076 }
6077 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6078 
6079 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6080 {
6081         int r = EMULATE_DONE;
6082 
6083         ++vcpu->stat.insn_emulation_fail;
6084         trace_kvm_emulate_insn_failed(vcpu);
6085 
6086         if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6087                 return EMULATE_FAIL;
6088 
6089         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6090                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6091                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6092                 vcpu->run->internal.ndata = 0;
6093                 r = EMULATE_USER_EXIT;
6094         }
6095 
6096         kvm_queue_exception(vcpu, UD_VECTOR);
6097 
6098         return r;
6099 }
6100 
6101 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6102                                   bool write_fault_to_shadow_pgtable,
6103                                   int emulation_type)
6104 {
6105         gpa_t gpa = cr2;
6106         kvm_pfn_t pfn;
6107 
6108         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6109                 return false;
6110 
6111         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6112                 return false;
6113 
6114         if (!vcpu->arch.mmu->direct_map) {
6115                 /*
6116                  * Write permission should be allowed since only
6117                  * write access need to be emulated.
6118                  */
6119                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6120 
6121                 /*
6122                  * If the mapping is invalid in guest, let cpu retry
6123                  * it to generate fault.
6124                  */
6125                 if (gpa == UNMAPPED_GVA)
6126                         return true;
6127         }
6128 
6129         /*
6130          * Do not retry the unhandleable instruction if it faults on the
6131          * readonly host memory, otherwise it will goto a infinite loop:
6132          * retry instruction -> write #PF -> emulation fail -> retry
6133          * instruction -> ...
6134          */
6135         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6136 
6137         /*
6138          * If the instruction failed on the error pfn, it can not be fixed,
6139          * report the error to userspace.
6140          */
6141         if (is_error_noslot_pfn(pfn))
6142                 return false;
6143 
6144         kvm_release_pfn_clean(pfn);
6145 
6146         /* The instructions are well-emulated on direct mmu. */
6147         if (vcpu->arch.mmu->direct_map) {
6148                 unsigned int indirect_shadow_pages;
6149 
6150                 spin_lock(&vcpu->kvm->mmu_lock);
6151                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6152                 spin_unlock(&vcpu->kvm->mmu_lock);
6153 
6154                 if (indirect_shadow_pages)
6155                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6156 
6157                 return true;
6158         }
6159 
6160         /*
6161          * if emulation was due to access to shadowed page table
6162          * and it failed try to unshadow page and re-enter the
6163          * guest to let CPU execute the instruction.
6164          */
6165         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6166 
6167         /*
6168          * If the access faults on its page table, it can not
6169          * be fixed by unprotecting shadow page and it should
6170          * be reported to userspace.
6171          */
6172         return !write_fault_to_shadow_pgtable;
6173 }
6174 
6175 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6176                               unsigned long cr2,  int emulation_type)
6177 {
6178         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6179         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6180 
6181         last_retry_eip = vcpu->arch.last_retry_eip;
6182         last_retry_addr = vcpu->arch.last_retry_addr;
6183 
6184         /*
6185          * If the emulation is caused by #PF and it is non-page_table
6186          * writing instruction, it means the VM-EXIT is caused by shadow
6187          * page protected, we can zap the shadow page and retry this
6188          * instruction directly.
6189          *
6190          * Note: if the guest uses a non-page-table modifying instruction
6191          * on the PDE that points to the instruction, then we will unmap
6192          * the instruction and go to an infinite loop. So, we cache the
6193          * last retried eip and the last fault address, if we meet the eip
6194          * and the address again, we can break out of the potential infinite
6195          * loop.
6196          */
6197         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6198 
6199         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6200                 return false;
6201 
6202         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6203                 return false;
6204 
6205         if (x86_page_table_writing_insn(ctxt))
6206                 return false;
6207 
6208         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6209                 return false;
6210 
6211         vcpu->arch.last_retry_eip = ctxt->eip;
6212         vcpu->arch.last_retry_addr = cr2;
6213 
6214         if (!vcpu->arch.mmu->direct_map)
6215                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6216 
6217         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6218 
6219         return true;
6220 }
6221 
6222 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6223 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6224 
6225 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6226 {
6227         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6228                 /* This is a good place to trace that we are exiting SMM.  */
6229                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6230 
6231                 /* Process a latched INIT or SMI, if any.  */
6232                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6233         }
6234 
6235         kvm_mmu_reset_context(vcpu);
6236 }
6237 
6238 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6239 {
6240         unsigned changed = vcpu->arch.hflags ^ emul_flags;
6241 
6242         vcpu->arch.hflags = emul_flags;
6243 
6244         if (changed & HF_SMM_MASK)
6245                 kvm_smm_changed(vcpu);
6246 }
6247 
6248 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6249                                 unsigned long *db)
6250 {
6251         u32 dr6 = 0;
6252         int i;
6253         u32 enable, rwlen;
6254 
6255         enable = dr7;
6256         rwlen = dr7 >> 16;
6257         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6258                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6259                         dr6 |= (1 << i);
6260         return dr6;
6261 }
6262 
6263 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6264 {
6265         struct kvm_run *kvm_run = vcpu->run;
6266 
6267         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6268                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6269                 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6270                 kvm_run->debug.arch.exception = DB_VECTOR;
6271                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6272                 *r = EMULATE_USER_EXIT;
6273         } else {
6274                 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6275         }
6276 }
6277 
6278 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6279 {
6280         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6281         int r = EMULATE_DONE;
6282 
6283         kvm_x86_ops->skip_emulated_instruction(vcpu);
6284 
6285         /*
6286          * rflags is the old, "raw" value of the flags.  The new value has
6287          * not been saved yet.
6288          *
6289          * This is correct even for TF set by the guest, because "the
6290          * processor will not generate this exception after the instruction
6291          * that sets the TF flag".
6292          */
6293         if (unlikely(rflags & X86_EFLAGS_TF))
6294                 kvm_vcpu_do_singlestep(vcpu, &r);
6295         return r == EMULATE_DONE;
6296 }
6297 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6298 
6299 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6300 {
6301         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6302             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6303                 struct kvm_run *kvm_run = vcpu->run;
6304                 unsigned long eip = kvm_get_linear_rip(vcpu);
6305                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6306                                            vcpu->arch.guest_debug_dr7,
6307                                            vcpu->arch.eff_db);
6308 
6309                 if (dr6 != 0) {
6310                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6311                         kvm_run->debug.arch.pc = eip;
6312                         kvm_run->debug.arch.exception = DB_VECTOR;
6313                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6314                         *r = EMULATE_USER_EXIT;
6315                         return true;
6316                 }
6317         }
6318 
6319         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6320             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6321                 unsigned long eip = kvm_get_linear_rip(vcpu);
6322                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6323                                            vcpu->arch.dr7,
6324                                            vcpu->arch.db);
6325 
6326                 if (dr6 != 0) {
6327                         vcpu->arch.dr6 &= ~15;
6328                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6329                         kvm_queue_exception(vcpu, DB_VECTOR);
6330                         *r = EMULATE_DONE;
6331                         return true;
6332                 }
6333         }
6334 
6335         return false;
6336 }
6337 
6338 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6339 {
6340         switch (ctxt->opcode_len) {
6341         case 1:
6342                 switch (ctxt->b) {
6343                 case 0xe4:      /* IN */
6344                 case 0xe5:
6345                 case 0xec:
6346                 case 0xed:
6347                 case 0xe6:      /* OUT */
6348                 case 0xe7:
6349                 case 0xee:
6350                 case 0xef:
6351                 case 0x6c:      /* INS */
6352                 case 0x6d:
6353                 case 0x6e:      /* OUTS */
6354                 case 0x6f:
6355                         return true;
6356                 }
6357                 break;
6358         case 2:
6359                 switch (ctxt->b) {
6360                 case 0x33:      /* RDPMC */
6361                         return true;
6362                 }
6363                 break;
6364         }
6365 
6366         return false;
6367 }
6368 
6369 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6370                             unsigned long cr2,
6371                             int emulation_type,
6372                             void *insn,
6373                             int insn_len)
6374 {
6375         int r;
6376         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6377         bool writeback = true;
6378         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6379 
6380         vcpu->arch.l1tf_flush_l1d = true;
6381 
6382         /*
6383          * Clear write_fault_to_shadow_pgtable here to ensure it is
6384          * never reused.
6385          */
6386         vcpu->arch.write_fault_to_shadow_pgtable = false;
6387         kvm_clear_exception_queue(vcpu);
6388 
6389         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6390                 init_emulate_ctxt(vcpu);
6391 
6392                 /*
6393                  * We will reenter on the same instruction since
6394                  * we do not set complete_userspace_io.  This does not
6395                  * handle watchpoints yet, those would be handled in
6396                  * the emulate_ops.
6397                  */
6398                 if (!(emulation_type & EMULTYPE_SKIP) &&
6399                     kvm_vcpu_check_breakpoint(vcpu, &r))
6400                         return r;
6401 
6402                 ctxt->interruptibility = 0;
6403                 ctxt->have_exception = false;
6404                 ctxt->exception.vector = -1;
6405                 ctxt->perm_ok = false;
6406 
6407                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6408 
6409                 r = x86_decode_insn(ctxt, insn, insn_len);
6410 
6411                 trace_kvm_emulate_insn_start(vcpu);
6412                 ++vcpu->stat.insn_emulation;
6413                 if (r != EMULATION_OK)  {
6414                         if (emulation_type & EMULTYPE_TRAP_UD)
6415                                 return EMULATE_FAIL;
6416                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6417                                                 emulation_type))
6418                                 return EMULATE_DONE;
6419                         if (ctxt->have_exception && inject_emulated_exception(vcpu))
6420                                 return EMULATE_DONE;
6421                         if (emulation_type & EMULTYPE_SKIP)
6422                                 return EMULATE_FAIL;
6423                         return handle_emulation_failure(vcpu, emulation_type);
6424                 }
6425         }
6426 
6427         if ((emulation_type & EMULTYPE_VMWARE) &&
6428             !is_vmware_backdoor_opcode(ctxt))
6429                 return EMULATE_FAIL;
6430 
6431         if (emulation_type & EMULTYPE_SKIP) {
6432                 kvm_rip_write(vcpu, ctxt->_eip);
6433                 if (ctxt->eflags & X86_EFLAGS_RF)
6434                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6435                 return EMULATE_DONE;
6436         }
6437 
6438         if (retry_instruction(ctxt, cr2, emulation_type))
6439                 return EMULATE_DONE;
6440 
6441         /* this is needed for vmware backdoor interface to work since it
6442            changes registers values  during IO operation */
6443         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6444                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6445                 emulator_invalidate_register_cache(ctxt);
6446         }
6447 
6448 restart:
6449         /* Save the faulting GPA (cr2) in the address field */
6450         ctxt->exception.address = cr2;
6451 
6452         r = x86_emulate_insn(ctxt);
6453 
6454         if (r == EMULATION_INTERCEPTED)
6455                 return EMULATE_DONE;
6456 
6457         if (r == EMULATION_FAILED) {
6458                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6459                                         emulation_type))
6460                         return EMULATE_DONE;
6461 
6462                 return handle_emulation_failure(vcpu, emulation_type);
6463         }
6464 
6465         if (ctxt->have_exception) {
6466                 r = EMULATE_DONE;
6467                 if (inject_emulated_exception(vcpu))
6468                         return r;
6469         } else if (vcpu->arch.pio.count) {
6470                 if (!vcpu->arch.pio.in) {
6471                         /* FIXME: return into emulator if single-stepping.  */
6472                         vcpu->arch.pio.count = 0;
6473                 } else {
6474                         writeback = false;
6475                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6476                 }
6477                 r = EMULATE_USER_EXIT;
6478         } else if (vcpu->mmio_needed) {
6479                 if (!vcpu->mmio_is_write)
6480                         writeback = false;
6481                 r = EMULATE_USER_EXIT;
6482                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6483         } else if (r == EMULATION_RESTART)
6484                 goto restart;
6485         else
6486                 r = EMULATE_DONE;
6487 
6488         if (writeback) {
6489                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6490                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6491                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6492                 kvm_rip_write(vcpu, ctxt->eip);
6493                 if (r == EMULATE_DONE && ctxt->tf)
6494                         kvm_vcpu_do_singlestep(vcpu, &r);
6495                 if (!ctxt->have_exception ||
6496                     exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6497                         __kvm_set_rflags(vcpu, ctxt->eflags);
6498 
6499                 /*
6500                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6501                  * do nothing, and it will be requested again as soon as
6502                  * the shadow expires.  But we still need to check here,
6503                  * because POPF has no interrupt shadow.
6504                  */
6505                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6506                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6507         } else
6508                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6509 
6510         return r;
6511 }
6512 
6513 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6514 {
6515         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6516 }
6517 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6518 
6519 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6520                                         void *insn, int insn_len)
6521 {
6522         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6523 }
6524 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6525 
6526 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6527                             unsigned short port)
6528 {
6529         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6530         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6531                                             size, port, &val, 1);
6532         /* do not return to emulator after return from userspace */
6533         vcpu->arch.pio.count = 0;
6534         return ret;
6535 }
6536 
6537 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6538 {
6539         unsigned long val;
6540 
6541         /* We should only ever be called with arch.pio.count equal to 1 */
6542         BUG_ON(vcpu->arch.pio.count != 1);
6543 
6544         /* For size less than 4 we merge, else we zero extend */
6545         val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6546                                         : 0;
6547 
6548         /*
6549          * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6550          * the copy and tracing
6551          */
6552         emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6553                                  vcpu->arch.pio.port, &val, 1);
6554         kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6555 
6556         return 1;
6557 }
6558 
6559 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6560                            unsigned short port)
6561 {
6562         unsigned long val;
6563         int ret;
6564 
6565         /* For size less than 4 we merge, else we zero extend */
6566         val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6567 
6568         ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6569                                        &val, 1);
6570         if (ret) {
6571                 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6572                 return ret;
6573         }
6574 
6575         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6576 
6577         return 0;
6578 }
6579 
6580 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6581 {
6582         int ret = kvm_skip_emulated_instruction(vcpu);
6583 
6584         /*
6585          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6586          * KVM_EXIT_DEBUG here.
6587          */
6588         if (in)
6589                 return kvm_fast_pio_in(vcpu, size, port) && ret;
6590         else
6591                 return kvm_fast_pio_out(vcpu, size, port) && ret;
6592 }
6593 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6594 
6595 static int kvmclock_cpu_down_prep(unsigned int cpu)
6596 {
6597         __this_cpu_write(cpu_tsc_khz, 0);
6598         return 0;
6599 }
6600 
6601 static void tsc_khz_changed(void *data)
6602 {
6603         struct cpufreq_freqs *freq = data;
6604         unsigned long khz = 0;
6605 
6606         if (data)
6607                 khz = freq->new;
6608         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6609                 khz = cpufreq_quick_get(raw_smp_processor_id());
6610         if (!khz)
6611                 khz = tsc_khz;
6612         __this_cpu_write(cpu_tsc_khz, khz);
6613 }
6614 
6615 #ifdef CONFIG_X86_64
6616 static void kvm_hyperv_tsc_notifier(void)
6617 {
6618         struct kvm *kvm;
6619         struct kvm_vcpu *vcpu;
6620         int cpu;
6621 
6622         spin_lock(&kvm_lock);
6623         list_for_each_entry(kvm, &vm_list, vm_list)
6624                 kvm_make_mclock_inprogress_request(kvm);
6625 
6626         hyperv_stop_tsc_emulation();
6627 
6628         /* TSC frequency always matches when on Hyper-V */
6629         for_each_present_cpu(cpu)
6630                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6631         kvm_max_guest_tsc_khz = tsc_khz;
6632 
6633         list_for_each_entry(kvm, &vm_list, vm_list) {
6634                 struct kvm_arch *ka = &kvm->arch;
6635 
6636                 spin_lock(&ka->pvclock_gtod_sync_lock);
6637 
6638                 pvclock_update_vm_gtod_copy(kvm);
6639 
6640                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6641                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6642 
6643                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6644                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6645 
6646                 spin_unlock(&ka->pvclock_gtod_sync_lock);
6647         }
6648         spin_unlock(&kvm_lock);
6649 }
6650 #endif
6651 
6652 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6653                                      void *data)
6654 {
6655         struct cpufreq_freqs *freq = data;
6656         struct kvm *kvm;
6657         struct kvm_vcpu *vcpu;
6658         int i, send_ipi = 0;
6659 
6660         /*
6661          * We allow guests to temporarily run on slowing clocks,
6662          * provided we notify them after, or to run on accelerating
6663          * clocks, provided we notify them before.  Thus time never
6664          * goes backwards.
6665          *
6666          * However, we have a problem.  We can't atomically update
6667          * the frequency of a given CPU from this function; it is
6668          * merely a notifier, which can be called from any CPU.
6669          * Changing the TSC frequency at arbitrary points in time
6670          * requires a recomputation of local variables related to
6671          * the TSC for each VCPU.  We must flag these local variables
6672          * to be updated and be sure the update takes place with the
6673          * new frequency before any guests proceed.
6674          *
6675          * Unfortunately, the combination of hotplug CPU and frequency
6676          * change creates an intractable locking scenario; the order
6677          * of when these callouts happen is undefined with respect to
6678          * CPU hotplug, and they can race with each other.  As such,
6679          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6680          * undefined; you can actually have a CPU frequency change take
6681          * place in between the computation of X and the setting of the
6682          * variable.  To protect against this problem, all updates of
6683          * the per_cpu tsc_khz variable are done in an interrupt
6684          * protected IPI, and all callers wishing to update the value
6685          * must wait for a synchronous IPI to complete (which is trivial
6686          * if the caller is on the CPU already).  This establishes the
6687          * necessary total order on variable updates.
6688          *
6689          * Note that because a guest time update may take place
6690          * anytime after the setting of the VCPU's request bit, the
6691          * correct TSC value must be set before the request.  However,
6692          * to ensure the update actually makes it to any guest which
6693          * starts running in hardware virtualization between the set
6694          * and the acquisition of the spinlock, we must also ping the
6695          * CPU after setting the request bit.
6696          *
6697          */
6698 
6699         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6700                 return 0;
6701         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6702                 return 0;
6703 
6704         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6705 
6706         spin_lock(&kvm_lock);
6707         list_for_each_entry(kvm, &vm_list, vm_list) {
6708                 kvm_for_each_vcpu(i, vcpu, kvm) {
6709                         if (vcpu->cpu != freq->cpu)
6710                                 continue;
6711                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6712                         if (vcpu->cpu != smp_processor_id())
6713                                 send_ipi = 1;
6714                 }
6715         }
6716         spin_unlock(&kvm_lock);
6717 
6718         if (freq->old < freq->new && send_ipi) {
6719                 /*
6720                  * We upscale the frequency.  Must make the guest
6721                  * doesn't see old kvmclock values while running with
6722                  * the new frequency, otherwise we risk the guest sees
6723                  * time go backwards.
6724                  *
6725                  * In case we update the frequency for another cpu
6726                  * (which might be in guest context) send an interrupt
6727                  * to kick the cpu out of guest context.  Next time
6728                  * guest context is entered kvmclock will be updated,
6729                  * so the guest will not see stale values.
6730                  */
6731                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6732         }
6733         return 0;
6734 }
6735 
6736 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6737         .notifier_call  = kvmclock_cpufreq_notifier
6738 };
6739 
6740 static int kvmclock_cpu_online(unsigned int cpu)
6741 {
6742         tsc_khz_changed(NULL);
6743         return 0;
6744 }
6745 
6746 static void kvm_timer_init(void)
6747 {
6748         max_tsc_khz = tsc_khz;
6749 
6750         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6751 #ifdef CONFIG_CPU_FREQ
6752                 struct cpufreq_policy policy;
6753                 int cpu;
6754 
6755                 memset(&policy, 0, sizeof(policy));
6756                 cpu = get_cpu();
6757                 cpufreq_get_policy(&policy, cpu);
6758                 if (policy.cpuinfo.max_freq)
6759                         max_tsc_khz = policy.cpuinfo.max_freq;
6760                 put_cpu();
6761 #endif
6762                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6763                                           CPUFREQ_TRANSITION_NOTIFIER);
6764         }
6765         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6766 
6767         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6768                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
6769 }
6770 
6771 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6772 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6773 
6774 int kvm_is_in_guest(void)
6775 {
6776         return __this_cpu_read(current_vcpu) != NULL;
6777 }
6778 
6779 static int kvm_is_user_mode(void)
6780 {
6781         int user_mode = 3;
6782 
6783         if (__this_cpu_read(current_vcpu))
6784                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6785 
6786         return user_mode != 0;
6787 }
6788 
6789 static unsigned long kvm_get_guest_ip(void)
6790 {
6791         unsigned long ip = 0;
6792 
6793         if (__this_cpu_read(current_vcpu))
6794                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6795 
6796         return ip;
6797 }
6798 
6799 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6800         .is_in_guest            = kvm_is_in_guest,
6801         .is_user_mode           = kvm_is_user_mode,
6802         .get_guest_ip           = kvm_get_guest_ip,
6803 };
6804 
6805 static void kvm_set_mmio_spte_mask(void)
6806 {
6807         u64 mask;
6808         int maxphyaddr = boot_cpu_data.x86_phys_bits;
6809 
6810         /*
6811          * Set the reserved bits and the present bit of an paging-structure
6812          * entry to generate page fault with PFER.RSV = 1.
6813          */
6814 
6815         /*
6816          * Mask the uppermost physical address bit, which would be reserved as
6817          * long as the supported physical address width is less than 52.
6818          */
6819         mask = 1ull << 51;
6820 
6821         /* Set the present bit. */
6822         mask |= 1ull;
6823 
6824         /*
6825          * If reserved bit is not supported, clear the present bit to disable
6826          * mmio page fault.
6827          */
6828         if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6829                 mask &= ~1ull;
6830 
6831         kvm_mmu_set_mmio_spte_mask(mask, mask);
6832 }
6833 
6834 #ifdef CONFIG_X86_64
6835 static void pvclock_gtod_update_fn(struct work_struct *work)
6836 {
6837         struct kvm *kvm;
6838 
6839         struct kvm_vcpu *vcpu;
6840         int i;
6841 
6842         spin_lock(&kvm_lock);
6843         list_for_each_entry(kvm, &vm_list, vm_list)
6844                 kvm_for_each_vcpu(i, vcpu, kvm)
6845                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6846         atomic_set(&kvm_guest_has_master_clock, 0);
6847         spin_unlock(&kvm_lock);
6848 }
6849 
6850 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6851 
6852 /*
6853  * Notification about pvclock gtod data update.
6854  */
6855 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6856                                void *priv)
6857 {
6858         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6859         struct timekeeper *tk = priv;
6860 
6861         update_pvclock_gtod(tk);
6862 
6863         /* disable master clock if host does not trust, or does not
6864          * use, TSC based clocksource.
6865          */
6866         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6867             atomic_read(&kvm_guest_has_master_clock) != 0)
6868                 queue_work(system_long_wq, &pvclock_gtod_work);
6869 
6870         return 0;
6871 }
6872 
6873 static struct notifier_block pvclock_gtod_notifier = {
6874         .notifier_call = pvclock_gtod_notify,
6875 };
6876 #endif
6877 
6878 int kvm_arch_init(void *opaque)
6879 {
6880         int r;
6881         struct kvm_x86_ops *ops = opaque;
6882 
6883         if (kvm_x86_ops) {
6884                 printk(KERN_ERR "kvm: already loaded the other module\n");
6885                 r = -EEXIST;
6886                 goto out;
6887         }
6888 
6889         if (!ops->cpu_has_kvm_support()) {
6890                 printk(KERN_ERR "kvm: no hardware support\n");
6891                 r = -EOPNOTSUPP;
6892                 goto out;
6893         }
6894         if (ops->disabled_by_bios()) {
6895                 printk(KERN_ERR "kvm: disabled by bios\n");
6896                 r = -EOPNOTSUPP;
6897                 goto out;
6898         }
6899 
6900         /*
6901          * KVM explicitly assumes that the guest has an FPU and
6902          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6903          * vCPU's FPU state as a fxregs_state struct.
6904          */
6905         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6906                 printk(KERN_ERR "kvm: inadequate fpu\n");
6907                 r = -EOPNOTSUPP;
6908                 goto out;
6909         }
6910 
6911         r = -ENOMEM;
6912         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
6913                                           __alignof__(struct fpu), SLAB_ACCOUNT,
6914                                           NULL);
6915         if (!x86_fpu_cache) {
6916                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6917                 goto out;
6918         }
6919 
6920         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6921         if (!shared_msrs) {
6922                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6923                 goto out_free_x86_fpu_cache;
6924         }
6925 
6926         r = kvm_mmu_module_init();
6927         if (r)
6928                 goto out_free_percpu;
6929 
6930         kvm_set_mmio_spte_mask();
6931 
6932         kvm_x86_ops = ops;
6933 
6934         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6935                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
6936                         PT_PRESENT_MASK, 0, sme_me_mask);
6937         kvm_timer_init();
6938 
6939         perf_register_guest_info_callbacks(&kvm_guest_cbs);
6940 
6941         if (boot_cpu_has(X86_FEATURE_XSAVE))
6942                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6943 
6944         kvm_lapic_init();
6945 #ifdef CONFIG_X86_64
6946         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6947 
6948         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6949                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
6950 #endif
6951 
6952         return 0;
6953 
6954 out_free_percpu:
6955         free_percpu(shared_msrs);
6956 out_free_x86_fpu_cache:
6957         kmem_cache_destroy(x86_fpu_cache);
6958 out:
6959         return r;
6960 }
6961 
6962 void kvm_arch_exit(void)
6963 {
6964 #ifdef CONFIG_X86_64
6965         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6966                 clear_hv_tscchange_cb();
6967 #endif
6968         kvm_lapic_exit();
6969         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6970 
6971         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6972                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6973                                             CPUFREQ_TRANSITION_NOTIFIER);
6974         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6975 #ifdef CONFIG_X86_64
6976         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6977 #endif
6978         kvm_x86_ops = NULL;
6979         kvm_mmu_module_exit();
6980         free_percpu(shared_msrs);
6981         kmem_cache_destroy(x86_fpu_cache);
6982 }
6983 
6984 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6985 {
6986         ++vcpu->stat.halt_exits;
6987         if (lapic_in_kernel(vcpu)) {
6988                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6989                 return 1;
6990         } else {
6991                 vcpu->run->exit_reason = KVM_EXIT_HLT;
6992                 return 0;
6993         }
6994 }
6995 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6996 
6997 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6998 {
6999         int ret = kvm_skip_emulated_instruction(vcpu);
7000         /*
7001          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7002          * KVM_EXIT_DEBUG here.
7003          */
7004         return kvm_vcpu_halt(vcpu) && ret;
7005 }
7006 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7007 
7008 #ifdef CONFIG_X86_64
7009 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7010                                 unsigned long clock_type)
7011 {
7012         struct kvm_clock_pairing clock_pairing;
7013         struct timespec64 ts;
7014         u64 cycle;
7015         int ret;
7016 
7017         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7018                 return -KVM_EOPNOTSUPP;
7019 
7020         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7021                 return -KVM_EOPNOTSUPP;
7022 
7023         clock_pairing.sec = ts.tv_sec;
7024         clock_pairing.nsec = ts.tv_nsec;
7025         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7026         clock_pairing.flags = 0;
7027         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7028 
7029         ret = 0;
7030         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7031                             sizeof(struct kvm_clock_pairing)))
7032                 ret = -KVM_EFAULT;
7033 
7034         return ret;
7035 }
7036 #endif
7037 
7038 /*
7039  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7040  *
7041  * @apicid - apicid of vcpu to be kicked.
7042  */
7043 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7044 {
7045         struct kvm_lapic_irq lapic_irq;
7046 
7047         lapic_irq.shorthand = 0;
7048         lapic_irq.dest_mode = 0;
7049         lapic_irq.level = 0;
7050         lapic_irq.dest_id = apicid;
7051         lapic_irq.msi_redir_hint = false;
7052 
7053         lapic_irq.delivery_mode = APIC_DM_REMRD;
7054         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7055 }
7056 
7057 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7058 {
7059         if (!lapic_in_kernel(vcpu)) {
7060                 WARN_ON_ONCE(vcpu->arch.apicv_active);
7061                 return;
7062         }
7063         if (!vcpu->arch.apicv_active)
7064                 return;
7065 
7066         vcpu->arch.apicv_active = false;
7067         kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7068 }
7069 
7070 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7071 {
7072         unsigned long nr, a0, a1, a2, a3, ret;
7073         int op_64_bit;
7074 
7075         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7076                 return kvm_hv_hypercall(vcpu);
7077 
7078         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7079         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7080         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7081         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7082         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
7083 
7084         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7085 
7086         op_64_bit = is_64_bit_mode(vcpu);
7087         if (!op_64_bit) {
7088                 nr &= 0xFFFFFFFF;
7089                 a0 &= 0xFFFFFFFF;
7090                 a1 &= 0xFFFFFFFF;
7091                 a2 &= 0xFFFFFFFF;
7092                 a3 &= 0xFFFFFFFF;
7093         }
7094 
7095         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7096                 ret = -KVM_EPERM;
7097                 goto out;
7098         }
7099 
7100         switch (nr) {
7101         case KVM_HC_VAPIC_POLL_IRQ:
7102                 ret = 0;
7103                 break;
7104         case KVM_HC_KICK_CPU:
7105                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7106                 ret = 0;
7107                 break;
7108 #ifdef CONFIG_X86_64
7109         case KVM_HC_CLOCK_PAIRING:
7110                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7111                 break;
7112 #endif
7113         case KVM_HC_SEND_IPI:
7114                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7115                 break;
7116         default:
7117                 ret = -KVM_ENOSYS;
7118                 break;
7119         }
7120 out:
7121         if (!op_64_bit)
7122                 ret = (u32)ret;
7123         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
7124 
7125         ++vcpu->stat.hypercalls;
7126         return kvm_skip_emulated_instruction(vcpu);
7127 }
7128 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7129 
7130 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7131 {
7132         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7133         char instruction[3];
7134         unsigned long rip = kvm_rip_read(vcpu);
7135 
7136         kvm_x86_ops->patch_hypercall(vcpu, instruction);
7137 
7138         return emulator_write_emulated(ctxt, rip, instruction, 3,
7139                 &ctxt->exception);
7140 }
7141 
7142 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7143 {
7144         return vcpu->run->request_interrupt_window &&
7145                 likely(!pic_in_kernel(vcpu->kvm));
7146 }
7147 
7148 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7149 {
7150         struct kvm_run *kvm_run = vcpu->run;
7151 
7152         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7153         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7154         kvm_run->cr8 = kvm_get_cr8(vcpu);
7155         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7156         kvm_run->ready_for_interrupt_injection =
7157                 pic_in_kernel(vcpu->kvm) ||
7158                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7159 }
7160 
7161 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7162 {
7163         int max_irr, tpr;
7164 
7165         if (!kvm_x86_ops->update_cr8_intercept)
7166                 return;
7167 
7168         if (!lapic_in_kernel(vcpu))
7169                 return;
7170 
7171         if (vcpu->arch.apicv_active)
7172                 return;
7173 
7174         if (!vcpu->arch.apic->vapic_addr)
7175                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7176         else
7177                 max_irr = -1;
7178 
7179         if (max_irr != -1)
7180                 max_irr >>= 4;
7181 
7182         tpr = kvm_lapic_get_cr8(vcpu);
7183 
7184         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7185 }
7186 
7187 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7188 {
7189         int r;
7190 
7191         /* try to reinject previous events if any */
7192 
7193         if (vcpu->arch.exception.injected)
7194                 kvm_x86_ops->queue_exception(vcpu);
7195         /*
7196          * Do not inject an NMI or interrupt if there is a pending
7197          * exception.  Exceptions and interrupts are recognized at
7198          * instruction boundaries, i.e. the start of an instruction.
7199          * Trap-like exceptions, e.g. #DB, have higher priority than
7200          * NMIs and interrupts, i.e. traps are recognized before an
7201          * NMI/interrupt that's pending on the same instruction.
7202          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7203          * priority, but are only generated (pended) during instruction
7204          * execution, i.e. a pending fault-like exception means the
7205          * fault occurred on the *previous* instruction and must be
7206          * serviced prior to recognizing any new events in order to
7207          * fully complete the previous instruction.
7208          */
7209         else if (!vcpu->arch.exception.pending) {
7210                 if (vcpu->arch.nmi_injected)
7211                         kvm_x86_ops->set_nmi(vcpu);
7212                 else if (vcpu->arch.interrupt.injected)
7213                         kvm_x86_ops->set_irq(vcpu);
7214         }
7215 
7216         /*
7217          * Call check_nested_events() even if we reinjected a previous event
7218          * in order for caller to determine if it should require immediate-exit
7219          * from L2 to L1 due to pending L1 events which require exit
7220          * from L2 to L1.
7221          */
7222         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7223                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7224                 if (r != 0)
7225                         return r;
7226         }
7227 
7228         /* try to inject new event if pending */
7229         if (vcpu->arch.exception.pending) {
7230                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7231                                         vcpu->arch.exception.has_error_code,
7232                                         vcpu->arch.exception.error_code);
7233 
7234                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7235                 vcpu->arch.exception.pending = false;
7236                 vcpu->arch.exception.injected = true;
7237 
7238                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7239                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7240                                              X86_EFLAGS_RF);
7241 
7242                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7243                         /*
7244                          * This code assumes that nSVM doesn't use
7245                          * check_nested_events(). If it does, the
7246                          * DR6/DR7 changes should happen before L1
7247                          * gets a #VMEXIT for an intercepted #DB in
7248                          * L2.  (Under VMX, on the other hand, the
7249                          * DR6/DR7 changes should not happen in the
7250                          * event of a VM-exit to L1 for an intercepted
7251                          * #DB in L2.)
7252                          */
7253                         kvm_deliver_exception_payload(vcpu);
7254                         if (vcpu->arch.dr7 & DR7_GD) {
7255                                 vcpu->arch.dr7 &= ~DR7_GD;
7256                                 kvm_update_dr7(vcpu);
7257                         }
7258                 }
7259 
7260                 kvm_x86_ops->queue_exception(vcpu);
7261         }
7262 
7263         /* Don't consider new event if we re-injected an event */
7264         if (kvm_event_needs_reinjection(vcpu))
7265                 return 0;
7266 
7267         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7268             kvm_x86_ops->smi_allowed(vcpu)) {
7269                 vcpu->arch.smi_pending = false;
7270                 ++vcpu->arch.smi_count;
7271                 enter_smm(vcpu);
7272         } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7273                 --vcpu->arch.nmi_pending;
7274                 vcpu->arch.nmi_injected = true;
7275                 kvm_x86_ops->set_nmi(vcpu);
7276         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7277                 /*
7278                  * Because interrupts can be injected asynchronously, we are
7279                  * calling check_nested_events again here to avoid a race condition.
7280                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7281                  * proposal and current concerns.  Perhaps we should be setting
7282                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7283                  */
7284                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7285                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7286                         if (r != 0)
7287                                 return r;
7288                 }
7289                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7290                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7291                                             false);
7292                         kvm_x86_ops->set_irq(vcpu);
7293                 }
7294         }
7295 
7296         return 0;
7297 }
7298 
7299 static void process_nmi(struct kvm_vcpu *vcpu)
7300 {
7301         unsigned limit = 2;
7302 
7303         /*
7304          * x86 is limited to one NMI running, and one NMI pending after it.
7305          * If an NMI is already in progress, limit further NMIs to just one.
7306          * Otherwise, allow two (and we'll inject the first one immediately).
7307          */
7308         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7309                 limit = 1;
7310 
7311         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7312         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7313         kvm_make_request(KVM_REQ_EVENT, vcpu);
7314 }
7315 
7316 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7317 {
7318         u32 flags = 0;
7319         flags |= seg->g       << 23;
7320         flags |= seg->db      << 22;
7321         flags |= seg->l       << 21;
7322         flags |= seg->avl     << 20;
7323         flags |= seg->present << 15;
7324         flags |= seg->dpl     << 13;
7325         flags |= seg->s       << 12;
7326         flags |= seg->type    << 8;
7327         return flags;
7328 }
7329 
7330 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7331 {
7332         struct kvm_segment seg;
7333         int offset;
7334 
7335         kvm_get_segment(vcpu, &seg, n);
7336         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7337 
7338         if (n < 3)
7339                 offset = 0x7f84 + n * 12;
7340         else
7341                 offset = 0x7f2c + (n - 3) * 12;
7342 
7343         put_smstate(u32, buf, offset + 8, seg.base);
7344         put_smstate(u32, buf, offset + 4, seg.limit);
7345         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7346 }
7347 
7348 #ifdef CONFIG_X86_64
7349 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7350 {
7351         struct kvm_segment seg;
7352         int offset;
7353         u16 flags;
7354 
7355         kvm_get_segment(vcpu, &seg, n);
7356         offset = 0x7e00 + n * 16;
7357 
7358         flags = enter_smm_get_segment_flags(&seg) >> 8;
7359         put_smstate(u16, buf, offset, seg.selector);
7360         put_smstate(u16, buf, offset + 2, flags);
7361         put_smstate(u32, buf, offset + 4, seg.limit);
7362         put_smstate(u64, buf, offset + 8, seg.base);
7363 }
7364 #endif
7365 
7366 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7367 {
7368         struct desc_ptr dt;
7369         struct kvm_segment seg;
7370         unsigned long val;
7371         int i;
7372 
7373         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7374         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7375         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7376         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7377 
7378         for (i = 0; i < 8; i++)
7379                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7380 
7381         kvm_get_dr(vcpu, 6, &val);
7382         put_smstate(u32, buf, 0x7fcc, (u32)val);
7383         kvm_get_dr(vcpu, 7, &val);
7384         put_smstate(u32, buf, 0x7fc8, (u32)val);
7385 
7386         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7387         put_smstate(u32, buf, 0x7fc4, seg.selector);
7388         put_smstate(u32, buf, 0x7f64, seg.base);
7389         put_smstate(u32, buf, 0x7f60, seg.limit);
7390         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7391 
7392         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7393         put_smstate(u32, buf, 0x7fc0, seg.selector);
7394         put_smstate(u32, buf, 0x7f80, seg.base);
7395         put_smstate(u32, buf, 0x7f7c, seg.limit);
7396         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7397 
7398         kvm_x86_ops->get_gdt(vcpu, &dt);
7399         put_smstate(u32, buf, 0x7f74, dt.address);
7400         put_smstate(u32, buf, 0x7f70, dt.size);
7401 
7402         kvm_x86_ops->get_idt(vcpu, &dt);
7403         put_smstate(u32, buf, 0x7f58, dt.address);
7404         put_smstate(u32, buf, 0x7f54, dt.size);
7405 
7406         for (i = 0; i < 6; i++)
7407                 enter_smm_save_seg_32(vcpu, buf, i);
7408 
7409         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7410 
7411         /* revision id */
7412         put_smstate(u32, buf, 0x7efc, 0x00020000);
7413         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7414 }
7415 
7416 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7417 {
7418 #ifdef CONFIG_X86_64
7419         struct desc_ptr dt;
7420         struct kvm_segment seg;
7421         unsigned long val;
7422         int i;
7423 
7424         for (i = 0; i < 16; i++)
7425                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7426 
7427         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7428         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7429 
7430         kvm_get_dr(vcpu, 6, &val);
7431         put_smstate(u64, buf, 0x7f68, val);
7432         kvm_get_dr(vcpu, 7, &val);
7433         put_smstate(u64, buf, 0x7f60, val);
7434 
7435         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7436         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7437         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7438 
7439         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7440 
7441         /* revision id */
7442         put_smstate(u32, buf, 0x7efc, 0x00020064);
7443 
7444         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7445 
7446         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7447         put_smstate(u16, buf, 0x7e90, seg.selector);
7448         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7449         put_smstate(u32, buf, 0x7e94, seg.limit);
7450         put_smstate(u64, buf, 0x7e98, seg.base);
7451 
7452         kvm_x86_ops->get_idt(vcpu, &dt);
7453         put_smstate(u32, buf, 0x7e84, dt.size);
7454         put_smstate(u64, buf, 0x7e88, dt.address);
7455 
7456         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7457         put_smstate(u16, buf, 0x7e70, seg.selector);
7458         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7459         put_smstate(u32, buf, 0x7e74, seg.limit);
7460         put_smstate(u64, buf, 0x7e78, seg.base);
7461 
7462         kvm_x86_ops->get_gdt(vcpu, &dt);
7463         put_smstate(u32, buf, 0x7e64, dt.size);
7464         put_smstate(u64, buf, 0x7e68, dt.address);
7465 
7466         for (i = 0; i < 6; i++)
7467                 enter_smm_save_seg_64(vcpu, buf, i);
7468 #else
7469         WARN_ON_ONCE(1);
7470 #endif
7471 }
7472 
7473 static void enter_smm(struct kvm_vcpu *vcpu)
7474 {
7475         struct kvm_segment cs, ds;
7476         struct desc_ptr dt;
7477         char buf[512];
7478         u32 cr0;
7479 
7480         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7481         memset(buf, 0, 512);
7482         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7483                 enter_smm_save_state_64(vcpu, buf);
7484         else
7485                 enter_smm_save_state_32(vcpu, buf);
7486 
7487         /*
7488          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7489          * vCPU state (e.g. leave guest mode) after we've saved the state into
7490          * the SMM state-save area.
7491          */
7492         kvm_x86_ops->pre_enter_smm(vcpu, buf);
7493 
7494         vcpu->arch.hflags |= HF_SMM_MASK;
7495         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7496 
7497         if (kvm_x86_ops->get_nmi_mask(vcpu))
7498                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7499         else
7500                 kvm_x86_ops->set_nmi_mask(vcpu, true);
7501 
7502         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7503         kvm_rip_write(vcpu, 0x8000);
7504 
7505         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7506         kvm_x86_ops->set_cr0(vcpu, cr0);
7507         vcpu->arch.cr0 = cr0;
7508 
7509         kvm_x86_ops->set_cr4(vcpu, 0);
7510 
7511         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7512         dt.address = dt.size = 0;
7513         kvm_x86_ops->set_idt(vcpu, &dt);
7514 
7515         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7516 
7517         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7518         cs.base = vcpu->arch.smbase;
7519 
7520         ds.selector = 0;
7521         ds.base = 0;
7522 
7523         cs.limit    = ds.limit = 0xffffffff;
7524         cs.type     = ds.type = 0x3;
7525         cs.dpl      = ds.dpl = 0;
7526         cs.db       = ds.db = 0;
7527         cs.s        = ds.