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Linux/arch/x86/kvm/x86.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * derived from drivers/kvm/kvm_main.c
  5  *
  6  * Copyright (C) 2006 Qumranet, Inc.
  7  * Copyright (C) 2008 Qumranet, Inc.
  8  * Copyright IBM Corporation, 2008
  9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 10  *
 11  * Authors:
 12  *   Avi Kivity   <avi@qumranet.com>
 13  *   Yaniv Kamay  <yaniv@qumranet.com>
 14  *   Amit Shah    <amit.shah@qumranet.com>
 15  *   Ben-Ami Yassour <benami@il.ibm.com>
 16  *
 17  * This work is licensed under the terms of the GNU GPL, version 2.  See
 18  * the COPYING file in the top-level directory.
 19  *
 20  */
 21 
 22 #include <linux/kvm_host.h>
 23 #include "irq.h"
 24 #include "mmu.h"
 25 #include "i8254.h"
 26 #include "tss.h"
 27 #include "kvm_cache_regs.h"
 28 #include "x86.h"
 29 #include "cpuid.h"
 30 
 31 #include <linux/clocksource.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/kvm.h>
 34 #include <linux/fs.h>
 35 #include <linux/vmalloc.h>
 36 #include <linux/module.h>
 37 #include <linux/mman.h>
 38 #include <linux/highmem.h>
 39 #include <linux/iommu.h>
 40 #include <linux/intel-iommu.h>
 41 #include <linux/cpufreq.h>
 42 #include <linux/user-return-notifier.h>
 43 #include <linux/srcu.h>
 44 #include <linux/slab.h>
 45 #include <linux/perf_event.h>
 46 #include <linux/uaccess.h>
 47 #include <linux/hash.h>
 48 #include <linux/pci.h>
 49 #include <linux/timekeeper_internal.h>
 50 #include <linux/pvclock_gtod.h>
 51 #include <trace/events/kvm.h>
 52 
 53 #define CREATE_TRACE_POINTS
 54 #include "trace.h"
 55 
 56 #include <asm/debugreg.h>
 57 #include <asm/msr.h>
 58 #include <asm/desc.h>
 59 #include <asm/mtrr.h>
 60 #include <asm/mce.h>
 61 #include <asm/i387.h>
 62 #include <asm/fpu-internal.h> /* Ugh! */
 63 #include <asm/xcr.h>
 64 #include <asm/pvclock.h>
 65 #include <asm/div64.h>
 66 
 67 #define MAX_IO_MSRS 256
 68 #define KVM_MAX_MCE_BANKS 32
 69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
 70 
 71 #define emul_to_vcpu(ctxt) \
 72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
 73 
 74 /* EFER defaults:
 75  * - enable syscall per default because its emulated by KVM
 76  * - enable LME and LMA per default on 64 bit KVM
 77  */
 78 #ifdef CONFIG_X86_64
 79 static
 80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
 81 #else
 82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
 83 #endif
 84 
 85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
 86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
 87 
 88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 89 static void process_nmi(struct kvm_vcpu *vcpu);
 90 
 91 struct kvm_x86_ops *kvm_x86_ops;
 92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 93 
 94 static bool ignore_msrs = 0;
 95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 96 
 97 unsigned int min_timer_period_us = 500;
 98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 99 
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32  kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104 
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108 
109 #define KVM_NR_SHARED_MSRS 16
110 
111 struct kvm_shared_msrs_global {
112         int nr;
113         u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115 
116 struct kvm_shared_msrs {
117         struct user_return_notifier urn;
118         bool registered;
119         struct kvm_shared_msr_values {
120                 u64 host;
121                 u64 curr;
122         } values[KVM_NR_SHARED_MSRS];
123 };
124 
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127 
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129         { "pf_fixed", VCPU_STAT(pf_fixed) },
130         { "pf_guest", VCPU_STAT(pf_guest) },
131         { "tlb_flush", VCPU_STAT(tlb_flush) },
132         { "invlpg", VCPU_STAT(invlpg) },
133         { "exits", VCPU_STAT(exits) },
134         { "io_exits", VCPU_STAT(io_exits) },
135         { "mmio_exits", VCPU_STAT(mmio_exits) },
136         { "signal_exits", VCPU_STAT(signal_exits) },
137         { "irq_window", VCPU_STAT(irq_window_exits) },
138         { "nmi_window", VCPU_STAT(nmi_window_exits) },
139         { "halt_exits", VCPU_STAT(halt_exits) },
140         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141         { "hypercalls", VCPU_STAT(hypercalls) },
142         { "request_irq", VCPU_STAT(request_irq_exits) },
143         { "irq_exits", VCPU_STAT(irq_exits) },
144         { "host_state_reload", VCPU_STAT(host_state_reload) },
145         { "efer_reload", VCPU_STAT(efer_reload) },
146         { "fpu_reload", VCPU_STAT(fpu_reload) },
147         { "insn_emulation", VCPU_STAT(insn_emulation) },
148         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149         { "irq_injections", VCPU_STAT(irq_injections) },
150         { "nmi_injections", VCPU_STAT(nmi_injections) },
151         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155         { "mmu_flooded", VM_STAT(mmu_flooded) },
156         { "mmu_recycled", VM_STAT(mmu_recycled) },
157         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158         { "mmu_unsync", VM_STAT(mmu_unsync) },
159         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160         { "largepages", VM_STAT(lpages) },
161         { NULL }
162 };
163 
164 u64 __read_mostly host_xcr0;
165 
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167 
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170         int i;
171         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172                 vcpu->arch.apf.gfns[i] = ~0;
173 }
174 
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177         unsigned slot;
178         struct kvm_shared_msrs *locals
179                 = container_of(urn, struct kvm_shared_msrs, urn);
180         struct kvm_shared_msr_values *values;
181 
182         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183                 values = &locals->values[slot];
184                 if (values->host != values->curr) {
185                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
186                         values->curr = values->host;
187                 }
188         }
189         locals->registered = false;
190         user_return_notifier_unregister(urn);
191 }
192 
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195         u64 value;
196         unsigned int cpu = smp_processor_id();
197         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198 
199         /* only read, and nobody should modify it at this time,
200          * so don't need lock */
201         if (slot >= shared_msrs_global.nr) {
202                 printk(KERN_ERR "kvm: invalid MSR slot!");
203                 return;
204         }
205         rdmsrl_safe(msr, &value);
206         smsr->values[slot].host = value;
207         smsr->values[slot].curr = value;
208 }
209 
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212         if (slot >= shared_msrs_global.nr)
213                 shared_msrs_global.nr = slot + 1;
214         shared_msrs_global.msrs[slot] = msr;
215         /* we need ensured the shared_msr_global have been updated */
216         smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219 
220 static void kvm_shared_msr_cpu_online(void)
221 {
222         unsigned i;
223 
224         for (i = 0; i < shared_msrs_global.nr; ++i)
225                 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227 
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230         unsigned int cpu = smp_processor_id();
231         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232 
233         if (((value ^ smsr->values[slot].curr) & mask) == 0)
234                 return;
235         smsr->values[slot].curr = value;
236         wrmsrl(shared_msrs_global.msrs[slot], value);
237         if (!smsr->registered) {
238                 smsr->urn.on_user_return = kvm_on_user_return;
239                 user_return_notifier_register(&smsr->urn);
240                 smsr->registered = true;
241         }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244 
245 static void drop_user_return_notifiers(void *ignore)
246 {
247         unsigned int cpu = smp_processor_id();
248         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249 
250         if (smsr->registered)
251                 kvm_on_user_return(&smsr->urn);
252 }
253 
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256         return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259 
260 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261 {
262         /* TODO: reserve bits check */
263         kvm_lapic_set_base(vcpu, data);
264 }
265 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266 
267 asmlinkage void kvm_spurious_fault(void)
268 {
269         /* Fault while not rebooting.  We want the trace. */
270         BUG();
271 }
272 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273 
274 #define EXCPT_BENIGN            0
275 #define EXCPT_CONTRIBUTORY      1
276 #define EXCPT_PF                2
277 
278 static int exception_class(int vector)
279 {
280         switch (vector) {
281         case PF_VECTOR:
282                 return EXCPT_PF;
283         case DE_VECTOR:
284         case TS_VECTOR:
285         case NP_VECTOR:
286         case SS_VECTOR:
287         case GP_VECTOR:
288                 return EXCPT_CONTRIBUTORY;
289         default:
290                 break;
291         }
292         return EXCPT_BENIGN;
293 }
294 
295 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
296                 unsigned nr, bool has_error, u32 error_code,
297                 bool reinject)
298 {
299         u32 prev_nr;
300         int class1, class2;
301 
302         kvm_make_request(KVM_REQ_EVENT, vcpu);
303 
304         if (!vcpu->arch.exception.pending) {
305         queue:
306                 vcpu->arch.exception.pending = true;
307                 vcpu->arch.exception.has_error_code = has_error;
308                 vcpu->arch.exception.nr = nr;
309                 vcpu->arch.exception.error_code = error_code;
310                 vcpu->arch.exception.reinject = reinject;
311                 return;
312         }
313 
314         /* to check exception */
315         prev_nr = vcpu->arch.exception.nr;
316         if (prev_nr == DF_VECTOR) {
317                 /* triple fault -> shutdown */
318                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
319                 return;
320         }
321         class1 = exception_class(prev_nr);
322         class2 = exception_class(nr);
323         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325                 /* generate double fault per SDM Table 5-5 */
326                 vcpu->arch.exception.pending = true;
327                 vcpu->arch.exception.has_error_code = true;
328                 vcpu->arch.exception.nr = DF_VECTOR;
329                 vcpu->arch.exception.error_code = 0;
330         } else
331                 /* replace previous exception with a new one in a hope
332                    that instruction re-execution will regenerate lost
333                    exception */
334                 goto queue;
335 }
336 
337 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338 {
339         kvm_multiple_exception(vcpu, nr, false, 0, false);
340 }
341 EXPORT_SYMBOL_GPL(kvm_queue_exception);
342 
343 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344 {
345         kvm_multiple_exception(vcpu, nr, false, 0, true);
346 }
347 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348 
349 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
350 {
351         if (err)
352                 kvm_inject_gp(vcpu, 0);
353         else
354                 kvm_x86_ops->skip_emulated_instruction(vcpu);
355 }
356 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
357 
358 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360         ++vcpu->stat.pf_guest;
361         vcpu->arch.cr2 = fault->address;
362         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
363 }
364 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
365 
366 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
367 {
368         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
370         else
371                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
372 }
373 
374 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375 {
376         atomic_inc(&vcpu->arch.nmi_queued);
377         kvm_make_request(KVM_REQ_NMI, vcpu);
378 }
379 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380 
381 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382 {
383         kvm_multiple_exception(vcpu, nr, true, error_code, false);
384 }
385 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386 
387 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388 {
389         kvm_multiple_exception(vcpu, nr, true, error_code, true);
390 }
391 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392 
393 /*
394  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
395  * a #GP and return false.
396  */
397 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
398 {
399         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400                 return true;
401         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402         return false;
403 }
404 EXPORT_SYMBOL_GPL(kvm_require_cpl);
405 
406 /*
407  * This function will be used to read from the physical memory of the currently
408  * running guest. The difference to kvm_read_guest_page is that this function
409  * can read from guest physical or from the guest's guest physical memory.
410  */
411 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412                             gfn_t ngfn, void *data, int offset, int len,
413                             u32 access)
414 {
415         gfn_t real_gfn;
416         gpa_t ngpa;
417 
418         ngpa     = gfn_to_gpa(ngfn);
419         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420         if (real_gfn == UNMAPPED_GVA)
421                 return -EFAULT;
422 
423         real_gfn = gpa_to_gfn(real_gfn);
424 
425         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426 }
427 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428 
429 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430                                void *data, int offset, int len, u32 access)
431 {
432         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433                                        data, offset, len, access);
434 }
435 
436 /*
437  * Load the pae pdptrs.  Return true is they are all valid.
438  */
439 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
440 {
441         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443         int i;
444         int ret;
445         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
446 
447         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448                                       offset * sizeof(u64), sizeof(pdpte),
449                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
450         if (ret < 0) {
451                 ret = 0;
452                 goto out;
453         }
454         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
455                 if (is_present_gpte(pdpte[i]) &&
456                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
457                         ret = 0;
458                         goto out;
459                 }
460         }
461         ret = 1;
462 
463         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
464         __set_bit(VCPU_EXREG_PDPTR,
465                   (unsigned long *)&vcpu->arch.regs_avail);
466         __set_bit(VCPU_EXREG_PDPTR,
467                   (unsigned long *)&vcpu->arch.regs_dirty);
468 out:
469 
470         return ret;
471 }
472 EXPORT_SYMBOL_GPL(load_pdptrs);
473 
474 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475 {
476         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
477         bool changed = true;
478         int offset;
479         gfn_t gfn;
480         int r;
481 
482         if (is_long_mode(vcpu) || !is_pae(vcpu))
483                 return false;
484 
485         if (!test_bit(VCPU_EXREG_PDPTR,
486                       (unsigned long *)&vcpu->arch.regs_avail))
487                 return true;
488 
489         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
491         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
493         if (r < 0)
494                 goto out;
495         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
496 out:
497 
498         return changed;
499 }
500 
501 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
502 {
503         unsigned long old_cr0 = kvm_read_cr0(vcpu);
504         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505                                     X86_CR0_CD | X86_CR0_NW;
506 
507         cr0 |= X86_CR0_ET;
508 
509 #ifdef CONFIG_X86_64
510         if (cr0 & 0xffffffff00000000UL)
511                 return 1;
512 #endif
513 
514         cr0 &= ~CR0_RESERVED_BITS;
515 
516         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517                 return 1;
518 
519         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520                 return 1;
521 
522         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523 #ifdef CONFIG_X86_64
524                 if ((vcpu->arch.efer & EFER_LME)) {
525                         int cs_db, cs_l;
526 
527                         if (!is_pae(vcpu))
528                                 return 1;
529                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
530                         if (cs_l)
531                                 return 1;
532                 } else
533 #endif
534                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
535                                                  kvm_read_cr3(vcpu)))
536                         return 1;
537         }
538 
539         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540                 return 1;
541 
542         kvm_x86_ops->set_cr0(vcpu, cr0);
543 
544         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
545                 kvm_clear_async_pf_completion_queue(vcpu);
546                 kvm_async_pf_hash_reset(vcpu);
547         }
548 
549         if ((cr0 ^ old_cr0) & update_bits)
550                 kvm_mmu_reset_context(vcpu);
551         return 0;
552 }
553 EXPORT_SYMBOL_GPL(kvm_set_cr0);
554 
555 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
556 {
557         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
558 }
559 EXPORT_SYMBOL_GPL(kvm_lmsw);
560 
561 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562 {
563         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564                         !vcpu->guest_xcr0_loaded) {
565                 /* kvm_set_xcr() also depends on this */
566                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567                 vcpu->guest_xcr0_loaded = 1;
568         }
569 }
570 
571 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572 {
573         if (vcpu->guest_xcr0_loaded) {
574                 if (vcpu->arch.xcr0 != host_xcr0)
575                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576                 vcpu->guest_xcr0_loaded = 0;
577         }
578 }
579 
580 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581 {
582         u64 xcr0;
583         u64 valid_bits;
584 
585         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
586         if (index != XCR_XFEATURE_ENABLED_MASK)
587                 return 1;
588         xcr0 = xcr;
589         if (!(xcr0 & XSTATE_FP))
590                 return 1;
591         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592                 return 1;
593 
594         /*
595          * Do not allow the guest to set bits that we do not support
596          * saving.  However, xcr0 bit 0 is always set, even if the
597          * emulated CPU does not support XSAVE (see fx_init).
598          */
599         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600         if (xcr0 & ~valid_bits)
601                 return 1;
602 
603         kvm_put_guest_xcr0(vcpu);
604         vcpu->arch.xcr0 = xcr0;
605         return 0;
606 }
607 
608 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609 {
610         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611             __kvm_set_xcr(vcpu, index, xcr)) {
612                 kvm_inject_gp(vcpu, 0);
613                 return 1;
614         }
615         return 0;
616 }
617 EXPORT_SYMBOL_GPL(kvm_set_xcr);
618 
619 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
620 {
621         unsigned long old_cr4 = kvm_read_cr4(vcpu);
622         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623                                    X86_CR4_PAE | X86_CR4_SMEP;
624         if (cr4 & CR4_RESERVED_BITS)
625                 return 1;
626 
627         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628                 return 1;
629 
630         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631                 return 1;
632 
633         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
634                 return 1;
635 
636         if (is_long_mode(vcpu)) {
637                 if (!(cr4 & X86_CR4_PAE))
638                         return 1;
639         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640                    && ((cr4 ^ old_cr4) & pdptr_bits)
641                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642                                    kvm_read_cr3(vcpu)))
643                 return 1;
644 
645         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646                 if (!guest_cpuid_has_pcid(vcpu))
647                         return 1;
648 
649                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651                         return 1;
652         }
653 
654         if (kvm_x86_ops->set_cr4(vcpu, cr4))
655                 return 1;
656 
657         if (((cr4 ^ old_cr4) & pdptr_bits) ||
658             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
659                 kvm_mmu_reset_context(vcpu);
660 
661         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
662                 kvm_update_cpuid(vcpu);
663 
664         return 0;
665 }
666 EXPORT_SYMBOL_GPL(kvm_set_cr4);
667 
668 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
669 {
670         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
671                 kvm_mmu_sync_roots(vcpu);
672                 kvm_mmu_flush_tlb(vcpu);
673                 return 0;
674         }
675 
676         if (is_long_mode(vcpu)) {
677                 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
678                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679                                 return 1;
680                 } else
681                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
682                                 return 1;
683         } else {
684                 if (is_pae(vcpu)) {
685                         if (cr3 & CR3_PAE_RESERVED_BITS)
686                                 return 1;
687                         if (is_paging(vcpu) &&
688                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
689                                 return 1;
690                 }
691                 /*
692                  * We don't check reserved bits in nonpae mode, because
693                  * this isn't enforced, and VMware depends on this.
694                  */
695         }
696 
697         vcpu->arch.cr3 = cr3;
698         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
699         kvm_mmu_new_cr3(vcpu);
700         return 0;
701 }
702 EXPORT_SYMBOL_GPL(kvm_set_cr3);
703 
704 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
705 {
706         if (cr8 & CR8_RESERVED_BITS)
707                 return 1;
708         if (irqchip_in_kernel(vcpu->kvm))
709                 kvm_lapic_set_tpr(vcpu, cr8);
710         else
711                 vcpu->arch.cr8 = cr8;
712         return 0;
713 }
714 EXPORT_SYMBOL_GPL(kvm_set_cr8);
715 
716 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
717 {
718         if (irqchip_in_kernel(vcpu->kvm))
719                 return kvm_lapic_get_cr8(vcpu);
720         else
721                 return vcpu->arch.cr8;
722 }
723 EXPORT_SYMBOL_GPL(kvm_get_cr8);
724 
725 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726 {
727         unsigned long dr7;
728 
729         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730                 dr7 = vcpu->arch.guest_debug_dr7;
731         else
732                 dr7 = vcpu->arch.dr7;
733         kvm_x86_ops->set_dr7(vcpu, dr7);
734         vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735 }
736 
737 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
738 {
739         switch (dr) {
740         case 0 ... 3:
741                 vcpu->arch.db[dr] = val;
742                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743                         vcpu->arch.eff_db[dr] = val;
744                 break;
745         case 4:
746                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747                         return 1; /* #UD */
748                 /* fall through */
749         case 6:
750                 if (val & 0xffffffff00000000ULL)
751                         return -1; /* #GP */
752                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753                 break;
754         case 5:
755                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756                         return 1; /* #UD */
757                 /* fall through */
758         default: /* 7 */
759                 if (val & 0xffffffff00000000ULL)
760                         return -1; /* #GP */
761                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
762                 kvm_update_dr7(vcpu);
763                 break;
764         }
765 
766         return 0;
767 }
768 
769 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770 {
771         int res;
772 
773         res = __kvm_set_dr(vcpu, dr, val);
774         if (res > 0)
775                 kvm_queue_exception(vcpu, UD_VECTOR);
776         else if (res < 0)
777                 kvm_inject_gp(vcpu, 0);
778 
779         return res;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_dr);
782 
783 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
784 {
785         switch (dr) {
786         case 0 ... 3:
787                 *val = vcpu->arch.db[dr];
788                 break;
789         case 4:
790                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
791                         return 1;
792                 /* fall through */
793         case 6:
794                 *val = vcpu->arch.dr6;
795                 break;
796         case 5:
797                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
798                         return 1;
799                 /* fall through */
800         default: /* 7 */
801                 *val = vcpu->arch.dr7;
802                 break;
803         }
804 
805         return 0;
806 }
807 
808 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 {
810         if (_kvm_get_dr(vcpu, dr, val)) {
811                 kvm_queue_exception(vcpu, UD_VECTOR);
812                 return 1;
813         }
814         return 0;
815 }
816 EXPORT_SYMBOL_GPL(kvm_get_dr);
817 
818 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819 {
820         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821         u64 data;
822         int err;
823 
824         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825         if (err)
826                 return err;
827         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829         return err;
830 }
831 EXPORT_SYMBOL_GPL(kvm_rdpmc);
832 
833 /*
834  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836  *
837  * This list is modified at module load time to reflect the
838  * capabilities of the host cpu. This capabilities test skips MSRs that are
839  * kvm-specific. Those are put in the beginning of the list.
840  */
841 
842 #define KVM_SAVE_MSRS_BEGIN     10
843 static u32 msrs_to_save[] = {
844         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
845         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
846         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
847         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
848         MSR_KVM_PV_EOI_EN,
849         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
850         MSR_STAR,
851 #ifdef CONFIG_X86_64
852         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
853 #endif
854         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
855         MSR_IA32_FEATURE_CONTROL
856 };
857 
858 static unsigned num_msrs_to_save;
859 
860 static const u32 emulated_msrs[] = {
861         MSR_IA32_TSC_ADJUST,
862         MSR_IA32_TSCDEADLINE,
863         MSR_IA32_MISC_ENABLE,
864         MSR_IA32_MCG_STATUS,
865         MSR_IA32_MCG_CTL,
866 };
867 
868 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
869 {
870         if (efer & efer_reserved_bits)
871                 return false;
872 
873         if (efer & EFER_FFXSR) {
874                 struct kvm_cpuid_entry2 *feat;
875 
876                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
877                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
878                         return false;
879         }
880 
881         if (efer & EFER_SVME) {
882                 struct kvm_cpuid_entry2 *feat;
883 
884                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
885                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
886                         return false;
887         }
888 
889         return true;
890 }
891 EXPORT_SYMBOL_GPL(kvm_valid_efer);
892 
893 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
894 {
895         u64 old_efer = vcpu->arch.efer;
896 
897         if (!kvm_valid_efer(vcpu, efer))
898                 return 1;
899 
900         if (is_paging(vcpu)
901             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
902                 return 1;
903 
904         efer &= ~EFER_LMA;
905         efer |= vcpu->arch.efer & EFER_LMA;
906 
907         kvm_x86_ops->set_efer(vcpu, efer);
908 
909         /* Update reserved bits */
910         if ((efer ^ old_efer) & EFER_NX)
911                 kvm_mmu_reset_context(vcpu);
912 
913         return 0;
914 }
915 
916 void kvm_enable_efer_bits(u64 mask)
917 {
918        efer_reserved_bits &= ~mask;
919 }
920 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
921 
922 
923 /*
924  * Writes msr value into into the appropriate "register".
925  * Returns 0 on success, non-0 otherwise.
926  * Assumes vcpu_load() was already called.
927  */
928 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
929 {
930         return kvm_x86_ops->set_msr(vcpu, msr);
931 }
932 
933 /*
934  * Adapt set_msr() to msr_io()'s calling convention
935  */
936 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
937 {
938         struct msr_data msr;
939 
940         msr.data = *data;
941         msr.index = index;
942         msr.host_initiated = true;
943         return kvm_set_msr(vcpu, &msr);
944 }
945 
946 #ifdef CONFIG_X86_64
947 struct pvclock_gtod_data {
948         seqcount_t      seq;
949 
950         struct { /* extract of a clocksource struct */
951                 int vclock_mode;
952                 cycle_t cycle_last;
953                 cycle_t mask;
954                 u32     mult;
955                 u32     shift;
956         } clock;
957 
958         /* open coded 'struct timespec' */
959         u64             monotonic_time_snsec;
960         time_t          monotonic_time_sec;
961 };
962 
963 static struct pvclock_gtod_data pvclock_gtod_data;
964 
965 static void update_pvclock_gtod(struct timekeeper *tk)
966 {
967         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
968 
969         write_seqcount_begin(&vdata->seq);
970 
971         /* copy pvclock gtod data */
972         vdata->clock.vclock_mode        = tk->clock->archdata.vclock_mode;
973         vdata->clock.cycle_last         = tk->clock->cycle_last;
974         vdata->clock.mask               = tk->clock->mask;
975         vdata->clock.mult               = tk->mult;
976         vdata->clock.shift              = tk->shift;
977 
978         vdata->monotonic_time_sec       = tk->xtime_sec
979                                         + tk->wall_to_monotonic.tv_sec;
980         vdata->monotonic_time_snsec     = tk->xtime_nsec
981                                         + (tk->wall_to_monotonic.tv_nsec
982                                                 << tk->shift);
983         while (vdata->monotonic_time_snsec >=
984                                         (((u64)NSEC_PER_SEC) << tk->shift)) {
985                 vdata->monotonic_time_snsec -=
986                                         ((u64)NSEC_PER_SEC) << tk->shift;
987                 vdata->monotonic_time_sec++;
988         }
989 
990         write_seqcount_end(&vdata->seq);
991 }
992 #endif
993 
994 
995 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
996 {
997         int version;
998         int r;
999         struct pvclock_wall_clock wc;
1000         struct timespec boot;
1001 
1002         if (!wall_clock)
1003                 return;
1004 
1005         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1006         if (r)
1007                 return;
1008 
1009         if (version & 1)
1010                 ++version;  /* first time write, random junk */
1011 
1012         ++version;
1013 
1014         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1015 
1016         /*
1017          * The guest calculates current wall clock time by adding
1018          * system time (updated by kvm_guest_time_update below) to the
1019          * wall clock specified here.  guest system time equals host
1020          * system time for us, thus we must fill in host boot time here.
1021          */
1022         getboottime(&boot);
1023 
1024         if (kvm->arch.kvmclock_offset) {
1025                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1026                 boot = timespec_sub(boot, ts);
1027         }
1028         wc.sec = boot.tv_sec;
1029         wc.nsec = boot.tv_nsec;
1030         wc.version = version;
1031 
1032         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1033 
1034         version++;
1035         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1036 }
1037 
1038 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1039 {
1040         uint32_t quotient, remainder;
1041 
1042         /* Don't try to replace with do_div(), this one calculates
1043          * "(dividend << 32) / divisor" */
1044         __asm__ ( "divl %4"
1045                   : "=a" (quotient), "=d" (remainder)
1046                   : "" (0), "1" (dividend), "r" (divisor) );
1047         return quotient;
1048 }
1049 
1050 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1051                                s8 *pshift, u32 *pmultiplier)
1052 {
1053         uint64_t scaled64;
1054         int32_t  shift = 0;
1055         uint64_t tps64;
1056         uint32_t tps32;
1057 
1058         tps64 = base_khz * 1000LL;
1059         scaled64 = scaled_khz * 1000LL;
1060         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1061                 tps64 >>= 1;
1062                 shift--;
1063         }
1064 
1065         tps32 = (uint32_t)tps64;
1066         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1067                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1068                         scaled64 >>= 1;
1069                 else
1070                         tps32 <<= 1;
1071                 shift++;
1072         }
1073 
1074         *pshift = shift;
1075         *pmultiplier = div_frac(scaled64, tps32);
1076 
1077         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1078                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1079 }
1080 
1081 static inline u64 get_kernel_ns(void)
1082 {
1083         struct timespec ts;
1084 
1085         WARN_ON(preemptible());
1086         ktime_get_ts(&ts);
1087         monotonic_to_bootbased(&ts);
1088         return timespec_to_ns(&ts);
1089 }
1090 
1091 #ifdef CONFIG_X86_64
1092 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1093 #endif
1094 
1095 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1096 unsigned long max_tsc_khz;
1097 
1098 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1099 {
1100         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1101                                    vcpu->arch.virtual_tsc_shift);
1102 }
1103 
1104 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1105 {
1106         u64 v = (u64)khz * (1000000 + ppm);
1107         do_div(v, 1000000);
1108         return v;
1109 }
1110 
1111 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1112 {
1113         u32 thresh_lo, thresh_hi;
1114         int use_scaling = 0;
1115 
1116         /* tsc_khz can be zero if TSC calibration fails */
1117         if (this_tsc_khz == 0)
1118                 return;
1119 
1120         /* Compute a scale to convert nanoseconds in TSC cycles */
1121         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1122                            &vcpu->arch.virtual_tsc_shift,
1123                            &vcpu->arch.virtual_tsc_mult);
1124         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1125 
1126         /*
1127          * Compute the variation in TSC rate which is acceptable
1128          * within the range of tolerance and decide if the
1129          * rate being applied is within that bounds of the hardware
1130          * rate.  If so, no scaling or compensation need be done.
1131          */
1132         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1133         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1134         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1135                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1136                 use_scaling = 1;
1137         }
1138         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1139 }
1140 
1141 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1142 {
1143         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1144                                       vcpu->arch.virtual_tsc_mult,
1145                                       vcpu->arch.virtual_tsc_shift);
1146         tsc += vcpu->arch.this_tsc_write;
1147         return tsc;
1148 }
1149 
1150 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1151 {
1152 #ifdef CONFIG_X86_64
1153         bool vcpus_matched;
1154         bool do_request = false;
1155         struct kvm_arch *ka = &vcpu->kvm->arch;
1156         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1157 
1158         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1159                          atomic_read(&vcpu->kvm->online_vcpus));
1160 
1161         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1162                 if (!ka->use_master_clock)
1163                         do_request = 1;
1164 
1165         if (!vcpus_matched && ka->use_master_clock)
1166                         do_request = 1;
1167 
1168         if (do_request)
1169                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1170 
1171         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1172                             atomic_read(&vcpu->kvm->online_vcpus),
1173                             ka->use_master_clock, gtod->clock.vclock_mode);
1174 #endif
1175 }
1176 
1177 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1178 {
1179         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1180         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1181 }
1182 
1183 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1184 {
1185         struct kvm *kvm = vcpu->kvm;
1186         u64 offset, ns, elapsed;
1187         unsigned long flags;
1188         s64 usdiff;
1189         bool matched;
1190         u64 data = msr->data;
1191 
1192         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1193         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1194         ns = get_kernel_ns();
1195         elapsed = ns - kvm->arch.last_tsc_nsec;
1196 
1197         if (vcpu->arch.virtual_tsc_khz) {
1198                 int faulted = 0;
1199 
1200                 /* n.b - signed multiplication and division required */
1201                 usdiff = data - kvm->arch.last_tsc_write;
1202 #ifdef CONFIG_X86_64
1203                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1204 #else
1205                 /* do_div() only does unsigned */
1206                 asm("1: idivl %[divisor]\n"
1207                     "2: xor %%edx, %%edx\n"
1208                     "   movl $0, %[faulted]\n"
1209                     "3:\n"
1210                     ".section .fixup,\"ax\"\n"
1211                     "4: movl $1, %[faulted]\n"
1212                     "   jmp  3b\n"
1213                     ".previous\n"
1214 
1215                 _ASM_EXTABLE(1b, 4b)
1216 
1217                 : "=A"(usdiff), [faulted] "=r" (faulted)
1218                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1219 
1220 #endif
1221                 do_div(elapsed, 1000);
1222                 usdiff -= elapsed;
1223                 if (usdiff < 0)
1224                         usdiff = -usdiff;
1225 
1226                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1227                 if (faulted)
1228                         usdiff = USEC_PER_SEC;
1229         } else
1230                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1231 
1232         /*
1233          * Special case: TSC write with a small delta (1 second) of virtual
1234          * cycle time against real time is interpreted as an attempt to
1235          * synchronize the CPU.
1236          *
1237          * For a reliable TSC, we can match TSC offsets, and for an unstable
1238          * TSC, we add elapsed time in this computation.  We could let the
1239          * compensation code attempt to catch up if we fall behind, but
1240          * it's better to try to match offsets from the beginning.
1241          */
1242         if (usdiff < USEC_PER_SEC &&
1243             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1244                 if (!check_tsc_unstable()) {
1245                         offset = kvm->arch.cur_tsc_offset;
1246                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1247                 } else {
1248                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1249                         data += delta;
1250                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1251                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1252                 }
1253                 matched = true;
1254         } else {
1255                 /*
1256                  * We split periods of matched TSC writes into generations.
1257                  * For each generation, we track the original measured
1258                  * nanosecond time, offset, and write, so if TSCs are in
1259                  * sync, we can match exact offset, and if not, we can match
1260                  * exact software computation in compute_guest_tsc()
1261                  *
1262                  * These values are tracked in kvm->arch.cur_xxx variables.
1263                  */
1264                 kvm->arch.cur_tsc_generation++;
1265                 kvm->arch.cur_tsc_nsec = ns;
1266                 kvm->arch.cur_tsc_write = data;
1267                 kvm->arch.cur_tsc_offset = offset;
1268                 matched = false;
1269                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1270                          kvm->arch.cur_tsc_generation, data);
1271         }
1272 
1273         /*
1274          * We also track th most recent recorded KHZ, write and time to
1275          * allow the matching interval to be extended at each write.
1276          */
1277         kvm->arch.last_tsc_nsec = ns;
1278         kvm->arch.last_tsc_write = data;
1279         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1280 
1281         /* Reset of TSC must disable overshoot protection below */
1282         vcpu->arch.hv_clock.tsc_timestamp = 0;
1283         vcpu->arch.last_guest_tsc = data;
1284 
1285         /* Keep track of which generation this VCPU has synchronized to */
1286         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1287         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1288         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1289 
1290         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1291                 update_ia32_tsc_adjust_msr(vcpu, offset);
1292         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1293         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1294 
1295         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1296         if (matched)
1297                 kvm->arch.nr_vcpus_matched_tsc++;
1298         else
1299                 kvm->arch.nr_vcpus_matched_tsc = 0;
1300 
1301         kvm_track_tsc_matching(vcpu);
1302         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1303 }
1304 
1305 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1306 
1307 #ifdef CONFIG_X86_64
1308 
1309 static cycle_t read_tsc(void)
1310 {
1311         cycle_t ret;
1312         u64 last;
1313 
1314         /*
1315          * Empirically, a fence (of type that depends on the CPU)
1316          * before rdtsc is enough to ensure that rdtsc is ordered
1317          * with respect to loads.  The various CPU manuals are unclear
1318          * as to whether rdtsc can be reordered with later loads,
1319          * but no one has ever seen it happen.
1320          */
1321         rdtsc_barrier();
1322         ret = (cycle_t)vget_cycles();
1323 
1324         last = pvclock_gtod_data.clock.cycle_last;
1325 
1326         if (likely(ret >= last))
1327                 return ret;
1328 
1329         /*
1330          * GCC likes to generate cmov here, but this branch is extremely
1331          * predictable (it's just a funciton of time and the likely is
1332          * very likely) and there's a data dependence, so force GCC
1333          * to generate a branch instead.  I don't barrier() because
1334          * we don't actually need a barrier, and if this function
1335          * ever gets inlined it will generate worse code.
1336          */
1337         asm volatile ("");
1338         return last;
1339 }
1340 
1341 static inline u64 vgettsc(cycle_t *cycle_now)
1342 {
1343         long v;
1344         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1345 
1346         *cycle_now = read_tsc();
1347 
1348         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1349         return v * gtod->clock.mult;
1350 }
1351 
1352 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1353 {
1354         unsigned long seq;
1355         u64 ns;
1356         int mode;
1357         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1358 
1359         ts->tv_nsec = 0;
1360         do {
1361                 seq = read_seqcount_begin(&gtod->seq);
1362                 mode = gtod->clock.vclock_mode;
1363                 ts->tv_sec = gtod->monotonic_time_sec;
1364                 ns = gtod->monotonic_time_snsec;
1365                 ns += vgettsc(cycle_now);
1366                 ns >>= gtod->clock.shift;
1367         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1368         timespec_add_ns(ts, ns);
1369 
1370         return mode;
1371 }
1372 
1373 /* returns true if host is using tsc clocksource */
1374 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1375 {
1376         struct timespec ts;
1377 
1378         /* checked again under seqlock below */
1379         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1380                 return false;
1381 
1382         if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1383                 return false;
1384 
1385         monotonic_to_bootbased(&ts);
1386         *kernel_ns = timespec_to_ns(&ts);
1387 
1388         return true;
1389 }
1390 #endif
1391 
1392 /*
1393  *
1394  * Assuming a stable TSC across physical CPUS, and a stable TSC
1395  * across virtual CPUs, the following condition is possible.
1396  * Each numbered line represents an event visible to both
1397  * CPUs at the next numbered event.
1398  *
1399  * "timespecX" represents host monotonic time. "tscX" represents
1400  * RDTSC value.
1401  *
1402  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1403  *
1404  * 1.  read timespec0,tsc0
1405  * 2.                                   | timespec1 = timespec0 + N
1406  *                                      | tsc1 = tsc0 + M
1407  * 3. transition to guest               | transition to guest
1408  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1409  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1410  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1411  *
1412  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1413  *
1414  *      - ret0 < ret1
1415  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1416  *              ...
1417  *      - 0 < N - M => M < N
1418  *
1419  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1420  * always the case (the difference between two distinct xtime instances
1421  * might be smaller then the difference between corresponding TSC reads,
1422  * when updating guest vcpus pvclock areas).
1423  *
1424  * To avoid that problem, do not allow visibility of distinct
1425  * system_timestamp/tsc_timestamp values simultaneously: use a master
1426  * copy of host monotonic time values. Update that master copy
1427  * in lockstep.
1428  *
1429  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1430  *
1431  */
1432 
1433 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1434 {
1435 #ifdef CONFIG_X86_64
1436         struct kvm_arch *ka = &kvm->arch;
1437         int vclock_mode;
1438         bool host_tsc_clocksource, vcpus_matched;
1439 
1440         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1441                         atomic_read(&kvm->online_vcpus));
1442 
1443         /*
1444          * If the host uses TSC clock, then passthrough TSC as stable
1445          * to the guest.
1446          */
1447         host_tsc_clocksource = kvm_get_time_and_clockread(
1448                                         &ka->master_kernel_ns,
1449                                         &ka->master_cycle_now);
1450 
1451         ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1452 
1453         if (ka->use_master_clock)
1454                 atomic_set(&kvm_guest_has_master_clock, 1);
1455 
1456         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1457         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1458                                         vcpus_matched);
1459 #endif
1460 }
1461 
1462 static void kvm_gen_update_masterclock(struct kvm *kvm)
1463 {
1464 #ifdef CONFIG_X86_64
1465         int i;
1466         struct kvm_vcpu *vcpu;
1467         struct kvm_arch *ka = &kvm->arch;
1468 
1469         spin_lock(&ka->pvclock_gtod_sync_lock);
1470         kvm_make_mclock_inprogress_request(kvm);
1471         /* no guest entries from this point */
1472         pvclock_update_vm_gtod_copy(kvm);
1473 
1474         kvm_for_each_vcpu(i, vcpu, kvm)
1475                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1476 
1477         /* guest entries allowed */
1478         kvm_for_each_vcpu(i, vcpu, kvm)
1479                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1480 
1481         spin_unlock(&ka->pvclock_gtod_sync_lock);
1482 #endif
1483 }
1484 
1485 static int kvm_guest_time_update(struct kvm_vcpu *v)
1486 {
1487         unsigned long flags, this_tsc_khz;
1488         struct kvm_vcpu_arch *vcpu = &v->arch;
1489         struct kvm_arch *ka = &v->kvm->arch;
1490         s64 kernel_ns, max_kernel_ns;
1491         u64 tsc_timestamp, host_tsc;
1492         struct pvclock_vcpu_time_info guest_hv_clock;
1493         u8 pvclock_flags;
1494         bool use_master_clock;
1495 
1496         kernel_ns = 0;
1497         host_tsc = 0;
1498 
1499         /*
1500          * If the host uses TSC clock, then passthrough TSC as stable
1501          * to the guest.
1502          */
1503         spin_lock(&ka->pvclock_gtod_sync_lock);
1504         use_master_clock = ka->use_master_clock;
1505         if (use_master_clock) {
1506                 host_tsc = ka->master_cycle_now;
1507                 kernel_ns = ka->master_kernel_ns;
1508         }
1509         spin_unlock(&ka->pvclock_gtod_sync_lock);
1510 
1511         /* Keep irq disabled to prevent changes to the clock */
1512         local_irq_save(flags);
1513         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1514         if (unlikely(this_tsc_khz == 0)) {
1515                 local_irq_restore(flags);
1516                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1517                 return 1;
1518         }
1519         if (!use_master_clock) {
1520                 host_tsc = native_read_tsc();
1521                 kernel_ns = get_kernel_ns();
1522         }
1523 
1524         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1525 
1526         /*
1527          * We may have to catch up the TSC to match elapsed wall clock
1528          * time for two reasons, even if kvmclock is used.
1529          *   1) CPU could have been running below the maximum TSC rate
1530          *   2) Broken TSC compensation resets the base at each VCPU
1531          *      entry to avoid unknown leaps of TSC even when running
1532          *      again on the same CPU.  This may cause apparent elapsed
1533          *      time to disappear, and the guest to stand still or run
1534          *      very slowly.
1535          */
1536         if (vcpu->tsc_catchup) {
1537                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1538                 if (tsc > tsc_timestamp) {
1539                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1540                         tsc_timestamp = tsc;
1541                 }
1542         }
1543 
1544         local_irq_restore(flags);
1545 
1546         if (!vcpu->pv_time_enabled)
1547                 return 0;
1548 
1549         /*
1550          * Time as measured by the TSC may go backwards when resetting the base
1551          * tsc_timestamp.  The reason for this is that the TSC resolution is
1552          * higher than the resolution of the other clock scales.  Thus, many
1553          * possible measurments of the TSC correspond to one measurement of any
1554          * other clock, and so a spread of values is possible.  This is not a
1555          * problem for the computation of the nanosecond clock; with TSC rates
1556          * around 1GHZ, there can only be a few cycles which correspond to one
1557          * nanosecond value, and any path through this code will inevitably
1558          * take longer than that.  However, with the kernel_ns value itself,
1559          * the precision may be much lower, down to HZ granularity.  If the
1560          * first sampling of TSC against kernel_ns ends in the low part of the
1561          * range, and the second in the high end of the range, we can get:
1562          *
1563          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1564          *
1565          * As the sampling errors potentially range in the thousands of cycles,
1566          * it is possible such a time value has already been observed by the
1567          * guest.  To protect against this, we must compute the system time as
1568          * observed by the guest and ensure the new system time is greater.
1569          */
1570         max_kernel_ns = 0;
1571         if (vcpu->hv_clock.tsc_timestamp) {
1572                 max_kernel_ns = vcpu->last_guest_tsc -
1573                                 vcpu->hv_clock.tsc_timestamp;
1574                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1575                                     vcpu->hv_clock.tsc_to_system_mul,
1576                                     vcpu->hv_clock.tsc_shift);
1577                 max_kernel_ns += vcpu->last_kernel_ns;
1578         }
1579 
1580         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1581                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582                                    &vcpu->hv_clock.tsc_shift,
1583                                    &vcpu->hv_clock.tsc_to_system_mul);
1584                 vcpu->hw_tsc_khz = this_tsc_khz;
1585         }
1586 
1587         /* with a master <monotonic time, tsc value> tuple,
1588          * pvclock clock reads always increase at the (scaled) rate
1589          * of guest TSC - no need to deal with sampling errors.
1590          */
1591         if (!use_master_clock) {
1592                 if (max_kernel_ns > kernel_ns)
1593                         kernel_ns = max_kernel_ns;
1594         }
1595         /* With all the info we got, fill in the values */
1596         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1597         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1598         vcpu->last_kernel_ns = kernel_ns;
1599         vcpu->last_guest_tsc = tsc_timestamp;
1600 
1601         /*
1602          * The interface expects us to write an even number signaling that the
1603          * update is finished. Since the guest won't see the intermediate
1604          * state, we just increase by 2 at the end.
1605          */
1606         vcpu->hv_clock.version += 2;
1607 
1608         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1609                 &guest_hv_clock, sizeof(guest_hv_clock))))
1610                 return 0;
1611 
1612         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1613         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1614 
1615         if (vcpu->pvclock_set_guest_stopped_request) {
1616                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1617                 vcpu->pvclock_set_guest_stopped_request = false;
1618         }
1619 
1620         /* If the host uses TSC clocksource, then it is stable */
1621         if (use_master_clock)
1622                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1623 
1624         vcpu->hv_clock.flags = pvclock_flags;
1625 
1626         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1627                                 &vcpu->hv_clock,
1628                                 sizeof(vcpu->hv_clock));
1629         return 0;
1630 }
1631 
1632 /*
1633  * kvmclock updates which are isolated to a given vcpu, such as
1634  * vcpu->cpu migration, should not allow system_timestamp from
1635  * the rest of the vcpus to remain static. Otherwise ntp frequency
1636  * correction applies to one vcpu's system_timestamp but not
1637  * the others.
1638  *
1639  * So in those cases, request a kvmclock update for all vcpus.
1640  * The worst case for a remote vcpu to update its kvmclock
1641  * is then bounded by maximum nohz sleep latency.
1642  */
1643 
1644 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1645 {
1646         int i;
1647         struct kvm *kvm = v->kvm;
1648         struct kvm_vcpu *vcpu;
1649 
1650         kvm_for_each_vcpu(i, vcpu, kvm) {
1651                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1652                 kvm_vcpu_kick(vcpu);
1653         }
1654 }
1655 
1656 static bool msr_mtrr_valid(unsigned msr)
1657 {
1658         switch (msr) {
1659         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1660         case MSR_MTRRfix64K_00000:
1661         case MSR_MTRRfix16K_80000:
1662         case MSR_MTRRfix16K_A0000:
1663         case MSR_MTRRfix4K_C0000:
1664         case MSR_MTRRfix4K_C8000:
1665         case MSR_MTRRfix4K_D0000:
1666         case MSR_MTRRfix4K_D8000:
1667         case MSR_MTRRfix4K_E0000:
1668         case MSR_MTRRfix4K_E8000:
1669         case MSR_MTRRfix4K_F0000:
1670         case MSR_MTRRfix4K_F8000:
1671         case MSR_MTRRdefType:
1672         case MSR_IA32_CR_PAT:
1673                 return true;
1674         case 0x2f8:
1675                 return true;
1676         }
1677         return false;
1678 }
1679 
1680 static bool valid_pat_type(unsigned t)
1681 {
1682         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1683 }
1684 
1685 static bool valid_mtrr_type(unsigned t)
1686 {
1687         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1688 }
1689 
1690 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1691 {
1692         int i;
1693 
1694         if (!msr_mtrr_valid(msr))
1695                 return false;
1696 
1697         if (msr == MSR_IA32_CR_PAT) {
1698                 for (i = 0; i < 8; i++)
1699                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1700                                 return false;
1701                 return true;
1702         } else if (msr == MSR_MTRRdefType) {
1703                 if (data & ~0xcff)
1704                         return false;
1705                 return valid_mtrr_type(data & 0xff);
1706         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1707                 for (i = 0; i < 8 ; i++)
1708                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1709                                 return false;
1710                 return true;
1711         }
1712 
1713         /* variable MTRRs */
1714         return valid_mtrr_type(data & 0xff);
1715 }
1716 
1717 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1718 {
1719         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1720 
1721         if (!mtrr_valid(vcpu, msr, data))
1722                 return 1;
1723 
1724         if (msr == MSR_MTRRdefType) {
1725                 vcpu->arch.mtrr_state.def_type = data;
1726                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1727         } else if (msr == MSR_MTRRfix64K_00000)
1728                 p[0] = data;
1729         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1730                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1731         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1732                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1733         else if (msr == MSR_IA32_CR_PAT)
1734                 vcpu->arch.pat = data;
1735         else {  /* Variable MTRRs */
1736                 int idx, is_mtrr_mask;
1737                 u64 *pt;
1738 
1739                 idx = (msr - 0x200) / 2;
1740                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1741                 if (!is_mtrr_mask)
1742                         pt =
1743                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1744                 else
1745                         pt =
1746                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1747                 *pt = data;
1748         }
1749 
1750         kvm_mmu_reset_context(vcpu);
1751         return 0;
1752 }
1753 
1754 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1755 {
1756         u64 mcg_cap = vcpu->arch.mcg_cap;
1757         unsigned bank_num = mcg_cap & 0xff;
1758 
1759         switch (msr) {
1760         case MSR_IA32_MCG_STATUS:
1761                 vcpu->arch.mcg_status = data;
1762                 break;
1763         case MSR_IA32_MCG_CTL:
1764                 if (!(mcg_cap & MCG_CTL_P))
1765                         return 1;
1766                 if (data != 0 && data != ~(u64)0)
1767                         return -1;
1768                 vcpu->arch.mcg_ctl = data;
1769                 break;
1770         default:
1771                 if (msr >= MSR_IA32_MC0_CTL &&
1772                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1773                         u32 offset = msr - MSR_IA32_MC0_CTL;
1774                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1775                          * some Linux kernels though clear bit 10 in bank 4 to
1776                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1777                          * this to avoid an uncatched #GP in the guest
1778                          */
1779                         if ((offset & 0x3) == 0 &&
1780                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1781                                 return -1;
1782                         vcpu->arch.mce_banks[offset] = data;
1783                         break;
1784                 }
1785                 return 1;
1786         }
1787         return 0;
1788 }
1789 
1790 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1791 {
1792         struct kvm *kvm = vcpu->kvm;
1793         int lm = is_long_mode(vcpu);
1794         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1795                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1796         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1797                 : kvm->arch.xen_hvm_config.blob_size_32;
1798         u32 page_num = data & ~PAGE_MASK;
1799         u64 page_addr = data & PAGE_MASK;
1800         u8 *page;
1801         int r;
1802 
1803         r = -E2BIG;
1804         if (page_num >= blob_size)
1805                 goto out;
1806         r = -ENOMEM;
1807         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1808         if (IS_ERR(page)) {
1809                 r = PTR_ERR(page);
1810                 goto out;
1811         }
1812         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1813                 goto out_free;
1814         r = 0;
1815 out_free:
1816         kfree(page);
1817 out:
1818         return r;
1819 }
1820 
1821 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1822 {
1823         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1824 }
1825 
1826 static bool kvm_hv_msr_partition_wide(u32 msr)
1827 {
1828         bool r = false;
1829         switch (msr) {
1830         case HV_X64_MSR_GUEST_OS_ID:
1831         case HV_X64_MSR_HYPERCALL:
1832                 r = true;
1833                 break;
1834         }
1835 
1836         return r;
1837 }
1838 
1839 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1840 {
1841         struct kvm *kvm = vcpu->kvm;
1842 
1843         switch (msr) {
1844         case HV_X64_MSR_GUEST_OS_ID:
1845                 kvm->arch.hv_guest_os_id = data;
1846                 /* setting guest os id to zero disables hypercall page */
1847                 if (!kvm->arch.hv_guest_os_id)
1848                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1849                 break;
1850         case HV_X64_MSR_HYPERCALL: {
1851                 u64 gfn;
1852                 unsigned long addr;
1853                 u8 instructions[4];
1854 
1855                 /* if guest os id is not set hypercall should remain disabled */
1856                 if (!kvm->arch.hv_guest_os_id)
1857                         break;
1858                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1859                         kvm->arch.hv_hypercall = data;
1860                         break;
1861                 }
1862                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1863                 addr = gfn_to_hva(kvm, gfn);
1864                 if (kvm_is_error_hva(addr))
1865                         return 1;
1866                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1867                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1868                 if (__copy_to_user((void __user *)addr, instructions, 4))
1869                         return 1;
1870                 kvm->arch.hv_hypercall = data;
1871                 break;
1872         }
1873         default:
1874                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1875                             "data 0x%llx\n", msr, data);
1876                 return 1;
1877         }
1878         return 0;
1879 }
1880 
1881 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1882 {
1883         switch (msr) {
1884         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1885                 unsigned long addr;
1886 
1887                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1888                         vcpu->arch.hv_vapic = data;
1889                         break;
1890                 }
1891                 addr = gfn_to_hva(vcpu->kvm, data >>
1892                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1893                 if (kvm_is_error_hva(addr))
1894                         return 1;
1895                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1896                         return 1;
1897                 vcpu->arch.hv_vapic = data;
1898                 break;
1899         }
1900         case HV_X64_MSR_EOI:
1901                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1902         case HV_X64_MSR_ICR:
1903                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1904         case HV_X64_MSR_TPR:
1905                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1906         default:
1907                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1908                             "data 0x%llx\n", msr, data);
1909                 return 1;
1910         }
1911 
1912         return 0;
1913 }
1914 
1915 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1916 {
1917         gpa_t gpa = data & ~0x3f;
1918 
1919         /* Bits 2:5 are reserved, Should be zero */
1920         if (data & 0x3c)
1921                 return 1;
1922 
1923         vcpu->arch.apf.msr_val = data;
1924 
1925         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1926                 kvm_clear_async_pf_completion_queue(vcpu);
1927                 kvm_async_pf_hash_reset(vcpu);
1928                 return 0;
1929         }
1930 
1931         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1932                                         sizeof(u32)))
1933                 return 1;
1934 
1935         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1936         kvm_async_pf_wakeup_all(vcpu);
1937         return 0;
1938 }
1939 
1940 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1941 {
1942         vcpu->arch.pv_time_enabled = false;
1943 }
1944 
1945 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1946 {
1947         u64 delta;
1948 
1949         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1950                 return;
1951 
1952         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1953         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1954         vcpu->arch.st.accum_steal = delta;
1955 }
1956 
1957 static void record_steal_time(struct kvm_vcpu *vcpu)
1958 {
1959         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1960                 return;
1961 
1962         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1963                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1964                 return;
1965 
1966         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1967         vcpu->arch.st.steal.version += 2;
1968         vcpu->arch.st.accum_steal = 0;
1969 
1970         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1971                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1972 }
1973 
1974 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1975 {
1976         bool pr = false;
1977         u32 msr = msr_info->index;
1978         u64 data = msr_info->data;
1979 
1980         switch (msr) {
1981         case MSR_AMD64_NB_CFG:
1982         case MSR_IA32_UCODE_REV:
1983         case MSR_IA32_UCODE_WRITE:
1984         case MSR_VM_HSAVE_PA:
1985         case MSR_AMD64_PATCH_LOADER:
1986         case MSR_AMD64_BU_CFG2:
1987                 break;
1988 
1989         case MSR_EFER:
1990                 return set_efer(vcpu, data);
1991         case MSR_K7_HWCR:
1992                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1993                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1994                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1995                 if (data != 0) {
1996                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1997                                     data);
1998                         return 1;
1999                 }
2000                 break;
2001         case MSR_FAM10H_MMIO_CONF_BASE:
2002                 if (data != 0) {
2003                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2004                                     "0x%llx\n", data);
2005                         return 1;
2006                 }
2007                 break;
2008         case MSR_IA32_DEBUGCTLMSR:
2009                 if (!data) {
2010                         /* We support the non-activated case already */
2011                         break;
2012                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2013                         /* Values other than LBR and BTF are vendor-specific,
2014                            thus reserved and should throw a #GP */
2015                         return 1;
2016                 }
2017                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2018                             __func__, data);
2019                 break;
2020         case 0x200 ... 0x2ff:
2021                 return set_msr_mtrr(vcpu, msr, data);
2022         case MSR_IA32_APICBASE:
2023                 kvm_set_apic_base(vcpu, data);
2024                 break;
2025         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2026                 return kvm_x2apic_msr_write(vcpu, msr, data);
2027         case MSR_IA32_TSCDEADLINE:
2028                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2029                 break;
2030         case MSR_IA32_TSC_ADJUST:
2031                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2032                         if (!msr_info->host_initiated) {
2033                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2034                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2035                         }
2036                         vcpu->arch.ia32_tsc_adjust_msr = data;
2037                 }
2038                 break;
2039         case MSR_IA32_MISC_ENABLE:
2040                 vcpu->arch.ia32_misc_enable_msr = data;
2041                 break;
2042         case MSR_KVM_WALL_CLOCK_NEW:
2043         case MSR_KVM_WALL_CLOCK:
2044                 vcpu->kvm->arch.wall_clock = data;
2045                 kvm_write_wall_clock(vcpu->kvm, data);
2046                 break;
2047         case MSR_KVM_SYSTEM_TIME_NEW:
2048         case MSR_KVM_SYSTEM_TIME: {
2049                 u64 gpa_offset;
2050                 kvmclock_reset(vcpu);
2051 
2052                 vcpu->arch.time = data;
2053                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2054 
2055                 /* we verify if the enable bit is set... */
2056                 if (!(data & 1))
2057                         break;
2058 
2059                 gpa_offset = data & ~(PAGE_MASK | 1);
2060 
2061                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2062                      &vcpu->arch.pv_time, data & ~1ULL,
2063                      sizeof(struct pvclock_vcpu_time_info)))
2064                         vcpu->arch.pv_time_enabled = false;
2065                 else
2066                         vcpu->arch.pv_time_enabled = true;
2067 
2068                 break;
2069         }
2070         case MSR_KVM_ASYNC_PF_EN:
2071                 if (kvm_pv_enable_async_pf(vcpu, data))
2072                         return 1;
2073                 break;
2074         case MSR_KVM_STEAL_TIME:
2075 
2076                 if (unlikely(!sched_info_on()))
2077                         return 1;
2078 
2079                 if (data & KVM_STEAL_RESERVED_MASK)
2080                         return 1;
2081 
2082                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2083                                                 data & KVM_STEAL_VALID_BITS,
2084                                                 sizeof(struct kvm_steal_time)))
2085                         return 1;
2086 
2087                 vcpu->arch.st.msr_val = data;
2088 
2089                 if (!(data & KVM_MSR_ENABLED))
2090                         break;
2091 
2092                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2093 
2094                 preempt_disable();
2095                 accumulate_steal_time(vcpu);
2096                 preempt_enable();
2097 
2098                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2099 
2100                 break;
2101         case MSR_KVM_PV_EOI_EN:
2102                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2103                         return 1;
2104                 break;
2105 
2106         case MSR_IA32_MCG_CTL:
2107         case MSR_IA32_MCG_STATUS:
2108         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2109                 return set_msr_mce(vcpu, msr, data);
2110 
2111         /* Performance counters are not protected by a CPUID bit,
2112          * so we should check all of them in the generic path for the sake of
2113          * cross vendor migration.
2114          * Writing a zero into the event select MSRs disables them,
2115          * which we perfectly emulate ;-). Any other value should be at least
2116          * reported, some guests depend on them.
2117          */
2118         case MSR_K7_EVNTSEL0:
2119         case MSR_K7_EVNTSEL1:
2120         case MSR_K7_EVNTSEL2:
2121         case MSR_K7_EVNTSEL3:
2122                 if (data != 0)
2123                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2124                                     "0x%x data 0x%llx\n", msr, data);
2125                 break;
2126         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2127          * so we ignore writes to make it happy.
2128          */
2129         case MSR_K7_PERFCTR0:
2130         case MSR_K7_PERFCTR1:
2131         case MSR_K7_PERFCTR2:
2132         case MSR_K7_PERFCTR3:
2133                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2134                             "0x%x data 0x%llx\n", msr, data);
2135                 break;
2136         case MSR_P6_PERFCTR0:
2137         case MSR_P6_PERFCTR1:
2138                 pr = true;
2139         case MSR_P6_EVNTSEL0:
2140         case MSR_P6_EVNTSEL1:
2141                 if (kvm_pmu_msr(vcpu, msr))
2142                         return kvm_pmu_set_msr(vcpu, msr_info);
2143 
2144                 if (pr || data != 0)
2145                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2146                                     "0x%x data 0x%llx\n", msr, data);
2147                 break;
2148         case MSR_K7_CLK_CTL:
2149                 /*
2150                  * Ignore all writes to this no longer documented MSR.
2151                  * Writes are only relevant for old K7 processors,
2152                  * all pre-dating SVM, but a recommended workaround from
2153                  * AMD for these chips. It is possible to specify the
2154                  * affected processor models on the command line, hence
2155                  * the need to ignore the workaround.
2156                  */
2157                 break;
2158         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2159                 if (kvm_hv_msr_partition_wide(msr)) {
2160                         int r;
2161                         mutex_lock(&vcpu->kvm->lock);
2162                         r = set_msr_hyperv_pw(vcpu, msr, data);
2163                         mutex_unlock(&vcpu->kvm->lock);
2164                         return r;
2165                 } else
2166                         return set_msr_hyperv(vcpu, msr, data);
2167                 break;
2168         case MSR_IA32_BBL_CR_CTL3:
2169                 /* Drop writes to this legacy MSR -- see rdmsr
2170                  * counterpart for further detail.
2171                  */
2172                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2173                 break;
2174         case MSR_AMD64_OSVW_ID_LENGTH:
2175                 if (!guest_cpuid_has_osvw(vcpu))
2176                         return 1;
2177                 vcpu->arch.osvw.length = data;
2178                 break;
2179         case MSR_AMD64_OSVW_STATUS:
2180                 if (!guest_cpuid_has_osvw(vcpu))
2181                         return 1;
2182                 vcpu->arch.osvw.status = data;
2183                 break;
2184         default:
2185                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2186                         return xen_hvm_config(vcpu, data);
2187                 if (kvm_pmu_msr(vcpu, msr))
2188                         return kvm_pmu_set_msr(vcpu, msr_info);
2189                 if (!ignore_msrs) {
2190                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2191                                     msr, data);
2192                         return 1;
2193                 } else {
2194                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2195                                     msr, data);
2196                         break;
2197                 }
2198         }
2199         return 0;
2200 }
2201 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2202 
2203 
2204 /*
2205  * Reads an msr value (of 'msr_index') into 'pdata'.
2206  * Returns 0 on success, non-0 otherwise.
2207  * Assumes vcpu_load() was already called.
2208  */
2209 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2210 {
2211         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2212 }
2213 
2214 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2215 {
2216         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2217 
2218         if (!msr_mtrr_valid(msr))
2219                 return 1;
2220 
2221         if (msr == MSR_MTRRdefType)
2222                 *pdata = vcpu->arch.mtrr_state.def_type +
2223                          (vcpu->arch.mtrr_state.enabled << 10);
2224         else if (msr == MSR_MTRRfix64K_00000)
2225                 *pdata = p[0];
2226         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2227                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2228         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2229                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2230         else if (msr == MSR_IA32_CR_PAT)
2231                 *pdata = vcpu->arch.pat;
2232         else {  /* Variable MTRRs */
2233                 int idx, is_mtrr_mask;
2234                 u64 *pt;
2235 
2236                 idx = (msr - 0x200) / 2;
2237                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2238                 if (!is_mtrr_mask)
2239                         pt =
2240                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2241                 else
2242                         pt =
2243                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2244                 *pdata = *pt;
2245         }
2246 
2247         return 0;
2248 }
2249 
2250 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2251 {
2252         u64 data;
2253         u64 mcg_cap = vcpu->arch.mcg_cap;
2254         unsigned bank_num = mcg_cap & 0xff;
2255 
2256         switch (msr) {
2257         case MSR_IA32_P5_MC_ADDR:
2258         case MSR_IA32_P5_MC_TYPE:
2259                 data = 0;
2260                 break;
2261         case MSR_IA32_MCG_CAP:
2262                 data = vcpu->arch.mcg_cap;
2263                 break;
2264         case MSR_IA32_MCG_CTL:
2265                 if (!(mcg_cap & MCG_CTL_P))
2266                         return 1;
2267                 data = vcpu->arch.mcg_ctl;
2268                 break;
2269         case MSR_IA32_MCG_STATUS:
2270                 data = vcpu->arch.mcg_status;
2271                 break;
2272         default:
2273                 if (msr >= MSR_IA32_MC0_CTL &&
2274                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2275                         u32 offset = msr - MSR_IA32_MC0_CTL;
2276                         data = vcpu->arch.mce_banks[offset];
2277                         break;
2278                 }
2279                 return 1;
2280         }
2281         *pdata = data;
2282         return 0;
2283 }
2284 
2285 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2286 {
2287         u64 data = 0;
2288         struct kvm *kvm = vcpu->kvm;
2289 
2290         switch (msr) {
2291         case HV_X64_MSR_GUEST_OS_ID:
2292                 data = kvm->arch.hv_guest_os_id;
2293                 break;
2294         case HV_X64_MSR_HYPERCALL:
2295                 data = kvm->arch.hv_hypercall;
2296                 break;
2297         default:
2298                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2299                 return 1;
2300         }
2301 
2302         *pdata = data;
2303         return 0;
2304 }
2305 
2306 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2307 {
2308         u64 data = 0;
2309 
2310         switch (msr) {
2311         case HV_X64_MSR_VP_INDEX: {
2312                 int r;
2313                 struct kvm_vcpu *v;
2314                 kvm_for_each_vcpu(r, v, vcpu->kvm)
2315                         if (v == vcpu)
2316                                 data = r;
2317                 break;
2318         }
2319         case HV_X64_MSR_EOI:
2320                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2321         case HV_X64_MSR_ICR:
2322                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2323         case HV_X64_MSR_TPR:
2324                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2325         case HV_X64_MSR_APIC_ASSIST_PAGE:
2326                 data = vcpu->arch.hv_vapic;
2327                 break;
2328         default:
2329                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2330                 return 1;
2331         }
2332         *pdata = data;
2333         return 0;
2334 }
2335 
2336 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2337 {
2338         u64 data;
2339 
2340         switch (msr) {
2341         case MSR_IA32_PLATFORM_ID:
2342         case MSR_IA32_EBL_CR_POWERON:
2343         case MSR_IA32_DEBUGCTLMSR:
2344         case MSR_IA32_LASTBRANCHFROMIP:
2345         case MSR_IA32_LASTBRANCHTOIP:
2346         case MSR_IA32_LASTINTFROMIP:
2347         case MSR_IA32_LASTINTTOIP:
2348         case MSR_K8_SYSCFG:
2349         case MSR_K7_HWCR:
2350         case MSR_VM_HSAVE_PA:
2351         case MSR_K7_EVNTSEL0:
2352         case MSR_K7_PERFCTR0:
2353         case MSR_K8_INT_PENDING_MSG:
2354         case MSR_AMD64_NB_CFG:
2355         case MSR_FAM10H_MMIO_CONF_BASE:
2356         case MSR_AMD64_BU_CFG2:
2357                 data = 0;
2358                 break;
2359         case MSR_P6_PERFCTR0:
2360         case MSR_P6_PERFCTR1:
2361         case MSR_P6_EVNTSEL0:
2362         case MSR_P6_EVNTSEL1:
2363                 if (kvm_pmu_msr(vcpu, msr))
2364                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2365                 data = 0;
2366                 break;
2367         case MSR_IA32_UCODE_REV:
2368                 data = 0x100000000ULL;
2369                 break;
2370         case MSR_MTRRcap:
2371                 data = 0x500 | KVM_NR_VAR_MTRR;
2372                 break;
2373         case 0x200 ... 0x2ff:
2374                 return get_msr_mtrr(vcpu, msr, pdata);
2375         case 0xcd: /* fsb frequency */
2376                 data = 3;
2377                 break;
2378                 /*
2379                  * MSR_EBC_FREQUENCY_ID
2380                  * Conservative value valid for even the basic CPU models.
2381                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2382                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2383                  * and 266MHz for model 3, or 4. Set Core Clock
2384                  * Frequency to System Bus Frequency Ratio to 1 (bits
2385                  * 31:24) even though these are only valid for CPU
2386                  * models > 2, however guests may end up dividing or
2387                  * multiplying by zero otherwise.
2388                  */
2389         case MSR_EBC_FREQUENCY_ID:
2390                 data = 1 << 24;
2391                 break;
2392         case MSR_IA32_APICBASE:
2393                 data = kvm_get_apic_base(vcpu);
2394                 break;
2395         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2396                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2397                 break;
2398         case MSR_IA32_TSCDEADLINE:
2399                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2400                 break;
2401         case MSR_IA32_TSC_ADJUST:
2402                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2403                 break;
2404         case MSR_IA32_MISC_ENABLE:
2405                 data = vcpu->arch.ia32_misc_enable_msr;
2406                 break;
2407         case MSR_IA32_PERF_STATUS:
2408                 /* TSC increment by tick */
2409                 data = 1000ULL;
2410                 /* CPU multiplier */
2411                 data |= (((uint64_t)4ULL) << 40);
2412                 break;
2413         case MSR_EFER:
2414                 data = vcpu->arch.efer;
2415                 break;
2416         case MSR_KVM_WALL_CLOCK:
2417         case MSR_KVM_WALL_CLOCK_NEW:
2418                 data = vcpu->kvm->arch.wall_clock;
2419                 break;
2420         case MSR_KVM_SYSTEM_TIME:
2421         case MSR_KVM_SYSTEM_TIME_NEW:
2422                 data = vcpu->arch.time;
2423                 break;
2424         case MSR_KVM_ASYNC_PF_EN:
2425                 data = vcpu->arch.apf.msr_val;
2426                 break;
2427         case MSR_KVM_STEAL_TIME:
2428                 data = vcpu->arch.st.msr_val;
2429                 break;
2430         case MSR_KVM_PV_EOI_EN:
2431                 data = vcpu->arch.pv_eoi.msr_val;
2432                 break;
2433         case MSR_IA32_P5_MC_ADDR:
2434         case MSR_IA32_P5_MC_TYPE:
2435         case MSR_IA32_MCG_CAP:
2436         case MSR_IA32_MCG_CTL:
2437         case MSR_IA32_MCG_STATUS:
2438         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2439                 return get_msr_mce(vcpu, msr, pdata);
2440         case MSR_K7_CLK_CTL:
2441                 /*
2442                  * Provide expected ramp-up count for K7. All other
2443                  * are set to zero, indicating minimum divisors for
2444                  * every field.
2445                  *
2446                  * This prevents guest kernels on AMD host with CPU
2447                  * type 6, model 8 and higher from exploding due to
2448                  * the rdmsr failing.
2449                  */
2450                 data = 0x20000000;
2451                 break;
2452         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2453                 if (kvm_hv_msr_partition_wide(msr)) {
2454                         int r;
2455                         mutex_lock(&vcpu->kvm->lock);
2456                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2457                         mutex_unlock(&vcpu->kvm->lock);
2458                         return r;
2459                 } else
2460                         return get_msr_hyperv(vcpu, msr, pdata);
2461                 break;
2462         case MSR_IA32_BBL_CR_CTL3:
2463                 /* This legacy MSR exists but isn't fully documented in current
2464                  * silicon.  It is however accessed by winxp in very narrow
2465                  * scenarios where it sets bit #19, itself documented as
2466                  * a "reserved" bit.  Best effort attempt to source coherent
2467                  * read data here should the balance of the register be
2468                  * interpreted by the guest:
2469                  *
2470                  * L2 cache control register 3: 64GB range, 256KB size,
2471                  * enabled, latency 0x1, configured
2472                  */
2473                 data = 0xbe702111;
2474                 break;
2475         case MSR_AMD64_OSVW_ID_LENGTH:
2476                 if (!guest_cpuid_has_osvw(vcpu))
2477                         return 1;
2478                 data = vcpu->arch.osvw.length;
2479                 break;
2480         case MSR_AMD64_OSVW_STATUS:
2481                 if (!guest_cpuid_has_osvw(vcpu))
2482                         return 1;
2483                 data = vcpu->arch.osvw.status;
2484                 break;
2485         default:
2486                 if (kvm_pmu_msr(vcpu, msr))
2487                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2488                 if (!ignore_msrs) {
2489                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2490                         return 1;
2491                 } else {
2492                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2493                         data = 0;
2494                 }
2495                 break;
2496         }
2497         *pdata = data;
2498         return 0;
2499 }
2500 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2501 
2502 /*
2503  * Read or write a bunch of msrs. All parameters are kernel addresses.
2504  *
2505  * @return number of msrs set successfully.
2506  */
2507 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2508                     struct kvm_msr_entry *entries,
2509                     int (*do_msr)(struct kvm_vcpu *vcpu,
2510                                   unsigned index, u64 *data))
2511 {
2512         int i, idx;
2513 
2514         idx = srcu_read_lock(&vcpu->kvm->srcu);
2515         for (i = 0; i < msrs->nmsrs; ++i)
2516                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2517                         break;
2518         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2519 
2520         return i;
2521 }
2522 
2523 /*
2524  * Read or write a bunch of msrs. Parameters are user addresses.
2525  *
2526  * @return number of msrs set successfully.
2527  */
2528 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2529                   int (*do_msr)(struct kvm_vcpu *vcpu,
2530                                 unsigned index, u64 *data),
2531                   int writeback)
2532 {
2533         struct kvm_msrs msrs;
2534         struct kvm_msr_entry *entries;
2535         int r, n;
2536         unsigned size;
2537 
2538         r = -EFAULT;
2539         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2540                 goto out;
2541 
2542         r = -E2BIG;
2543         if (msrs.nmsrs >= MAX_IO_MSRS)
2544                 goto out;
2545 
2546         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2547         entries = memdup_user(user_msrs->entries, size);
2548         if (IS_ERR(entries)) {
2549                 r = PTR_ERR(entries);
2550                 goto out;
2551         }
2552 
2553         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2554         if (r < 0)
2555                 goto out_free;
2556 
2557         r = -EFAULT;
2558         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2559                 goto out_free;
2560 
2561         r = n;
2562 
2563 out_free:
2564         kfree(entries);
2565 out:
2566         return r;
2567 }
2568 
2569 int kvm_dev_ioctl_check_extension(long ext)
2570 {
2571         int r;
2572 
2573         switch (ext) {
2574         case KVM_CAP_IRQCHIP:
2575         case KVM_CAP_HLT:
2576         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2577         case KVM_CAP_SET_TSS_ADDR:
2578         case KVM_CAP_EXT_CPUID:
2579         case KVM_CAP_EXT_EMUL_CPUID:
2580         case KVM_CAP_CLOCKSOURCE:
2581         case KVM_CAP_PIT:
2582         case KVM_CAP_NOP_IO_DELAY:
2583         case KVM_CAP_MP_STATE:
2584         case KVM_CAP_SYNC_MMU:
2585         case KVM_CAP_USER_NMI:
2586         case KVM_CAP_REINJECT_CONTROL:
2587         case KVM_CAP_IRQ_INJECT_STATUS:
2588         case KVM_CAP_IRQFD:
2589         case KVM_CAP_IOEVENTFD:
2590         case KVM_CAP_PIT2:
2591         case KVM_CAP_PIT_STATE2:
2592         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2593         case KVM_CAP_XEN_HVM:
2594         case KVM_CAP_ADJUST_CLOCK:
2595         case KVM_CAP_VCPU_EVENTS:
2596         case KVM_CAP_HYPERV:
2597         case KVM_CAP_HYPERV_VAPIC:
2598         case KVM_CAP_HYPERV_SPIN:
2599         case KVM_CAP_PCI_SEGMENT:
2600         case KVM_CAP_DEBUGREGS:
2601         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2602         case KVM_CAP_XSAVE:
2603         case KVM_CAP_ASYNC_PF:
2604         case KVM_CAP_GET_TSC_KHZ:
2605         case KVM_CAP_KVMCLOCK_CTRL:
2606         case KVM_CAP_READONLY_MEM:
2607 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2608         case KVM_CAP_ASSIGN_DEV_IRQ:
2609         case KVM_CAP_PCI_2_3:
2610 #endif
2611                 r = 1;
2612                 break;
2613         case KVM_CAP_COALESCED_MMIO:
2614                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2615                 break;
2616         case KVM_CAP_VAPIC:
2617                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2618                 break;
2619         case KVM_CAP_NR_VCPUS:
2620                 r = KVM_SOFT_MAX_VCPUS;
2621                 break;
2622         case KVM_CAP_MAX_VCPUS:
2623                 r = KVM_MAX_VCPUS;
2624                 break;
2625         case KVM_CAP_NR_MEMSLOTS:
2626                 r = KVM_USER_MEM_SLOTS;
2627                 break;
2628         case KVM_CAP_PV_MMU:    /* obsolete */
2629                 r = 0;
2630                 break;
2631 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2632         case KVM_CAP_IOMMU:
2633                 r = iommu_present(&pci_bus_type);
2634                 break;
2635 #endif
2636         case KVM_CAP_MCE:
2637                 r = KVM_MAX_MCE_BANKS;
2638                 break;
2639         case KVM_CAP_XCRS:
2640                 r = cpu_has_xsave;
2641                 break;
2642         case KVM_CAP_TSC_CONTROL:
2643                 r = kvm_has_tsc_control;
2644                 break;
2645         case KVM_CAP_TSC_DEADLINE_TIMER:
2646                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2647                 break;
2648         default:
2649                 r = 0;
2650                 break;
2651         }
2652         return r;
2653 
2654 }
2655 
2656 long kvm_arch_dev_ioctl(struct file *filp,
2657                         unsigned int ioctl, unsigned long arg)
2658 {
2659         void __user *argp = (void __user *)arg;
2660         long r;
2661 
2662         switch (ioctl) {
2663         case KVM_GET_MSR_INDEX_LIST: {
2664                 struct kvm_msr_list __user *user_msr_list = argp;
2665                 struct kvm_msr_list msr_list;
2666                 unsigned n;
2667 
2668                 r = -EFAULT;
2669                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2670                         goto out;
2671                 n = msr_list.nmsrs;
2672                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2673                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2674                         goto out;
2675                 r = -E2BIG;
2676                 if (n < msr_list.nmsrs)
2677                         goto out;
2678                 r = -EFAULT;
2679                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2680                                  num_msrs_to_save * sizeof(u32)))
2681                         goto out;
2682                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2683                                  &emulated_msrs,
2684                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2685                         goto out;
2686                 r = 0;
2687                 break;
2688         }
2689         case KVM_GET_SUPPORTED_CPUID:
2690         case KVM_GET_EMULATED_CPUID: {
2691                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2692                 struct kvm_cpuid2 cpuid;
2693 
2694                 r = -EFAULT;
2695                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2696                         goto out;
2697 
2698                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2699                                             ioctl);
2700                 if (r)
2701                         goto out;
2702 
2703                 r = -EFAULT;
2704                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2705                         goto out;
2706                 r = 0;
2707                 break;
2708         }
2709         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2710                 u64 mce_cap;
2711 
2712                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2713                 r = -EFAULT;
2714                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2715                         goto out;
2716                 r = 0;
2717                 break;
2718         }
2719         default:
2720                 r = -EINVAL;
2721         }
2722 out:
2723         return r;
2724 }
2725 
2726 static void wbinvd_ipi(void *garbage)
2727 {
2728         wbinvd();
2729 }
2730 
2731 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2732 {
2733         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2734 }
2735 
2736 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2737 {
2738         /* Address WBINVD may be executed by guest */
2739         if (need_emulate_wbinvd(vcpu)) {
2740                 if (kvm_x86_ops->has_wbinvd_exit())
2741                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2742                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2743                         smp_call_function_single(vcpu->cpu,
2744                                         wbinvd_ipi, NULL, 1);
2745         }
2746 
2747         kvm_x86_ops->vcpu_load(vcpu, cpu);
2748 
2749         /* Apply any externally detected TSC adjustments (due to suspend) */
2750         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2751                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2752                 vcpu->arch.tsc_offset_adjustment = 0;
2753                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2754         }
2755 
2756         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2757                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2758                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2759                 if (tsc_delta < 0)
2760                         mark_tsc_unstable("KVM discovered backwards TSC");
2761                 if (check_tsc_unstable()) {
2762                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2763                                                 vcpu->arch.last_guest_tsc);
2764                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2765                         vcpu->arch.tsc_catchup = 1;
2766                 }
2767                 /*
2768                  * On a host with synchronized TSC, there is no need to update
2769                  * kvmclock on vcpu->cpu migration
2770                  */
2771                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2772                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2773                 if (vcpu->cpu != cpu)
2774                         kvm_migrate_timers(vcpu);
2775                 vcpu->cpu = cpu;
2776         }
2777 
2778         accumulate_steal_time(vcpu);
2779         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2780 }
2781 
2782 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2783 {
2784         kvm_x86_ops->vcpu_put(vcpu);
2785         kvm_put_guest_fpu(vcpu);
2786         vcpu->arch.last_host_tsc = native_read_tsc();
2787 }
2788 
2789 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2790                                     struct kvm_lapic_state *s)
2791 {
2792         kvm_x86_ops->sync_pir_to_irr(vcpu);
2793         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2794 
2795         return 0;
2796 }
2797 
2798 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2799                                     struct kvm_lapic_state *s)
2800 {
2801         kvm_apic_post_state_restore(vcpu, s);
2802         update_cr8_intercept(vcpu);
2803 
2804         return 0;
2805 }
2806 
2807 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2808                                     struct kvm_interrupt *irq)
2809 {
2810         if (irq->irq >= KVM_NR_INTERRUPTS)
2811                 return -EINVAL;
2812         if (irqchip_in_kernel(vcpu->kvm))
2813                 return -ENXIO;
2814 
2815         kvm_queue_interrupt(vcpu, irq->irq, false);
2816         kvm_make_request(KVM_REQ_EVENT, vcpu);
2817 
2818         return 0;
2819 }
2820 
2821 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2822 {
2823         kvm_inject_nmi(vcpu);
2824 
2825         return 0;
2826 }
2827 
2828 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2829                                            struct kvm_tpr_access_ctl *tac)
2830 {
2831         if (tac->flags)
2832                 return -EINVAL;
2833         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2834         return 0;
2835 }
2836 
2837 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2838                                         u64 mcg_cap)
2839 {
2840         int r;
2841         unsigned bank_num = mcg_cap & 0xff, bank;
2842 
2843         r = -EINVAL;
2844         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2845                 goto out;
2846         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2847                 goto out;
2848         r = 0;
2849         vcpu->arch.mcg_cap = mcg_cap;
2850         /* Init IA32_MCG_CTL to all 1s */
2851         if (mcg_cap & MCG_CTL_P)
2852                 vcpu->arch.mcg_ctl = ~(u64)0;
2853         /* Init IA32_MCi_CTL to all 1s */
2854         for (bank = 0; bank < bank_num; bank++)
2855                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2856 out:
2857         return r;
2858 }
2859 
2860 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2861                                       struct kvm_x86_mce *mce)
2862 {
2863         u64 mcg_cap = vcpu->arch.mcg_cap;
2864         unsigned bank_num = mcg_cap & 0xff;
2865         u64 *banks = vcpu->arch.mce_banks;
2866 
2867         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2868                 return -EINVAL;
2869         /*
2870          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2871          * reporting is disabled
2872          */
2873         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2874             vcpu->arch.mcg_ctl != ~(u64)0)
2875                 return 0;
2876         banks += 4 * mce->bank;
2877         /*
2878          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2879          * reporting is disabled for the bank
2880          */
2881         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2882                 return 0;
2883         if (mce->status & MCI_STATUS_UC) {
2884                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2885                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2886                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2887                         return 0;
2888                 }
2889                 if (banks[1] & MCI_STATUS_VAL)
2890                         mce->status |= MCI_STATUS_OVER;
2891                 banks[2] = mce->addr;
2892                 banks[3] = mce->misc;
2893                 vcpu->arch.mcg_status = mce->mcg_status;
2894                 banks[1] = mce->status;
2895                 kvm_queue_exception(vcpu, MC_VECTOR);
2896         } else if (!(banks[1] & MCI_STATUS_VAL)
2897                    || !(banks[1] & MCI_STATUS_UC)) {
2898                 if (banks[1] & MCI_STATUS_VAL)
2899                         mce->status |= MCI_STATUS_OVER;
2900                 banks[2] = mce->addr;
2901                 banks[3] = mce->misc;
2902                 banks[1] = mce->status;
2903         } else
2904                 banks[1] |= MCI_STATUS_OVER;
2905         return 0;
2906 }
2907 
2908 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2909                                                struct kvm_vcpu_events *events)
2910 {
2911         process_nmi(vcpu);
2912         events->exception.injected =
2913                 vcpu->arch.exception.pending &&
2914                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2915         events->exception.nr = vcpu->arch.exception.nr;
2916         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2917         events->exception.pad = 0;
2918         events->exception.error_code = vcpu->arch.exception.error_code;
2919 
2920         events->interrupt.injected =
2921                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2922         events->interrupt.nr = vcpu->arch.interrupt.nr;
2923         events->interrupt.soft = 0;
2924         events->interrupt.shadow =
2925                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2926                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2927 
2928         events->nmi.injected = vcpu->arch.nmi_injected;
2929         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2930         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2931         events->nmi.pad = 0;
2932 
2933         events->sipi_vector = 0; /* never valid when reporting to user space */
2934 
2935         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2936                          | KVM_VCPUEVENT_VALID_SHADOW);
2937         memset(&events->reserved, 0, sizeof(events->reserved));
2938 }
2939 
2940 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2941                                               struct kvm_vcpu_events *events)
2942 {
2943         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2944                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2945                               | KVM_VCPUEVENT_VALID_SHADOW))
2946                 return -EINVAL;
2947 
2948         process_nmi(vcpu);
2949         vcpu->arch.exception.pending = events->exception.injected;
2950         vcpu->arch.exception.nr = events->exception.nr;
2951         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2952         vcpu->arch.exception.error_code = events->exception.error_code;
2953 
2954         vcpu->arch.interrupt.pending = events->interrupt.injected;
2955         vcpu->arch.interrupt.nr = events->interrupt.nr;
2956         vcpu->arch.interrupt.soft = events->interrupt.soft;
2957         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2958                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2959                                                   events->interrupt.shadow);
2960 
2961         vcpu->arch.nmi_injected = events->nmi.injected;
2962         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2963                 vcpu->arch.nmi_pending = events->nmi.pending;
2964         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2965 
2966         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2967             kvm_vcpu_has_lapic(vcpu))
2968                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2969 
2970         kvm_make_request(KVM_REQ_EVENT, vcpu);
2971 
2972         return 0;
2973 }
2974 
2975 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2976                                              struct kvm_debugregs *dbgregs)
2977 {
2978         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2979         dbgregs->dr6 = vcpu->arch.dr6;
2980         dbgregs->dr7 = vcpu->arch.dr7;
2981         dbgregs->flags = 0;
2982         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2983 }
2984 
2985 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2986                                             struct kvm_debugregs *dbgregs)
2987 {
2988         if (dbgregs->flags)
2989                 return -EINVAL;
2990 
2991         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2992         vcpu->arch.dr6 = dbgregs->dr6;
2993         vcpu->arch.dr7 = dbgregs->dr7;
2994 
2995         return 0;
2996 }
2997 
2998 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2999                                          struct kvm_xsave *guest_xsave)
3000 {
3001         if (cpu_has_xsave) {
3002                 memcpy(guest_xsave->region,
3003                         &vcpu->arch.guest_fpu.state->xsave,
3004                         vcpu->arch.guest_xstate_size);
3005                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3006                         vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3007         } else {
3008                 memcpy(guest_xsave->region,
3009                         &vcpu->arch.guest_fpu.state->fxsave,
3010                         sizeof(struct i387_fxsave_struct));
3011                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3012                         XSTATE_FPSSE;
3013         }
3014 }
3015 
3016 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3017                                         struct kvm_xsave *guest_xsave)
3018 {
3019         u64 xstate_bv =
3020                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3021 
3022         if (cpu_has_xsave) {
3023                 /*
3024                  * Here we allow setting states that are not present in
3025                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3026                  * with old userspace.
3027                  */
3028                 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3029                         return -EINVAL;
3030                 if (xstate_bv & ~host_xcr0)
3031                         return -EINVAL;
3032                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3033                         guest_xsave->region, vcpu->arch.guest_xstate_size);
3034         } else {
3035                 if (xstate_bv & ~XSTATE_FPSSE)
3036                         return -EINVAL;
3037                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3038                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3039         }
3040         return 0;
3041 }
3042 
3043 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3044                                         struct kvm_xcrs *guest_xcrs)
3045 {
3046         if (!cpu_has_xsave) {
3047                 guest_xcrs->nr_xcrs = 0;
3048                 return;
3049         }
3050 
3051         guest_xcrs->nr_xcrs = 1;
3052         guest_xcrs->flags = 0;
3053         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3054         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3055 }
3056 
3057 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3058                                        struct kvm_xcrs *guest_xcrs)
3059 {
3060         int i, r = 0;
3061 
3062         if (!cpu_has_xsave)
3063                 return -EINVAL;
3064 
3065         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3066                 return -EINVAL;
3067 
3068         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3069                 /* Only support XCR0 currently */
3070                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3071                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3072                                 guest_xcrs->xcrs[i].value);
3073                         break;
3074                 }
3075         if (r)
3076                 r = -EINVAL;
3077         return r;
3078 }
3079 
3080 /*
3081  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3082  * stopped by the hypervisor.  This function will be called from the host only.
3083  * EINVAL is returned when the host attempts to set the flag for a guest that
3084  * does not support pv clocks.
3085  */
3086 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3087 {
3088         if (!vcpu->arch.pv_time_enabled)
3089                 return -EINVAL;
3090         vcpu->arch.pvclock_set_guest_stopped_request = true;
3091         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3092         return 0;
3093 }
3094 
3095 long kvm_arch_vcpu_ioctl(struct file *filp,
3096                          unsigned int ioctl, unsigned long arg)
3097 {
3098         struct kvm_vcpu *vcpu = filp->private_data;
3099         void __user *argp = (void __user *)arg;
3100         int r;
3101         union {
3102                 struct kvm_lapic_state *lapic;
3103                 struct kvm_xsave *xsave;
3104                 struct kvm_xcrs *xcrs;
3105                 void *buffer;
3106         } u;
3107 
3108         u.buffer = NULL;
3109         switch (ioctl) {
3110         case KVM_GET_LAPIC: {
3111                 r = -EINVAL;
3112                 if (!vcpu->arch.apic)
3113                         goto out;
3114                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3115 
3116                 r = -ENOMEM;
3117                 if (!u.lapic)
3118                         goto out;
3119                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3120                 if (r)
3121                         goto out;
3122                 r = -EFAULT;
3123                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3124                         goto out;
3125                 r = 0;
3126                 break;
3127         }
3128         case KVM_SET_LAPIC: {
3129                 r = -EINVAL;
3130                 if (!vcpu->arch.apic)
3131                         goto out;
3132                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3133                 if (IS_ERR(u.lapic))
3134                         return PTR_ERR(u.lapic);
3135 
3136                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3137                 break;
3138         }
3139         case KVM_INTERRUPT: {
3140                 struct kvm_interrupt irq;
3141 
3142                 r = -EFAULT;
3143                 if (copy_from_user(&irq, argp, sizeof irq))
3144                         goto out;
3145                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3146                 break;
3147         }
3148         case KVM_NMI: {
3149                 r = kvm_vcpu_ioctl_nmi(vcpu);
3150                 break;
3151         }
3152         case KVM_SET_CPUID: {
3153                 struct kvm_cpuid __user *cpuid_arg = argp;
3154                 struct kvm_cpuid cpuid;
3155 
3156                 r = -EFAULT;
3157                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3158                         goto out;
3159                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3160                 break;
3161         }
3162         case KVM_SET_CPUID2: {
3163                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3164                 struct kvm_cpuid2 cpuid;
3165 
3166                 r = -EFAULT;
3167                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3168                         goto out;
3169                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3170                                               cpuid_arg->entries);
3171                 break;
3172         }
3173         case KVM_GET_CPUID2: {
3174                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3175                 struct kvm_cpuid2 cpuid;
3176 
3177                 r = -EFAULT;
3178                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3179                         goto out;
3180                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3181                                               cpuid_arg->entries);
3182                 if (r)
3183                         goto out;
3184                 r = -EFAULT;
3185                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3186                         goto out;
3187                 r = 0;
3188                 break;
3189         }
3190         case KVM_GET_MSRS:
3191                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3192                 break;
3193         case KVM_SET_MSRS:
3194                 r = msr_io(vcpu, argp, do_set_msr, 0);
3195                 break;
3196         case KVM_TPR_ACCESS_REPORTING: {
3197                 struct kvm_tpr_access_ctl tac;
3198 
3199                 r = -EFAULT;
3200                 if (copy_from_user(&tac, argp, sizeof tac))
3201                         goto out;
3202                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3203                 if (r)
3204                         goto out;
3205                 r = -EFAULT;
3206                 if (copy_to_user(argp, &tac, sizeof tac))
3207                         goto out;
3208                 r = 0;
3209                 break;
3210         };
3211         case KVM_SET_VAPIC_ADDR: {
3212                 struct kvm_vapic_addr va;
3213 
3214                 r = -EINVAL;
3215                 if (!irqchip_in_kernel(vcpu->kvm))
3216                         goto out;
3217                 r = -EFAULT;
3218                 if (copy_from_user(&va, argp, sizeof va))
3219                         goto out;
3220                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3221                 break;
3222         }
3223         case KVM_X86_SETUP_MCE: {
3224                 u64 mcg_cap;
3225 
3226                 r = -EFAULT;
3227                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3228                         goto out;
3229                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3230                 break;
3231         }
3232         case KVM_X86_SET_MCE: {
3233                 struct kvm_x86_mce mce;
3234 
3235                 r = -EFAULT;
3236                 if (copy_from_user(&mce, argp, sizeof mce))
3237                         goto out;
3238                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3239                 break;
3240         }
3241         case KVM_GET_VCPU_EVENTS: {
3242                 struct kvm_vcpu_events events;
3243 
3244                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3245 
3246                 r = -EFAULT;
3247                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3248                         break;
3249                 r = 0;
3250                 break;
3251         }
3252         case KVM_SET_VCPU_EVENTS: {
3253                 struct kvm_vcpu_events events;
3254 
3255                 r = -EFAULT;
3256                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3257                         break;
3258 
3259                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3260                 break;
3261         }
3262         case KVM_GET_DEBUGREGS: {
3263                 struct kvm_debugregs dbgregs;
3264 
3265                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3266 
3267                 r = -EFAULT;
3268                 if (copy_to_user(argp, &dbgregs,
3269                                  sizeof(struct kvm_debugregs)))
3270                         break;
3271                 r = 0;
3272                 break;
3273         }
3274         case KVM_SET_DEBUGREGS: {
3275                 struct kvm_debugregs dbgregs;
3276 
3277                 r = -EFAULT;
3278                 if (copy_from_user(&dbgregs, argp,
3279                                    sizeof(struct kvm_debugregs)))
3280                         break;
3281 
3282                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3283                 break;
3284         }
3285         case KVM_GET_XSAVE: {
3286                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3287                 r = -ENOMEM;
3288                 if (!u.xsave)
3289                         break;
3290 
3291                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3292 
3293                 r = -EFAULT;
3294                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3295                         break;
3296                 r = 0;
3297                 break;
3298         }
3299         case KVM_SET_XSAVE: {
3300                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3301                 if (IS_ERR(u.xsave))
3302                         return PTR_ERR(u.xsave);
3303 
3304                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3305                 break;
3306         }
3307         case KVM_GET_XCRS: {
3308                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3309                 r = -ENOMEM;
3310                 if (!u.xcrs)
3311                         break;
3312 
3313                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3314 
3315                 r = -EFAULT;
3316                 if (copy_to_user(argp, u.xcrs,
3317                                  sizeof(struct kvm_xcrs)))
3318                         break;
3319                 r = 0;
3320                 break;
3321         }
3322         case KVM_SET_XCRS: {
3323                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3324                 if (IS_ERR(u.xcrs))
3325                         return PTR_ERR(u.xcrs);
3326 
3327                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3328                 break;
3329         }
3330         case KVM_SET_TSC_KHZ: {
3331                 u32 user_tsc_khz;
3332 
3333                 r = -EINVAL;
3334                 user_tsc_khz = (u32)arg;
3335 
3336                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3337                         goto out;
3338 
3339                 if (user_tsc_khz == 0)
3340                         user_tsc_khz = tsc_khz;
3341 
3342                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3343 
3344                 r = 0;
3345                 goto out;
3346         }
3347         case KVM_GET_TSC_KHZ: {
3348                 r = vcpu->arch.virtual_tsc_khz;
3349                 goto out;
3350         }
3351         case KVM_KVMCLOCK_CTRL: {
3352                 r = kvm_set_guest_paused(vcpu);
3353                 goto out;
3354         }
3355         default:
3356                 r = -EINVAL;
3357         }
3358 out:
3359         kfree(u.buffer);
3360         return r;
3361 }
3362 
3363 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3364 {
3365         return VM_FAULT_SIGBUS;
3366 }
3367 
3368 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3369 {
3370         int ret;
3371 
3372         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3373                 return -EINVAL;
3374         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3375         return ret;
3376 }
3377 
3378 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3379                                               u64 ident_addr)
3380 {
3381         kvm->arch.ept_identity_map_addr = ident_addr;
3382         return 0;
3383 }
3384 
3385 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3386                                           u32 kvm_nr_mmu_pages)
3387 {
3388         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3389                 return -EINVAL;
3390 
3391         mutex_lock(&kvm->slots_lock);
3392 
3393         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3394         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3395 
3396         mutex_unlock(&kvm->slots_lock);
3397         return 0;
3398 }
3399 
3400 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3401 {
3402         return kvm->arch.n_max_mmu_pages;
3403 }
3404 
3405 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3406 {
3407         int r;
3408 
3409         r = 0;
3410         switch (chip->chip_id) {
3411         case KVM_IRQCHIP_PIC_MASTER:
3412                 memcpy(&chip->chip.pic,
3413                         &pic_irqchip(kvm)->pics[0],
3414                         sizeof(struct kvm_pic_state));
3415                 break;
3416         case KVM_IRQCHIP_PIC_SLAVE:
3417                 memcpy(&chip->chip.pic,
3418                         &pic_irqchip(kvm)->pics[1],
3419                         sizeof(struct kvm_pic_state));
3420                 break;
3421         case KVM_IRQCHIP_IOAPIC:
3422                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3423                 break;
3424         default:
3425                 r = -EINVAL;
3426                 break;
3427         }
3428         return r;
3429 }
3430 
3431 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3432 {
3433         int r;
3434 
3435         r = 0;
3436         switch (chip->chip_id) {
3437         case KVM_IRQCHIP_PIC_MASTER:
3438                 spin_lock(&pic_irqchip(kvm)->lock);
3439                 memcpy(&pic_irqchip(kvm)->pics[0],
3440                         &chip->chip.pic,
3441                         sizeof(struct kvm_pic_state));
3442                 spin_unlock(&pic_irqchip(kvm)->lock);
3443                 break;
3444         case KVM_IRQCHIP_PIC_SLAVE:
3445                 spin_lock(&pic_irqchip(kvm)->lock);
3446                 memcpy(&pic_irqchip(kvm)->pics[1],
3447                         &chip->chip.pic,
3448                         sizeof(struct kvm_pic_state));
3449                 spin_unlock(&pic_irqchip(kvm)->lock);
3450                 break;
3451         case KVM_IRQCHIP_IOAPIC:
3452                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3453                 break;
3454         default:
3455                 r = -EINVAL;
3456                 break;
3457         }
3458         kvm_pic_update_irq(pic_irqchip(kvm));
3459         return r;
3460 }
3461 
3462 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3463 {
3464         int r = 0;
3465 
3466         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3467         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3468         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3469         return r;
3470 }
3471 
3472 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3473 {
3474         int r = 0;
3475 
3476         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3477         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3478         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3479         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3480         return r;
3481 }
3482 
3483 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3484 {
3485         int r = 0;
3486 
3487         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3488         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3489                 sizeof(ps->channels));
3490         ps->flags = kvm->arch.vpit->pit_state.flags;
3491         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3492         memset(&ps->reserved, 0, sizeof(ps->reserved));
3493         return r;
3494 }
3495 
3496 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3497 {
3498         int r = 0, start = 0;
3499         u32 prev_legacy, cur_legacy;
3500         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3501         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3502         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3503         if (!prev_legacy && cur_legacy)
3504                 start = 1;
3505         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3506                sizeof(kvm->arch.vpit->pit_state.channels));
3507         kvm->arch.vpit->pit_state.flags = ps->flags;
3508         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3509         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3510         return r;
3511 }
3512 
3513 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3514                                  struct kvm_reinject_control *control)
3515 {
3516         if (!kvm->arch.vpit)
3517                 return -ENXIO;
3518         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3519         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3520         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3521         return 0;
3522 }
3523 
3524 /**
3525  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3526  * @kvm: kvm instance
3527  * @log: slot id and address to which we copy the log
3528  *
3529  * We need to keep it in mind that VCPU threads can write to the bitmap
3530  * concurrently.  So, to avoid losing data, we keep the following order for
3531  * each bit:
3532  *
3533  *   1. Take a snapshot of the bit and clear it if needed.
3534  *   2. Write protect the corresponding page.
3535  *   3. Flush TLB's if needed.
3536  *   4. Copy the snapshot to the userspace.
3537  *
3538  * Between 2 and 3, the guest may write to the page using the remaining TLB
3539  * entry.  This is not a problem because the page will be reported dirty at
3540  * step 4 using the snapshot taken before and step 3 ensures that successive
3541  * writes will be logged for the next call.
3542  */
3543 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3544 {
3545         int r;
3546         struct kvm_memory_slot *memslot;
3547         unsigned long n, i;
3548         unsigned long *dirty_bitmap;
3549         unsigned long *dirty_bitmap_buffer;
3550         bool is_dirty = false;
3551 
3552         mutex_lock(&kvm->slots_lock);
3553 
3554         r = -EINVAL;
3555         if (log->slot >= KVM_USER_MEM_SLOTS)
3556                 goto out;
3557 
3558         memslot = id_to_memslot(kvm->memslots, log->slot);
3559 
3560         dirty_bitmap = memslot->dirty_bitmap;
3561         r = -ENOENT;
3562         if (!dirty_bitmap)
3563                 goto out;
3564 
3565         n = kvm_dirty_bitmap_bytes(memslot);
3566 
3567         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3568         memset(dirty_bitmap_buffer, 0, n);
3569 
3570         spin_lock(&kvm->mmu_lock);
3571 
3572         for (i = 0; i < n / sizeof(long); i++) {
3573                 unsigned long mask;
3574                 gfn_t offset;
3575 
3576                 if (!dirty_bitmap[i])
3577                         continue;
3578 
3579                 is_dirty = true;
3580 
3581                 mask = xchg(&dirty_bitmap[i], 0);
3582                 dirty_bitmap_buffer[i] = mask;
3583 
3584                 offset = i * BITS_PER_LONG;
3585                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3586         }
3587         if (is_dirty)
3588                 kvm_flush_remote_tlbs(kvm);
3589 
3590         spin_unlock(&kvm->mmu_lock);
3591 
3592         r = -EFAULT;
3593         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3594                 goto out;
3595 
3596         r = 0;
3597 out:
3598         mutex_unlock(&kvm->slots_lock);
3599         return r;
3600 }
3601 
3602 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3603                         bool line_status)
3604 {
3605         if (!irqchip_in_kernel(kvm))
3606                 return -ENXIO;
3607 
3608         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3609                                         irq_event->irq, irq_event->level,
3610                                         line_status);
3611         return 0;
3612 }
3613 
3614 long kvm_arch_vm_ioctl(struct file *filp,
3615                        unsigned int ioctl, unsigned long arg)
3616 {
3617         struct kvm *kvm = filp->private_data;
3618         void __user *argp = (void __user *)arg;
3619         int r = -ENOTTY;
3620         /*
3621          * This union makes it completely explicit to gcc-3.x
3622          * that these two variables' stack usage should be
3623          * combined, not added together.
3624          */
3625         union {
3626                 struct kvm_pit_state ps;
3627                 struct kvm_pit_state2 ps2;
3628                 struct kvm_pit_config pit_config;
3629         } u;
3630 
3631         switch (ioctl) {
3632         case KVM_SET_TSS_ADDR:
3633                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3634                 break;
3635         case KVM_SET_IDENTITY_MAP_ADDR: {
3636                 u64 ident_addr;
3637 
3638                 r = -EFAULT;
3639                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3640                         goto out;
3641                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3642                 break;
3643         }
3644         case KVM_SET_NR_MMU_PAGES:
3645                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3646                 break;
3647         case KVM_GET_NR_MMU_PAGES:
3648                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3649                 break;
3650         case KVM_CREATE_IRQCHIP: {
3651                 struct kvm_pic *vpic;
3652 
3653                 mutex_lock(&kvm->lock);
3654                 r = -EEXIST;
3655                 if (kvm->arch.vpic)
3656                         goto create_irqchip_unlock;
3657                 r = -EINVAL;
3658                 if (atomic_read(&kvm->online_vcpus))
3659                         goto create_irqchip_unlock;
3660                 r = -ENOMEM;
3661                 vpic = kvm_create_pic(kvm);
3662                 if (vpic) {
3663                         r = kvm_ioapic_init(kvm);
3664                         if (r) {
3665                                 mutex_lock(&kvm->slots_lock);
3666                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3667                                                           &vpic->dev_master);
3668                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3669                                                           &vpic->dev_slave);
3670                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3671                                                           &vpic->dev_eclr);
3672                                 mutex_unlock(&kvm->slots_lock);
3673                                 kfree(vpic);
3674                                 goto create_irqchip_unlock;
3675                         }
3676                 } else
3677                         goto create_irqchip_unlock;
3678                 smp_wmb();
3679                 kvm->arch.vpic = vpic;
3680                 smp_wmb();
3681                 r = kvm_setup_default_irq_routing(kvm);
3682                 if (r) {
3683                         mutex_lock(&kvm->slots_lock);
3684                         mutex_lock(&kvm->irq_lock);
3685                         kvm_ioapic_destroy(kvm);
3686                         kvm_destroy_pic(kvm);
3687                         mutex_unlock(&kvm->irq_lock);
3688                         mutex_unlock(&kvm->slots_lock);
3689                 }
3690         create_irqchip_unlock:
3691                 mutex_unlock(&kvm->lock);
3692                 break;
3693         }
3694         case KVM_CREATE_PIT:
3695                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3696                 goto create_pit;
3697         case KVM_CREATE_PIT2:
3698                 r = -EFAULT;
3699                 if (copy_from_user(&u.pit_config, argp,
3700                                    sizeof(struct kvm_pit_config)))
3701                         goto out;
3702         create_pit:
3703                 mutex_lock(&kvm->slots_lock);
3704                 r = -EEXIST;
3705                 if (kvm->arch.vpit)
3706                         goto create_pit_unlock;
3707                 r = -ENOMEM;
3708                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3709                 if (kvm->arch.vpit)
3710                         r = 0;
3711         create_pit_unlock:
3712                 mutex_unlock(&kvm->slots_lock);
3713                 break;
3714         case KVM_GET_IRQCHIP: {
3715                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3716                 struct kvm_irqchip *chip;
3717 
3718                 chip = memdup_user(argp, sizeof(*chip));
3719                 if (IS_ERR(chip)) {
3720                         r = PTR_ERR(chip);
3721                         goto out;
3722                 }
3723 
3724                 r = -ENXIO;
3725                 if (!irqchip_in_kernel(kvm))
3726                         goto get_irqchip_out;
3727                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3728                 if (r)
3729                         goto get_irqchip_out;
3730                 r = -EFAULT;
3731                 if (copy_to_user(argp, chip, sizeof *chip))
3732                         goto get_irqchip_out;
3733                 r = 0;
3734         get_irqchip_out:
3735                 kfree(chip);
3736                 break;
3737         }
3738         case KVM_SET_IRQCHIP: {
3739                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3740                 struct kvm_irqchip *chip;
3741 
3742                 chip = memdup_user(argp, sizeof(*chip));
3743                 if (IS_ERR(chip)) {
3744                         r = PTR_ERR(chip);
3745                         goto out;
3746                 }
3747 
3748                 r = -ENXIO;
3749                 if (!irqchip_in_kernel(kvm))
3750                         goto set_irqchip_out;
3751                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3752                 if (r)
3753                         goto set_irqchip_out;
3754                 r = 0;
3755         set_irqchip_out:
3756                 kfree(chip);
3757                 break;
3758         }
3759         case KVM_GET_PIT: {
3760                 r = -EFAULT;
3761                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3762                         goto out;
3763                 r = -ENXIO;
3764                 if (!kvm->arch.vpit)
3765                         goto out;
3766                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3767                 if (r)
3768                         goto out;
3769                 r = -EFAULT;
3770                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3771                         goto out;
3772                 r = 0;
3773                 break;
3774         }
3775         case KVM_SET_PIT: {
3776                 r = -EFAULT;
3777                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3778                         goto out;
3779                 r = -ENXIO;
3780                 if (!kvm->arch.vpit)
3781                         goto out;
3782                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3783                 break;
3784         }
3785         case KVM_GET_PIT2: {
3786                 r = -ENXIO;
3787                 if (!kvm->arch.vpit)
3788                         goto out;
3789                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3790                 if (r)
3791                         goto out;
3792                 r = -EFAULT;
3793                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3794                         goto out;
3795                 r = 0;
3796                 break;
3797         }
3798         case KVM_SET_PIT2: {
3799                 r = -EFAULT;
3800                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3801                         goto out;
3802                 r = -ENXIO;
3803                 if (!kvm->arch.vpit)
3804                         goto out;
3805                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3806                 break;
3807         }
3808         case KVM_REINJECT_CONTROL: {
3809                 struct kvm_reinject_control control;
3810                 r =  -EFAULT;
3811                 if (copy_from_user(&control, argp, sizeof(control)))
3812                         goto out;
3813                 r = kvm_vm_ioctl_reinject(kvm, &control);
3814                 break;
3815         }
3816         case KVM_XEN_HVM_CONFIG: {
3817                 r = -EFAULT;
3818                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3819                                    sizeof(struct kvm_xen_hvm_config)))
3820                         goto out;
3821                 r = -EINVAL;
3822                 if (kvm->arch.xen_hvm_config.flags)
3823                         goto out;
3824                 r = 0;
3825                 break;
3826         }
3827         case KVM_SET_CLOCK: {
3828                 struct kvm_clock_data user_ns;
3829                 u64 now_ns;
3830                 s64 delta;
3831 
3832                 r = -EFAULT;
3833                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3834                         goto out;
3835 
3836                 r = -EINVAL;
3837                 if (user_ns.flags)
3838                         goto out;
3839 
3840                 r = 0;
3841                 local_irq_disable();
3842                 now_ns = get_kernel_ns();
3843                 delta = user_ns.clock - now_ns;
3844                 local_irq_enable();
3845                 kvm->arch.kvmclock_offset = delta;
3846                 kvm_gen_update_masterclock(kvm);
3847                 break;
3848         }
3849         case KVM_GET_CLOCK: {
3850                 struct kvm_clock_data user_ns;
3851                 u64 now_ns;
3852 
3853                 local_irq_disable();
3854                 now_ns = get_kernel_ns();
3855                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3856                 local_irq_enable();
3857                 user_ns.flags = 0;
3858                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3859 
3860                 r = -EFAULT;
3861                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3862                         goto out;
3863                 r = 0;
3864                 break;
3865         }
3866 
3867         default:
3868                 ;
3869         }
3870 out:
3871         return r;
3872 }
3873 
3874 static void kvm_init_msr_list(void)
3875 {
3876         u32 dummy[2];
3877         unsigned i, j;
3878 
3879         /* skip the first msrs in the list. KVM-specific */
3880         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3881                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3882                         continue;
3883                 if (j < i)
3884                         msrs_to_save[j] = msrs_to_save[i];
3885                 j++;
3886         }
3887         num_msrs_to_save = j;
3888 }
3889 
3890 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3891                            const void *v)
3892 {
3893         int handled = 0;
3894         int n;
3895 
3896         do {
3897                 n = min(len, 8);
3898                 if (!(vcpu->arch.apic &&
3899                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3900                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3901                         break;
3902                 handled += n;
3903                 addr += n;
3904                 len -= n;
3905                 v += n;
3906         } while (len);
3907 
3908         return handled;
3909 }
3910 
3911 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3912 {
3913         int handled = 0;
3914         int n;
3915 
3916         do {
3917                 n = min(len, 8);
3918                 if (!(vcpu->arch.apic &&
3919                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3920                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3921                         break;
3922                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3923                 handled += n;
3924                 addr += n;
3925                 len -= n;
3926                 v += n;
3927         } while (len);
3928 
3929         return handled;
3930 }
3931 
3932 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3933                         struct kvm_segment *var, int seg)
3934 {
3935         kvm_x86_ops->set_segment(vcpu, var, seg);
3936 }
3937 
3938 void kvm_get_segment(struct kvm_vcpu *vcpu,
3939                      struct kvm_segment *var, int seg)
3940 {
3941         kvm_x86_ops->get_segment(vcpu, var, seg);
3942 }
3943 
3944 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3945 {
3946         gpa_t t_gpa;
3947         struct x86_exception exception;
3948 
3949         BUG_ON(!mmu_is_nested(vcpu));
3950 
3951         /* NPT walks are always user-walks */
3952         access |= PFERR_USER_MASK;
3953         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3954 
3955         return t_gpa;
3956 }
3957 
3958 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3959                               struct x86_exception *exception)
3960 {
3961         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3962         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3963 }
3964 
3965  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3966                                 struct x86_exception *exception)
3967 {
3968         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3969         access |= PFERR_FETCH_MASK;
3970         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3971 }
3972 
3973 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3974                                struct x86_exception *exception)
3975 {
3976         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3977         access |= PFERR_WRITE_MASK;
3978         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3979 }
3980 
3981 /* uses this to access any guest's mapped memory without checking CPL */
3982 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3983                                 struct x86_exception *exception)
3984 {
3985         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3986 }
3987 
3988 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3989                                       struct kvm_vcpu *vcpu, u32 access,
3990                                       struct x86_exception *exception)
3991 {
3992         void *data = val;
3993         int r = X86EMUL_CONTINUE;
3994 
3995         while (bytes) {
3996                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3997                                                             exception);
3998                 unsigned offset = addr & (PAGE_SIZE-1);
3999                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4000                 int ret;
4001 
4002                 if (gpa == UNMAPPED_GVA)
4003                         return X86EMUL_PROPAGATE_FAULT;
4004                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4005                 if (ret < 0) {
4006                         r = X86EMUL_IO_NEEDED;
4007                         goto out;
4008                 }
4009 
4010                 bytes -= toread;
4011                 data += toread;
4012                 addr += toread;
4013         }
4014 out:
4015         return r;
4016 }
4017 
4018 /* used for instruction fetching */
4019 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4020                                 gva_t addr, void *val, unsigned int bytes,
4021                                 struct x86_exception *exception)
4022 {
4023         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4024         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4025 
4026         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4027                                           access | PFERR_FETCH_MASK,
4028                                           exception);
4029 }
4030 
4031 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4032                                gva_t addr, void *val, unsigned int bytes,
4033                                struct x86_exception *exception)
4034 {
4035         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4036         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4037 
4038         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4039                                           exception);
4040 }
4041 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4042 
4043 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4044                                       gva_t addr, void *val, unsigned int bytes,
4045                                       struct x86_exception *exception)
4046 {
4047         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4048         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4049 }
4050 
4051 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4052                                        gva_t addr, void *val,
4053                                        unsigned int bytes,
4054                                        struct x86_exception *exception)
4055 {
4056         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4057         void *data = val;
4058         int r = X86EMUL_CONTINUE;
4059 
4060         while (bytes) {
4061                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4062                                                              PFERR_WRITE_MASK,
4063                                                              exception);
4064                 unsigned offset = addr & (PAGE_SIZE-1);
4065                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4066                 int ret;
4067 
4068                 if (gpa == UNMAPPED_GVA)
4069                         return X86EMUL_PROPAGATE_FAULT;
4070                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4071                 if (ret < 0) {
4072                         r = X86EMUL_IO_NEEDED;
4073                         goto out;
4074                 }
4075 
4076                 bytes -= towrite;
4077                 data += towrite;
4078                 addr += towrite;
4079         }
4080 out:
4081         return r;
4082 }
4083 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4084 
4085 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4086                                 gpa_t *gpa, struct x86_exception *exception,
4087                                 bool write)
4088 {
4089         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4090                 | (write ? PFERR_WRITE_MASK : 0);
4091 
4092         if (vcpu_match_mmio_gva(vcpu, gva)
4093             && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4094                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4095                                         (gva & (PAGE_SIZE - 1));
4096                 trace_vcpu_match_mmio(gva, *gpa, write, false);
4097                 return 1;
4098         }
4099 
4100         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4101 
4102         if (*gpa == UNMAPPED_GVA)
4103                 return -1;
4104 
4105         /* For APIC access vmexit */
4106         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4107                 return 1;
4108 
4109         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4110                 trace_vcpu_match_mmio(gva, *gpa, write, true);
4111                 return 1;
4112         }
4113 
4114         return 0;
4115 }
4116 
4117 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4118                         const void *val, int bytes)
4119 {
4120         int ret;
4121 
4122         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4123         if (ret < 0)
4124                 return 0;
4125         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4126         return 1;
4127 }
4128 
4129 struct read_write_emulator_ops {
4130         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4131                                   int bytes);
4132         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4133                                   void *val, int bytes);
4134         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4135                                int bytes, void *val);
4136         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4137                                     void *val, int bytes);
4138         bool write;
4139 };
4140 
4141 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4142 {
4143         if (vcpu->mmio_read_completed) {
4144                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4145                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4146                 vcpu->mmio_read_completed = 0;
4147                 return 1;
4148         }
4149 
4150         return 0;
4151 }
4152 
4153 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4154                         void *val, int bytes)
4155 {
4156         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4157 }
4158 
4159 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4160                          void *val, int bytes)
4161 {
4162         return emulator_write_phys(vcpu, gpa, val, bytes);
4163 }
4164 
4165 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4166 {
4167         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4168         return vcpu_mmio_write(vcpu, gpa, bytes, val);
4169 }
4170 
4171 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4172                           void *val, int bytes)
4173 {
4174         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4175         return X86EMUL_IO_NEEDED;
4176 }
4177 
4178 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4179                            void *val, int bytes)
4180 {
4181         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4182 
4183         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4184         return X86EMUL_CONTINUE;
4185 }
4186 
4187 static const struct read_write_emulator_ops read_emultor = {
4188         .read_write_prepare = read_prepare,
4189         .read_write_emulate = read_emulate,
4190         .read_write_mmio = vcpu_mmio_read,
4191         .read_write_exit_mmio = read_exit_mmio,
4192 };
4193 
4194 static const struct read_write_emulator_ops write_emultor = {
4195         .read_write_emulate = write_emulate,
4196         .read_write_mmio = write_mmio,
4197         .read_write_exit_mmio = write_exit_mmio,
4198         .write = true,
4199 };
4200 
4201 static int emulator_read_write_onepage(unsigned long addr, void *val,
4202                                        unsigned int bytes,
4203                                        struct x86_exception *exception,
4204                                        struct kvm_vcpu *vcpu,
4205                                        const struct read_write_emulator_ops *ops)
4206 {
4207         gpa_t gpa;
4208         int handled, ret;
4209         bool write = ops->write;
4210         struct kvm_mmio_fragment *frag;
4211 
4212         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4213 
4214         if (ret < 0)
4215                 return X86EMUL_PROPAGATE_FAULT;
4216 
4217         /* For APIC access vmexit */
4218         if (ret)
4219                 goto mmio;
4220 
4221         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4222                 return X86EMUL_CONTINUE;
4223 
4224 mmio:
4225         /*
4226          * Is this MMIO handled locally?
4227          */
4228         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4229         if (handled == bytes)
4230                 return X86EMUL_CONTINUE;
4231 
4232         gpa += handled;
4233         bytes -= handled;
4234         val += handled;
4235 
4236         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4237         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4238         frag->gpa = gpa;
4239         frag->data = val;
4240         frag->len = bytes;
4241         return X86EMUL_CONTINUE;
4242 }
4243 
4244 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4245                         void *val, unsigned int bytes,
4246                         struct x86_exception *exception,
4247                         const struct read_write_emulator_ops *ops)
4248 {
4249         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4250         gpa_t gpa;
4251         int rc;
4252 
4253         if (ops->read_write_prepare &&
4254                   ops->read_write_prepare(vcpu, val, bytes))
4255                 return X86EMUL_CONTINUE;
4256 
4257         vcpu->mmio_nr_fragments = 0;
4258 
4259         /* Crossing a page boundary? */
4260         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4261                 int now;
4262 
4263                 now = -addr & ~PAGE_MASK;
4264                 rc = emulator_read_write_onepage(addr, val, now, exception,
4265                                                  vcpu, ops);
4266 
4267                 if (rc != X86EMUL_CONTINUE)
4268                         return rc;
4269                 addr += now;
4270                 val += now;
4271                 bytes -= now;
4272         }
4273 
4274         rc = emulator_read_write_onepage(addr, val, bytes, exception,
4275                                          vcpu, ops);
4276         if (rc != X86EMUL_CONTINUE)
4277                 return rc;
4278 
4279         if (!vcpu->mmio_nr_fragments)
4280                 return rc;
4281 
4282         gpa = vcpu->mmio_fragments[0].gpa;
4283 
4284         vcpu->mmio_needed = 1;
4285         vcpu->mmio_cur_fragment = 0;
4286 
4287         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4288         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4289         vcpu->run->exit_reason = KVM_EXIT_MMIO;
4290         vcpu->run->mmio.phys_addr = gpa;
4291 
4292         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4293 }
4294 
4295 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4296                                   unsigned long addr,
4297                                   void *val,
4298                                   unsigned int bytes,
4299                                   struct x86_exception *exception)
4300 {
4301         return emulator_read_write(ctxt, addr, val, bytes,
4302                                    exception, &read_emultor);
4303 }
4304 
4305 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4306                             unsigned long addr,
4307                             const void *val,
4308                             unsigned int bytes,
4309                             struct x86_exception *exception)
4310 {
4311         return emulator_read_write(ctxt, addr, (void *)val, bytes,
4312                                    exception, &write_emultor);
4313 }
4314 
4315 #define CMPXCHG_TYPE(t, ptr, old, new) \
4316         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4317 
4318 #ifdef CONFIG_X86_64
4319 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4320 #else
4321 #  define CMPXCHG64(ptr, old, new) \
4322         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4323 #endif
4324 
4325 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4326                                      unsigned long addr,
4327                                      const void *old,
4328                                      const void *new,
4329                                      unsigned int bytes,
4330                                      struct x86_exception *exception)
4331 {
4332         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4333         gpa_t gpa;
4334         struct page *page;
4335         char *kaddr;
4336         bool exchanged;
4337 
4338         /* guests cmpxchg8b have to be emulated atomically */
4339         if (bytes > 8 || (bytes & (bytes - 1)))
4340                 goto emul_write;
4341 
4342         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4343 
4344         if (gpa == UNMAPPED_GVA ||
4345             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4346                 goto emul_write;
4347 
4348         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4349                 goto emul_write;
4350 
4351         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4352         if (is_error_page(page))
4353                 goto emul_write;
4354 
4355         kaddr = kmap_atomic(page);
4356         kaddr += offset_in_page(gpa);
4357         switch (bytes) {
4358         case 1:
4359                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4360                 break;
4361         case 2:
4362                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4363                 break;
4364         case 4:
4365                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4366                 break;
4367         case 8:
4368                 exchanged = CMPXCHG64(kaddr, old, new);
4369                 break;
4370         default:
4371                 BUG();
4372         }
4373         kunmap_atomic(kaddr);
4374         kvm_release_page_dirty(page);
4375 
4376         if (!exchanged)
4377                 return X86EMUL_CMPXCHG_FAILED;
4378 
4379         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4380 
4381         return X86EMUL_CONTINUE;
4382 
4383 emul_write:
4384         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4385 
4386         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4387 }
4388 
4389 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4390 {
4391         /* TODO: String I/O for in kernel device */
4392         int r;
4393 
4394         if (vcpu->arch.pio.in)
4395                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4396                                     vcpu->arch.pio.size, pd);
4397         else
4398                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4399                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4400                                      pd);
4401         return r;
4402 }
4403 
4404 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4405                                unsigned short port, void *val,
4406                                unsigned int count, bool in)
4407 {
4408         trace_kvm_pio(!in, port, size, count);
4409 
4410         vcpu->arch.pio.port = port;
4411         vcpu->arch.pio.in = in;
4412         vcpu->arch.pio.count  = count;
4413         vcpu->arch.pio.size = size;
4414 
4415         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4416                 vcpu->arch.pio.count = 0;
4417                 return 1;
4418         }
4419 
4420         vcpu->run->exit_reason = KVM_EXIT_IO;
4421         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4422         vcpu->run->io.size = size;
4423         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4424         vcpu->run->io.count = count;
4425         vcpu->run->io.port = port;
4426 
4427         return 0;
4428 }
4429 
4430 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4431                                     int size, unsigned short port, void *val,
4432                                     unsigned int count)
4433 {
4434         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4435         int ret;
4436 
4437         if (vcpu->arch.pio.count)
4438                 goto data_avail;
4439 
4440         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4441         if (ret) {
4442 data_avail:
4443                 memcpy(val, vcpu->arch.pio_data, size * count);
4444                 vcpu->arch.pio.count = 0;
4445                 return 1;
4446         }
4447 
4448         return 0;
4449 }
4450 
4451 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4452                                      int size, unsigned short port,
4453                                      const void *val, unsigned int count)
4454 {
4455         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4456 
4457         memcpy(vcpu->arch.pio_data, val, size * count);
4458         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4459 }
4460 
4461 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4462 {
4463         return kvm_x86_ops->get_segment_base(vcpu, seg);
4464 }
4465 
4466 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4467 {
4468         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4469 }
4470 
4471 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4472 {
4473         if (!need_emulate_wbinvd(vcpu))
4474                 return X86EMUL_CONTINUE;
4475 
4476         if (kvm_x86_ops->has_wbinvd_exit()) {
4477                 int cpu = get_cpu();
4478 
4479                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4480                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4481                                 wbinvd_ipi, NULL, 1);
4482                 put_cpu();
4483                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4484         } else
4485                 wbinvd();
4486         return X86EMUL_CONTINUE;
4487 }
4488 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4489 
4490 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4491 {
4492         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4493 }
4494 
4495 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4496 {
4497         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4498 }
4499 
4500 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4501 {
4502 
4503         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4504 }
4505 
4506 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4507 {
4508         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4509 }
4510 
4511 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4512 {
4513         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4514         unsigned long value;
4515 
4516         switch (cr) {
4517         case 0:
4518                 value = kvm_read_cr0(vcpu);
4519                 break;
4520         case 2:
4521                 value = vcpu->arch.cr2;
4522                 break;
4523         case 3:
4524                 value = kvm_read_cr3(vcpu);
4525                 break;
4526         case 4:
4527                 value = kvm_read_cr4(vcpu);
4528                 break;
4529         case 8:
4530                 value = kvm_get_cr8(vcpu);
4531                 break;
4532         default:
4533                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4534                 return 0;
4535         }
4536 
4537         return value;
4538 }
4539 
4540 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4541 {
4542         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4543         int res = 0;
4544 
4545         switch (cr) {
4546         case 0:
4547                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4548                 break;
4549         case 2:
4550                 vcpu->arch.cr2 = val;
4551                 break;
4552         case 3:
4553                 res = kvm_set_cr3(vcpu, val);
4554                 break;
4555         case 4:
4556                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4557                 break;
4558         case 8:
4559                 res = kvm_set_cr8(vcpu, val);
4560                 break;
4561         default:
4562                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4563                 res = -1;
4564         }
4565 
4566         return res;
4567 }
4568 
4569 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4570 {
4571         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4572 }
4573 
4574 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4575 {
4576         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4577 }
4578 
4579 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4580 {
4581         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4582 }
4583 
4584 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4585 {
4586         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4587 }
4588 
4589 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4590 {
4591         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4592 }
4593 
4594 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4595 {
4596         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4597 }
4598 
4599 static unsigned long emulator_get_cached_segment_base(
4600         struct x86_emulate_ctxt *ctxt, int seg)
4601 {
4602         return get_segment_base(emul_to_vcpu(ctxt), seg);
4603 }
4604 
4605 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4606                                  struct desc_struct *desc, u32 *base3,
4607                                  int seg)
4608 {
4609         struct kvm_segment var;
4610 
4611         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4612         *selector = var.selector;
4613 
4614         if (var.unusable) {
4615                 memset(desc, 0, sizeof(*desc));
4616                 return false;
4617         }
4618 
4619         if (var.g)
4620                 var.limit >>= 12;
4621         set_desc_limit(desc, var.limit);
4622         set_desc_base(desc, (unsigned long)var.base);
4623 #ifdef CONFIG_X86_64
4624         if (base3)
4625                 *base3 = var.base >> 32;
4626 #endif
4627         desc->type = var.type;
4628         desc->s = var.s;
4629         desc->dpl = var.dpl;
4630         desc->p = var.present;
4631         desc->avl = var.avl;
4632         desc->l = var.l;
4633         desc->d = var.db;
4634         desc->g = var.g;
4635 
4636         return true;
4637 }
4638 
4639 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4640                                  struct desc_struct *desc, u32 base3,
4641                                  int seg)
4642 {
4643         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4644         struct kvm_segment var;
4645 
4646         var.selector = selector;
4647         var.base = get_desc_base(desc);
4648 #ifdef CONFIG_X86_64
4649         var.base |= ((u64)base3) << 32;
4650 #endif
4651         var.limit = get_desc_limit(desc);
4652         if (desc->g)
4653                 var.limit = (var.limit << 12) | 0xfff;
4654         var.type = desc->type;
4655         var.present = desc->p;
4656         var.dpl = desc->dpl;
4657         var.db = desc->d;
4658         var.s = desc->s;
4659         var.l = desc->l;
4660         var.g = desc->g;
4661         var.avl = desc->avl;
4662         var.present = desc->p;
4663         var.unusable = !var.present;
4664         var.padding = 0;
4665 
4666         kvm_set_segment(vcpu, &var, seg);
4667         return;
4668 }
4669 
4670 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4671                             u32 msr_index, u64 *pdata)
4672 {
4673         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4674 }
4675 
4676 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4677                             u32 msr_index, u64 data)
4678 {
4679         struct msr_data msr;
4680 
4681         msr.data = data;
4682         msr.index = msr_index;
4683         msr.host_initiated = false;
4684         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4685 }
4686 
4687 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4688                              u32 pmc, u64 *pdata)
4689 {
4690         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4691 }
4692 
4693 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4694 {
4695         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4696 }
4697 
4698 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4699 {
4700         preempt_disable();
4701         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4702         /*
4703          * CR0.TS may reference the host fpu state, not the guest fpu state,
4704          * so it may be clear at this point.
4705          */
4706         clts();
4707 }
4708 
4709 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4710 {
4711         preempt_enable();
4712 }
4713 
4714 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4715                               struct x86_instruction_info *info,
4716                               enum x86_intercept_stage stage)
4717 {
4718         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4719 }
4720 
4721 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4722                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4723 {
4724         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4725 }
4726 
4727 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4728 {
4729         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4730 }
4731 
4732 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4733 {
4734         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4735 }
4736 
4737 static const struct x86_emulate_ops emulate_ops = {
4738         .read_gpr            = emulator_read_gpr,
4739         .write_gpr           = emulator_write_gpr,
4740         .read_std            = kvm_read_guest_virt_system,
4741         .write_std           = kvm_write_guest_virt_system,
4742         .fetch               = kvm_fetch_guest_virt,
4743         .read_emulated       = emulator_read_emulated,
4744         .write_emulated      = emulator_write_emulated,
4745         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4746         .invlpg              = emulator_invlpg,
4747         .pio_in_emulated     = emulator_pio_in_emulated,
4748         .pio_out_emulated    = emulator_pio_out_emulated,
4749         .get_segment         = emulator_get_segment,
4750         .set_segment         = emulator_set_segment,
4751         .get_cached_segment_base = emulator_get_cached_segment_base,
4752         .get_gdt             = emulator_get_gdt,
4753         .get_idt             = emulator_get_idt,
4754         .set_gdt             = emulator_set_gdt,
4755         .set_idt             = emulator_set_idt,
4756         .get_cr              = emulator_get_cr,
4757         .set_cr              = emulator_set_cr,
4758         .set_rflags          = emulator_set_rflags,
4759         .cpl                 = emulator_get_cpl,
4760         .get_dr              = emulator_get_dr,
4761         .set_dr              = emulator_set_dr,
4762         .set_msr             = emulator_set_msr,
4763         .get_msr             = emulator_get_msr,
4764         .read_pmc            = emulator_read_pmc,
4765         .halt                = emulator_halt,
4766         .wbinvd              = emulator_wbinvd,
4767         .fix_hypercall       = emulator_fix_hypercall,
4768         .get_fpu             = emulator_get_fpu,
4769         .put_fpu             = emulator_put_fpu,
4770         .intercept           = emulator_intercept,
4771         .get_cpuid           = emulator_get_cpuid,
4772 };
4773 
4774 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4775 {
4776         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4777         /*
4778          * an sti; sti; sequence only disable interrupts for the first
4779          * instruction. So, if the last instruction, be it emulated or
4780          * not, left the system with the INT_STI flag enabled, it
4781          * means that the last instruction is an sti. We should not
4782          * leave the flag on in this case. The same goes for mov ss
4783          */
4784         if (!(int_shadow & mask))
4785                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4786 }
4787 
4788 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4789 {
4790         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4791         if (ctxt->exception.vector == PF_VECTOR)
4792                 kvm_propagate_fault(vcpu, &ctxt->exception);
4793         else if (ctxt->exception.error_code_valid)
4794                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4795                                       ctxt->exception.error_code);
4796         else
4797                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4798 }
4799 
4800 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4801 {
4802         memset(&ctxt->opcode_len, 0,
4803                (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4804 
4805         ctxt->fetch.start = 0;
4806         ctxt->fetch.end = 0;
4807         ctxt->io_read.pos = 0;
4808         ctxt->io_read.end = 0;
4809         ctxt->mem_read.pos = 0;
4810         ctxt->mem_read.end = 0;
4811 }
4812 
4813 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4814 {
4815         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4816         int cs_db, cs_l;
4817 
4818         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4819 
4820         ctxt->eflags = kvm_get_rflags(vcpu);
4821         ctxt->eip = kvm_rip_read(vcpu);
4822         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4823                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4824                      cs_l                               ? X86EMUL_MODE_PROT64 :
4825                      cs_db                              ? X86EMUL_MODE_PROT32 :
4826                                                           X86EMUL_MODE_PROT16;
4827         ctxt->guest_mode = is_guest_mode(vcpu);
4828 
4829         init_decode_cache(ctxt);
4830         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4831 }
4832 
4833 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4834 {
4835         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4836         int ret;
4837 
4838         init_emulate_ctxt(vcpu);
4839 
4840         ctxt->op_bytes = 2;
4841         ctxt->ad_bytes = 2;
4842         ctxt->_eip = ctxt->eip + inc_eip;
4843         ret = emulate_int_real(ctxt, irq);
4844 
4845         if (ret != X86EMUL_CONTINUE)
4846                 return EMULATE_FAIL;
4847 
4848         ctxt->eip = ctxt->_eip;
4849         kvm_rip_write(vcpu, ctxt->eip);
4850         kvm_set_rflags(vcpu, ctxt->eflags);
4851 
4852         if (irq == NMI_VECTOR)
4853                 vcpu->arch.nmi_pending = 0;
4854         else
4855                 vcpu->arch.interrupt.pending = false;
4856 
4857         return EMULATE_DONE;
4858 }
4859 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4860 
4861 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4862 {
4863         int r = EMULATE_DONE;
4864 
4865         ++vcpu->stat.insn_emulation_fail;
4866         trace_kvm_emulate_insn_failed(vcpu);
4867         if (!is_guest_mode(vcpu)) {
4868                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4869                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4870                 vcpu->run->internal.ndata = 0;
4871                 r = EMULATE_FAIL;
4872         }
4873         kvm_queue_exception(vcpu, UD_VECTOR);
4874 
4875         return r;
4876 }
4877 
4878 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4879                                   bool write_fault_to_shadow_pgtable,
4880                                   int emulation_type)
4881 {
4882         gpa_t gpa = cr2;
4883         pfn_t pfn;
4884 
4885         if (emulation_type & EMULTYPE_NO_REEXECUTE)
4886                 return false;
4887 
4888         if (!vcpu->arch.mmu.direct_map) {
4889                 /*
4890                  * Write permission should be allowed since only
4891                  * write access need to be emulated.
4892                  */
4893                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4894 
4895                 /*
4896                  * If the mapping is invalid in guest, let cpu retry
4897                  * it to generate fault.
4898                  */
4899                 if (gpa == UNMAPPED_GVA)
4900                         return true;
4901         }
4902 
4903         /*
4904          * Do not retry the unhandleable instruction if it faults on the
4905          * readonly host memory, otherwise it will goto a infinite loop:
4906          * retry instruction -> write #PF -> emulation fail -> retry
4907          * instruction -> ...
4908          */
4909         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4910 
4911         /*
4912          * If the instruction failed on the error pfn, it can not be fixed,
4913          * report the error to userspace.
4914          */
4915         if (is_error_noslot_pfn(pfn))
4916                 return false;
4917 
4918         kvm_release_pfn_clean(pfn);
4919 
4920         /* The instructions are well-emulated on direct mmu. */
4921         if (vcpu->arch.mmu.direct_map) {
4922                 unsigned int indirect_shadow_pages;
4923 
4924                 spin_lock(&vcpu->kvm->mmu_lock);
4925                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4926                 spin_unlock(&vcpu->kvm->mmu_lock);
4927 
4928                 if (indirect_shadow_pages)
4929                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4930 
4931                 return true;
4932         }
4933 
4934         /*
4935          * if emulation was due to access to shadowed page table
4936          * and it failed try to unshadow page and re-enter the
4937          * guest to let CPU execute the instruction.
4938          */
4939         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4940 
4941         /*
4942          * If the access faults on its page table, it can not
4943          * be fixed by unprotecting shadow page and it should
4944          * be reported to userspace.
4945          */
4946         return !write_fault_to_shadow_pgtable;
4947 }
4948 
4949 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4950                               unsigned long cr2,  int emulation_type)
4951 {
4952         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4953         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4954 
4955         last_retry_eip = vcpu->arch.last_retry_eip;
4956         last_retry_addr = vcpu->arch.last_retry_addr;
4957 
4958         /*
4959          * If the emulation is caused by #PF and it is non-page_table
4960          * writing instruction, it means the VM-EXIT is caused by shadow
4961          * page protected, we can zap the shadow page and retry this
4962          * instruction directly.
4963          *
4964          * Note: if the guest uses a non-page-table modifying instruction
4965          * on the PDE that points to the instruction, then we will unmap
4966          * the instruction and go to an infinite loop. So, we cache the
4967          * last retried eip and the last fault address, if we meet the eip
4968          * and the address again, we can break out of the potential infinite
4969          * loop.
4970          */
4971         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4972 
4973         if (!(emulation_type & EMULTYPE_RETRY))
4974                 return false;
4975 
4976         if (x86_page_table_writing_insn(ctxt))
4977                 return false;
4978 
4979         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4980                 return false;
4981 
4982         vcpu->arch.last_retry_eip = ctxt->eip;
4983         vcpu->arch.last_retry_addr = cr2;
4984 
4985         if (!vcpu->arch.mmu.direct_map)
4986                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4987 
4988         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4989 
4990         return true;
4991 }
4992 
4993 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4994 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4995 
4996 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4997                                 unsigned long *db)
4998 {
4999         u32 dr6 = 0;
5000         int i;
5001         u32 enable, rwlen;
5002 
5003         enable = dr7;
5004         rwlen = dr7 >> 16;
5005         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5006                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5007                         dr6 |= (1 << i);
5008         return dr6;
5009 }
5010 
5011 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5012 {
5013         struct kvm_run *kvm_run = vcpu->run;
5014 
5015         /*
5016          * Use the "raw" value to see if TF was passed to the processor.
5017          * Note that the new value of the flags has not been saved yet.
5018          *
5019          * This is correct even for TF set by the guest, because "the
5020          * processor will not generate this exception after the instruction
5021          * that sets the TF flag".
5022          */
5023         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5024 
5025         if (unlikely(rflags & X86_EFLAGS_TF)) {
5026                 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5027                         kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5028                         kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5029                         kvm_run->debug.arch.exception = DB_VECTOR;
5030                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5031                         *r = EMULATE_USER_EXIT;
5032                 } else {
5033                         vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5034                         /*
5035                          * "Certain debug exceptions may clear bit 0-3.  The
5036                          * remaining contents of the DR6 register are never
5037                          * cleared by the processor".
5038                          */
5039                         vcpu->arch.dr6 &= ~15;
5040                         vcpu->arch.dr6 |= DR6_BS;
5041                         kvm_queue_exception(vcpu, DB_VECTOR);
5042                 }
5043         }
5044 }
5045 
5046 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5047 {
5048         struct kvm_run *kvm_run = vcpu->run;
5049         unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5050         u32 dr6 = 0;
5051 
5052         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5053             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5054                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5055                                            vcpu->arch.guest_debug_dr7,
5056                                            vcpu->arch.eff_db);
5057 
5058                 if (dr6 != 0) {
5059                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5060                         kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5061                                 get_segment_base(vcpu, VCPU_SREG_CS);
5062 
5063                         kvm_run->debug.arch.exception = DB_VECTOR;
5064                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5065                         *r = EMULATE_USER_EXIT;
5066                         return true;
5067                 }
5068         }
5069 
5070         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5071                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5072                                            vcpu->arch.dr7,
5073                                            vcpu->arch.db);
5074 
5075                 if (dr6 != 0) {
5076                         vcpu->arch.dr6 &= ~15;
5077                         vcpu->arch.dr6 |= dr6;
5078                         kvm_queue_exception(vcpu, DB_VECTOR);
5079                         *r = EMULATE_DONE;
5080                         return true;
5081                 }
5082         }
5083 
5084         return false;
5085 }
5086 
5087 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5088                             unsigned long cr2,
5089                             int emulation_type,
5090                             void *insn,
5091                             int insn_len)
5092 {
5093         int r;
5094         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5095         bool writeback = true;
5096         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5097 
5098         /*
5099          * Clear write_fault_to_shadow_pgtable here to ensure it is
5100          * never reused.
5101          */
5102         vcpu->arch.write_fault_to_shadow_pgtable = false;
5103         kvm_clear_exception_queue(vcpu);
5104 
5105         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5106                 init_emulate_ctxt(vcpu);
5107 
5108                 /*
5109                  * We will reenter on the same instruction since
5110                  * we do not set complete_userspace_io.  This does not
5111                  * handle watchpoints yet, those would be handled in
5112                  * the emulate_ops.
5113                  */
5114                 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5115                         return r;
5116 
5117                 ctxt->interruptibility = 0;
5118                 ctxt->have_exception = false;
5119                 ctxt->perm_ok = false;
5120 
5121                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5122 
5123                 r = x86_decode_insn(ctxt, insn, insn_len);
5124 
5125                 trace_kvm_emulate_insn_start(vcpu);
5126                 ++vcpu->stat.insn_emulation;
5127                 if (r != EMULATION_OK)  {
5128                         if (emulation_type & EMULTYPE_TRAP_UD)
5129                                 return EMULATE_FAIL;
5130                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5131                                                 emulation_type))
5132                                 return EMULATE_DONE;
5133                         if (emulation_type & EMULTYPE_SKIP)
5134                                 return EMULATE_FAIL;
5135                         return handle_emulation_failure(vcpu);
5136                 }
5137         }
5138 
5139         if (emulation_type & EMULTYPE_SKIP) {
5140                 kvm_rip_write(vcpu, ctxt->_eip);
5141                 return EMULATE_DONE;
5142         }
5143 
5144         if (retry_instruction(ctxt, cr2, emulation_type))
5145                 return EMULATE_DONE;
5146 
5147         /* this is needed for vmware backdoor interface to work since it
5148            changes registers values  during IO operation */
5149         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5150                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5151                 emulator_invalidate_register_cache(ctxt);
5152         }
5153 
5154 restart:
5155         r = x86_emulate_insn(ctxt);
5156 
5157         if (r == EMULATION_INTERCEPTED)
5158                 return EMULATE_DONE;
5159 
5160         if (r == EMULATION_FAILED) {
5161                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5162                                         emulation_type))
5163                         return EMULATE_DONE;
5164 
5165                 return handle_emulation_failure(vcpu);
5166         }
5167 
5168         if (ctxt->have_exception) {
5169                 inject_emulated_exception(vcpu);
5170                 r = EMULATE_DONE;
5171         } else if (vcpu->arch.pio.count) {
5172                 if (!vcpu->arch.pio.in) {
5173                         /* FIXME: return into emulator if single-stepping.  */
5174                         vcpu->arch.pio.count = 0;
5175                 } else {
5176                         writeback = false;
5177                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
5178                 }
5179                 r = EMULATE_USER_EXIT;
5180         } else if (vcpu->mmio_needed) {
5181                 if (!vcpu->mmio_is_write)
5182                         writeback = false;
5183                 r = EMULATE_USER_EXIT;
5184                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5185         } else if (r == EMULATION_RESTART)
5186                 goto restart;
5187         else
5188                 r = EMULATE_DONE;
5189 
5190         if (writeback) {
5191                 toggle_interruptibility(vcpu, ctxt->interruptibility);
5192                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5193                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5194                 kvm_rip_write(vcpu, ctxt->eip);
5195                 if (r == EMULATE_DONE)
5196                         kvm_vcpu_check_singlestep(vcpu, &r);
5197                 kvm_set_rflags(vcpu, ctxt->eflags);
5198         } else
5199                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5200 
5201         return r;
5202 }
5203 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5204 
5205 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5206 {
5207         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5208         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5209                                             size, port, &val, 1);
5210         /* do not return to emulator after return from userspace */
5211         vcpu->arch.pio.count = 0;
5212         return ret;
5213 }
5214 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5215 
5216 static void tsc_bad(void *info)
5217 {
5218         __this_cpu_write(cpu_tsc_khz, 0);
5219 }
5220 
5221 static void tsc_khz_changed(void *data)
5222 {
5223         struct cpufreq_freqs *freq = data;
5224         unsigned long khz = 0;
5225 
5226         if (data)
5227                 khz = freq->new;
5228         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5229                 khz = cpufreq_quick_get(raw_smp_processor_id());
5230         if (!khz)
5231                 khz = tsc_khz;
5232         __this_cpu_write(cpu_tsc_khz, khz);
5233 }
5234 
5235 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5236                                      void *data)
5237 {
5238         struct cpufreq_freqs *freq = data;
5239         struct kvm *kvm;
5240         struct kvm_vcpu *vcpu;
5241         int i, send_ipi = 0;
5242 
5243         /*
5244          * We allow guests to temporarily run on slowing clocks,
5245          * provided we notify them after, or to run on accelerating
5246          * clocks, provided we notify them before.  Thus time never
5247          * goes backwards.
5248          *
5249          * However, we have a problem.  We can't atomically update
5250          * the frequency of a given CPU from this function; it is
5251          * merely a notifier, which can be called from any CPU.
5252          * Changing the TSC frequency at arbitrary points in time
5253          * requires a recomputation of local variables related to
5254          * the TSC for each VCPU.  We must flag these local variables
5255          * to be updated and be sure the update takes place with the
5256          * new frequency before any guests proceed.
5257          *
5258          * Unfortunately, the combination of hotplug CPU and frequency
5259          * change creates an intractable locking scenario; the order
5260          * of when these callouts happen is undefined with respect to
5261          * CPU hotplug, and they can race with each other.  As such,
5262          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5263          * undefined; you can actually have a CPU frequency change take
5264          * place in between the computation of X and the setting of the
5265          * variable.  To protect against this problem, all updates of
5266          * the per_cpu tsc_khz variable are done in an interrupt
5267          * protected IPI, and all callers wishing to update the value
5268          * must wait for a synchronous IPI to complete (which is trivial
5269          * if the caller is on the CPU already).  This establishes the
5270          * necessary total order on variable updates.
5271          *
5272          * Note that because a guest time update may take place
5273          * anytime after the setting of the VCPU's request bit, the
5274          * correct TSC value must be set before the request.  However,
5275          * to ensure the update actually makes it to any guest which
5276          * starts running in hardware virtualization between the set
5277          * and the acquisition of the spinlock, we must also ping the
5278          * CPU after setting the request bit.
5279          *
5280          */
5281 
5282         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5283                 return 0;
5284         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5285                 return 0;
5286 
5287         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5288 
5289         spin_lock(&kvm_lock);
5290         list_for_each_entry(kvm, &vm_list, vm_list) {
5291                 kvm_for_each_vcpu(i, vcpu, kvm) {
5292                         if (vcpu->cpu != freq->cpu)
5293                                 continue;
5294                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5295                         if (vcpu->cpu != smp_processor_id())
5296                                 send_ipi = 1;
5297                 }
5298         }
5299         spin_unlock(&kvm_lock);
5300 
5301         if (freq->old < freq->new && send_ipi) {
5302                 /*
5303                  * We upscale the frequency.  Must make the guest
5304                  * doesn't see old kvmclock values while running with
5305                  * the new frequency, otherwise we risk the guest sees
5306                  * time go backwards.
5307                  *
5308                  * In case we update the frequency for another cpu
5309                  * (which might be in guest context) send an interrupt
5310                  * to kick the cpu out of guest context.  Next time
5311                  * guest context is entered kvmclock will be updated,
5312                  * so the guest will not see stale values.
5313                  */
5314                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5315         }
5316         return 0;
5317 }
5318 
5319 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5320         .notifier_call  = kvmclock_cpufreq_notifier
5321 };
5322 
5323 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5324                                         unsigned long action, void *hcpu)
5325 {
5326         unsigned int cpu = (unsigned long)hcpu;
5327 
5328         switch (action) {
5329                 case CPU_ONLINE:
5330                 case CPU_DOWN_FAILED:
5331                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5332                         break;
5333                 case CPU_DOWN_PREPARE:
5334                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
5335                         break;
5336         }
5337         return NOTIFY_OK;
5338 }
5339 
5340 static struct notifier_block kvmclock_cpu_notifier_block = {
5341         .notifier_call  = kvmclock_cpu_notifier,
5342         .priority = -INT_MAX
5343 };
5344 
5345 static void kvm_timer_init(void)
5346 {
5347         int cpu;
5348 
5349         max_tsc_khz = tsc_khz;
5350         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5351         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5352 #ifdef CONFIG_CPU_FREQ
5353                 struct cpufreq_policy policy;
5354                 memset(&policy, 0, sizeof(policy));
5355                 cpu = get_cpu();
5356                 cpufreq_get_policy(&policy, cpu);
5357                 if (policy.cpuinfo.max_freq)
5358                         max_tsc_khz = policy.cpuinfo.max_freq;
5359                 put_cpu();
5360 #endif
5361                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5362                                           CPUFREQ_TRANSITION_NOTIFIER);
5363         }
5364         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5365         for_each_online_cpu(cpu)
5366                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5367 }
5368 
5369 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5370 
5371 int kvm_is_in_guest(void)
5372 {
5373         return __this_cpu_read(current_vcpu) != NULL;
5374 }
5375 
5376 static int kvm_is_user_mode(void)
5377 {
5378         int user_mode = 3;
5379 
5380         if (__this_cpu_read(current_vcpu))
5381                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5382 
5383         return user_mode != 0;
5384 }
5385 
5386 static unsigned long kvm_get_guest_ip(void)
5387 {
5388         unsigned long ip = 0;
5389 
5390         if (__this_cpu_read(current_vcpu))
5391                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5392 
5393         return ip;
5394 }
5395 
5396 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5397         .is_in_guest            = kvm_is_in_guest,
5398         .is_user_mode           = kvm_is_user_mode,
5399         .get_guest_ip           = kvm_get_guest_ip,
5400 };
5401 
5402 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5403 {
5404         __this_cpu_write(current_vcpu, vcpu);
5405 }
5406 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5407 
5408 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5409 {
5410         __this_cpu_write(current_vcpu, NULL);
5411 }
5412 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5413 
5414 static void kvm_set_mmio_spte_mask(void)
5415 {
5416         u64 mask;
5417         int maxphyaddr = boot_cpu_data.x86_phys_bits;
5418 
5419         /*
5420          * Set the reserved bits and the present bit of an paging-structure
5421          * entry to generate page fault with PFER.RSV = 1.
5422          */
5423          /* Mask the reserved physical address bits. */
5424         mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5425 
5426         /* Bit 62 is always reserved for 32bit host. */
5427         mask |= 0x3ull << 62;
5428 
5429         /* Set the present bit. */
5430         mask |= 1ull;
5431 
5432 #ifdef CONFIG_X86_64
5433         /*
5434          * If reserved bit is not supported, clear the present bit to disable
5435          * mmio page fault.
5436          */
5437         if (maxphyaddr == 52)
5438                 mask &= ~1ull;
5439 #endif
5440 
5441         kvm_mmu_set_mmio_spte_mask(mask);
5442 }
5443 
5444 #ifdef CONFIG_X86_64
5445 static void pvclock_gtod_update_fn(struct work_struct *work)
5446 {
5447         struct kvm *kvm;
5448 
5449         struct kvm_vcpu *vcpu;
5450         int i;
5451 
5452         spin_lock(&kvm_lock);
5453         list_for_each_entry(kvm, &vm_list, vm_list)
5454                 kvm_for_each_vcpu(i, vcpu, kvm)
5455                         set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5456         atomic_set(&kvm_guest_has_master_clock, 0);
5457         spin_unlock(&kvm_lock);
5458 }
5459 
5460 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5461 
5462 /*
5463  * Notification about pvclock gtod data update.
5464  */
5465 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5466                                void *priv)
5467 {
5468         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5469         struct timekeeper *tk = priv;
5470 
5471         update_pvclock_gtod(tk);
5472 
5473         /* disable master clock if host does not trust, or does not
5474          * use, TSC clocksource
5475          */
5476         if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5477             atomic_read(&kvm_guest_has_master_clock) != 0)
5478                 queue_work(system_long_wq, &pvclock_gtod_work);
5479 
5480         return 0;
5481 }
5482 
5483 static struct notifier_block pvclock_gtod_notifier = {
5484         .notifier_call = pvclock_gtod_notify,
5485 };
5486 #endif
5487 
5488 int kvm_arch_init(void *opaque)
5489 {
5490         int r;
5491         struct kvm_x86_ops *ops = opaque;
5492 
5493         if (kvm_x86_ops) {
5494                 printk(KERN_ERR "kvm: already loaded the other module\n");
5495                 r = -EEXIST;
5496                 goto out;
5497         }
5498 
5499         if (!ops->cpu_has_kvm_support()) {
5500                 printk(KERN_ERR "kvm: no hardware support\n");
5501                 r = -EOPNOTSUPP;
5502                 goto out;
5503         }
5504         if (ops->disabled_by_bios()) {
5505                 printk(KERN_ERR "kvm: disabled by bios\n");
5506                 r = -EOPNOTSUPP;
5507                 goto out;
5508         }
5509 
5510         r = -ENOMEM;
5511         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5512         if (!shared_msrs) {
5513                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5514                 goto out;
5515         }
5516 
5517         r = kvm_mmu_module_init();
5518         if (r)
5519                 goto out_free_percpu;
5520 
5521         kvm_set_mmio_spte_mask();
5522         kvm_init_msr_list();
5523 
5524         kvm_x86_ops = ops;
5525         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5526                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
5527 
5528         kvm_timer_init();
5529 
5530         perf_register_guest_info_callbacks(&kvm_guest_cbs);
5531 
5532         if (cpu_has_xsave)
5533                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5534 
5535         kvm_lapic_init();
5536 #ifdef CONFIG_X86_64
5537         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5538 #endif
5539 
5540         return 0;
5541 
5542 out_free_percpu:
5543         free_percpu(shared_msrs);
5544 out:
5545         return r;
5546 }
5547 
5548 void kvm_arch_exit(void)
5549 {
5550         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5551 
5552         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5553                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5554                                             CPUFREQ_TRANSITION_NOTIFIER);
5555         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5556 #ifdef CONFIG_X86_64
5557         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5558 #endif
5559         kvm_x86_ops = NULL;
5560         kvm_mmu_module_exit();
5561         free_percpu(shared_msrs);
5562 }
5563 
5564 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5565 {
5566         ++vcpu->stat.halt_exits;
5567         if (irqchip_in_kernel(vcpu->kvm)) {
5568                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5569                 return 1;
5570         } else {
5571                 vcpu->run->exit_reason = KVM_EXIT_HLT;
5572                 return 0;
5573         }
5574 }
5575 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5576 
5577 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5578 {
5579         u64 param, ingpa, outgpa, ret;
5580         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5581         bool fast, longmode;
5582         int cs_db, cs_l;
5583 
5584         /*
5585          * hypercall generates UD from non zero cpl and real mode
5586          * per HYPER-V spec
5587          */
5588         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5589                 kvm_queue_exception(vcpu, UD_VECTOR);
5590                 return 0;
5591         }
5592 
5593         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5594         longmode = is_long_mode(vcpu) && cs_l == 1;
5595 
5596         if (!longmode) {
5597                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5598                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5599                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5600                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5601                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5602                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5603         }
5604 #ifdef CONFIG_X86_64
5605         else {
5606                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5607                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5608                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5609         }
5610 #endif
5611 
5612         code = param & 0xffff;
5613         fast = (param >> 16) & 0x1;
5614         rep_cnt = (param >> 32) & 0xfff;
5615         rep_idx = (param >> 48) & 0xfff;
5616 
5617         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5618 
5619         switch (code) {
5620         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5621                 kvm_vcpu_on_spin(vcpu);
5622                 break;
5623         default:
5624                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5625                 break;
5626         }
5627 
5628         ret = res | (((u64)rep_done & 0xfff) << 32);
5629         if (longmode) {
5630                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5631         } else {
5632                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5633                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5634         }
5635 
5636         return 1;
5637 }
5638 
5639 /*
5640  * kvm_pv_kick_cpu_op:  Kick a vcpu.
5641  *
5642  * @apicid - apicid of vcpu to be kicked.
5643  */
5644 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5645 {
5646         struct kvm_lapic_irq lapic_irq;
5647 
5648         lapic_irq.shorthand = 0;
5649         lapic_irq.dest_mode = 0;
5650         lapic_irq.dest_id = apicid;
5651 
5652         lapic_irq.delivery_mode = APIC_DM_REMRD;
5653         kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5654 }
5655 
5656 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5657 {
5658         unsigned long nr, a0, a1, a2, a3, ret;
5659         int r = 1;
5660 
5661         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5662                 return kvm_hv_hypercall(vcpu);
5663 
5664         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5665         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5666         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5667         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5668         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5669 
5670         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5671 
5672         if (!is_long_mode(vcpu)) {
5673                 nr &= 0xFFFFFFFF;
5674                 a0 &= 0xFFFFFFFF;
5675                 a1 &= 0xFFFFFFFF;
5676                 a2 &= 0xFFFFFFFF;
5677                 a3 &= 0xFFFFFFFF;
5678         }
5679 
5680         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5681                 ret = -KVM_EPERM;
5682                 goto out;
5683         }
5684 
5685         switch (nr) {
5686         case KVM_HC_VAPIC_POLL_IRQ:
5687                 ret = 0;
5688                 break;
5689         case KVM_HC_KICK_CPU:
5690                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5691                 ret = 0;
5692                 break;
5693         default:
5694                 ret = -KVM_ENOSYS;
5695                 break;
5696         }
5697 out:
5698         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5699         ++vcpu->stat.hypercalls;
5700         return r;
5701 }
5702 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5703 
5704 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5705 {
5706         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5707         char instruction[3];
5708         unsigned long rip = kvm_rip_read(vcpu);
5709 
5710         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5711 
5712         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5713 }
5714 
5715 /*
5716  * Check if userspace requested an interrupt window, and that the
5717  * interrupt window is open.
5718  *
5719  * No need to exit to userspace if we already have an interrupt queued.
5720  */
5721 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5722 {
5723         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5724                 vcpu->run->request_interrupt_window &&
5725                 kvm_arch_interrupt_allowed(vcpu));
5726 }
5727 
5728 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5729 {
5730         struct kvm_run *kvm_run = vcpu->run;
5731 
5732         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5733         kvm_run->cr8 = kvm_get_cr8(vcpu);
5734         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5735         if (irqchip_in_kernel(vcpu->kvm))
5736                 kvm_run->ready_for_interrupt_injection = 1;
5737         else
5738                 kvm_run->ready_for_interrupt_injection =
5739                         kvm_arch_interrupt_allowed(vcpu) &&
5740                         !kvm_cpu_has_interrupt(vcpu) &&
5741                         !kvm_event_needs_reinjection(vcpu);
5742 }
5743 
5744 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5745 {
5746         int max_irr, tpr;
5747 
5748         if (!kvm_x86_ops->update_cr8_intercept)
5749                 return;
5750 
5751         if (!vcpu->arch.apic)
5752                 return;
5753 
5754         if (!vcpu->arch.apic->vapic_addr)
5755                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5756         else
5757                 max_irr = -1;
5758 
5759         if (max_irr != -1)
5760                 max_irr >>= 4;
5761 
5762         tpr = kvm_lapic_get_cr8(vcpu);
5763 
5764         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5765 }
5766 
5767 static void inject_pending_event(struct kvm_vcpu *vcpu)
5768 {
5769         /* try to reinject previous events if any */
5770         if (vcpu->arch.exception.pending) {
5771                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5772                                         vcpu->arch.exception.has_error_code,
5773                                         vcpu->arch.exception.error_code);
5774                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5775                                           vcpu->arch.exception.has_error_code,
5776                                           vcpu->arch.exception.error_code,
5777                                           vcpu->arch.exception.reinject);
5778                 return;
5779         }
5780 
5781         if (vcpu->arch.nmi_injected) {
5782                 kvm_x86_ops->set_nmi(vcpu);
5783                 return;
5784         }
5785 
5786         if (vcpu->arch.interrupt.pending) {
5787                 kvm_x86_ops->set_irq(vcpu);
5788                 return;
5789         }
5790 
5791         /* try to inject new event if pending */
5792         if (vcpu->arch.nmi_pending) {
5793                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5794                         --vcpu->arch.nmi_pending;
5795                         vcpu->arch.nmi_injected = true;
5796                         kvm_x86_ops->set_nmi(vcpu);
5797                 }
5798         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5799                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5800                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5801                                             false);
5802                         kvm_x86_ops->set_irq(vcpu);
5803                 }
5804         }
5805 }
5806 
5807 static void process_nmi(struct kvm_vcpu *vcpu)
5808 {
5809         unsigned limit = 2;
5810 
5811         /*
5812          * x86 is limited to one NMI running, and one NMI pending after it.
5813          * If an NMI is already in progress, limit further NMIs to just one.
5814          * Otherwise, allow two (and we'll inject the first one immediately).
5815          */
5816         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5817                 limit = 1;
5818 
5819         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5820         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5821         kvm_make_request(KVM_REQ_EVENT, vcpu);
5822 }
5823 
5824 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5825 {
5826         u64 eoi_exit_bitmap[4];
5827         u32 tmr[8];
5828 
5829         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5830                 return;
5831 
5832         memset(eoi_exit_bitmap, 0, 32);
5833         memset(tmr, 0, 32);
5834 
5835         kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5836         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5837         kvm_apic_update_tmr(vcpu, tmr);
5838 }
5839 
5840 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5841 {
5842         int r;
5843         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5844                 vcpu->run->request_interrupt_window;
5845         bool req_immediate_exit = false;
5846 
5847         if (vcpu->requests) {
5848                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5849                         kvm_mmu_unload(vcpu);
5850                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5851                         __kvm_migrate_timers(vcpu);
5852                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5853                         kvm_gen_update_masterclock(vcpu->kvm);
5854                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5855                         kvm_gen_kvmclock_update(vcpu);
5856                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5857                         r = kvm_guest_time_update(vcpu);
5858                         if (unlikely(r))
5859                                 goto out;
5860                 }
5861                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5862                         kvm_mmu_sync_roots(vcpu);
5863                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5864                         kvm_x86_ops->tlb_flush(vcpu);
5865                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5866                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5867                         r = 0;
5868                         goto out;
5869                 }
5870                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5871                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5872                         r = 0;
5873                         goto out;
5874                 }
5875                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5876                         vcpu->fpu_active = 0;
5877                         kvm_x86_ops->fpu_deactivate(vcpu);
5878                 }
5879                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5880                         /* Page is swapped out. Do synthetic halt */
5881                         vcpu->arch.apf.halted = true;
5882                         r = 1;
5883                         goto out;
5884                 }
5885                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5886                         record_steal_time(vcpu);
5887                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5888                         process_nmi(vcpu);
5889                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5890                         kvm_handle_pmu_event(vcpu);
5891                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5892                         kvm_deliver_pmi(vcpu);
5893                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5894                         vcpu_scan_ioapic(vcpu);
5895         }
5896 
5897         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5898                 kvm_apic_accept_events(vcpu);
5899                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5900                         r = 1;
5901                         goto out;
5902                 }
5903 
5904                 inject_pending_event(vcpu);
5905 
5906                 /* enable NMI/IRQ window open exits if needed */
5907                 if (vcpu->arch.nmi_pending)
5908                         req_immediate_exit =
5909                                 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5910                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5911                         req_immediate_exit =
5912                                 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5913 
5914                 if (kvm_lapic_enabled(vcpu)) {
5915                         /*
5916                          * Update architecture specific hints for APIC
5917                          * virtual interrupt delivery.
5918                          */
5919                         if (kvm_x86_ops->hwapic_irr_update)
5920                                 kvm_x86_ops->hwapic_irr_update(vcpu,
5921                                         kvm_lapic_find_highest_irr(vcpu));
5922                         update_cr8_intercept(vcpu);
5923                         kvm_lapic_sync_to_vapic(vcpu);
5924                 }
5925         }
5926 
5927         r = kvm_mmu_reload(vcpu);
5928         if (unlikely(r)) {
5929                 goto cancel_injection;
5930         }
5931 
5932         preempt_disable();
5933 
5934         kvm_x86_ops-