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TOMOYO Linux Cross Reference
Linux/arch/x86/lguest/boot.c

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  1 /*P:010
  2  * A hypervisor allows multiple Operating Systems to run on a single machine.
  3  * To quote David Wheeler: "Any problem in computer science can be solved with
  4  * another layer of indirection."
  5  *
  6  * We keep things simple in two ways.  First, we start with a normal Linux
  7  * kernel and insert a module (lg.ko) which allows us to run other Linux
  8  * kernels the same way we'd run processes.  We call the first kernel the Host,
  9  * and the others the Guests.  The program which sets up and configures Guests
 10  * (such as the example in tools/lguest/lguest.c) is called the Launcher.
 11  *
 12  * Secondly, we only run specially modified Guests, not normal kernels: setting
 13  * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows
 14  * how to be a Guest at boot time.  This means that you can use the same kernel
 15  * you boot normally (ie. as a Host) as a Guest.
 16  *
 17  * These Guests know that they cannot do privileged operations, such as disable
 18  * interrupts, and that they have to ask the Host to do such things explicitly.
 19  * This file consists of all the replacements for such low-level native
 20  * hardware operations: these special Guest versions call the Host.
 21  *
 22  * So how does the kernel know it's a Guest?  We'll see that later, but let's
 23  * just say that we end up here where we replace the native functions various
 24  * "paravirt" structures with our Guest versions, then boot like normal.
 25 :*/
 26 
 27 /*
 28  * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation.
 29  *
 30  * This program is free software; you can redistribute it and/or modify
 31  * it under the terms of the GNU General Public License as published by
 32  * the Free Software Foundation; either version 2 of the License, or
 33  * (at your option) any later version.
 34  *
 35  * This program is distributed in the hope that it will be useful, but
 36  * WITHOUT ANY WARRANTY; without even the implied warranty of
 37  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 38  * NON INFRINGEMENT.  See the GNU General Public License for more
 39  * details.
 40  *
 41  * You should have received a copy of the GNU General Public License
 42  * along with this program; if not, write to the Free Software
 43  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 44  */
 45 #include <linux/kernel.h>
 46 #include <linux/start_kernel.h>
 47 #include <linux/string.h>
 48 #include <linux/console.h>
 49 #include <linux/screen_info.h>
 50 #include <linux/irq.h>
 51 #include <linux/interrupt.h>
 52 #include <linux/clocksource.h>
 53 #include <linux/clockchips.h>
 54 #include <linux/lguest.h>
 55 #include <linux/lguest_launcher.h>
 56 #include <linux/virtio_console.h>
 57 #include <linux/pm.h>
 58 #include <linux/export.h>
 59 #include <linux/pci.h>
 60 #include <linux/virtio_pci.h>
 61 #include <asm/acpi.h>
 62 #include <asm/apic.h>
 63 #include <asm/lguest.h>
 64 #include <asm/paravirt.h>
 65 #include <asm/param.h>
 66 #include <asm/page.h>
 67 #include <asm/pgtable.h>
 68 #include <asm/desc.h>
 69 #include <asm/setup.h>
 70 #include <asm/e820.h>
 71 #include <asm/mce.h>
 72 #include <asm/io.h>
 73 #include <asm/fpu/api.h>
 74 #include <asm/stackprotector.h>
 75 #include <asm/reboot.h>         /* for struct machine_ops */
 76 #include <asm/kvm_para.h>
 77 #include <asm/pci_x86.h>
 78 #include <asm/pci-direct.h>
 79 
 80 /*G:010
 81  * Welcome to the Guest!
 82  *
 83  * The Guest in our tale is a simple creature: identical to the Host but
 84  * behaving in simplified but equivalent ways.  In particular, the Guest is the
 85  * same kernel as the Host (or at least, built from the same source code).
 86 :*/
 87 
 88 struct lguest_data lguest_data = {
 89         .hcall_status = { [0 ... LHCALL_RING_SIZE-1] = 0xFF },
 90         .noirq_iret = (u32)lguest_noirq_iret,
 91         .kernel_address = PAGE_OFFSET,
 92         .blocked_interrupts = { 1 }, /* Block timer interrupts */
 93         .syscall_vec = IA32_SYSCALL_VECTOR,
 94 };
 95 
 96 /*G:037
 97  * async_hcall() is pretty simple: I'm quite proud of it really.  We have a
 98  * ring buffer of stored hypercalls which the Host will run though next time we
 99  * do a normal hypercall.  Each entry in the ring has 5 slots for the hypercall
100  * arguments, and a "hcall_status" word which is 0 if the call is ready to go,
101  * and 255 once the Host has finished with it.
102  *
103  * If we come around to a slot which hasn't been finished, then the table is
104  * full and we just make the hypercall directly.  This has the nice side
105  * effect of causing the Host to run all the stored calls in the ring buffer
106  * which empties it for next time!
107  */
108 static void async_hcall(unsigned long call, unsigned long arg1,
109                         unsigned long arg2, unsigned long arg3,
110                         unsigned long arg4)
111 {
112         /* Note: This code assumes we're uniprocessor. */
113         static unsigned int next_call;
114         unsigned long flags;
115 
116         /*
117          * Disable interrupts if not already disabled: we don't want an
118          * interrupt handler making a hypercall while we're already doing
119          * one!
120          */
121         local_irq_save(flags);
122         if (lguest_data.hcall_status[next_call] != 0xFF) {
123                 /* Table full, so do normal hcall which will flush table. */
124                 hcall(call, arg1, arg2, arg3, arg4);
125         } else {
126                 lguest_data.hcalls[next_call].arg0 = call;
127                 lguest_data.hcalls[next_call].arg1 = arg1;
128                 lguest_data.hcalls[next_call].arg2 = arg2;
129                 lguest_data.hcalls[next_call].arg3 = arg3;
130                 lguest_data.hcalls[next_call].arg4 = arg4;
131                 /* Arguments must all be written before we mark it to go */
132                 wmb();
133                 lguest_data.hcall_status[next_call] = 0;
134                 if (++next_call == LHCALL_RING_SIZE)
135                         next_call = 0;
136         }
137         local_irq_restore(flags);
138 }
139 
140 /*G:035
141  * Notice the lazy_hcall() above, rather than hcall().  This is our first real
142  * optimization trick!
143  *
144  * When lazy_mode is set, it means we're allowed to defer all hypercalls and do
145  * them as a batch when lazy_mode is eventually turned off.  Because hypercalls
146  * are reasonably expensive, batching them up makes sense.  For example, a
147  * large munmap might update dozens of page table entries: that code calls
148  * paravirt_enter_lazy_mmu(), does the dozen updates, then calls
149  * lguest_leave_lazy_mode().
150  *
151  * So, when we're in lazy mode, we call async_hcall() to store the call for
152  * future processing:
153  */
154 static void lazy_hcall1(unsigned long call, unsigned long arg1)
155 {
156         if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
157                 hcall(call, arg1, 0, 0, 0);
158         else
159                 async_hcall(call, arg1, 0, 0, 0);
160 }
161 
162 /* You can imagine what lazy_hcall2, 3 and 4 look like. :*/
163 static void lazy_hcall2(unsigned long call,
164                         unsigned long arg1,
165                         unsigned long arg2)
166 {
167         if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
168                 hcall(call, arg1, arg2, 0, 0);
169         else
170                 async_hcall(call, arg1, arg2, 0, 0);
171 }
172 
173 static void lazy_hcall3(unsigned long call,
174                         unsigned long arg1,
175                         unsigned long arg2,
176                         unsigned long arg3)
177 {
178         if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
179                 hcall(call, arg1, arg2, arg3, 0);
180         else
181                 async_hcall(call, arg1, arg2, arg3, 0);
182 }
183 
184 #ifdef CONFIG_X86_PAE
185 static void lazy_hcall4(unsigned long call,
186                         unsigned long arg1,
187                         unsigned long arg2,
188                         unsigned long arg3,
189                         unsigned long arg4)
190 {
191         if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
192                 hcall(call, arg1, arg2, arg3, arg4);
193         else
194                 async_hcall(call, arg1, arg2, arg3, arg4);
195 }
196 #endif
197 
198 /*G:036
199  * When lazy mode is turned off, we issue the do-nothing hypercall to
200  * flush any stored calls, and call the generic helper to reset the
201  * per-cpu lazy mode variable.
202  */
203 static void lguest_leave_lazy_mmu_mode(void)
204 {
205         hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0);
206         paravirt_leave_lazy_mmu();
207 }
208 
209 /*
210  * We also catch the end of context switch; we enter lazy mode for much of
211  * that too, so again we need to flush here.
212  *
213  * (Technically, this is lazy CPU mode, and normally we're in lazy MMU
214  * mode, but unlike Xen, lguest doesn't care about the difference).
215  */
216 static void lguest_end_context_switch(struct task_struct *next)
217 {
218         hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0);
219         paravirt_end_context_switch(next);
220 }
221 
222 /*G:032
223  * After that diversion we return to our first native-instruction
224  * replacements: four functions for interrupt control.
225  *
226  * The simplest way of implementing these would be to have "turn interrupts
227  * off" and "turn interrupts on" hypercalls.  Unfortunately, this is too slow:
228  * these are by far the most commonly called functions of those we override.
229  *
230  * So instead we keep an "irq_enabled" field inside our "struct lguest_data",
231  * which the Guest can update with a single instruction.  The Host knows to
232  * check there before it tries to deliver an interrupt.
233  */
234 
235 /*
236  * save_flags() is expected to return the processor state (ie. "flags").  The
237  * flags word contains all kind of stuff, but in practice Linux only cares
238  * about the interrupt flag.  Our "save_flags()" just returns that.
239  */
240 asmlinkage __visible unsigned long lguest_save_fl(void)
241 {
242         return lguest_data.irq_enabled;
243 }
244 
245 /* Interrupts go off... */
246 asmlinkage __visible void lguest_irq_disable(void)
247 {
248         lguest_data.irq_enabled = 0;
249 }
250 
251 /*
252  * Let's pause a moment.  Remember how I said these are called so often?
253  * Jeremy Fitzhardinge optimized them so hard early in 2009 that he had to
254  * break some rules.  In particular, these functions are assumed to save their
255  * own registers if they need to: normal C functions assume they can trash the
256  * eax register.  To use normal C functions, we use
257  * PV_CALLEE_SAVE_REGS_THUNK(), which pushes %eax onto the stack, calls the
258  * C function, then restores it.
259  */
260 PV_CALLEE_SAVE_REGS_THUNK(lguest_save_fl);
261 PV_CALLEE_SAVE_REGS_THUNK(lguest_irq_disable);
262 /*:*/
263 
264 /* These are in head_32.S */
265 extern void lg_irq_enable(void);
266 extern void lg_restore_fl(unsigned long flags);
267 
268 /*M:003
269  * We could be more efficient in our checking of outstanding interrupts, rather
270  * than using a branch.  One way would be to put the "irq_enabled" field in a
271  * page by itself, and have the Host write-protect it when an interrupt comes
272  * in when irqs are disabled.  There will then be a page fault as soon as
273  * interrupts are re-enabled.
274  *
275  * A better method is to implement soft interrupt disable generally for x86:
276  * instead of disabling interrupts, we set a flag.  If an interrupt does come
277  * in, we then disable them for real.  This is uncommon, so we could simply use
278  * a hypercall for interrupt control and not worry about efficiency.
279 :*/
280 
281 /*G:034
282  * The Interrupt Descriptor Table (IDT).
283  *
284  * The IDT tells the processor what to do when an interrupt comes in.  Each
285  * entry in the table is a 64-bit descriptor: this holds the privilege level,
286  * address of the handler, and... well, who cares?  The Guest just asks the
287  * Host to make the change anyway, because the Host controls the real IDT.
288  */
289 static void lguest_write_idt_entry(gate_desc *dt,
290                                    int entrynum, const gate_desc *g)
291 {
292         /*
293          * The gate_desc structure is 8 bytes long: we hand it to the Host in
294          * two 32-bit chunks.  The whole 32-bit kernel used to hand descriptors
295          * around like this; typesafety wasn't a big concern in Linux's early
296          * years.
297          */
298         u32 *desc = (u32 *)g;
299         /* Keep the local copy up to date. */
300         native_write_idt_entry(dt, entrynum, g);
301         /* Tell Host about this new entry. */
302         hcall(LHCALL_LOAD_IDT_ENTRY, entrynum, desc[0], desc[1], 0);
303 }
304 
305 /*
306  * Changing to a different IDT is very rare: we keep the IDT up-to-date every
307  * time it is written, so we can simply loop through all entries and tell the
308  * Host about them.
309  */
310 static void lguest_load_idt(const struct desc_ptr *desc)
311 {
312         unsigned int i;
313         struct desc_struct *idt = (void *)desc->address;
314 
315         for (i = 0; i < (desc->size+1)/8; i++)
316                 hcall(LHCALL_LOAD_IDT_ENTRY, i, idt[i].a, idt[i].b, 0);
317 }
318 
319 /*
320  * The Global Descriptor Table.
321  *
322  * The Intel architecture defines another table, called the Global Descriptor
323  * Table (GDT).  You tell the CPU where it is (and its size) using the "lgdt"
324  * instruction, and then several other instructions refer to entries in the
325  * table.  There are three entries which the Switcher needs, so the Host simply
326  * controls the entire thing and the Guest asks it to make changes using the
327  * LOAD_GDT hypercall.
328  *
329  * This is the exactly like the IDT code.
330  */
331 static void lguest_load_gdt(const struct desc_ptr *desc)
332 {
333         unsigned int i;
334         struct desc_struct *gdt = (void *)desc->address;
335 
336         for (i = 0; i < (desc->size+1)/8; i++)
337                 hcall(LHCALL_LOAD_GDT_ENTRY, i, gdt[i].a, gdt[i].b, 0);
338 }
339 
340 /*
341  * For a single GDT entry which changes, we simply change our copy and
342  * then tell the host about it.
343  */
344 static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
345                                    const void *desc, int type)
346 {
347         native_write_gdt_entry(dt, entrynum, desc, type);
348         /* Tell Host about this new entry. */
349         hcall(LHCALL_LOAD_GDT_ENTRY, entrynum,
350               dt[entrynum].a, dt[entrynum].b, 0);
351 }
352 
353 /*
354  * There are three "thread local storage" GDT entries which change
355  * on every context switch (these three entries are how glibc implements
356  * __thread variables).  As an optimization, we have a hypercall
357  * specifically for this case.
358  *
359  * Wouldn't it be nicer to have a general LOAD_GDT_ENTRIES hypercall
360  * which took a range of entries?
361  */
362 static void lguest_load_tls(struct thread_struct *t, unsigned int cpu)
363 {
364         /*
365          * There's one problem which normal hardware doesn't have: the Host
366          * can't handle us removing entries we're currently using.  So we clear
367          * the GS register here: if it's needed it'll be reloaded anyway.
368          */
369         lazy_load_gs(0);
370         lazy_hcall2(LHCALL_LOAD_TLS, __pa(&t->tls_array), cpu);
371 }
372 
373 /*G:038
374  * That's enough excitement for now, back to ploughing through each of the
375  * different pv_ops structures (we're about 1/3 of the way through).
376  *
377  * This is the Local Descriptor Table, another weird Intel thingy.  Linux only
378  * uses this for some strange applications like Wine.  We don't do anything
379  * here, so they'll get an informative and friendly Segmentation Fault.
380  */
381 static void lguest_set_ldt(const void *addr, unsigned entries)
382 {
383 }
384 
385 /*
386  * This loads a GDT entry into the "Task Register": that entry points to a
387  * structure called the Task State Segment.  Some comments scattered though the
388  * kernel code indicate that this used for task switching in ages past, along
389  * with blood sacrifice and astrology.
390  *
391  * Now there's nothing interesting in here that we don't get told elsewhere.
392  * But the native version uses the "ltr" instruction, which makes the Host
393  * complain to the Guest about a Segmentation Fault and it'll oops.  So we
394  * override the native version with a do-nothing version.
395  */
396 static void lguest_load_tr_desc(void)
397 {
398 }
399 
400 /*
401  * The "cpuid" instruction is a way of querying both the CPU identity
402  * (manufacturer, model, etc) and its features.  It was introduced before the
403  * Pentium in 1993 and keeps getting extended by both Intel, AMD and others.
404  * As you might imagine, after a decade and a half this treatment, it is now a
405  * giant ball of hair.  Its entry in the current Intel manual runs to 28 pages.
406  *
407  * This instruction even it has its own Wikipedia entry.  The Wikipedia entry
408  * has been translated into 6 languages.  I am not making this up!
409  *
410  * We could get funky here and identify ourselves as "GenuineLguest", but
411  * instead we just use the real "cpuid" instruction.  Then I pretty much turned
412  * off feature bits until the Guest booted.  (Don't say that: you'll damage
413  * lguest sales!)  Shut up, inner voice!  (Hey, just pointing out that this is
414  * hardly future proof.)  No one's listening!  They don't like you anyway,
415  * parenthetic weirdo!
416  *
417  * Replacing the cpuid so we can turn features off is great for the kernel, but
418  * anyone (including userspace) can just use the raw "cpuid" instruction and
419  * the Host won't even notice since it isn't privileged.  So we try not to get
420  * too worked up about it.
421  */
422 static void lguest_cpuid(unsigned int *ax, unsigned int *bx,
423                          unsigned int *cx, unsigned int *dx)
424 {
425         int function = *ax;
426 
427         native_cpuid(ax, bx, cx, dx);
428         switch (function) {
429         /*
430          * CPUID 0 gives the highest legal CPUID number (and the ID string).
431          * We futureproof our code a little by sticking to known CPUID values.
432          */
433         case 0:
434                 if (*ax > 5)
435                         *ax = 5;
436                 break;
437 
438         /*
439          * CPUID 1 is a basic feature request.
440          *
441          * CX: we only allow kernel to see SSE3, CMPXCHG16B and SSSE3
442          * DX: SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, TSC, FPU and PAE.
443          */
444         case 1:
445                 *cx &= 0x00002201;
446                 *dx &= 0x07808151;
447                 /*
448                  * The Host can do a nice optimization if it knows that the
449                  * kernel mappings (addresses above 0xC0000000 or whatever
450                  * PAGE_OFFSET is set to) haven't changed.  But Linux calls
451                  * flush_tlb_user() for both user and kernel mappings unless
452                  * the Page Global Enable (PGE) feature bit is set.
453                  */
454                 *dx |= 0x00002000;
455                 /*
456                  * We also lie, and say we're family id 5.  6 or greater
457                  * leads to a rdmsr in early_init_intel which we can't handle.
458                  * Family ID is returned as bits 8-12 in ax.
459                  */
460                 *ax &= 0xFFFFF0FF;
461                 *ax |= 0x00000500;
462                 break;
463 
464         /*
465          * This is used to detect if we're running under KVM.  We might be,
466          * but that's a Host matter, not us.  So say we're not.
467          */
468         case KVM_CPUID_SIGNATURE:
469                 *bx = *cx = *dx = 0;
470                 break;
471 
472         /*
473          * 0x80000000 returns the highest Extended Function, so we futureproof
474          * like we do above by limiting it to known fields.
475          */
476         case 0x80000000:
477                 if (*ax > 0x80000008)
478                         *ax = 0x80000008;
479                 break;
480 
481         /*
482          * PAE systems can mark pages as non-executable.  Linux calls this the
483          * NX bit.  Intel calls it XD (eXecute Disable), AMD EVP (Enhanced
484          * Virus Protection).  We just switch it off here, since we don't
485          * support it.
486          */
487         case 0x80000001:
488                 *dx &= ~(1 << 20);
489                 break;
490         }
491 }
492 
493 /*
494  * Intel has four control registers, imaginatively named cr0, cr2, cr3 and cr4.
495  * I assume there's a cr1, but it hasn't bothered us yet, so we'll not bother
496  * it.  The Host needs to know when the Guest wants to change them, so we have
497  * a whole series of functions like read_cr0() and write_cr0().
498  *
499  * We start with cr0.  cr0 allows you to turn on and off all kinds of basic
500  * features, but Linux only really cares about one: the horrifically-named Task
501  * Switched (TS) bit at bit 3 (ie. 8)
502  *
503  * What does the TS bit do?  Well, it causes the CPU to trap (interrupt 7) if
504  * the floating point unit is used.  Which allows us to restore FPU state
505  * lazily after a task switch, and Linux uses that gratefully, but wouldn't a
506  * name like "FPUTRAP bit" be a little less cryptic?
507  *
508  * We store cr0 locally because the Host never changes it.  The Guest sometimes
509  * wants to read it and we'd prefer not to bother the Host unnecessarily.
510  */
511 static unsigned long current_cr0;
512 static void lguest_write_cr0(unsigned long val)
513 {
514         lazy_hcall1(LHCALL_TS, val & X86_CR0_TS);
515         current_cr0 = val;
516 }
517 
518 static unsigned long lguest_read_cr0(void)
519 {
520         return current_cr0;
521 }
522 
523 /*
524  * Intel provided a special instruction to clear the TS bit for people too cool
525  * to use write_cr0() to do it.  This "clts" instruction is faster, because all
526  * the vowels have been optimized out.
527  */
528 static void lguest_clts(void)
529 {
530         lazy_hcall1(LHCALL_TS, 0);
531         current_cr0 &= ~X86_CR0_TS;
532 }
533 
534 /*
535  * cr2 is the virtual address of the last page fault, which the Guest only ever
536  * reads.  The Host kindly writes this into our "struct lguest_data", so we
537  * just read it out of there.
538  */
539 static unsigned long lguest_read_cr2(void)
540 {
541         return lguest_data.cr2;
542 }
543 
544 /* See lguest_set_pte() below. */
545 static bool cr3_changed = false;
546 static unsigned long current_cr3;
547 
548 /*
549  * cr3 is the current toplevel pagetable page: the principle is the same as
550  * cr0.  Keep a local copy, and tell the Host when it changes.
551  */
552 static void lguest_write_cr3(unsigned long cr3)
553 {
554         lazy_hcall1(LHCALL_NEW_PGTABLE, cr3);
555         current_cr3 = cr3;
556 
557         /* These two page tables are simple, linear, and used during boot */
558         if (cr3 != __pa_symbol(swapper_pg_dir) &&
559             cr3 != __pa_symbol(initial_page_table))
560                 cr3_changed = true;
561 }
562 
563 static unsigned long lguest_read_cr3(void)
564 {
565         return current_cr3;
566 }
567 
568 /* cr4 is used to enable and disable PGE, but we don't care. */
569 static unsigned long lguest_read_cr4(void)
570 {
571         return 0;
572 }
573 
574 static void lguest_write_cr4(unsigned long val)
575 {
576 }
577 
578 /*
579  * Page Table Handling.
580  *
581  * Now would be a good time to take a rest and grab a coffee or similarly
582  * relaxing stimulant.  The easy parts are behind us, and the trek gradually
583  * winds uphill from here.
584  *
585  * Quick refresher: memory is divided into "pages" of 4096 bytes each.  The CPU
586  * maps virtual addresses to physical addresses using "page tables".  We could
587  * use one huge index of 1 million entries: each address is 4 bytes, so that's
588  * 1024 pages just to hold the page tables.   But since most virtual addresses
589  * are unused, we use a two level index which saves space.  The cr3 register
590  * contains the physical address of the top level "page directory" page, which
591  * contains physical addresses of up to 1024 second-level pages.  Each of these
592  * second level pages contains up to 1024 physical addresses of actual pages,
593  * or Page Table Entries (PTEs).
594  *
595  * Here's a diagram, where arrows indicate physical addresses:
596  *
597  * cr3 ---> +---------+
598  *          |      --------->+---------+
599  *          |         |      | PADDR1  |
600  *        Mid-level   |      | PADDR2  |
601  *        (PMD) page  |      |         |
602  *          |         |    Lower-level |
603  *          |         |    (PTE) page  |
604  *          |         |      |         |
605  *            ....               ....
606  *
607  * So to convert a virtual address to a physical address, we look up the top
608  * level, which points us to the second level, which gives us the physical
609  * address of that page.  If the top level entry was not present, or the second
610  * level entry was not present, then the virtual address is invalid (we
611  * say "the page was not mapped").
612  *
613  * Put another way, a 32-bit virtual address is divided up like so:
614  *
615  *  1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
616  * |<---- 10 bits ---->|<---- 10 bits ---->|<------ 12 bits ------>|
617  *    Index into top     Index into second      Offset within page
618  *  page directory page    pagetable page
619  *
620  * Now, unfortunately, this isn't the whole story: Intel added Physical Address
621  * Extension (PAE) to allow 32 bit systems to use 64GB of memory (ie. 36 bits).
622  * These are held in 64-bit page table entries, so we can now only fit 512
623  * entries in a page, and the neat three-level tree breaks down.
624  *
625  * The result is a four level page table:
626  *
627  * cr3 --> [ 4 Upper  ]
628  *         [   Level  ]
629  *         [  Entries ]
630  *         [(PUD Page)]---> +---------+
631  *                          |      --------->+---------+
632  *                          |         |      | PADDR1  |
633  *                        Mid-level   |      | PADDR2  |
634  *                        (PMD) page  |      |         |
635  *                          |         |    Lower-level |
636  *                          |         |    (PTE) page  |
637  *                          |         |      |         |
638  *                            ....               ....
639  *
640  *
641  * And the virtual address is decoded as:
642  *
643  *         1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
644  *      |<-2->|<--- 9 bits ---->|<---- 9 bits --->|<------ 12 bits ------>|
645  * Index into    Index into mid    Index into lower    Offset within page
646  * top entries   directory page     pagetable page
647  *
648  * It's too hard to switch between these two formats at runtime, so Linux only
649  * supports one or the other depending on whether CONFIG_X86_PAE is set.  Many
650  * distributions turn it on, and not just for people with silly amounts of
651  * memory: the larger PTE entries allow room for the NX bit, which lets the
652  * kernel disable execution of pages and increase security.
653  *
654  * This was a problem for lguest, which couldn't run on these distributions;
655  * then Matias Zabaljauregui figured it all out and implemented it, and only a
656  * handful of puppies were crushed in the process!
657  *
658  * Back to our point: the kernel spends a lot of time changing both the
659  * top-level page directory and lower-level pagetable pages.  The Guest doesn't
660  * know physical addresses, so while it maintains these page tables exactly
661  * like normal, it also needs to keep the Host informed whenever it makes a
662  * change: the Host will create the real page tables based on the Guests'.
663  */
664 
665 /*
666  * The Guest calls this after it has set a second-level entry (pte), ie. to map
667  * a page into a process' address space.  We tell the Host the toplevel and
668  * address this corresponds to.  The Guest uses one pagetable per process, so
669  * we need to tell the Host which one we're changing (mm->pgd).
670  */
671 static void lguest_pte_update(struct mm_struct *mm, unsigned long addr,
672                                pte_t *ptep)
673 {
674 #ifdef CONFIG_X86_PAE
675         /* PAE needs to hand a 64 bit page table entry, so it uses two args. */
676         lazy_hcall4(LHCALL_SET_PTE, __pa(mm->pgd), addr,
677                     ptep->pte_low, ptep->pte_high);
678 #else
679         lazy_hcall3(LHCALL_SET_PTE, __pa(mm->pgd), addr, ptep->pte_low);
680 #endif
681 }
682 
683 /* This is the "set and update" combo-meal-deal version. */
684 static void lguest_set_pte_at(struct mm_struct *mm, unsigned long addr,
685                               pte_t *ptep, pte_t pteval)
686 {
687         native_set_pte(ptep, pteval);
688         lguest_pte_update(mm, addr, ptep);
689 }
690 
691 /*
692  * The Guest calls lguest_set_pud to set a top-level entry and lguest_set_pmd
693  * to set a middle-level entry when PAE is activated.
694  *
695  * Again, we set the entry then tell the Host which page we changed,
696  * and the index of the entry we changed.
697  */
698 #ifdef CONFIG_X86_PAE
699 static void lguest_set_pud(pud_t *pudp, pud_t pudval)
700 {
701         native_set_pud(pudp, pudval);
702 
703         /* 32 bytes aligned pdpt address and the index. */
704         lazy_hcall2(LHCALL_SET_PGD, __pa(pudp) & 0xFFFFFFE0,
705                    (__pa(pudp) & 0x1F) / sizeof(pud_t));
706 }
707 
708 static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval)
709 {
710         native_set_pmd(pmdp, pmdval);
711         lazy_hcall2(LHCALL_SET_PMD, __pa(pmdp) & PAGE_MASK,
712                    (__pa(pmdp) & (PAGE_SIZE - 1)) / sizeof(pmd_t));
713 }
714 #else
715 
716 /* The Guest calls lguest_set_pmd to set a top-level entry when !PAE. */
717 static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval)
718 {
719         native_set_pmd(pmdp, pmdval);
720         lazy_hcall2(LHCALL_SET_PGD, __pa(pmdp) & PAGE_MASK,
721                    (__pa(pmdp) & (PAGE_SIZE - 1)) / sizeof(pmd_t));
722 }
723 #endif
724 
725 /*
726  * There are a couple of legacy places where the kernel sets a PTE, but we
727  * don't know the top level any more.  This is useless for us, since we don't
728  * know which pagetable is changing or what address, so we just tell the Host
729  * to forget all of them.  Fortunately, this is very rare.
730  *
731  * ... except in early boot when the kernel sets up the initial pagetables,
732  * which makes booting astonishingly slow: 48 seconds!  So we don't even tell
733  * the Host anything changed until we've done the first real page table switch,
734  * which brings boot back to 4.3 seconds.
735  */
736 static void lguest_set_pte(pte_t *ptep, pte_t pteval)
737 {
738         native_set_pte(ptep, pteval);
739         if (cr3_changed)
740                 lazy_hcall1(LHCALL_FLUSH_TLB, 1);
741 }
742 
743 #ifdef CONFIG_X86_PAE
744 /*
745  * With 64-bit PTE values, we need to be careful setting them: if we set 32
746  * bits at a time, the hardware could see a weird half-set entry.  These
747  * versions ensure we update all 64 bits at once.
748  */
749 static void lguest_set_pte_atomic(pte_t *ptep, pte_t pte)
750 {
751         native_set_pte_atomic(ptep, pte);
752         if (cr3_changed)
753                 lazy_hcall1(LHCALL_FLUSH_TLB, 1);
754 }
755 
756 static void lguest_pte_clear(struct mm_struct *mm, unsigned long addr,
757                              pte_t *ptep)
758 {
759         native_pte_clear(mm, addr, ptep);
760         lguest_pte_update(mm, addr, ptep);
761 }
762 
763 static void lguest_pmd_clear(pmd_t *pmdp)
764 {
765         lguest_set_pmd(pmdp, __pmd(0));
766 }
767 #endif
768 
769 /*
770  * Unfortunately for Lguest, the pv_mmu_ops for page tables were based on
771  * native page table operations.  On native hardware you can set a new page
772  * table entry whenever you want, but if you want to remove one you have to do
773  * a TLB flush (a TLB is a little cache of page table entries kept by the CPU).
774  *
775  * So the lguest_set_pte_at() and lguest_set_pmd() functions above are only
776  * called when a valid entry is written, not when it's removed (ie. marked not
777  * present).  Instead, this is where we come when the Guest wants to remove a
778  * page table entry: we tell the Host to set that entry to 0 (ie. the present
779  * bit is zero).
780  */
781 static void lguest_flush_tlb_single(unsigned long addr)
782 {
783         /* Simply set it to zero: if it was not, it will fault back in. */
784         lazy_hcall3(LHCALL_SET_PTE, current_cr3, addr, 0);
785 }
786 
787 /*
788  * This is what happens after the Guest has removed a large number of entries.
789  * This tells the Host that any of the page table entries for userspace might
790  * have changed, ie. virtual addresses below PAGE_OFFSET.
791  */
792 static void lguest_flush_tlb_user(void)
793 {
794         lazy_hcall1(LHCALL_FLUSH_TLB, 0);
795 }
796 
797 /*
798  * This is called when the kernel page tables have changed.  That's not very
799  * common (unless the Guest is using highmem, which makes the Guest extremely
800  * slow), so it's worth separating this from the user flushing above.
801  */
802 static void lguest_flush_tlb_kernel(void)
803 {
804         lazy_hcall1(LHCALL_FLUSH_TLB, 1);
805 }
806 
807 /*
808  * The Unadvanced Programmable Interrupt Controller.
809  *
810  * This is an attempt to implement the simplest possible interrupt controller.
811  * I spent some time looking though routines like set_irq_chip_and_handler,
812  * set_irq_chip_and_handler_name, set_irq_chip_data and set_phasers_to_stun and
813  * I *think* this is as simple as it gets.
814  *
815  * We can tell the Host what interrupts we want blocked ready for using the
816  * lguest_data.interrupts bitmap, so disabling (aka "masking") them is as
817  * simple as setting a bit.  We don't actually "ack" interrupts as such, we
818  * just mask and unmask them.  I wonder if we should be cleverer?
819  */
820 static void disable_lguest_irq(struct irq_data *data)
821 {
822         set_bit(data->irq, lguest_data.blocked_interrupts);
823 }
824 
825 static void enable_lguest_irq(struct irq_data *data)
826 {
827         clear_bit(data->irq, lguest_data.blocked_interrupts);
828 }
829 
830 /* This structure describes the lguest IRQ controller. */
831 static struct irq_chip lguest_irq_controller = {
832         .name           = "lguest",
833         .irq_mask       = disable_lguest_irq,
834         .irq_mask_ack   = disable_lguest_irq,
835         .irq_unmask     = enable_lguest_irq,
836 };
837 
838 /*
839  * Interrupt descriptors are allocated as-needed, but low-numbered ones are
840  * reserved by the generic x86 code.  So we ignore irq_alloc_desc_at if it
841  * tells us the irq is already used: other errors (ie. ENOMEM) we take
842  * seriously.
843  */
844 static int lguest_setup_irq(unsigned int irq)
845 {
846         struct irq_desc *desc;
847         int err;
848 
849         /* Returns -ve error or vector number. */
850         err = irq_alloc_desc_at(irq, 0);
851         if (err < 0 && err != -EEXIST)
852                 return err;
853 
854         /*
855          * Tell the Linux infrastructure that the interrupt is
856          * controlled by our level-based lguest interrupt controller.
857          */
858         irq_set_chip_and_handler_name(irq, &lguest_irq_controller,
859                                       handle_level_irq, "level");
860 
861         /* Some systems map "vectors" to interrupts weirdly.  Not us! */
862         desc = irq_to_desc(irq);
863         __this_cpu_write(vector_irq[FIRST_EXTERNAL_VECTOR + irq], desc);
864         return 0;
865 }
866 
867 static int lguest_enable_irq(struct pci_dev *dev)
868 {
869         int err;
870         u8 line = 0;
871 
872         /* We literally use the PCI interrupt line as the irq number. */
873         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
874         err = lguest_setup_irq(line);
875         if (!err)
876                 dev->irq = line;
877         return err;
878 }
879 
880 /* We don't do hotplug PCI, so this shouldn't be called. */
881 static void lguest_disable_irq(struct pci_dev *dev)
882 {
883         WARN_ON(1);
884 }
885 
886 /*
887  * This sets up the Interrupt Descriptor Table (IDT) entry for each hardware
888  * interrupt (except 128, which is used for system calls).
889  */
890 static void __init lguest_init_IRQ(void)
891 {
892         unsigned int i;
893 
894         for (i = FIRST_EXTERNAL_VECTOR; i < FIRST_SYSTEM_VECTOR; i++) {
895                 if (i != IA32_SYSCALL_VECTOR)
896                         set_intr_gate(i, irq_entries_start +
897                                         8 * (i - FIRST_EXTERNAL_VECTOR));
898         }
899 
900         /*
901          * This call is required to set up for 4k stacks, where we have
902          * separate stacks for hard and soft interrupts.
903          */
904         irq_ctx_init(smp_processor_id());
905 }
906 
907 /*
908  * Time.
909  *
910  * It would be far better for everyone if the Guest had its own clock, but
911  * until then the Host gives us the time on every interrupt.
912  */
913 static void lguest_get_wallclock(struct timespec *now)
914 {
915         *now = lguest_data.time;
916 }
917 
918 /*
919  * The TSC is an Intel thing called the Time Stamp Counter.  The Host tells us
920  * what speed it runs at, or 0 if it's unusable as a reliable clock source.
921  * This matches what we want here: if we return 0 from this function, the x86
922  * TSC clock will give up and not register itself.
923  */
924 static unsigned long lguest_tsc_khz(void)
925 {
926         return lguest_data.tsc_khz;
927 }
928 
929 /*
930  * If we can't use the TSC, the kernel falls back to our lower-priority
931  * "lguest_clock", where we read the time value given to us by the Host.
932  */
933 static cycle_t lguest_clock_read(struct clocksource *cs)
934 {
935         unsigned long sec, nsec;
936 
937         /*
938          * Since the time is in two parts (seconds and nanoseconds), we risk
939          * reading it just as it's changing from 99 & 0.999999999 to 100 and 0,
940          * and getting 99 and 0.  As Linux tends to come apart under the stress
941          * of time travel, we must be careful:
942          */
943         do {
944                 /* First we read the seconds part. */
945                 sec = lguest_data.time.tv_sec;
946                 /*
947                  * This read memory barrier tells the compiler and the CPU that
948                  * this can't be reordered: we have to complete the above
949                  * before going on.
950                  */
951                 rmb();
952                 /* Now we read the nanoseconds part. */
953                 nsec = lguest_data.time.tv_nsec;
954                 /* Make sure we've done that. */
955                 rmb();
956                 /* Now if the seconds part has changed, try again. */
957         } while (unlikely(lguest_data.time.tv_sec != sec));
958 
959         /* Our lguest clock is in real nanoseconds. */
960         return sec*1000000000ULL + nsec;
961 }
962 
963 /* This is the fallback clocksource: lower priority than the TSC clocksource. */
964 static struct clocksource lguest_clock = {
965         .name           = "lguest",
966         .rating         = 200,
967         .read           = lguest_clock_read,
968         .mask           = CLOCKSOURCE_MASK(64),
969         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
970 };
971 
972 /*
973  * We also need a "struct clock_event_device": Linux asks us to set it to go
974  * off some time in the future.  Actually, James Morris figured all this out, I
975  * just applied the patch.
976  */
977 static int lguest_clockevent_set_next_event(unsigned long delta,
978                                            struct clock_event_device *evt)
979 {
980         /* FIXME: I don't think this can ever happen, but James tells me he had
981          * to put this code in.  Maybe we should remove it now.  Anyone? */
982         if (delta < LG_CLOCK_MIN_DELTA) {
983                 if (printk_ratelimit())
984                         printk(KERN_DEBUG "%s: small delta %lu ns\n",
985                                __func__, delta);
986                 return -ETIME;
987         }
988 
989         /* Please wake us this far in the future. */
990         hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0, 0);
991         return 0;
992 }
993 
994 static int lguest_clockevent_shutdown(struct clock_event_device *evt)
995 {
996         /* A 0 argument shuts the clock down. */
997         hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0, 0);
998         return 0;
999 }
1000 
1001 /* This describes our primitive timer chip. */
1002 static struct clock_event_device lguest_clockevent = {
1003         .name                   = "lguest",
1004         .features               = CLOCK_EVT_FEAT_ONESHOT,
1005         .set_next_event         = lguest_clockevent_set_next_event,
1006         .set_state_shutdown     = lguest_clockevent_shutdown,
1007         .rating                 = INT_MAX,
1008         .mult                   = 1,
1009         .shift                  = 0,
1010         .min_delta_ns           = LG_CLOCK_MIN_DELTA,
1011         .max_delta_ns           = LG_CLOCK_MAX_DELTA,
1012 };
1013 
1014 /*
1015  * This is the Guest timer interrupt handler (hardware interrupt 0).  We just
1016  * call the clockevent infrastructure and it does whatever needs doing.
1017  */
1018 static void lguest_time_irq(struct irq_desc *desc)
1019 {
1020         unsigned long flags;
1021 
1022         /* Don't interrupt us while this is running. */
1023         local_irq_save(flags);
1024         lguest_clockevent.event_handler(&lguest_clockevent);
1025         local_irq_restore(flags);
1026 }
1027 
1028 /*
1029  * At some point in the boot process, we get asked to set up our timing
1030  * infrastructure.  The kernel doesn't expect timer interrupts before this, but
1031  * we cleverly initialized the "blocked_interrupts" field of "struct
1032  * lguest_data" so that timer interrupts were blocked until now.
1033  */
1034 static void lguest_time_init(void)
1035 {
1036         /* Set up the timer interrupt (0) to go to our simple timer routine */
1037         if (lguest_setup_irq(0) != 0)
1038                 panic("Could not set up timer irq");
1039         irq_set_handler(0, lguest_time_irq);
1040 
1041         clocksource_register_hz(&lguest_clock, NSEC_PER_SEC);
1042 
1043         /* We can't set cpumask in the initializer: damn C limitations!  Set it
1044          * here and register our timer device. */
1045         lguest_clockevent.cpumask = cpumask_of(0);
1046         clockevents_register_device(&lguest_clockevent);
1047 
1048         /* Finally, we unblock the timer interrupt. */
1049         clear_bit(0, lguest_data.blocked_interrupts);
1050 }
1051 
1052 /*
1053  * Miscellaneous bits and pieces.
1054  *
1055  * Here is an oddball collection of functions which the Guest needs for things
1056  * to work.  They're pretty simple.
1057  */
1058 
1059 /*
1060  * The Guest needs to tell the Host what stack it expects traps to use.  For
1061  * native hardware, this is part of the Task State Segment mentioned above in
1062  * lguest_load_tr_desc(), but to help hypervisors there's this special call.
1063  *
1064  * We tell the Host the segment we want to use (__KERNEL_DS is the kernel data
1065  * segment), the privilege level (we're privilege level 1, the Host is 0 and
1066  * will not tolerate us trying to use that), the stack pointer, and the number
1067  * of pages in the stack.
1068  */
1069 static void lguest_load_sp0(struct tss_struct *tss,
1070                             struct thread_struct *thread)
1071 {
1072         lazy_hcall3(LHCALL_SET_STACK, __KERNEL_DS | 0x1, thread->sp0,
1073                    THREAD_SIZE / PAGE_SIZE);
1074         tss->x86_tss.sp0 = thread->sp0;
1075 }
1076 
1077 /* Let's just say, I wouldn't do debugging under a Guest. */
1078 static unsigned long lguest_get_debugreg(int regno)
1079 {
1080         /* FIXME: Implement */
1081         return 0;
1082 }
1083 
1084 static void lguest_set_debugreg(int regno, unsigned long value)
1085 {
1086         /* FIXME: Implement */
1087 }
1088 
1089 /*
1090  * There are times when the kernel wants to make sure that no memory writes are
1091  * caught in the cache (that they've all reached real hardware devices).  This
1092  * doesn't matter for the Guest which has virtual hardware.
1093  *
1094  * On the Pentium 4 and above, cpuid() indicates that the Cache Line Flush
1095  * (clflush) instruction is available and the kernel uses that.  Otherwise, it
1096  * uses the older "Write Back and Invalidate Cache" (wbinvd) instruction.
1097  * Unlike clflush, wbinvd can only be run at privilege level 0.  So we can
1098  * ignore clflush, but replace wbinvd.
1099  */
1100 static void lguest_wbinvd(void)
1101 {
1102 }
1103 
1104 /*
1105  * If the Guest expects to have an Advanced Programmable Interrupt Controller,
1106  * we play dumb by ignoring writes and returning 0 for reads.  So it's no
1107  * longer Programmable nor Controlling anything, and I don't think 8 lines of
1108  * code qualifies for Advanced.  It will also never interrupt anything.  It
1109  * does, however, allow us to get through the Linux boot code.
1110  */
1111 #ifdef CONFIG_X86_LOCAL_APIC
1112 static void lguest_apic_write(u32 reg, u32 v)
1113 {
1114 }
1115 
1116 static u32 lguest_apic_read(u32 reg)
1117 {
1118         return 0;
1119 }
1120 
1121 static u64 lguest_apic_icr_read(void)
1122 {
1123         return 0;
1124 }
1125 
1126 static void lguest_apic_icr_write(u32 low, u32 id)
1127 {
1128         /* Warn to see if there's any stray references */
1129         WARN_ON(1);
1130 }
1131 
1132 static void lguest_apic_wait_icr_idle(void)
1133 {
1134         return;
1135 }
1136 
1137 static u32 lguest_apic_safe_wait_icr_idle(void)
1138 {
1139         return 0;
1140 }
1141 
1142 static void set_lguest_basic_apic_ops(void)
1143 {
1144         apic->read = lguest_apic_read;
1145         apic->write = lguest_apic_write;
1146         apic->icr_read = lguest_apic_icr_read;
1147         apic->icr_write = lguest_apic_icr_write;
1148         apic->wait_icr_idle = lguest_apic_wait_icr_idle;
1149         apic->safe_wait_icr_idle = lguest_apic_safe_wait_icr_idle;
1150 };
1151 #endif
1152 
1153 /* STOP!  Until an interrupt comes in. */
1154 static void lguest_safe_halt(void)
1155 {
1156         hcall(LHCALL_HALT, 0, 0, 0, 0);
1157 }
1158 
1159 /*
1160  * The SHUTDOWN hypercall takes a string to describe what's happening, and
1161  * an argument which says whether this to restart (reboot) the Guest or not.
1162  *
1163  * Note that the Host always prefers that the Guest speak in physical addresses
1164  * rather than virtual addresses, so we use __pa() here.
1165  */
1166 static void lguest_power_off(void)
1167 {
1168         hcall(LHCALL_SHUTDOWN, __pa("Power down"),
1169               LGUEST_SHUTDOWN_POWEROFF, 0, 0);
1170 }
1171 
1172 /*
1173  * Panicing.
1174  *
1175  * Don't.  But if you did, this is what happens.
1176  */
1177 static int lguest_panic(struct notifier_block *nb, unsigned long l, void *p)
1178 {
1179         hcall(LHCALL_SHUTDOWN, __pa(p), LGUEST_SHUTDOWN_POWEROFF, 0, 0);
1180         /* The hcall won't return, but to keep gcc happy, we're "done". */
1181         return NOTIFY_DONE;
1182 }
1183 
1184 static struct notifier_block paniced = {
1185         .notifier_call = lguest_panic
1186 };
1187 
1188 /* Setting up memory is fairly easy. */
1189 static __init char *lguest_memory_setup(void)
1190 {
1191         /*
1192          * The Linux bootloader header contains an "e820" memory map: the
1193          * Launcher populated the first entry with our memory limit.
1194          */
1195         e820_add_region(boot_params.e820_map[0].addr,
1196                           boot_params.e820_map[0].size,
1197                           boot_params.e820_map[0].type);
1198 
1199         /* This string is for the boot messages. */
1200         return "LGUEST";
1201 }
1202 
1203 /* Offset within PCI config space of BAR access capability. */
1204 static int console_cfg_offset = 0;
1205 static int console_access_cap;
1206 
1207 /* Set up so that we access off in bar0 (on bus 0, device 1, function 0) */
1208 static void set_cfg_window(u32 cfg_offset, u32 off)
1209 {
1210         write_pci_config_byte(0, 1, 0,
1211                               cfg_offset + offsetof(struct virtio_pci_cap, bar),
1212                               0);
1213         write_pci_config(0, 1, 0,
1214                          cfg_offset + offsetof(struct virtio_pci_cap, length),
1215                          4);
1216         write_pci_config(0, 1, 0,
1217                          cfg_offset + offsetof(struct virtio_pci_cap, offset),
1218                          off);
1219 }
1220 
1221 static void write_bar_via_cfg(u32 cfg_offset, u32 off, u32 val)
1222 {
1223         /*
1224          * We could set this up once, then leave it; nothing else in the *
1225          * kernel should touch these registers.  But if it went wrong, that
1226          * would be a horrible bug to find.
1227          */
1228         set_cfg_window(cfg_offset, off);
1229         write_pci_config(0, 1, 0,
1230                          cfg_offset + sizeof(struct virtio_pci_cap), val);
1231 }
1232 
1233 static void probe_pci_console(void)
1234 {
1235         u8 cap, common_cap = 0, device_cap = 0;
1236         /* Offset within BAR0 */
1237         u32 device_offset;
1238         u32 device_len;
1239 
1240         /* Avoid recursive printk into here. */
1241         console_cfg_offset = -1;
1242 
1243         if (!early_pci_allowed()) {
1244                 printk(KERN_ERR "lguest: early PCI access not allowed!\n");
1245                 return;
1246         }
1247 
1248         /* We expect a console PCI device at BUS0, slot 1. */
1249         if (read_pci_config(0, 1, 0, 0) != 0x10431AF4) {
1250                 printk(KERN_ERR "lguest: PCI device is %#x!\n",
1251                        read_pci_config(0, 1, 0, 0));
1252                 return;
1253         }
1254 
1255         /* Find the capabilities we need (must be in bar0) */
1256         cap = read_pci_config_byte(0, 1, 0, PCI_CAPABILITY_LIST);
1257         while (cap) {
1258                 u8 vndr = read_pci_config_byte(0, 1, 0, cap);
1259                 if (vndr == PCI_CAP_ID_VNDR) {
1260                         u8 type, bar;
1261                         u32 offset, length;
1262 
1263                         type = read_pci_config_byte(0, 1, 0,
1264                             cap + offsetof(struct virtio_pci_cap, cfg_type));
1265                         bar = read_pci_config_byte(0, 1, 0,
1266                             cap + offsetof(struct virtio_pci_cap, bar));
1267                         offset = read_pci_config(0, 1, 0,
1268                             cap + offsetof(struct virtio_pci_cap, offset));
1269                         length = read_pci_config(0, 1, 0,
1270                             cap + offsetof(struct virtio_pci_cap, length));
1271 
1272                         switch (type) {
1273                         case VIRTIO_PCI_CAP_DEVICE_CFG:
1274                                 if (bar == 0) {
1275                                         device_cap = cap;
1276                                         device_offset = offset;
1277                                         device_len = length;
1278                                 }
1279                                 break;
1280                         case VIRTIO_PCI_CAP_PCI_CFG:
1281                                 console_access_cap = cap;
1282                                 break;
1283                         }
1284                 }
1285                 cap = read_pci_config_byte(0, 1, 0, cap + PCI_CAP_LIST_NEXT);
1286         }
1287         if (!device_cap || !console_access_cap) {
1288                 printk(KERN_ERR "lguest: No caps (%u/%u/%u) in console!\n",
1289                        common_cap, device_cap, console_access_cap);
1290                 return;
1291         }
1292 
1293         /*
1294          * Note that we can't check features, until we've set the DRIVER
1295          * status bit.  We don't want to do that until we have a real driver,
1296          * so we just check that the device-specific config has room for
1297          * emerg_wr.  If it doesn't support VIRTIO_CONSOLE_F_EMERG_WRITE
1298          * it should ignore the access.
1299          */
1300         if (device_len < (offsetof(struct virtio_console_config, emerg_wr)
1301                           + sizeof(u32))) {
1302                 printk(KERN_ERR "lguest: console missing emerg_wr field\n");
1303                 return;
1304         }
1305 
1306         console_cfg_offset = device_offset;
1307         printk(KERN_INFO "lguest: Console via virtio-pci emerg_wr\n");
1308 }
1309 
1310 /*
1311  * We will eventually use the virtio console device to produce console output,
1312  * but before that is set up we use the virtio PCI console's backdoor mmio
1313  * access and the "emergency" write facility (which is legal even before the
1314  * device is configured).
1315  */
1316 static __init int early_put_chars(u32 vtermno, const char *buf, int count)
1317 {
1318         /* If we couldn't find PCI console, forget it. */
1319         if (console_cfg_offset < 0)
1320                 return count;
1321 
1322         if (unlikely(!console_cfg_offset)) {
1323                 probe_pci_console();
1324                 if (console_cfg_offset < 0)
1325                         return count;
1326         }
1327 
1328         write_bar_via_cfg(console_access_cap,
1329                           console_cfg_offset
1330                           + offsetof(struct virtio_console_config, emerg_wr),
1331                           buf[0]);
1332         return 1;
1333 }
1334 
1335 /*
1336  * Rebooting also tells the Host we're finished, but the RESTART flag tells the
1337  * Launcher to reboot us.
1338  */
1339 static void lguest_restart(char *reason)
1340 {
1341         hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0, 0);
1342 }
1343 
1344 /*G:050
1345  * Patching (Powerfully Placating Performance Pedants)
1346  *
1347  * We have already seen that pv_ops structures let us replace simple native
1348  * instructions with calls to the appropriate back end all throughout the
1349  * kernel.  This allows the same kernel to run as a Guest and as a native
1350  * kernel, but it's slow because of all the indirect branches.
1351  *
1352  * Remember that David Wheeler quote about "Any problem in computer science can
1353  * be solved with another layer of indirection"?  The rest of that quote is
1354  * "... But that usually will create another problem."  This is the first of
1355  * those problems.
1356  *
1357  * Our current solution is to allow the paravirt back end to optionally patch
1358  * over the indirect calls to replace them with something more efficient.  We
1359  * patch two of the simplest of the most commonly called functions: disable
1360  * interrupts and save interrupts.  We usually have 6 or 10 bytes to patch
1361  * into: the Guest versions of these operations are small enough that we can
1362  * fit comfortably.
1363  *
1364  * First we need assembly templates of each of the patchable Guest operations,
1365  * and these are in head_32.S.
1366  */
1367 
1368 /*G:060 We construct a table from the assembler templates: */
1369 static const struct lguest_insns
1370 {
1371         const char *start, *end;
1372 } lguest_insns[] = {
1373         [PARAVIRT_PATCH(pv_irq_ops.irq_disable)] = { lgstart_cli, lgend_cli },
1374         [PARAVIRT_PATCH(pv_irq_ops.save_fl)] = { lgstart_pushf, lgend_pushf },
1375 };
1376 
1377 /*
1378  * Now our patch routine is fairly simple (based on the native one in
1379  * paravirt.c).  If we have a replacement, we copy it in and return how much of
1380  * the available space we used.
1381  */
1382 static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf,
1383                              unsigned long addr, unsigned len)
1384 {
1385         unsigned int insn_len;
1386 
1387         /* Don't do anything special if we don't have a replacement */
1388         if (type >= ARRAY_SIZE(lguest_insns) || !lguest_insns[type].start)
1389                 return paravirt_patch_default(type, clobber, ibuf, addr, len);
1390 
1391         insn_len = lguest_insns[type].end - lguest_insns[type].start;
1392 
1393         /* Similarly if it can't fit (doesn't happen, but let's be thorough). */
1394         if (len < insn_len)
1395                 return paravirt_patch_default(type, clobber, ibuf, addr, len);
1396 
1397         /* Copy in our instructions. */
1398         memcpy(ibuf, lguest_insns[type].start, insn_len);
1399         return insn_len;
1400 }
1401 
1402 /*G:029
1403  * Once we get to lguest_init(), we know we're a Guest.  The various
1404  * pv_ops structures in the kernel provide points for (almost) every routine we
1405  * have to override to avoid privileged instructions.
1406  */
1407 __init void lguest_init(void)
1408 {
1409         /* We're under lguest. */
1410         pv_info.name = "lguest";
1411         /* We're running at privilege level 1, not 0 as normal. */
1412         pv_info.kernel_rpl = 1;
1413         /* Everyone except Xen runs with this set. */
1414         pv_info.shared_kernel_pmd = 1;
1415 
1416         /*
1417          * We set up all the lguest overrides for sensitive operations.  These
1418          * are detailed with the operations themselves.
1419          */
1420 
1421         /* Interrupt-related operations */
1422         pv_irq_ops.save_fl = PV_CALLEE_SAVE(lguest_save_fl);
1423         pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(lg_restore_fl);
1424         pv_irq_ops.irq_disable = PV_CALLEE_SAVE(lguest_irq_disable);
1425         pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(lg_irq_enable);
1426         pv_irq_ops.safe_halt = lguest_safe_halt;
1427 
1428         /* Setup operations */
1429         pv_init_ops.patch = lguest_patch;
1430 
1431         /* Intercepts of various CPU instructions */
1432         pv_cpu_ops.load_gdt = lguest_load_gdt;
1433         pv_cpu_ops.cpuid = lguest_cpuid;
1434         pv_cpu_ops.load_idt = lguest_load_idt;
1435         pv_cpu_ops.iret = lguest_iret;
1436         pv_cpu_ops.load_sp0 = lguest_load_sp0;
1437         pv_cpu_ops.load_tr_desc = lguest_load_tr_desc;
1438         pv_cpu_ops.set_ldt = lguest_set_ldt;
1439         pv_cpu_ops.load_tls = lguest_load_tls;
1440         pv_cpu_ops.get_debugreg = lguest_get_debugreg;
1441         pv_cpu_ops.set_debugreg = lguest_set_debugreg;
1442         pv_cpu_ops.clts = lguest_clts;
1443         pv_cpu_ops.read_cr0 = lguest_read_cr0;
1444         pv_cpu_ops.write_cr0 = lguest_write_cr0;
1445         pv_cpu_ops.read_cr4 = lguest_read_cr4;
1446         pv_cpu_ops.write_cr4 = lguest_write_cr4;
1447         pv_cpu_ops.write_gdt_entry = lguest_write_gdt_entry;
1448         pv_cpu_ops.write_idt_entry = lguest_write_idt_entry;
1449         pv_cpu_ops.wbinvd = lguest_wbinvd;
1450         pv_cpu_ops.start_context_switch = paravirt_start_context_switch;
1451         pv_cpu_ops.end_context_switch = lguest_end_context_switch;
1452 
1453         /* Pagetable management */
1454         pv_mmu_ops.write_cr3 = lguest_write_cr3;
1455         pv_mmu_ops.flush_tlb_user = lguest_flush_tlb_user;
1456         pv_mmu_ops.flush_tlb_single = lguest_flush_tlb_single;
1457         pv_mmu_ops.flush_tlb_kernel = lguest_flush_tlb_kernel;
1458         pv_mmu_ops.set_pte = lguest_set_pte;
1459         pv_mmu_ops.set_pte_at = lguest_set_pte_at;
1460         pv_mmu_ops.set_pmd = lguest_set_pmd;
1461 #ifdef CONFIG_X86_PAE
1462         pv_mmu_ops.set_pte_atomic = lguest_set_pte_atomic;
1463         pv_mmu_ops.pte_clear = lguest_pte_clear;
1464         pv_mmu_ops.pmd_clear = lguest_pmd_clear;
1465         pv_mmu_ops.set_pud = lguest_set_pud;
1466 #endif
1467         pv_mmu_ops.read_cr2 = lguest_read_cr2;
1468         pv_mmu_ops.read_cr3 = lguest_read_cr3;
1469         pv_mmu_ops.lazy_mode.enter = paravirt_enter_lazy_mmu;
1470         pv_mmu_ops.lazy_mode.leave = lguest_leave_lazy_mmu_mode;
1471         pv_mmu_ops.lazy_mode.flush = paravirt_flush_lazy_mmu;
1472         pv_mmu_ops.pte_update = lguest_pte_update;
1473 
1474 #ifdef CONFIG_X86_LOCAL_APIC
1475         /* APIC read/write intercepts */
1476         set_lguest_basic_apic_ops();
1477 #endif
1478 
1479         x86_init.resources.memory_setup = lguest_memory_setup;
1480         x86_init.irqs.intr_init = lguest_init_IRQ;
1481         x86_init.timers.timer_init = lguest_time_init;
1482         x86_platform.calibrate_tsc = lguest_tsc_khz;
1483         x86_platform.get_wallclock =  lguest_get_wallclock;
1484 
1485         /*
1486          * Now is a good time to look at the implementations of these functions
1487          * before returning to the rest of lguest_init().
1488          */
1489 
1490         /*G:070
1491          * Now we've seen all the paravirt_ops, we return to
1492          * lguest_init() where the rest of the fairly chaotic boot setup
1493          * occurs.
1494          */
1495 
1496         /*
1497          * The stack protector is a weird thing where gcc places a canary
1498          * value on the stack and then checks it on return.  This file is
1499          * compiled with -fno-stack-protector it, so we got this far without
1500          * problems.  The value of the canary is kept at offset 20 from the
1501          * %gs register, so we need to set that up before calling C functions
1502          * in other files.
1503          */
1504         setup_stack_canary_segment(0);
1505 
1506         /*
1507          * We could just call load_stack_canary_segment(), but we might as well
1508          * call switch_to_new_gdt() which loads the whole table and sets up the
1509          * per-cpu segment descriptor register %fs as well.
1510          */
1511         switch_to_new_gdt(0);
1512 
1513         /*
1514          * The Host<->Guest Switcher lives at the top of our address space, and
1515          * the Host told us how big it is when we made LGUEST_INIT hypercall:
1516          * it put the answer in lguest_data.reserve_mem
1517          */
1518         reserve_top_address(lguest_data.reserve_mem);
1519 
1520         /* Hook in our special panic hypercall code. */
1521         atomic_notifier_chain_register(&panic_notifier_list, &paniced);
1522 
1523         /*
1524          * This is messy CPU setup stuff which the native boot code does before
1525          * start_kernel, so we have to do, too:
1526          */
1527         cpu_detect(&new_cpu_data);
1528         /* head.S usually sets up the first capability word, so do it here. */
1529         new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
1530 
1531         /* Math is always hard! */
1532         set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
1533 
1534         /* We don't have features.  We have puppies!  Puppies! */
1535 #ifdef CONFIG_X86_MCE
1536         mca_cfg.disabled = true;
1537 #endif
1538 #ifdef CONFIG_ACPI
1539         acpi_disabled = 1;
1540 #endif
1541 
1542         /*
1543          * We set the preferred console to "hvc".  This is the "hypervisor
1544          * virtual console" driver written by the PowerPC people, which we also
1545          * adapted for lguest's use.
1546          */
1547         add_preferred_console("hvc", 0, NULL);
1548 
1549         /* Register our very early console. */
1550         virtio_cons_early_init(early_put_chars);
1551 
1552         /* Don't let ACPI try to control our PCI interrupts. */
1553         disable_acpi();
1554 
1555         /* We control them ourselves, by overriding these two hooks. */
1556         pcibios_enable_irq = lguest_enable_irq;
1557         pcibios_disable_irq = lguest_disable_irq;
1558 
1559         /*
1560          * Last of all, we set the power management poweroff hook to point to
1561          * the Guest routine to power off, and the reboot hook to our restart
1562          * routine.
1563          */
1564         pm_power_off = lguest_power_off;
1565         machine_ops.restart = lguest_restart;
1566 
1567         /*
1568          * Now we're set up, call i386_start_kernel() in head32.c and we proceed
1569          * to boot as normal.  It never returns.
1570          */
1571         i386_start_kernel();
1572 }
1573 /*
1574  * This marks the end of stage II of our journey, The Guest.
1575  *
1576  * It is now time for us to explore the layer of virtual drivers and complete
1577  * our understanding of the Guest in "make Drivers".
1578  */
1579 

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