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Linux/arch/x86/platform/intel-mid/intel-mid.c

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  1 /*
  2  * intel-mid.c: Intel MID platform setup code
  3  *
  4  * (C) Copyright 2008, 2012 Intel Corporation
  5  * Author: Jacob Pan (jacob.jun.pan@intel.com)
  6  * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * as published by the Free Software Foundation; version 2
 11  * of the License.
 12  */
 13 
 14 #define pr_fmt(fmt) "intel_mid: " fmt
 15 
 16 #include <linux/init.h>
 17 #include <linux/kernel.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/scatterlist.h>
 20 #include <linux/sfi.h>
 21 #include <linux/irq.h>
 22 #include <linux/module.h>
 23 #include <linux/notifier.h>
 24 
 25 #include <asm/setup.h>
 26 #include <asm/mpspec_def.h>
 27 #include <asm/hw_irq.h>
 28 #include <asm/apic.h>
 29 #include <asm/io_apic.h>
 30 #include <asm/intel-mid.h>
 31 #include <asm/intel_mid_vrtc.h>
 32 #include <asm/io.h>
 33 #include <asm/i8259.h>
 34 #include <asm/intel_scu_ipc.h>
 35 #include <asm/apb_timer.h>
 36 #include <asm/reboot.h>
 37 
 38 #include "intel_mid_weak_decls.h"
 39 
 40 /*
 41  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
 42  * cmdline option x86_intel_mid_timer can be used to override the configuration
 43  * to prefer one or the other.
 44  * at runtime, there are basically three timer configurations:
 45  * 1. per cpu apbt clock only
 46  * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
 47  * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
 48  *
 49  * by default (without cmdline option), platform code first detects cpu type
 50  * to see if we are on lincroft or penwell, then set up both lapic or apbt
 51  * clocks accordingly.
 52  * i.e. by default, medfield uses configuration #2, moorestown uses #1.
 53  * config #3 is supported but not recommended on medfield.
 54  *
 55  * rating and feature summary:
 56  * lapic (with C3STOP) --------- 100
 57  * apbt (always-on) ------------ 110
 58  * lapic (always-on,ARAT) ------ 150
 59  */
 60 
 61 enum intel_mid_timer_options intel_mid_timer_options;
 62 
 63 /* intel_mid_ops to store sub arch ops */
 64 struct intel_mid_ops *intel_mid_ops;
 65 /* getter function for sub arch ops*/
 66 static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
 67 enum intel_mid_cpu_type __intel_mid_cpu_chip;
 68 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 69 
 70 static void intel_mid_power_off(void)
 71 {
 72 };
 73 
 74 static void intel_mid_reboot(void)
 75 {
 76         intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
 77 }
 78 
 79 static unsigned long __init intel_mid_calibrate_tsc(void)
 80 {
 81         return 0;
 82 }
 83 
 84 static void __init intel_mid_time_init(void)
 85 {
 86         sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
 87         switch (intel_mid_timer_options) {
 88         case INTEL_MID_TIMER_APBT_ONLY:
 89                 break;
 90         case INTEL_MID_TIMER_LAPIC_APBT:
 91                 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
 92                 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
 93                 break;
 94         default:
 95                 if (!boot_cpu_has(X86_FEATURE_ARAT))
 96                         break;
 97                 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
 98                 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
 99                 return;
100         }
101         /* we need at least one APB timer */
102         pre_init_apic_IRQ0();
103         apbt_time_init();
104 }
105 
106 static void intel_mid_arch_setup(void)
107 {
108         if (boot_cpu_data.x86 != 6) {
109                 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
110                         boot_cpu_data.x86, boot_cpu_data.x86_model);
111                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
112                 goto out;
113         }
114 
115         switch (boot_cpu_data.x86_model) {
116         case 0x35:
117                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
118                 break;
119         case 0x3C:
120         case 0x4A:
121                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
122                 break;
123         case 0x27:
124         default:
125                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
126                 break;
127         }
128 
129         if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
130                 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
131         else {
132                 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
133                 pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
134         }
135 
136 out:
137         if (intel_mid_ops->arch_setup)
138                 intel_mid_ops->arch_setup();
139 }
140 
141 /* MID systems don't have i8042 controller */
142 static int intel_mid_i8042_detect(void)
143 {
144         return 0;
145 }
146 
147 /*
148  * Moorestown does not have external NMI source nor port 0x61 to report
149  * NMI status. The possible NMI sources are from pmu as a result of NMI
150  * watchdog or lock debug. Reading io port 0x61 results in 0xff which
151  * misled NMI handler.
152  */
153 static unsigned char intel_mid_get_nmi_reason(void)
154 {
155         return 0;
156 }
157 
158 /*
159  * Moorestown specific x86_init function overrides and early setup
160  * calls.
161  */
162 void __init x86_intel_mid_early_setup(void)
163 {
164         x86_init.resources.probe_roms = x86_init_noop;
165         x86_init.resources.reserve_resources = x86_init_noop;
166 
167         x86_init.timers.timer_init = intel_mid_time_init;
168         x86_init.timers.setup_percpu_clockev = x86_init_noop;
169 
170         x86_init.irqs.pre_vector_init = x86_init_noop;
171 
172         x86_init.oem.arch_setup = intel_mid_arch_setup;
173 
174         x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
175 
176         x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
177         x86_platform.i8042_detect = intel_mid_i8042_detect;
178         x86_init.timers.wallclock_init = intel_mid_rtc_init;
179         x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
180 
181         x86_init.pci.init = intel_mid_pci_init;
182         x86_init.pci.fixup_irqs = x86_init_noop;
183 
184         legacy_pic = &null_legacy_pic;
185 
186         pm_power_off = intel_mid_power_off;
187         machine_ops.emergency_restart  = intel_mid_reboot;
188 
189         /* Avoid searching for BIOS MP tables */
190         x86_init.mpparse.find_smp_config = x86_init_noop;
191         x86_init.mpparse.get_smp_config = x86_init_uint_noop;
192         set_bit(MP_BUS_ISA, mp_bus_not_pci);
193 }
194 
195 /*
196  * if user does not want to use per CPU apb timer, just give it a lower rating
197  * than local apic timer and skip the late per cpu timer init.
198  */
199 static inline int __init setup_x86_intel_mid_timer(char *arg)
200 {
201         if (!arg)
202                 return -EINVAL;
203 
204         if (strcmp("apbt_only", arg) == 0)
205                 intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
206         else if (strcmp("lapic_and_apbt", arg) == 0)
207                 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
208         else {
209                 pr_warn("X86 INTEL_MID timer option %s not recognised"
210                            " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
211                            arg);
212                 return -EINVAL;
213         }
214         return 0;
215 }
216 __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
217 
218 

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