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Linux/arch/x86/platform/intel-mid/intel-mid.c

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  1 /*
  2  * intel-mid.c: Intel MID platform setup code
  3  *
  4  * (C) Copyright 2008, 2012 Intel Corporation
  5  * Author: Jacob Pan (jacob.jun.pan@intel.com)
  6  * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * as published by the Free Software Foundation; version 2
 11  * of the License.
 12  */
 13 
 14 #define pr_fmt(fmt) "intel_mid: " fmt
 15 
 16 #include <linux/init.h>
 17 #include <linux/kernel.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/regulator/machine.h>
 20 #include <linux/scatterlist.h>
 21 #include <linux/sfi.h>
 22 #include <linux/irq.h>
 23 #include <linux/export.h>
 24 #include <linux/notifier.h>
 25 
 26 #include <asm/setup.h>
 27 #include <asm/mpspec_def.h>
 28 #include <asm/hw_irq.h>
 29 #include <asm/apic.h>
 30 #include <asm/io_apic.h>
 31 #include <asm/intel-mid.h>
 32 #include <asm/intel_mid_vrtc.h>
 33 #include <asm/io.h>
 34 #include <asm/i8259.h>
 35 #include <asm/intel_scu_ipc.h>
 36 #include <asm/apb_timer.h>
 37 #include <asm/reboot.h>
 38 
 39 #include "intel_mid_weak_decls.h"
 40 
 41 /*
 42  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
 43  * cmdline option x86_intel_mid_timer can be used to override the configuration
 44  * to prefer one or the other.
 45  * at runtime, there are basically three timer configurations:
 46  * 1. per cpu apbt clock only
 47  * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
 48  * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
 49  *
 50  * by default (without cmdline option), platform code first detects cpu type
 51  * to see if we are on lincroft or penwell, then set up both lapic or apbt
 52  * clocks accordingly.
 53  * i.e. by default, medfield uses configuration #2, moorestown uses #1.
 54  * config #3 is supported but not recommended on medfield.
 55  *
 56  * rating and feature summary:
 57  * lapic (with C3STOP) --------- 100
 58  * apbt (always-on) ------------ 110
 59  * lapic (always-on,ARAT) ------ 150
 60  */
 61 
 62 enum intel_mid_timer_options intel_mid_timer_options;
 63 
 64 /* intel_mid_ops to store sub arch ops */
 65 static struct intel_mid_ops *intel_mid_ops;
 66 /* getter function for sub arch ops*/
 67 static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
 68 enum intel_mid_cpu_type __intel_mid_cpu_chip;
 69 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 70 
 71 static void intel_mid_power_off(void)
 72 {
 73         /* Shut down South Complex via PWRMU */
 74         intel_mid_pwr_power_off();
 75 
 76         /* Only for Tangier, the rest will ignore this command */
 77         intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
 78 };
 79 
 80 static void intel_mid_reboot(void)
 81 {
 82         intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
 83 }
 84 
 85 static unsigned long __init intel_mid_calibrate_tsc(void)
 86 {
 87         return 0;
 88 }
 89 
 90 static void __init intel_mid_setup_bp_timer(void)
 91 {
 92         apbt_time_init();
 93         setup_boot_APIC_clock();
 94 }
 95 
 96 static void __init intel_mid_time_init(void)
 97 {
 98         sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
 99 
100         switch (intel_mid_timer_options) {
101         case INTEL_MID_TIMER_APBT_ONLY:
102                 break;
103         case INTEL_MID_TIMER_LAPIC_APBT:
104                 /* Use apbt and local apic */
105                 x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer;
106                 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
107                 return;
108         default:
109                 if (!boot_cpu_has(X86_FEATURE_ARAT))
110                         break;
111                 /* Lapic only, no apbt */
112                 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
113                 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
114                 return;
115         }
116 
117         x86_init.timers.setup_percpu_clockev = apbt_time_init;
118 }
119 
120 static void intel_mid_arch_setup(void)
121 {
122         if (boot_cpu_data.x86 != 6) {
123                 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
124                         boot_cpu_data.x86, boot_cpu_data.x86_model);
125                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
126                 goto out;
127         }
128 
129         switch (boot_cpu_data.x86_model) {
130         case 0x35:
131                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
132                 break;
133         case 0x3C:
134         case 0x4A:
135                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
136                 break;
137         case 0x27:
138         default:
139                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
140                 break;
141         }
142 
143         if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
144                 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
145         else {
146                 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
147                 pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
148         }
149 
150 out:
151         if (intel_mid_ops->arch_setup)
152                 intel_mid_ops->arch_setup();
153 
154         /*
155          * Intel MID platforms are using explicitly defined regulators.
156          *
157          * Let the regulator core know that we do not have any additional
158          * regulators left. This lets it substitute unprovided regulators with
159          * dummy ones:
160          */
161         regulator_has_full_constraints();
162 }
163 
164 /*
165  * Moorestown does not have external NMI source nor port 0x61 to report
166  * NMI status. The possible NMI sources are from pmu as a result of NMI
167  * watchdog or lock debug. Reading io port 0x61 results in 0xff which
168  * misled NMI handler.
169  */
170 static unsigned char intel_mid_get_nmi_reason(void)
171 {
172         return 0;
173 }
174 
175 /*
176  * Moorestown specific x86_init function overrides and early setup
177  * calls.
178  */
179 void __init x86_intel_mid_early_setup(void)
180 {
181         x86_init.resources.probe_roms = x86_init_noop;
182         x86_init.resources.reserve_resources = x86_init_noop;
183 
184         x86_init.timers.timer_init = intel_mid_time_init;
185         x86_init.timers.setup_percpu_clockev = x86_init_noop;
186         x86_init.timers.wallclock_init = intel_mid_rtc_init;
187 
188         x86_init.irqs.pre_vector_init = x86_init_noop;
189 
190         x86_init.oem.arch_setup = intel_mid_arch_setup;
191 
192         x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
193 
194         x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
195         x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
196 
197         x86_init.pci.init = intel_mid_pci_init;
198         x86_init.pci.fixup_irqs = x86_init_noop;
199 
200         legacy_pic = &null_legacy_pic;
201 
202         pm_power_off = intel_mid_power_off;
203         machine_ops.emergency_restart  = intel_mid_reboot;
204 
205         /* Avoid searching for BIOS MP tables */
206         x86_init.mpparse.find_smp_config = x86_init_noop;
207         x86_init.mpparse.get_smp_config = x86_init_uint_noop;
208         set_bit(MP_BUS_ISA, mp_bus_not_pci);
209 }
210 
211 /*
212  * if user does not want to use per CPU apb timer, just give it a lower rating
213  * than local apic timer and skip the late per cpu timer init.
214  */
215 static inline int __init setup_x86_intel_mid_timer(char *arg)
216 {
217         if (!arg)
218                 return -EINVAL;
219 
220         if (strcmp("apbt_only", arg) == 0)
221                 intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
222         else if (strcmp("lapic_and_apbt", arg) == 0)
223                 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
224         else {
225                 pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
226                         arg);
227                 return -EINVAL;
228         }
229         return 0;
230 }
231 __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
232 

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