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Linux/arch/x86/ras/mce_amd_inj.c

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  1 /*
  2  * A simple MCE injection facility for testing different aspects of the RAS
  3  * code. This driver should be built as module so that it can be loaded
  4  * on production kernels for testing purposes.
  5  *
  6  * This file may be distributed under the terms of the GNU General Public
  7  * License version 2.
  8  *
  9  * Copyright (c) 2010-15:  Borislav Petkov <bp@alien8.de>
 10  *                      Advanced Micro Devices Inc.
 11  */
 12 
 13 #include <linux/kobject.h>
 14 #include <linux/debugfs.h>
 15 #include <linux/device.h>
 16 #include <linux/module.h>
 17 #include <linux/cpu.h>
 18 #include <linux/string.h>
 19 #include <linux/uaccess.h>
 20 #include <linux/pci.h>
 21 
 22 #include <asm/mce.h>
 23 #include <asm/smp.h>
 24 #include <asm/amd_nb.h>
 25 #include <asm/irq_vectors.h>
 26 
 27 #include "../kernel/cpu/mcheck/mce-internal.h"
 28 
 29 /*
 30  * Collect all the MCi_XXX settings
 31  */
 32 static struct mce i_mce;
 33 static struct dentry *dfs_inj;
 34 
 35 static u8 n_banks;
 36 
 37 #define MAX_FLAG_OPT_SIZE       3
 38 #define NBCFG                   0x44
 39 
 40 enum injection_type {
 41         SW_INJ = 0,     /* SW injection, simply decode the error */
 42         HW_INJ,         /* Trigger a #MC */
 43         DFR_INT_INJ,    /* Trigger Deferred error interrupt */
 44         THR_INT_INJ,    /* Trigger threshold interrupt */
 45         N_INJ_TYPES,
 46 };
 47 
 48 static const char * const flags_options[] = {
 49         [SW_INJ] = "sw",
 50         [HW_INJ] = "hw",
 51         [DFR_INT_INJ] = "df",
 52         [THR_INT_INJ] = "th",
 53         NULL
 54 };
 55 
 56 /* Set default injection to SW_INJ */
 57 static enum injection_type inj_type = SW_INJ;
 58 
 59 #define MCE_INJECT_SET(reg)                                             \
 60 static int inj_##reg##_set(void *data, u64 val)                         \
 61 {                                                                       \
 62         struct mce *m = (struct mce *)data;                             \
 63                                                                         \
 64         m->reg = val;                                                   \
 65         return 0;                                                       \
 66 }
 67 
 68 MCE_INJECT_SET(status);
 69 MCE_INJECT_SET(misc);
 70 MCE_INJECT_SET(addr);
 71 
 72 #define MCE_INJECT_GET(reg)                                             \
 73 static int inj_##reg##_get(void *data, u64 *val)                        \
 74 {                                                                       \
 75         struct mce *m = (struct mce *)data;                             \
 76                                                                         \
 77         *val = m->reg;                                                  \
 78         return 0;                                                       \
 79 }
 80 
 81 MCE_INJECT_GET(status);
 82 MCE_INJECT_GET(misc);
 83 MCE_INJECT_GET(addr);
 84 
 85 DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
 86 DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
 87 DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
 88 
 89 /*
 90  * Caller needs to be make sure this cpu doesn't disappear
 91  * from under us, i.e.: get_cpu/put_cpu.
 92  */
 93 static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
 94 {
 95         u32 l, h;
 96         int err;
 97 
 98         err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
 99         if (err) {
100                 pr_err("%s: error reading HWCR\n", __func__);
101                 return err;
102         }
103 
104         enable ? (l |= BIT(18)) : (l &= ~BIT(18));
105 
106         err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
107         if (err)
108                 pr_err("%s: error writing HWCR\n", __func__);
109 
110         return err;
111 }
112 
113 static int __set_inj(const char *buf)
114 {
115         int i;
116 
117         for (i = 0; i < N_INJ_TYPES; i++) {
118                 if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
119                         inj_type = i;
120                         return 0;
121                 }
122         }
123         return -EINVAL;
124 }
125 
126 static ssize_t flags_read(struct file *filp, char __user *ubuf,
127                           size_t cnt, loff_t *ppos)
128 {
129         char buf[MAX_FLAG_OPT_SIZE];
130         int n;
131 
132         n = sprintf(buf, "%s\n", flags_options[inj_type]);
133 
134         return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
135 }
136 
137 static ssize_t flags_write(struct file *filp, const char __user *ubuf,
138                            size_t cnt, loff_t *ppos)
139 {
140         char buf[MAX_FLAG_OPT_SIZE], *__buf;
141         int err;
142 
143         if (cnt > MAX_FLAG_OPT_SIZE)
144                 return -EINVAL;
145 
146         if (copy_from_user(&buf, ubuf, cnt))
147                 return -EFAULT;
148 
149         buf[cnt - 1] = 0;
150 
151         /* strip whitespace */
152         __buf = strstrip(buf);
153 
154         err = __set_inj(__buf);
155         if (err) {
156                 pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
157                 return err;
158         }
159 
160         *ppos += cnt;
161 
162         return cnt;
163 }
164 
165 static const struct file_operations flags_fops = {
166         .read           = flags_read,
167         .write          = flags_write,
168         .llseek         = generic_file_llseek,
169 };
170 
171 /*
172  * On which CPU to inject?
173  */
174 MCE_INJECT_GET(extcpu);
175 
176 static int inj_extcpu_set(void *data, u64 val)
177 {
178         struct mce *m = (struct mce *)data;
179 
180         if (val >= nr_cpu_ids || !cpu_online(val)) {
181                 pr_err("%s: Invalid CPU: %llu\n", __func__, val);
182                 return -EINVAL;
183         }
184         m->extcpu = val;
185         return 0;
186 }
187 
188 DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
189 
190 static void trigger_mce(void *info)
191 {
192         asm volatile("int $18");
193 }
194 
195 static void trigger_dfr_int(void *info)
196 {
197         asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
198 }
199 
200 static void trigger_thr_int(void *info)
201 {
202         asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
203 }
204 
205 static u32 get_nbc_for_node(int node_id)
206 {
207         struct cpuinfo_x86 *c = &boot_cpu_data;
208         u32 cores_per_node;
209 
210         cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket();
211 
212         return cores_per_node * node_id;
213 }
214 
215 static void toggle_nb_mca_mst_cpu(u16 nid)
216 {
217         struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
218         u32 val;
219         int err;
220 
221         if (!F3)
222                 return;
223 
224         err = pci_read_config_dword(F3, NBCFG, &val);
225         if (err) {
226                 pr_err("%s: Error reading F%dx%03x.\n",
227                        __func__, PCI_FUNC(F3->devfn), NBCFG);
228                 return;
229         }
230 
231         if (val & BIT(27))
232                 return;
233 
234         pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
235                __func__);
236 
237         val |= BIT(27);
238         err = pci_write_config_dword(F3, NBCFG, val);
239         if (err)
240                 pr_err("%s: Error writing F%dx%03x.\n",
241                        __func__, PCI_FUNC(F3->devfn), NBCFG);
242 }
243 
244 static void do_inject(void)
245 {
246         u64 mcg_status = 0;
247         unsigned int cpu = i_mce.extcpu;
248         u8 b = i_mce.bank;
249 
250         if (i_mce.misc)
251                 i_mce.status |= MCI_STATUS_MISCV;
252 
253         if (inj_type == SW_INJ) {
254                 mce_inject_log(&i_mce);
255                 return;
256         }
257 
258         /* prep MCE global settings for the injection */
259         mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
260 
261         if (!(i_mce.status & MCI_STATUS_PCC))
262                 mcg_status |= MCG_STATUS_RIPV;
263 
264         /*
265          * Ensure necessary status bits for deferred errors:
266          * - MCx_STATUS[Deferred]: make sure it is a deferred error
267          * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
268          */
269         if (inj_type == DFR_INT_INJ) {
270                 i_mce.status |= MCI_STATUS_DEFERRED;
271                 i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
272         }
273 
274         /*
275          * For multi node CPUs, logging and reporting of bank 4 errors happens
276          * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
277          * Fam10h and later BKDGs.
278          */
279         if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
280                 toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
281                 cpu = get_nbc_for_node(amd_get_nb_id(cpu));
282         }
283 
284         get_online_cpus();
285         if (!cpu_online(cpu))
286                 goto err;
287 
288         toggle_hw_mce_inject(cpu, true);
289 
290         wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
291                      (u32)mcg_status, (u32)(mcg_status >> 32));
292 
293         wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
294                      (u32)i_mce.status, (u32)(i_mce.status >> 32));
295 
296         wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
297                      (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
298 
299         wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
300                      (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
301 
302         toggle_hw_mce_inject(cpu, false);
303 
304         switch (inj_type) {
305         case DFR_INT_INJ:
306                 smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
307                 break;
308         case THR_INT_INJ:
309                 smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
310                 break;
311         default:
312                 smp_call_function_single(cpu, trigger_mce, NULL, 0);
313         }
314 
315 err:
316         put_online_cpus();
317 
318 }
319 
320 /*
321  * This denotes into which bank we're injecting and triggers
322  * the injection, at the same time.
323  */
324 static int inj_bank_set(void *data, u64 val)
325 {
326         struct mce *m = (struct mce *)data;
327 
328         if (val >= n_banks) {
329                 pr_err("Non-existent MCE bank: %llu\n", val);
330                 return -EINVAL;
331         }
332 
333         m->bank = val;
334         do_inject();
335 
336         return 0;
337 }
338 
339 MCE_INJECT_GET(bank);
340 
341 DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
342 
343 static const char readme_msg[] =
344 "Description of the files and their usages:\n"
345 "\n"
346 "Note1: i refers to the bank number below.\n"
347 "Note2: See respective BKDGs for the exact bit definitions of the files below\n"
348 "as they mirror the hardware registers.\n"
349 "\n"
350 "status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
351 "\t attributes of the error which caused the MCE.\n"
352 "\n"
353 "misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
354 "\t used for error thresholding purposes and its validity is indicated by\n"
355 "\t MCi_STATUS[MiscV].\n"
356 "\n"
357 "addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
358 "\t associated with the error.\n"
359 "\n"
360 "cpu:\t The CPU to inject the error on.\n"
361 "\n"
362 "bank:\t Specify the bank you want to inject the error into: the number of\n"
363 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
364 "\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
365 "\t injection.\n"
366 "\n"
367 "flags:\t Injection type to be performed. Writing to this file will trigger a\n"
368 "\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
369 "\t for AMD processors.\n"
370 "\n"
371 "\t Allowed error injection types:\n"
372 "\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
373 "\t    format only. Safe to use.\n"
374 "\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
375 "\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
376 "\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
377 "\t    before injecting.\n"
378 "\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
379 "\t    error APIC interrupt handler to handle the error if the feature is \n"
380 "\t    is present in hardware. \n"
381 "\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
382 "\t    APIC interrupt handler to handle the error. \n"
383 "\n";
384 
385 static ssize_t
386 inj_readme_read(struct file *filp, char __user *ubuf,
387                        size_t cnt, loff_t *ppos)
388 {
389         return simple_read_from_buffer(ubuf, cnt, ppos,
390                                         readme_msg, strlen(readme_msg));
391 }
392 
393 static const struct file_operations readme_fops = {
394         .read           = inj_readme_read,
395 };
396 
397 static struct dfs_node {
398         char *name;
399         struct dentry *d;
400         const struct file_operations *fops;
401         umode_t perm;
402 } dfs_fls[] = {
403         { .name = "status",     .fops = &status_fops, .perm = S_IRUSR | S_IWUSR },
404         { .name = "misc",       .fops = &misc_fops,   .perm = S_IRUSR | S_IWUSR },
405         { .name = "addr",       .fops = &addr_fops,   .perm = S_IRUSR | S_IWUSR },
406         { .name = "bank",       .fops = &bank_fops,   .perm = S_IRUSR | S_IWUSR },
407         { .name = "flags",      .fops = &flags_fops,  .perm = S_IRUSR | S_IWUSR },
408         { .name = "cpu",        .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR },
409         { .name = "README",     .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH },
410 };
411 
412 static int __init init_mce_inject(void)
413 {
414         int i;
415         u64 cap;
416 
417         rdmsrl(MSR_IA32_MCG_CAP, cap);
418         n_banks = cap & MCG_BANKCNT_MASK;
419 
420         dfs_inj = debugfs_create_dir("mce-inject", NULL);
421         if (!dfs_inj)
422                 return -EINVAL;
423 
424         for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
425                 dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
426                                                     dfs_fls[i].perm,
427                                                     dfs_inj,
428                                                     &i_mce,
429                                                     dfs_fls[i].fops);
430 
431                 if (!dfs_fls[i].d)
432                         goto err_dfs_add;
433         }
434 
435         return 0;
436 
437 err_dfs_add:
438         while (--i >= 0)
439                 debugfs_remove(dfs_fls[i].d);
440 
441         debugfs_remove(dfs_inj);
442         dfs_inj = NULL;
443 
444         return -ENOMEM;
445 }
446 
447 static void __exit exit_mce_inject(void)
448 {
449         int i;
450 
451         for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
452                 debugfs_remove(dfs_fls[i].d);
453 
454         memset(&dfs_fls, 0, sizeof(dfs_fls));
455 
456         debugfs_remove(dfs_inj);
457         dfs_inj = NULL;
458 }
459 module_init(init_mce_inject);
460 module_exit(exit_mce_inject);
461 
462 MODULE_LICENSE("GPL");
463 MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
464 MODULE_AUTHOR("AMD Inc.");
465 MODULE_DESCRIPTION("MCE injection facility for RAS testing");
466 

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