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TOMOYO Linux Cross Reference
Linux/arch/x86_64/kernel/io_apic.c

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  1 /*
  2  *      Intel IO-APIC support for multi-Pentium hosts.
  3  *
  4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
  5  *
  6  *      Many thanks to Stig Venaas for trying out countless experimental
  7  *      patches and reporting/debugging problems patiently!
  8  *
  9  *      (c) 1999, Multiple IO-APIC support, developed by
 10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
 13  *      and Ingo Molnar <mingo@redhat.com>
 14  *
 15  *      Fixes
 16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
 17  *                                      thanks to Eric Gilmore
 18  *                                      and Rolf G. Tews
 19  *                                      for testing these extensively
 20  *      Paul Diefenbaugh        :       Added full ACPI support
 21  */
 22 
 23 #include <linux/mm.h>
 24 #include <linux/irq.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/init.h>
 27 #include <linux/delay.h>
 28 #include <linux/sched.h>
 29 #include <linux/config.h>
 30 #include <linux/smp_lock.h>
 31 #include <linux/mc146818rtc.h>
 32 #include <linux/acpi.h>
 33 
 34 #include <asm/io.h>
 35 #include <asm/smp.h>
 36 #include <asm/desc.h>
 37 
 38 int sis_apic_bug; /* not actually supported, dummy for compile */
 39 
 40 #undef APIC_LOCKUP_DEBUG
 41 
 42 #define APIC_LOCKUP_DEBUG
 43 
 44 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
 45 
 46 /*
 47  * # of IRQ routing registers
 48  */
 49 int nr_ioapic_registers[MAX_IO_APICS];
 50 
 51 /*
 52  * Rough estimation of how many shared IRQs there are, can
 53  * be changed anytime.
 54  */
 55 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 56 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 57 
 58 /*
 59  * This is performance-critical, we want to do it O(1)
 60  *
 61  * the indexing order of this array favors 1:1 mappings
 62  * between pins and IRQs.
 63  */
 64 
 65 static struct irq_pin_list {
 66         short apic, pin, next;
 67 } irq_2_pin[PIN_MAP_SIZE];
 68 
 69 /*
 70  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 71  * shared ISA-space IRQs, so we have to support them. We are super
 72  * fast in the common case, and fast for shared ISA-space IRQs.
 73  */
 74 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
 75 {
 76         static int first_free_entry = NR_IRQS;
 77         struct irq_pin_list *entry = irq_2_pin + irq;
 78 
 79         while (entry->next)
 80                 entry = irq_2_pin + entry->next;
 81 
 82         if (entry->pin != -1) {
 83                 entry->next = first_free_entry;
 84                 entry = irq_2_pin + entry->next;
 85                 if (++first_free_entry >= PIN_MAP_SIZE)
 86                         panic("io_apic.c: whoops");
 87         }
 88         entry->apic = apic;
 89         entry->pin = pin;
 90 }
 91 
 92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 93                                                                         \
 94 {                                                                       \
 95         int pin;                                                        \
 96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 97                                                                         \
 98         for (;;) {                                                      \
 99                 unsigned int reg;                                       \
100                 pin = entry->pin;                                       \
101                 if (pin == -1)                                          \
102                         break;                                          \
103                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
104                 reg ACTION;                                             \
105                 io_apic_modify(entry->apic, reg);                       \
106                 if (!entry->next)                                       \
107                         break;                                          \
108                 entry = irq_2_pin + entry->next;                        \
109         }                                                               \
110         FINAL;                                                          \
111 }
112 
113 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
114                                                                         \
115         static void name##_IO_APIC_irq (unsigned int irq)               \
116         __DO_ACTION(R, ACTION, FINAL)
117 
118 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
119                                                 /* mask = 1 */
120 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
121                                                 /* mask = 0 */
122 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
123                                                 /* mask = 1, trigger = 0 */
124 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
125                                                 /* mask = 0, trigger = 1 */
126 
127 static void mask_IO_APIC_irq (unsigned int irq)
128 {
129         unsigned long flags;
130 
131         spin_lock_irqsave(&ioapic_lock, flags);
132         __mask_IO_APIC_irq(irq);
133         spin_unlock_irqrestore(&ioapic_lock, flags);
134 }
135 
136 static void unmask_IO_APIC_irq (unsigned int irq)
137 {
138         unsigned long flags;
139 
140         spin_lock_irqsave(&ioapic_lock, flags);
141         __unmask_IO_APIC_irq(irq);
142         spin_unlock_irqrestore(&ioapic_lock, flags);
143 }
144 
145 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
146 {
147         struct IO_APIC_route_entry entry;
148         unsigned long flags;
149 
150         /*
151          * Disable it in the IO-APIC irq-routing table:
152          */
153         memset(&entry, 0, sizeof(entry));
154         entry.mask = 1;
155         spin_lock_irqsave(&ioapic_lock, flags);
156         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
157         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
158         spin_unlock_irqrestore(&ioapic_lock, flags);
159 }
160 
161 static void clear_IO_APIC (void)
162 {
163         int apic, pin;
164 
165         for (apic = 0; apic < nr_ioapics; apic++)
166                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
167                         clear_IO_APIC_pin(apic, pin);
168 }
169 
170 /*
171  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
172  * specific CPU-side IRQs.
173  */
174 
175 #define MAX_PIRQS 8
176 int pirq_entries [MAX_PIRQS];
177 int pirqs_enabled;
178 int skip_ioapic_setup;
179 int ioapic_force;
180 
181 /* dummy parsing: see setup.c */
182 
183 static int __init disable_ioapic_setup(char *str)
184 {
185         skip_ioapic_setup = 1;
186         return 1;
187 }
188 
189 static int __init enable_ioapic_setup(char *str)
190 {
191         ioapic_force = 1;
192         skip_ioapic_setup = 0;
193         return 1;
194 }
195 
196 __setup("noapic", disable_ioapic_setup);
197 __setup("apic", enable_ioapic_setup);
198 
199 #ifndef CONFIG_SMP
200 #include <asm/pci-direct.h>
201 #include <linux/pci_ids.h>
202 #include <linux/pci.h>
203 
204 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
205    off. Check for an Nvidia or VIA PCI bridge and turn it off.
206    Use pci direct infrastructure because this runs before the PCI subsystem. 
207 
208    Can be overwritten with "apic" */
209 void __init check_ioapic(void) 
210 { 
211         int num,slot,func; 
212         if (ioapic_force) 
213                 return; 
214 
215         /* Poor man's PCI discovery */
216         for (num = 0; num < 32; num++) { 
217                 for (slot = 0; slot < 32; slot++) { 
218                         for (func = 0; func < 8; func++) { 
219                                 u32 class;
220                                 u32 vendor;
221                                 class = read_pci_config(num,slot,func,
222                                                         PCI_CLASS_REVISION);
223                                 if (class == 0xffffffff)
224                                         break; 
225 
226                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
227                                         continue; 
228 
229                                 vendor = read_pci_config(num, slot, func, 
230                                                          PCI_VENDOR_ID);
231                                 vendor &= 0xffff;
232                                 switch (vendor) { 
233                                 case PCI_VENDOR_ID_NVIDIA: 
234                                 case PCI_VENDOR_ID_VIA:
235                                         printk(KERN_INFO 
236      "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
237                                                num,slot,vendor); 
238                                         skip_ioapic_setup = 1;
239                                         return;
240                                 } 
241 
242                                 /* No multi-function device? */
243                                 u8 type = read_pci_config_byte(num,slot,func,
244                                                                PCI_HEADER_TYPE);
245                                 if (!(type & 0x80))
246                                         break;
247                         } 
248                 }
249         }
250 } 
251 #endif
252 
253 static int __init ioapic_pirq_setup(char *str)
254 {
255         int i, max;
256         int ints[MAX_PIRQS+1];
257 
258         get_options(str, ARRAY_SIZE(ints), ints);
259 
260         for (i = 0; i < MAX_PIRQS; i++)
261                 pirq_entries[i] = -1;
262 
263         pirqs_enabled = 1;
264         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
265         max = MAX_PIRQS;
266         if (ints[0] < MAX_PIRQS)
267                 max = ints[0];
268 
269         for (i = 0; i < max; i++) {
270                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
271                 /*
272                  * PIRQs are mapped upside down, usually.
273                  */
274                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
275         }
276         return 1;
277 }
278 
279 __setup("pirq=", ioapic_pirq_setup);
280 
281 /*
282  * Find the IRQ entry number of a certain pin.
283  */
284 static int __init find_irq_entry(int apic, int pin, int type)
285 {
286         int i;
287 
288         for (i = 0; i < mp_irq_entries; i++)
289                 if (mp_irqs[i].mpc_irqtype == type &&
290                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
291                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
292                     mp_irqs[i].mpc_dstirq == pin)
293                         return i;
294 
295         return -1;
296 }
297 
298 /*
299  * Find the pin to which IRQ[irq] (ISA) is connected
300  */
301 static int __init find_isa_irq_pin(int irq, int type)
302 {
303         int i;
304 
305         for (i = 0; i < mp_irq_entries; i++) {
306                 int lbus = mp_irqs[i].mpc_srcbus;
307 
308                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
309                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
310                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
311                     (mp_irqs[i].mpc_irqtype == type) &&
312                     (mp_irqs[i].mpc_srcbusirq == irq))
313 
314                         return mp_irqs[i].mpc_dstirq;
315         }
316         return -1;
317 }
318 
319 /*
320  * Find a specific PCI IRQ entry.
321  * Not an __init, possibly needed by modules
322  */
323 static int pin_2_irq(int idx, int apic, int pin);
324 
325 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
326 {
327         int apic, i, best_guess = -1;
328 
329         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
330                 bus, slot, pin);
331         if (mp_bus_id_to_pci_bus[bus] == -1) {
332                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
333                 return -1;
334         }
335         for (i = 0; i < mp_irq_entries; i++) {
336                 int lbus = mp_irqs[i].mpc_srcbus;
337 
338                 for (apic = 0; apic < nr_ioapics; apic++)
339                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
340                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
341                                 break;
342 
343                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
344                     !mp_irqs[i].mpc_irqtype &&
345                     (bus == lbus) &&
346                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
347                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
348 
349                         if (!(apic || IO_APIC_IRQ(irq)))
350                                 continue;
351 
352                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
353                                 return irq;
354                         /*
355                          * Use the first all-but-pin matching entry as a
356                          * best-guess fuzzy result for broken mptables.
357                          */
358                         if (best_guess < 0)
359                                 best_guess = irq;
360                 }
361         }
362         return best_guess;
363 }
364 
365 /*
366  * EISA Edge/Level control register, ELCR
367  */
368 static int __init EISA_ELCR(unsigned int irq)
369 {
370         if (irq < 16) {
371                 unsigned int port = 0x4d0 + (irq >> 3);
372                 return (inb(port) >> (irq & 7)) & 1;
373         }
374         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
375         return 0;
376 }
377 
378 /* EISA interrupts are always polarity zero and can be edge or level
379  * trigger depending on the ELCR value.  If an interrupt is listed as
380  * EISA conforming in the MP table, that means its trigger type must
381  * be read in from the ELCR */
382 
383 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
384 #define default_EISA_polarity(idx)      (0)
385 
386 /* ISA interrupts are always polarity zero edge triggered,
387  * when listed as conforming in the MP table. */
388 
389 #define default_ISA_trigger(idx)        (0)
390 #define default_ISA_polarity(idx)       (0)
391 
392 /* PCI interrupts are always polarity one level triggered,
393  * when listed as conforming in the MP table. */
394 
395 #define default_PCI_trigger(idx)        (1)
396 #define default_PCI_polarity(idx)       (1)
397 
398 /* MCA interrupts are always polarity zero level triggered,
399  * when listed as conforming in the MP table. */
400 
401 #define default_MCA_trigger(idx)        (1)
402 #define default_MCA_polarity(idx)       (0)
403 
404 static int __init MPBIOS_polarity(int idx)
405 {
406         int bus = mp_irqs[idx].mpc_srcbus;
407         int polarity;
408 
409         /*
410          * Determine IRQ line polarity (high active or low active):
411          */
412         switch (mp_irqs[idx].mpc_irqflag & 3)
413         {
414                 case 0: /* conforms, ie. bus-type dependent polarity */
415                 {
416                         switch (mp_bus_id_to_type[bus])
417                         {
418                                 case MP_BUS_ISA: /* ISA pin */
419                                 {
420                                         polarity = default_ISA_polarity(idx);
421                                         break;
422                                 }
423                                 case MP_BUS_EISA: /* EISA pin */
424                                 {
425                                         polarity = default_EISA_polarity(idx);
426                                         break;
427                                 }
428                                 case MP_BUS_PCI: /* PCI pin */
429                                 {
430                                         polarity = default_PCI_polarity(idx);
431                                         break;
432                                 }
433                                 case MP_BUS_MCA: /* MCA pin */
434                                 {
435                                         polarity = default_MCA_polarity(idx);
436                                         break;
437                                 }
438                                 default:
439                                 {
440                                         printk(KERN_WARNING "broken BIOS!!\n");
441                                         polarity = 1;
442                                         break;
443                                 }
444                         }
445                         break;
446                 }
447                 case 1: /* high active */
448                 {
449                         polarity = 0;
450                         break;
451                 }
452                 case 2: /* reserved */
453                 {
454                         printk(KERN_WARNING "broken BIOS!!\n");
455                         polarity = 1;
456                         break;
457                 }
458                 case 3: /* low active */
459                 {
460                         polarity = 1;
461                         break;
462                 }
463                 default: /* invalid */
464                 {
465                         printk(KERN_WARNING "broken BIOS!!\n");
466                         polarity = 1;
467                         break;
468                 }
469         }
470         return polarity;
471 }
472 
473 static int __init MPBIOS_trigger(int idx)
474 {
475         int bus = mp_irqs[idx].mpc_srcbus;
476         int trigger;
477 
478         /*
479          * Determine IRQ trigger mode (edge or level sensitive):
480          */
481         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
482         {
483                 case 0: /* conforms, ie. bus-type dependent */
484                 {
485                         switch (mp_bus_id_to_type[bus])
486                         {
487                                 case MP_BUS_ISA: /* ISA pin */
488                                 {
489                                         trigger = default_ISA_trigger(idx);
490                                         break;
491                                 }
492                                 case MP_BUS_EISA: /* EISA pin */
493                                 {
494                                         trigger = default_EISA_trigger(idx);
495                                         break;
496                                 }
497                                 case MP_BUS_PCI: /* PCI pin */
498                                 {
499                                         trigger = default_PCI_trigger(idx);
500                                         break;
501                                 }
502                                 case MP_BUS_MCA: /* MCA pin */
503                                 {
504                                         trigger = default_MCA_trigger(idx);
505                                         break;
506                                 }
507                                 default:
508                                 {
509                                         printk(KERN_WARNING "broken BIOS!!\n");
510                                         trigger = 1;
511                                         break;
512                                 }
513                         }
514                         break;
515                 }
516                 case 1: /* edge */
517                 {
518                         trigger = 0;
519                         break;
520                 }
521                 case 2: /* reserved */
522                 {
523                         printk(KERN_WARNING "broken BIOS!!\n");
524                         trigger = 1;
525                         break;
526                 }
527                 case 3: /* level */
528                 {
529                         trigger = 1;
530                         break;
531                 }
532                 default: /* invalid */
533                 {
534                         printk(KERN_WARNING "broken BIOS!!\n");
535                         trigger = 0;
536                         break;
537                 }
538         }
539         return trigger;
540 }
541 
542 static inline int irq_polarity(int idx)
543 {
544         return MPBIOS_polarity(idx);
545 }
546 
547 static inline int irq_trigger(int idx)
548 {
549         return MPBIOS_trigger(idx);
550 }
551 
552 static int pin_2_irq(int idx, int apic, int pin)
553 {
554         int irq, i;
555         int bus = mp_irqs[idx].mpc_srcbus;
556 
557         /*
558          * Debugging check, we are in big trouble if this message pops up!
559          */
560         if (mp_irqs[idx].mpc_dstirq != pin)
561                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
562 
563         switch (mp_bus_id_to_type[bus])
564         {
565                 case MP_BUS_ISA: /* ISA pin */
566                 case MP_BUS_EISA:
567                 case MP_BUS_MCA:
568                 {
569                         irq = mp_irqs[idx].mpc_srcbusirq;
570                         break;
571                 }
572                 case MP_BUS_PCI: /* PCI pin */
573                 {
574                         /*
575                          * PCI IRQs are mapped in order
576                          */
577                         i = irq = 0;
578                         while (i < apic)
579                                 irq += nr_ioapic_registers[i++];
580                         irq += pin;
581                         break;
582                 }
583                 default:
584                 {
585                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
586                         irq = 0;
587                         break;
588                 }
589         }
590 
591         /*
592          * PCI IRQ command line redirection. Yes, limits are hardcoded.
593          */
594         if ((pin >= 16) && (pin <= 23)) {
595                 if (pirq_entries[pin-16] != -1) {
596                         if (!pirq_entries[pin-16]) {
597                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
598                         } else {
599                                 irq = pirq_entries[pin-16];
600                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
601                                                 pin-16, irq);
602                         }
603                 }
604         }
605         return irq;
606 }
607 
608 static inline int IO_APIC_irq_trigger(int irq)
609 {
610         int apic, idx, pin;
611 
612         for (apic = 0; apic < nr_ioapics; apic++) {
613                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
614                         idx = find_irq_entry(apic,pin,mp_INT);
615                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
616                                 return irq_trigger(idx);
617                 }
618         }
619         /*
620          * nonexistent IRQs are edge default
621          */
622         return 0;
623 }
624 
625 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
626 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
627 
628 static int __init assign_irq_vector(int irq)
629 {
630         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
631         BUG_ON(irq >= NR_IRQ_VECTORS);
632         if (IO_APIC_VECTOR(irq) > 0)
633                 return IO_APIC_VECTOR(irq);
634 next:
635         current_vector += 8;
636         if (current_vector == IA32_SYSCALL_VECTOR)
637                 goto next;
638 
639         if (current_vector > FIRST_SYSTEM_VECTOR) {
640                 offset++;
641                 current_vector = FIRST_DEVICE_VECTOR + offset;
642         }
643 
644         if (current_vector == FIRST_SYSTEM_VECTOR)
645                 panic("ran out of interrupt sources!");
646 
647         IO_APIC_VECTOR(irq) = current_vector;
648         return current_vector;
649 }
650 
651 extern void (*interrupt[NR_IRQS])(void);
652 static struct hw_interrupt_type ioapic_level_irq_type;
653 static struct hw_interrupt_type ioapic_edge_irq_type;
654 
655 void __init setup_IO_APIC_irqs(void)
656 {
657         struct IO_APIC_route_entry entry;
658         int apic, pin, idx, irq, first_notcon = 1, vector;
659         unsigned long flags;
660 
661         printk(KERN_DEBUG "init IO_APIC IRQs\n");
662 
663         for (apic = 0; apic < nr_ioapics; apic++) {
664         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
665 
666                 /*
667                  * add it to the IO-APIC irq-routing table:
668                  */
669                 memset(&entry,0,sizeof(entry));
670 
671                 entry.delivery_mode = dest_LowestPrio;
672                 entry.dest_mode = INT_DELIVERY_MODE;
673                 entry.mask = 0;                         /* enable IRQ */
674                 entry.dest.logical.logical_dest = TARGET_CPUS;
675 
676                 idx = find_irq_entry(apic,pin,mp_INT);
677                 if (idx == -1) {
678                         if (first_notcon) {
679                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
680                                 first_notcon = 0;
681                         } else
682                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
683                         continue;
684                 }
685 
686                 entry.trigger = irq_trigger(idx);
687                 entry.polarity = irq_polarity(idx);
688 
689                 if (irq_trigger(idx)) {
690                         entry.trigger = 1;
691                         entry.mask = 1;
692                         entry.dest.logical.logical_dest = TARGET_CPUS;
693                 }
694 
695                 irq = pin_2_irq(idx, apic, pin);
696                 add_pin_to_irq(irq, apic, pin);
697 
698                 if (!apic && !IO_APIC_IRQ(irq))
699                         continue;
700 
701                 if (IO_APIC_IRQ(irq)) {
702                         vector = assign_irq_vector(irq);
703                         entry.vector = vector;
704 
705                         if (IO_APIC_irq_trigger(irq))
706                                 irq_desc[irq].handler = &ioapic_level_irq_type;
707                         else
708                                 irq_desc[irq].handler = &ioapic_edge_irq_type;
709 
710                         set_intr_gate(vector, interrupt[irq]);
711                 
712                         if (!apic && (irq < 16))
713                                 disable_8259A_irq(irq);
714                 }
715                 spin_lock_irqsave(&ioapic_lock, flags);
716                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
717                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
718                 spin_unlock_irqrestore(&ioapic_lock, flags);
719         }
720         }
721 
722         if (!first_notcon)
723                 printk(" not connected.\n");
724 }
725 
726 /*
727  * Set up the 8259A-master output pin as broadcast to all
728  * CPUs.
729  */
730 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
731 {
732         struct IO_APIC_route_entry entry;
733         unsigned long flags;
734 
735         memset(&entry,0,sizeof(entry));
736 
737         disable_8259A_irq(0);
738 
739         /* mask LVT0 */
740         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
741 
742         /*
743          * We use logical delivery to get the timer IRQ
744          * to the first CPU.
745          */
746         entry.dest_mode = INT_DELIVERY_MODE;
747         entry.mask = 0;                                 /* unmask IRQ now */
748         entry.dest.logical.logical_dest = TARGET_CPUS;
749         entry.delivery_mode = dest_LowestPrio;
750         entry.polarity = 0;
751         entry.trigger = 0;
752         entry.vector = vector;
753 
754         /*
755          * The timer IRQ doesn't have to know that behind the
756          * scene we have a 8259A-master in AEOI mode ...
757          */
758         irq_desc[0].handler = &ioapic_edge_irq_type;
759 
760         /*
761          * Add it to the IO-APIC irq-routing table:
762          */
763         spin_lock_irqsave(&ioapic_lock, flags);
764         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
765         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
766         spin_unlock_irqrestore(&ioapic_lock, flags);
767 
768         enable_8259A_irq(0);
769 }
770 
771 void __init UNEXPECTED_IO_APIC(void)
772 {
773 #if 0
774         printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
775         printk(KERN_WARNING "          to linux-smp@vger.kernel.org\n");
776 #endif
777 }
778 
779 void __init print_IO_APIC(void)
780 {
781         int apic, i;
782         union IO_APIC_reg_00 reg_00;
783         union IO_APIC_reg_01 reg_01;
784         union IO_APIC_reg_02 reg_02;
785         unsigned long flags;
786 
787         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
788         for (i = 0; i < nr_ioapics; i++)
789                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
790                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
791 
792         /*
793          * We are a bit conservative about what we expect.  We have to
794          * know about every hardware change ASAP.
795          */
796         printk(KERN_INFO "testing the IO APIC.......................\n");
797 
798         for (apic = 0; apic < nr_ioapics; apic++) {
799 
800         spin_lock_irqsave(&ioapic_lock, flags);
801         reg_00.raw = io_apic_read(apic, 0);
802         reg_01.raw = io_apic_read(apic, 1);
803         if (reg_01.bits.version >= 0x10)
804                 reg_02.raw = io_apic_read(apic, 2);
805         spin_unlock_irqrestore(&ioapic_lock, flags);
806 
807         printk("\n");
808         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
809         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
810         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
811         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
812                 UNEXPECTED_IO_APIC();
813 
814         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
815         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
816         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
817                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
818                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
819                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
820                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
821                 (reg_01.bits.entries != 0x2E) &&
822                 (reg_01.bits.entries != 0x3F) &&
823                 (reg_01.bits.entries != 0x03) 
824         )
825                 UNEXPECTED_IO_APIC();
826 
827         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
828         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
829         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
830                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
831                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
832                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
833                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
834                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
835         )
836                 UNEXPECTED_IO_APIC();
837         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
838                 UNEXPECTED_IO_APIC();
839 
840         if (reg_01.bits.version >= 0x10) {
841                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
842                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
843                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
844                         UNEXPECTED_IO_APIC();
845         }
846 
847         printk(KERN_DEBUG ".... IRQ redirection table:\n");
848 
849         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
850                           " Stat Dest Deli Vect:   \n");
851 
852         for (i = 0; i <= reg_01.bits.entries; i++) {
853                 struct IO_APIC_route_entry entry;
854 
855                 spin_lock_irqsave(&ioapic_lock, flags);
856                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
857                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
858                 spin_unlock_irqrestore(&ioapic_lock, flags);
859 
860                 printk(KERN_DEBUG " %02x %03X %02X  ",
861                         i,
862                         entry.dest.logical.logical_dest,
863                         entry.dest.physical.physical_dest
864                 );
865 
866                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
867                         entry.mask,
868                         entry.trigger,
869                         entry.irr,
870                         entry.polarity,
871                         entry.delivery_status,
872                         entry.dest_mode,
873                         entry.delivery_mode,
874                         entry.vector
875                 );
876         }
877         }
878         printk(KERN_DEBUG "IRQ to pin mappings:\n");
879         for (i = 0; i < NR_IRQS; i++) {
880                 struct irq_pin_list *entry = irq_2_pin + i;
881                 if (entry->pin < 0)
882                         continue;
883                 printk(KERN_DEBUG "IRQ%d ", i);
884                 for (;;) {
885                         printk("-> %d:%d", entry->apic, entry->pin);
886                         if (!entry->next)
887                                 break;
888                         entry = irq_2_pin + entry->next;
889                 }
890                 printk("\n");
891         }
892 
893         printk(KERN_INFO ".................................... done.\n");
894 
895         return;
896 }
897 
898 static void print_APIC_bitfield (int base)
899 {
900         unsigned int v;
901         int i, j;
902 
903         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
904         for (i = 0; i < 8; i++) {
905                 v = apic_read(base + i*0x10);
906                 for (j = 0; j < 32; j++) {
907                         if (v & (1<<j))
908                                 printk("1");
909                         else
910                                 printk("");
911                 }
912                 printk("\n");
913         }
914 }
915 
916 void /*__init*/ print_local_APIC(void * dummy)
917 {
918         unsigned int v, ver, maxlvt;
919 
920         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
921                 smp_processor_id(), hard_smp_processor_id());
922         v = apic_read(APIC_ID);
923         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
924         v = apic_read(APIC_LVR);
925         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
926         ver = GET_APIC_VERSION(v);
927         maxlvt = get_maxlvt();
928 
929         v = apic_read(APIC_TASKPRI);
930         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
931 
932         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
933                 v = apic_read(APIC_ARBPRI);
934                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
935                         v & APIC_ARBPRI_MASK);
936                 v = apic_read(APIC_PROCPRI);
937                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
938         }
939 
940         v = apic_read(APIC_EOI);
941         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
942         v = apic_read(APIC_RRR);
943         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
944         v = apic_read(APIC_LDR);
945         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
946         v = apic_read(APIC_DFR);
947         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
948         v = apic_read(APIC_SPIV);
949         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
950 
951         printk(KERN_DEBUG "... APIC ISR field:\n");
952         print_APIC_bitfield(APIC_ISR);
953         printk(KERN_DEBUG "... APIC TMR field:\n");
954         print_APIC_bitfield(APIC_TMR);
955         printk(KERN_DEBUG "... APIC IRR field:\n");
956         print_APIC_bitfield(APIC_IRR);
957 
958         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
959                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
960                         apic_write(APIC_ESR, 0);
961                 v = apic_read(APIC_ESR);
962                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
963         }
964 
965         v = apic_read(APIC_ICR);
966         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
967         v = apic_read(APIC_ICR2);
968         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
969 
970         v = apic_read(APIC_LVTT);
971         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
972 
973         if (maxlvt > 3) {                       /* PC is LVT#4. */
974                 v = apic_read(APIC_LVTPC);
975                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
976         }
977         v = apic_read(APIC_LVT0);
978         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
979         v = apic_read(APIC_LVT1);
980         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
981 
982         if (maxlvt > 2) {                       /* ERR is LVT#3. */
983                 v = apic_read(APIC_LVTERR);
984                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
985         }
986 
987         v = apic_read(APIC_TMICT);
988         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
989         v = apic_read(APIC_TMCCT);
990         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
991         v = apic_read(APIC_TDCR);
992         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
993         printk("\n");
994 }
995 
996 void print_all_local_APICs (void)
997 {
998         on_each_cpu(print_local_APIC, NULL, 1, 1);
999 }
1000 
1001 void /*__init*/ print_PIC(void)
1002 {
1003         extern spinlock_t i8259A_lock;
1004         unsigned int v;
1005         unsigned long flags;
1006 
1007         printk(KERN_DEBUG "\nprinting PIC contents\n");
1008 
1009         spin_lock_irqsave(&i8259A_lock, flags);
1010 
1011         v = inb(0xa1) << 8 | inb(0x21);
1012         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1013 
1014         v = inb(0xa0) << 8 | inb(0x20);
1015         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1016 
1017         outb(0x0b,0xa0);
1018         outb(0x0b,0x20);
1019         v = inb(0xa0) << 8 | inb(0x20);
1020         outb(0x0a,0xa0);
1021         outb(0x0a,0x20);
1022 
1023         spin_unlock_irqrestore(&i8259A_lock, flags);
1024 
1025         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1026 
1027         v = inb(0x4d1) << 8 | inb(0x4d0);
1028         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1029 }
1030 
1031 static void __init enable_IO_APIC(void)
1032 {
1033         union IO_APIC_reg_01 reg_01;
1034         int i;
1035         unsigned long flags;
1036 
1037         for (i = 0; i < PIN_MAP_SIZE; i++) {
1038                 irq_2_pin[i].pin = -1;
1039                 irq_2_pin[i].next = 0;
1040         }
1041         if (!pirqs_enabled)
1042                 for (i = 0; i < MAX_PIRQS; i++)
1043                         pirq_entries[i] = -1;
1044 
1045         /*
1046          * The number of IO-APIC IRQ registers (== #pins):
1047          */
1048         for (i = 0; i < nr_ioapics; i++) {
1049                 spin_lock_irqsave(&ioapic_lock, flags);
1050                 reg_01.raw = io_apic_read(i, 1);
1051                 spin_unlock_irqrestore(&ioapic_lock, flags);
1052                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1053         }
1054 
1055         /*
1056          * Do not trust the IO-APIC being empty at bootup
1057          */
1058         clear_IO_APIC();
1059 }
1060 
1061 /*
1062  * Not an __init, needed by the reboot code
1063  */
1064 void disable_IO_APIC(void)
1065 {
1066         /*
1067          * Clear the IO-APIC before rebooting:
1068          */
1069         clear_IO_APIC();
1070 
1071         disconnect_bsp_APIC();
1072 }
1073 
1074 /*
1075  * function to set the IO-APIC physical IDs based on the
1076  * values stored in the MPC table.
1077  *
1078  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1079  */
1080 
1081 static void __init setup_ioapic_ids_from_mpc (void)
1082 {
1083         union IO_APIC_reg_00 reg_00;
1084         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1085         int apic;
1086         int i;
1087         unsigned char old_id;
1088         unsigned long flags;
1089 
1090         if (acpi_ioapic) return; /* ACPI does that already */
1091 
1092         /*
1093          * Set the IOAPIC ID to the value stored in the MPC table.
1094          */
1095         for (apic = 0; apic < nr_ioapics; apic++) {
1096 
1097                 /* Read the register 0 value */
1098                 spin_lock_irqsave(&ioapic_lock, flags);
1099                 reg_00.raw = io_apic_read(apic, 0);
1100                 spin_unlock_irqrestore(&ioapic_lock, flags);
1101                 
1102                 old_id = mp_ioapics[apic].mpc_apicid;
1103 
1104                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1105                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1106                                 apic, mp_ioapics[apic].mpc_apicid);
1107                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1108                                 reg_00.bits.ID);
1109                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1110                 }
1111 
1112                 /*
1113                  * Sanity check, is the ID really free? Every APIC in a
1114                  * system must have a unique ID or we get lots of nice
1115                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1116                  */
1117                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1118                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1119                                 apic, mp_ioapics[apic].mpc_apicid);
1120                         for (i = 0; i < 0xf; i++)
1121                                 if (!physid_isset(i, phys_id_present_map))
1122                                         break;
1123                         if (i >= 0xf)
1124                                 panic("Max APIC ID exceeded!\n");
1125                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1126                                 i);
1127                         physid_set(i, phys_id_present_map);
1128                         mp_ioapics[apic].mpc_apicid = i;
1129                 } else {
1130                         printk(KERN_INFO 
1131                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1132                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1133                 }
1134 
1135 
1136                 /*
1137                  * We need to adjust the IRQ routing table
1138                  * if the ID changed.
1139                  */
1140                 if (old_id != mp_ioapics[apic].mpc_apicid)
1141                         for (i = 0; i < mp_irq_entries; i++)
1142                                 if (mp_irqs[i].mpc_dstapic == old_id)
1143                                         mp_irqs[i].mpc_dstapic
1144                                                 = mp_ioapics[apic].mpc_apicid;
1145 
1146                 /*
1147                  * Read the right value from the MPC table and
1148                  * write it into the ID register.
1149                  */
1150                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1151                                 mp_ioapics[apic].mpc_apicid);
1152 
1153                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1154                 spin_lock_irqsave(&ioapic_lock, flags);
1155                 io_apic_write(apic, 0, reg_00.raw);
1156                 spin_unlock_irqrestore(&ioapic_lock, flags);
1157 
1158                 /*
1159                  * Sanity check
1160                  */
1161                 spin_lock_irqsave(&ioapic_lock, flags);
1162                 reg_00.raw = io_apic_read(apic, 0);
1163                 spin_unlock_irqrestore(&ioapic_lock, flags);
1164                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1165                         panic("could not set ID!\n");
1166                 else
1167                         printk(" ok.\n");
1168         }
1169 }
1170 
1171 /*
1172  * There is a nasty bug in some older SMP boards, their mptable lies
1173  * about the timer IRQ. We do the following to work around the situation:
1174  *
1175  *      - timer IRQ defaults to IO-APIC IRQ
1176  *      - if this function detects that timer IRQs are defunct, then we fall
1177  *        back to ISA timer IRQs
1178  */
1179 static int __init timer_irq_works(void)
1180 {
1181         unsigned long t1 = jiffies;
1182 
1183         local_irq_enable();
1184         /* Let ten ticks pass... */
1185         mdelay((10 * 1000) / HZ);
1186 
1187         /*
1188          * Expect a few ticks at least, to be sure some possible
1189          * glue logic does not lock up after one or two first
1190          * ticks in a non-ExtINT mode.  Also the local APIC
1191          * might have cached one ExtINT interrupt.  Finally, at
1192          * least one tick may be lost due to delays.
1193          */
1194 
1195         /* jiffies wrap? */
1196         if (jiffies - t1 > 4)
1197                 return 1;
1198         return 0;
1199 }
1200 
1201 /*
1202  * In the SMP+IOAPIC case it might happen that there are an unspecified
1203  * number of pending IRQ events unhandled. These cases are very rare,
1204  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1205  * better to do it this way as thus we do not have to be aware of
1206  * 'pending' interrupts in the IRQ path, except at this point.
1207  */
1208 /*
1209  * Edge triggered needs to resend any interrupt
1210  * that was delayed but this is now handled in the device
1211  * independent code.
1212  */
1213 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1214 
1215 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1216 
1217 /*
1218  * Starting up a edge-triggered IO-APIC interrupt is
1219  * nasty - we need to make sure that we get the edge.
1220  * If it is already asserted for some reason, we need
1221  * return 1 to indicate that is was pending.
1222  *
1223  * This is not complete - we should be able to fake
1224  * an edge even if it isn't on the 8259A...
1225  */
1226 
1227 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1228 {
1229         int was_pending = 0;
1230         unsigned long flags;
1231 
1232         spin_lock_irqsave(&ioapic_lock, flags);
1233         if (irq < 16) {
1234                 disable_8259A_irq(irq);
1235                 if (i8259A_irq_pending(irq))
1236                         was_pending = 1;
1237         }
1238         __unmask_IO_APIC_irq(irq);
1239         spin_unlock_irqrestore(&ioapic_lock, flags);
1240 
1241         return was_pending;
1242 }
1243 
1244 #define shutdown_edge_ioapic_irq        disable_edge_ioapic_irq
1245 
1246 /*
1247  * Once we have recorded IRQ_PENDING already, we can mask the
1248  * interrupt for real. This prevents IRQ storms from unhandled
1249  * devices.
1250  */
1251 static void ack_edge_ioapic_irq(unsigned int irq)
1252 {
1253         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1254                                         == (IRQ_PENDING | IRQ_DISABLED))
1255                 mask_IO_APIC_irq(irq);
1256         ack_APIC_irq();
1257 }
1258 
1259 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1260 
1261 
1262 /*
1263  * Level triggered interrupts can just be masked,
1264  * and shutting down and starting up the interrupt
1265  * is the same as enabling and disabling them -- except
1266  * with a startup need to return a "was pending" value.
1267  *
1268  * Level triggered interrupts are special because we
1269  * do not touch any IO-APIC register while handling
1270  * them. We ack the APIC in the end-IRQ handler, not
1271  * in the start-IRQ-handler. Protection against reentrance
1272  * from the same interrupt is still provided, both by the
1273  * generic IRQ layer and by the fact that an unacked local
1274  * APIC does not accept IRQs.
1275  */
1276 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1277 {
1278         unmask_IO_APIC_irq(irq);
1279 
1280         return 0; /* don't check for pending */
1281 }
1282 
1283 #define shutdown_level_ioapic_irq       mask_IO_APIC_irq
1284 #define enable_level_ioapic_irq         unmask_IO_APIC_irq
1285 #define disable_level_ioapic_irq        mask_IO_APIC_irq
1286 
1287 static void end_level_ioapic_irq (unsigned int irq)
1288 {
1289         unsigned long v;
1290         int i;
1291 
1292 /*
1293  * It appears there is an erratum which affects at least version 0x11
1294  * of I/O APIC (that's the 82093AA and cores integrated into various
1295  * chipsets).  Under certain conditions a level-triggered interrupt is
1296  * erroneously delivered as edge-triggered one but the respective IRR
1297  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1298  * message but it will never arrive and further interrupts are blocked
1299  * from the source.  The exact reason is so far unknown, but the
1300  * phenomenon was observed when two consecutive interrupt requests
1301  * from a given source get delivered to the same CPU and the source is
1302  * temporarily disabled in between.
1303  *
1304  * A workaround is to simulate an EOI message manually.  We achieve it
1305  * by setting the trigger mode to edge and then to level when the edge
1306  * trigger mode gets detected in the TMR of a local APIC for a
1307  * level-triggered interrupt.  We mask the source for the time of the
1308  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1309  * The idea is from Manfred Spraul.  --macro
1310  */
1311         i = IO_APIC_VECTOR(irq);
1312         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1313 
1314         ack_APIC_irq();
1315 
1316         if (!(v & (1 << (i & 0x1f)))) {
1317 #ifdef APIC_LOCKUP_DEBUG
1318                 struct irq_pin_list *entry;
1319 #endif
1320 
1321 #ifdef APIC_MISMATCH_DEBUG
1322                 atomic_inc(&irq_mis_count);
1323 #endif
1324                 spin_lock(&ioapic_lock);
1325                 __mask_and_edge_IO_APIC_irq(irq);
1326 #ifdef APIC_LOCKUP_DEBUG
1327                 for (entry = irq_2_pin + irq;;) {
1328                         unsigned int reg;
1329 
1330                         if (entry->pin == -1)
1331                                 break;
1332                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1333                         if (reg & 0x00004000)
1334                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1335                                         " still set after unlock!\n");
1336                         if (!entry->next)
1337                                 break;
1338                         entry = irq_2_pin + entry->next;
1339                 }
1340 #endif
1341                 __unmask_and_level_IO_APIC_irq(irq);
1342                 spin_unlock(&ioapic_lock);
1343         }
1344 }
1345 
1346 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
1347 
1348 static void set_ioapic_affinity (unsigned int irq, cpumask_t mask)
1349 {
1350         unsigned long flags;
1351         unsigned int dest;
1352 
1353         dest = cpu_mask_to_apicid(mk_cpumask_const(mask));
1354 
1355         /*
1356          * Only the first 8 bits are valid.
1357          */
1358         dest = dest << 24;
1359 
1360         spin_lock_irqsave(&ioapic_lock, flags);
1361         __DO_ACTION(1, = dest, )
1362         spin_unlock_irqrestore(&ioapic_lock, flags);
1363 }
1364 
1365 /*
1366  * Level and edge triggered IO-APIC interrupts need different handling,
1367  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1368  * handled with the level-triggered descriptor, but that one has slightly
1369  * more overhead. Level-triggered interrupts cannot be handled with the
1370  * edge-triggered handler, without risking IRQ storms and other ugly
1371  * races.
1372  */
1373 
1374 static struct hw_interrupt_type ioapic_edge_irq_type = {
1375         .typename = "IO-APIC-edge",
1376         .startup = startup_edge_ioapic_irq,
1377         .shutdown = shutdown_edge_ioapic_irq,
1378         .enable = enable_edge_ioapic_irq,
1379         .disable = disable_edge_ioapic_irq,
1380         .ack = ack_edge_ioapic_irq,
1381         .end = end_edge_ioapic_irq,
1382         .set_affinity = set_ioapic_affinity,
1383 };
1384 
1385 static struct hw_interrupt_type ioapic_level_irq_type = {
1386         .typename = "IO-APIC-level",
1387         .startup = startup_level_ioapic_irq,
1388         .shutdown = shutdown_level_ioapic_irq,
1389         .enable = enable_level_ioapic_irq,
1390         .disable = disable_level_ioapic_irq,
1391         .ack = mask_and_ack_level_ioapic_irq,
1392         .end = end_level_ioapic_irq,
1393         .set_affinity = set_ioapic_affinity,
1394 };
1395 
1396 static inline void init_IO_APIC_traps(void)
1397 {
1398         int irq;
1399 
1400         /*
1401          * NOTE! The local APIC isn't very good at handling
1402          * multiple interrupts at the same interrupt level.
1403          * As the interrupt level is determined by taking the
1404          * vector number and shifting that right by 4, we
1405          * want to spread these out a bit so that they don't
1406          * all fall in the same interrupt level.
1407          *
1408          * Also, we've got to be careful not to trash gate
1409          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1410          */
1411         for (irq = 0; irq < NR_IRQS ; irq++) {
1412                 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1413                         /*
1414                          * Hmm.. We don't have an entry for this,
1415                          * so default to an old-fashioned 8259
1416                          * interrupt if we can..
1417                          */
1418                         if (irq < 16)
1419                                 make_8259A_irq(irq);
1420                         else
1421                                 /* Strange. Oh, well.. */
1422                                 irq_desc[irq].handler = &no_irq_type;
1423                 }
1424         }
1425 }
1426 
1427 static void enable_lapic_irq (unsigned int irq)
1428 {
1429         unsigned long v;
1430 
1431         v = apic_read(APIC_LVT0);
1432         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1433 }
1434 
1435 static void disable_lapic_irq (unsigned int irq)
1436 {
1437         unsigned long v;
1438 
1439         v = apic_read(APIC_LVT0);
1440         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1441 }
1442 
1443 static void ack_lapic_irq (unsigned int irq)
1444 {
1445         ack_APIC_irq();
1446 }
1447 
1448 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1449 
1450 static struct hw_interrupt_type lapic_irq_type = {
1451         .typename = "local-APIC-edge",
1452         .startup = NULL, /* startup_irq() not used for IRQ0 */
1453         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1454         .enable = enable_lapic_irq,
1455         .disable = disable_lapic_irq,
1456         .ack = ack_lapic_irq,
1457         .end = end_lapic_irq,
1458 };
1459 
1460 static void setup_nmi (void)
1461 {
1462         /*
1463          * Dirty trick to enable the NMI watchdog ...
1464          * We put the 8259A master into AEOI mode and
1465          * unmask on all local APICs LVT0 as NMI.
1466          *
1467          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1468          * is from Maciej W. Rozycki - so we do not have to EOI from
1469          * the NMI handler or the timer interrupt.
1470          */ 
1471         printk(KERN_INFO "activating NMI Watchdog ...");
1472 
1473         enable_NMI_through_LVT0(NULL);
1474 
1475         printk(" done.\n");
1476 }
1477 
1478 /*
1479  * This looks a bit hackish but it's about the only one way of sending
1480  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1481  * not support the ExtINT mode, unfortunately.  We need to send these
1482  * cycles as some i82489DX-based boards have glue logic that keeps the
1483  * 8259A interrupt line asserted until INTA.  --macro
1484  */
1485 static inline void unlock_ExtINT_logic(void)
1486 {
1487         int pin, i;
1488         struct IO_APIC_route_entry entry0, entry1;
1489         unsigned char save_control, save_freq_select;
1490         unsigned long flags;
1491 
1492         pin = find_isa_irq_pin(8, mp_INT);
1493         if (pin == -1)
1494                 return;
1495 
1496         spin_lock_irqsave(&ioapic_lock, flags);
1497         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1498         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1499         spin_unlock_irqrestore(&ioapic_lock, flags);
1500         clear_IO_APIC_pin(0, pin);
1501 
1502         memset(&entry1, 0, sizeof(entry1));
1503 
1504         entry1.dest_mode = 0;                   /* physical delivery */
1505         entry1.mask = 0;                        /* unmask IRQ now */
1506         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1507         entry1.delivery_mode = dest_ExtINT;
1508         entry1.polarity = entry0.polarity;
1509         entry1.trigger = 0;
1510         entry1.vector = 0;
1511 
1512         spin_lock_irqsave(&ioapic_lock, flags);
1513         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1514         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1515         spin_unlock_irqrestore(&ioapic_lock, flags);
1516 
1517         save_control = CMOS_READ(RTC_CONTROL);
1518         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1519         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1520                    RTC_FREQ_SELECT);
1521         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1522 
1523         i = 100;
1524         while (i-- > 0) {
1525                 mdelay(10);
1526                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1527                         i -= 10;
1528         }
1529 
1530         CMOS_WRITE(save_control, RTC_CONTROL);
1531         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1532         clear_IO_APIC_pin(0, pin);
1533 
1534         spin_lock_irqsave(&ioapic_lock, flags);
1535         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1536         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1537         spin_unlock_irqrestore(&ioapic_lock, flags);
1538 }
1539 
1540 /*
1541  * This code may look a bit paranoid, but it's supposed to cooperate with
1542  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1543  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1544  * fanatically on his truly buggy board.
1545  */
1546 static inline void check_timer(void)
1547 {
1548         int pin1, pin2;
1549         int vector;
1550 
1551         /*
1552          * get/set the timer IRQ vector:
1553          */
1554         disable_8259A_irq(0);
1555         vector = assign_irq_vector(0);
1556         set_intr_gate(vector, interrupt[0]);
1557 
1558         /*
1559          * Subtle, code in do_timer_interrupt() expects an AEOI
1560          * mode for the 8259A whenever interrupts are routed
1561          * through I/O APICs.  Also IRQ0 has to be enabled in
1562          * the 8259A which implies the virtual wire has to be
1563          * disabled in the local APIC.
1564          */
1565         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1566         init_8259A(1);
1567         enable_8259A_irq(0);
1568 
1569         pin1 = find_isa_irq_pin(0, mp_INT);
1570         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1571 
1572         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1573 
1574         if (pin1 != -1) {
1575                 /*
1576                  * Ok, does IRQ0 through the IOAPIC work?
1577                  */
1578                 unmask_IO_APIC_irq(0);
1579                 if (timer_irq_works()) {
1580                         if (nmi_watchdog == NMI_IO_APIC) {
1581                                 disable_8259A_irq(0);
1582                                 setup_nmi();
1583                                 enable_8259A_irq(0);
1584                                 check_nmi_watchdog();
1585                         }
1586                         return;
1587                 }
1588                 clear_IO_APIC_pin(0, pin1);
1589                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1590         }
1591 
1592         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1593         if (pin2 != -1) {
1594                 printk("\n..... (found pin %d) ...", pin2);
1595                 /*
1596                  * legacy devices should be connected to IO APIC #0
1597                  */
1598                 setup_ExtINT_IRQ0_pin(pin2, vector);
1599                 if (timer_irq_works()) {
1600                         printk("works.\n");
1601                         if (nmi_watchdog == NMI_IO_APIC) {
1602                                 setup_nmi();
1603                                 check_nmi_watchdog();
1604                         }
1605                         return;
1606                 }
1607                 /*
1608                  * Cleanup, just in case ...
1609                  */
1610                 clear_IO_APIC_pin(0, pin2);
1611         }
1612         printk(" failed.\n");
1613 
1614         if (nmi_watchdog) {
1615                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1616                 nmi_watchdog = 0;
1617         }
1618 
1619         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1620 
1621         disable_8259A_irq(0);
1622         irq_desc[0].handler = &lapic_irq_type;
1623         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1624         enable_8259A_irq(0);
1625 
1626         if (timer_irq_works()) {
1627                 printk(" works.\n");
1628                 return;
1629         }
1630         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1631         printk(" failed.\n");
1632 
1633         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1634 
1635         init_8259A(0);
1636         make_8259A_irq(0);
1637         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1638 
1639         unlock_ExtINT_logic();
1640 
1641         if (timer_irq_works()) {
1642                 printk(" works.\n");
1643                 return;
1644         }
1645         printk(" failed :(.\n");
1646         panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1647 }
1648 
1649 /*
1650  *
1651  * IRQ's that are handled by the old PIC in all cases:
1652  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1653  *   Linux doesn't really care, as it's not actually used
1654  *   for any interrupt handling anyway.
1655  * - There used to be IRQ13 here as well, but all
1656  *   MPS-compliant must not use it for FPU coupling and we
1657  *   want to use exception 16 anyway.  And there are
1658  *   systems who connect it to an I/O APIC for other uses.
1659  *   Thus we don't mark it special any longer.
1660  *
1661  * Additionally, something is definitely wrong with irq9
1662  * on PIIX4 boards.
1663  */
1664 #define PIC_IRQS        (1<<2)
1665 
1666 void __init setup_IO_APIC(void)
1667 {
1668         enable_IO_APIC();
1669 
1670         io_apic_irqs = ~PIC_IRQS;
1671         printk("ENABLING IO-APIC IRQs\n");
1672 
1673         /*
1674          * Set up the IO-APIC IRQ routing table.
1675          */
1676         setup_ioapic_ids_from_mpc();
1677         sync_Arb_IDs();
1678         setup_IO_APIC_irqs();
1679         init_IO_APIC_traps();
1680         check_timer();
1681         print_IO_APIC();
1682 }
1683 
1684 /* Ensure the ACPI SCI interrupt level is active low, edge-triggered */
1685 
1686 void __init mp_config_ioapic_for_sci(int irq)
1687 {
1688 #if 0 /* fixme */
1689        int ioapic;
1690        int ioapic_pin;
1691 
1692        ioapic = mp_find_ioapic(irq);
1693 
1694        ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start;
1695 
1696        io_apic_set_pci_routing(ioapic, ioapic_pin, irq);
1697 #endif
1698 }
1699 
1700 
1701 /* --------------------------------------------------------------------------
1702                           ACPI-based IOAPIC Configuration
1703    -------------------------------------------------------------------------- */
1704 
1705 #ifdef CONFIG_ACPI_BOOT
1706 
1707 #define IO_APIC_MAX_ID          15
1708 
1709 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1710 {
1711         union IO_APIC_reg_00 reg_00;
1712         static physid_mask_t apic_id_map;
1713         unsigned long flags;
1714         int i = 0;
1715 
1716         /*
1717          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
1718          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
1719          * supports up to 16 on one shared APIC bus.
1720          * 
1721          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1722          *      advantage of new APIC bus architecture.
1723          */
1724 
1725         if (!physids_empty(apic_id_map))
1726                 apic_id_map = phys_cpu_present_map;
1727 
1728         spin_lock_irqsave(&ioapic_lock, flags);
1729         reg_00.raw = io_apic_read(ioapic, 0);
1730         spin_unlock_irqrestore(&ioapic_lock, flags);
1731 
1732         if (apic_id >= IO_APIC_MAX_ID) {
1733                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1734                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1735                 apic_id = reg_00.bits.ID;
1736         }
1737 
1738         /*
1739          * Every APIC in a system must have a unique ID or we get lots of nice 
1740          * 'stuck on smp_invalidate_needed IPI wait' messages.
1741          */
1742         if (physid_isset(apic_id, apic_id_map)) {
1743 
1744                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1745                         if (!physid_isset(i, apic_id_map))
1746                                 break;
1747                 }
1748 
1749                 if (i == IO_APIC_MAX_ID)
1750                         panic("Max apic_id exceeded!\n");
1751 
1752                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1753                         "trying %d\n", ioapic, apic_id, i);
1754 
1755                 apic_id = i;
1756         } 
1757 
1758         physid_set(apic_id, apic_id_map);
1759 
1760         if (reg_00.bits.ID != apic_id) {
1761                 reg_00.bits.ID = apic_id;
1762 
1763                 spin_lock_irqsave(&ioapic_lock, flags);
1764                 io_apic_write(ioapic, 0, reg_00.raw);
1765                 reg_00.raw = io_apic_read(ioapic, 0);
1766                 spin_unlock_irqrestore(&ioapic_lock, flags);
1767 
1768                 /* Sanity check */
1769                 if (reg_00.bits.ID != apic_id)
1770                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1771         }
1772 
1773         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1774 
1775         return apic_id;
1776 }
1777 
1778 
1779 int __init io_apic_get_version (int ioapic)
1780 {
1781         union IO_APIC_reg_01    reg_01;
1782         unsigned long flags;
1783 
1784         spin_lock_irqsave(&ioapic_lock, flags);
1785         reg_01.raw = io_apic_read(ioapic, 1);
1786         spin_unlock_irqrestore(&ioapic_lock, flags);
1787 
1788         return reg_01.bits.version;
1789 }
1790 
1791 
1792 int __init io_apic_get_redir_entries (int ioapic)
1793 {
1794         union IO_APIC_reg_01    reg_01;
1795         unsigned long flags;
1796 
1797         spin_lock_irqsave(&ioapic_lock, flags);
1798         reg_01.raw = io_apic_read(ioapic, 1);
1799         spin_unlock_irqrestore(&ioapic_lock, flags);
1800 
1801         return reg_01.bits.entries;
1802 }
1803 
1804 
1805 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1806 {
1807         struct IO_APIC_route_entry entry;
1808         unsigned long flags;
1809 
1810         if (!IO_APIC_IRQ(irq)) {
1811                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1812                         ioapic);
1813                 return -EINVAL;
1814         }
1815 
1816         /*
1817          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1818          * Note that we mask (disable) IRQs now -- these get enabled when the
1819          * corresponding device driver registers for this IRQ.
1820          */
1821 
1822         memset(&entry,0,sizeof(entry));
1823 
1824         entry.delivery_mode = dest_LowestPrio;
1825         entry.dest_mode = INT_DELIVERY_MODE;
1826         entry.dest.logical.logical_dest = TARGET_CPUS;
1827         entry.trigger = edge_level;
1828         entry.polarity = active_high_low;
1829         entry.mask = 1;                                  /* Disabled (masked) */
1830 
1831         add_pin_to_irq(irq, ioapic, pin);
1832 
1833         entry.vector = assign_irq_vector(irq);
1834 
1835         printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1836                 "IRQ %d Mode:%i Active:%i)\n", ioapic, 
1837                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1838                edge_level, active_high_low);
1839 
1840         if (edge_level) {
1841                 irq_desc[irq].handler = &ioapic_level_irq_type;
1842         } else {
1843                 irq_desc[irq].handler = &ioapic_edge_irq_type;
1844         }
1845 
1846         set_intr_gate(entry.vector, interrupt[irq]);
1847 
1848         if (!ioapic && (irq < 16))
1849                 disable_8259A_irq(irq);
1850 
1851         spin_lock_irqsave(&ioapic_lock, flags);
1852         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1853         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1854         spin_unlock_irqrestore(&ioapic_lock, flags);
1855 
1856         return entry.vector;
1857 }
1858 
1859 #endif /*CONFIG_ACPI_BOOT*/
1860 
1861 #ifndef CONFIG_SMP
1862 void send_IPI_self(int vector)
1863 {
1864         unsigned int cfg;
1865 
1866        /*
1867         * Wait for idle.
1868         */
1869         apic_wait_icr_idle();
1870         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1871 
1872         /*
1873          * Send the IPI. The write to APIC_ICR fires this off.
1874          */
1875         apic_write_around(APIC_ICR, cfg);
1876 }
1877 #endif
1878 

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