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TOMOYO Linux Cross Reference
Linux/arch/x86_64/kernel/mpparse.c

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  1 /*
  2  *      Intel Multiprocessor Specification 1.1 and 1.4
  3  *      compliant MP-table parsing routines.
  4  *
  5  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  6  *      (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
  7  *
  8  *      Fixes
  9  *              Erich Boleyn    :       MP v1.4 and additional changes.
 10  *              Alan Cox        :       Added EBDA scanning
 11  *              Ingo Molnar     :       various cleanups and rewrites
 12  *      Maciej W. Rozycki       :       Bits for default MP configurations
 13  *              Paul Diefenbaugh:       Added full ACPI support
 14  */
 15 
 16 #include <linux/mm.h>
 17 #include <linux/irq.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/config.h>
 21 #include <linux/bootmem.h>
 22 #include <linux/smp_lock.h>
 23 #include <linux/kernel_stat.h>
 24 #include <linux/mc146818rtc.h>
 25 #include <linux/acpi.h>
 26 
 27 #include <asm/smp.h>
 28 #include <asm/mtrr.h>
 29 #include <asm/mpspec.h>
 30 #include <asm/pgalloc.h>
 31 #include <asm/io_apic.h>
 32 #include <asm/proto.h>
 33 
 34 /* Have we found an MP table */
 35 int smp_found_config;
 36 
 37 int acpi_found_madt;
 38 
 39 /*
 40  * Various Linux-internal data structures created from the
 41  * MP-table.
 42  */
 43 int apic_version [MAX_APICS];
 44 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
 45 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
 46 cpumask_t mp_bus_to_cpumask [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = CPU_MASK_ALL };
 47 
 48 int mp_current_pci_id = 0;
 49 /* I/O APIC entries */
 50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
 51 
 52 /* # of MP IRQ source entries */
 53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 54 
 55 /* MP IRQ source entries */
 56 int mp_irq_entries;
 57 
 58 int nr_ioapics;
 59 int pic_mode;
 60 unsigned long mp_lapic_addr = 0;
 61 
 62 
 63 
 64 /* Processor that is doing the boot up */
 65 unsigned int boot_cpu_id = -1U;
 66 /* Internal processor count */
 67 static unsigned int num_processors = 0;
 68 
 69 /* Bitmask of physically existing CPUs */
 70 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
 71 
 72 /* ACPI MADT entry parsing functions */
 73 #ifdef CONFIG_ACPI_BOOT
 74 extern struct acpi_boot_flags acpi_boot;
 75 #ifdef CONFIG_X86_LOCAL_APIC
 76 extern int acpi_parse_lapic (acpi_table_entry_header *header);
 77 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
 78 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
 79 #endif /*CONFIG_X86_LOCAL_APIC*/
 80 #ifdef CONFIG_X86_IO_APIC
 81 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
 82 #endif /*CONFIG_X86_IO_APIC*/
 83 #endif /*CONFIG_ACPI_BOOT*/
 84 
 85 /*
 86  * Intel MP BIOS table parsing routines:
 87  */
 88 
 89 /*
 90  * Checksum an MP configuration block.
 91  */
 92 
 93 static int __init mpf_checksum(unsigned char *mp, int len)
 94 {
 95         int sum = 0;
 96 
 97         while (len--)
 98                 sum += *mp++;
 99 
100         return sum & 0xFF;
101 }
102 
103 static void __init MP_processor_info (struct mpc_config_processor *m)
104 {
105         int ver;
106 
107         if (!(m->mpc_cpuflag & CPU_ENABLED))
108                 return;
109 
110         printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
111                 m->mpc_apicid,
112                (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
113                (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
114                 m->mpc_apicver);
115 
116         if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
117                 Dprintk("    Bootup CPU\n");
118                 boot_cpu_id = m->mpc_apicid;
119         }
120         num_processors++;
121 
122         if (m->mpc_apicid > MAX_APICS) {
123                 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
124                         m->mpc_apicid, MAX_APICS);
125                 return;
126         }
127         ver = m->mpc_apicver;
128 
129         physid_set(m->mpc_apicid, phys_cpu_present_map);
130         /*
131          * Validate version
132          */
133         if (ver == 0x0) {
134                 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
135                 ver = 0x10;
136         }
137         apic_version[m->mpc_apicid] = ver;
138 }
139 
140 static void __init MP_bus_info (struct mpc_config_bus *m)
141 {
142         char str[7];
143 
144         memcpy(str, m->mpc_bustype, 6);
145         str[6] = 0;
146         Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
147 
148         if (strncmp(str, "ISA", 3) == 0) {
149                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
150         } else if (strncmp(str, "EISA", 4) == 0) {
151                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
152         } else if (strncmp(str, "PCI", 3) == 0) {
153                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
154                 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
155                 mp_current_pci_id++;
156         } else if (strncmp(str, "MCA", 3) == 0) {
157                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
158         } else {
159                 printk(KERN_ERR "Unknown bustype %s\n", str);
160         }
161 }
162 
163 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
164 {
165         if (!(m->mpc_flags & MPC_APIC_USABLE))
166                 return;
167 
168         printk("I/O APIC #%d Version %d at 0x%X.\n",
169                 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
170         if (nr_ioapics >= MAX_IO_APICS) {
171                 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
172                         MAX_IO_APICS, nr_ioapics);
173                 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
174         }
175         if (!m->mpc_apicaddr) {
176                 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
177                         " found in MP table, skipping!\n");
178                 return;
179         }
180         mp_ioapics[nr_ioapics] = *m;
181         nr_ioapics++;
182 }
183 
184 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
185 {
186         mp_irqs [mp_irq_entries] = *m;
187         Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
188                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
189                         m->mpc_irqtype, m->mpc_irqflag & 3,
190                         (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
191                         m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
192         if (++mp_irq_entries == MAX_IRQ_SOURCES)
193                 panic("Max # of irq sources exceeded!!\n");
194 }
195 
196 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
197 {
198         Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
199                 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
200                         m->mpc_irqtype, m->mpc_irqflag & 3,
201                         (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
202                         m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
203         /*
204          * Well it seems all SMP boards in existence
205          * use ExtINT/LVT1 == LINT0 and
206          * NMI/LVT2 == LINT1 - the following check
207          * will show us if this assumptions is false.
208          * Until then we do not have to add baggage.
209          */
210         if ((m->mpc_irqtype == mp_ExtINT) &&
211                 (m->mpc_destapiclint != 0))
212                         BUG();
213         if ((m->mpc_irqtype == mp_NMI) &&
214                 (m->mpc_destapiclint != 1))
215                         BUG();
216 }
217 
218 /*
219  * Read/parse the MPC
220  */
221 
222 static int __init smp_read_mpc(struct mp_config_table *mpc)
223 {
224         char str[16];
225         int count=sizeof(*mpc);
226         unsigned char *mpt=((unsigned char *)mpc)+count;
227 
228         if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
229                 panic("SMP mptable: bad signature [%c%c%c%c]!\n",
230                         mpc->mpc_signature[0],
231                         mpc->mpc_signature[1],
232                         mpc->mpc_signature[2],
233                         mpc->mpc_signature[3]);
234                 return 0;
235         }
236         if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
237                 panic("SMP mptable: checksum error!\n");
238                 return 0;
239         }
240         if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
241                 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
242                         mpc->mpc_spec);
243                 return 0;
244         }
245         if (!mpc->mpc_lapic) {
246                 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
247                 return 0;
248         }
249         memcpy(str,mpc->mpc_oem,8);
250         str[8]=0;
251         printk(KERN_INFO "OEM ID: %s ",str);
252 
253         memcpy(str,mpc->mpc_productid,12);
254         str[12]=0;
255         printk(KERN_INFO "Product ID: %s ",str);
256 
257         printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
258 
259         /* save the local APIC address, it might be non-default */
260         if (!acpi_lapic)
261         mp_lapic_addr = mpc->mpc_lapic;
262 
263         /*
264          *      Now process the configuration blocks.
265          */
266         while (count < mpc->mpc_length) {
267                 switch(*mpt) {
268                         case MP_PROCESSOR:
269                         {
270                                 struct mpc_config_processor *m=
271                                         (struct mpc_config_processor *)mpt;
272                                 if (!acpi_lapic)
273                                 MP_processor_info(m);
274                                 mpt += sizeof(*m);
275                                 count += sizeof(*m);
276                                 break;
277                         }
278                         case MP_BUS:
279                         {
280                                 struct mpc_config_bus *m=
281                                         (struct mpc_config_bus *)mpt;
282                                 MP_bus_info(m);
283                                 mpt += sizeof(*m);
284                                 count += sizeof(*m);
285                                 break;
286                         }
287                         case MP_IOAPIC:
288                         {
289                                 struct mpc_config_ioapic *m=
290                                         (struct mpc_config_ioapic *)mpt;
291                                 MP_ioapic_info(m);
292                                 mpt+=sizeof(*m);
293                                 count+=sizeof(*m);
294                                 break;
295                         }
296                         case MP_INTSRC:
297                         {
298                                 struct mpc_config_intsrc *m=
299                                         (struct mpc_config_intsrc *)mpt;
300 
301                                 MP_intsrc_info(m);
302                                 mpt+=sizeof(*m);
303                                 count+=sizeof(*m);
304                                 break;
305                         }
306                         case MP_LINTSRC:
307                         {
308                                 struct mpc_config_lintsrc *m=
309                                         (struct mpc_config_lintsrc *)mpt;
310                                 MP_lintsrc_info(m);
311                                 mpt+=sizeof(*m);
312                                 count+=sizeof(*m);
313                                 break;
314                         }
315                 }
316         }
317         if (!num_processors)
318                 printk(KERN_ERR "SMP mptable: no processors registered!\n");
319         return num_processors;
320 }
321 
322 static int __init ELCR_trigger(unsigned int irq)
323 {
324         unsigned int port;
325 
326         port = 0x4d0 + (irq >> 3);
327         return (inb(port) >> (irq & 7)) & 1;
328 }
329 
330 static void __init construct_default_ioirq_mptable(int mpc_default_type)
331 {
332         struct mpc_config_intsrc intsrc;
333         int i;
334         int ELCR_fallback = 0;
335 
336         intsrc.mpc_type = MP_INTSRC;
337         intsrc.mpc_irqflag = 0;                 /* conforming */
338         intsrc.mpc_srcbus = 0;
339         intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
340 
341         intsrc.mpc_irqtype = mp_INT;
342 
343         /*
344          *  If true, we have an ISA/PCI system with no IRQ entries
345          *  in the MP table. To prevent the PCI interrupts from being set up
346          *  incorrectly, we try to use the ELCR. The sanity check to see if
347          *  there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
348          *  never be level sensitive, so we simply see if the ELCR agrees.
349          *  If it does, we assume it's valid.
350          */
351         if (mpc_default_type == 5) {
352                 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
353 
354                 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
355                         printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
356                 else {
357                         printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
358                         ELCR_fallback = 1;
359                 }
360         }
361 
362         for (i = 0; i < 16; i++) {
363                 switch (mpc_default_type) {
364                 case 2:
365                         if (i == 0 || i == 13)
366                                 continue;       /* IRQ0 & IRQ13 not connected */
367                         /* fall through */
368                 default:
369                         if (i == 2)
370                                 continue;       /* IRQ2 is never connected */
371                 }
372 
373                 if (ELCR_fallback) {
374                         /*
375                          *  If the ELCR indicates a level-sensitive interrupt, we
376                          *  copy that information over to the MP table in the
377                          *  irqflag field (level sensitive, active high polarity).
378                          */
379                         if (ELCR_trigger(i))
380                                 intsrc.mpc_irqflag = 13;
381                         else
382                                 intsrc.mpc_irqflag = 0;
383                 }
384 
385                 intsrc.mpc_srcbusirq = i;
386                 intsrc.mpc_dstirq = i ? i : 2;          /* IRQ0 to INTIN2 */
387                 MP_intsrc_info(&intsrc);
388         }
389 
390         intsrc.mpc_irqtype = mp_ExtINT;
391         intsrc.mpc_srcbusirq = 0;
392         intsrc.mpc_dstirq = 0;                          /* 8259A to INTIN0 */
393         MP_intsrc_info(&intsrc);
394 }
395 
396 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
397 {
398         struct mpc_config_processor processor;
399         struct mpc_config_bus bus;
400         struct mpc_config_ioapic ioapic;
401         struct mpc_config_lintsrc lintsrc;
402         int linttypes[2] = { mp_ExtINT, mp_NMI };
403         int i;
404 
405         /*
406          * local APIC has default address
407          */
408         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
409 
410         /*
411          * 2 CPUs, numbered 0 & 1.
412          */
413         processor.mpc_type = MP_PROCESSOR;
414         /* Either an integrated APIC or a discrete 82489DX. */
415         processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
416         processor.mpc_cpuflag = CPU_ENABLED;
417         processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
418                                    (boot_cpu_data.x86_model << 4) |
419                                    boot_cpu_data.x86_mask;
420         processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
421         processor.mpc_reserved[0] = 0;
422         processor.mpc_reserved[1] = 0;
423         for (i = 0; i < 2; i++) {
424                 processor.mpc_apicid = i;
425                 MP_processor_info(&processor);
426         }
427 
428         bus.mpc_type = MP_BUS;
429         bus.mpc_busid = 0;
430         switch (mpc_default_type) {
431                 default:
432                         printk(KERN_ERR "???\nUnknown standard configuration %d\n",
433                                 mpc_default_type);
434                         /* fall through */
435                 case 1:
436                 case 5:
437                         memcpy(bus.mpc_bustype, "ISA   ", 6);
438                         break;
439                 case 2:
440                 case 6:
441                 case 3:
442                         memcpy(bus.mpc_bustype, "EISA  ", 6);
443                         break;
444                 case 4:
445                 case 7:
446                         memcpy(bus.mpc_bustype, "MCA   ", 6);
447         }
448         MP_bus_info(&bus);
449         if (mpc_default_type > 4) {
450                 bus.mpc_busid = 1;
451                 memcpy(bus.mpc_bustype, "PCI   ", 6);
452                 MP_bus_info(&bus);
453         }
454 
455         ioapic.mpc_type = MP_IOAPIC;
456         ioapic.mpc_apicid = 2;
457         ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
458         ioapic.mpc_flags = MPC_APIC_USABLE;
459         ioapic.mpc_apicaddr = 0xFEC00000;
460         MP_ioapic_info(&ioapic);
461 
462         /*
463          * We set up most of the low 16 IO-APIC pins according to MPS rules.
464          */
465         construct_default_ioirq_mptable(mpc_default_type);
466 
467         lintsrc.mpc_type = MP_LINTSRC;
468         lintsrc.mpc_irqflag = 0;                /* conforming */
469         lintsrc.mpc_srcbusid = 0;
470         lintsrc.mpc_srcbusirq = 0;
471         lintsrc.mpc_destapic = MP_APIC_ALL;
472         for (i = 0; i < 2; i++) {
473                 lintsrc.mpc_irqtype = linttypes[i];
474                 lintsrc.mpc_destapiclint = i;
475                 MP_lintsrc_info(&lintsrc);
476         }
477 }
478 
479 static struct intel_mp_floating *mpf_found;
480 
481 /*
482  * Scan the memory blocks for an SMP configuration block.
483  */
484 void __init get_smp_config (void)
485 {
486         struct intel_mp_floating *mpf = mpf_found;
487 
488         /*
489          * ACPI may be used to obtain the entire SMP configuration or just to 
490          * enumerate/configure processors (CONFIG_ACPI_HT_ONLY).  Note that 
491          * ACPI supports both logical (e.g. Hyper-Threading) and physical 
492          * processors, where MPS only supports physical.
493          */
494         if (acpi_lapic && acpi_ioapic) {
495                 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
496                 return;
497         }
498         else if (acpi_lapic)
499                 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
500 
501         printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
502         if (mpf->mpf_feature2 & (1<<7)) {
503                 printk(KERN_INFO "    IMCR and PIC compatibility mode.\n");
504                 pic_mode = 1;
505         } else {
506                 printk(KERN_INFO "    Virtual Wire compatibility mode.\n");
507                 pic_mode = 0;
508         }
509 
510         /*
511          * Now see if we need to read further.
512          */
513         if (mpf->mpf_feature1 != 0) {
514 
515                 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
516                 construct_default_ISA_mptable(mpf->mpf_feature1);
517 
518         } else if (mpf->mpf_physptr) {
519 
520                 /*
521                  * Read the physical hardware table.  Anything here will
522                  * override the defaults.
523                  */
524                 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
525                         smp_found_config = 0;
526                         printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
527                         printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
528                         return;
529                 }
530                 /*
531                  * If there are no explicit MP IRQ entries, then we are
532                  * broken.  We set up most of the low 16 IO-APIC pins to
533                  * ISA defaults and hope it will work.
534                  */
535                 if (!mp_irq_entries) {
536                         struct mpc_config_bus bus;
537 
538                         printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
539 
540                         bus.mpc_type = MP_BUS;
541                         bus.mpc_busid = 0;
542                         memcpy(bus.mpc_bustype, "ISA   ", 6);
543                         MP_bus_info(&bus);
544 
545                         construct_default_ioirq_mptable(0);
546                 }
547 
548         } else
549                 BUG();
550 
551         printk(KERN_INFO "Processors: %d\n", num_processors);
552         /*
553          * Only use the first configuration found.
554          */
555 }
556 
557 static int __init smp_scan_config (unsigned long base, unsigned long length)
558 {
559         extern void __bad_mpf_size(void); 
560         unsigned int *bp = phys_to_virt(base);
561         struct intel_mp_floating *mpf;
562 
563         Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
564         if (sizeof(*mpf) != 16)
565                 __bad_mpf_size();
566 
567         while (length > 0) {
568                 mpf = (struct intel_mp_floating *)bp;
569                 if ((*bp == SMP_MAGIC_IDENT) &&
570                         (mpf->mpf_length == 1) &&
571                         !mpf_checksum((unsigned char *)bp, 16) &&
572                         ((mpf->mpf_specification == 1)
573                                 || (mpf->mpf_specification == 4)) ) {
574 
575                         smp_found_config = 1;
576                         printk(KERN_INFO "found SMP MP-table at %08lx\n",
577                                                 virt_to_phys(mpf));
578                         reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
579                         if (mpf->mpf_physptr)
580                                 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
581                         mpf_found = mpf;
582                         return 1;
583                 }
584                 bp += 4;
585                 length -= 16;
586         }
587         return 0;
588 }
589 
590 void __init find_intel_smp (void)
591 {
592         unsigned int address;
593 
594         /*
595          * FIXME: Linux assumes you have 640K of base ram..
596          * this continues the error...
597          *
598          * 1) Scan the bottom 1K for a signature
599          * 2) Scan the top 1K of base RAM
600          * 3) Scan the 64K of bios
601          */
602         if (smp_scan_config(0x0,0x400) ||
603                 smp_scan_config(639*0x400,0x400) ||
604                         smp_scan_config(0xF0000,0x10000))
605                 return;
606         /*
607          * If it is an SMP machine we should know now, unless the
608          * configuration is in an EISA/MCA bus machine with an
609          * extended bios data area.
610          *
611          * there is a real-mode segmented pointer pointing to the
612          * 4K EBDA area at 0x40E, calculate and scan it here.
613          *
614          * NOTE! There are Linux loaders that will corrupt the EBDA
615          * area, and as such this kind of SMP config may be less
616          * trustworthy, simply because the SMP table may have been
617          * stomped on during early boot. These loaders are buggy and
618          * should be fixed.
619          */
620 
621         address = *(unsigned short *)phys_to_virt(0x40E);
622         address <<= 4;
623         smp_scan_config(address, 0x1000);
624 }
625 
626 /*
627  * - Intel MP Configuration Table
628  */
629 void __init find_smp_config (void)
630 {
631 #ifdef CONFIG_X86_LOCAL_APIC
632         find_intel_smp();
633 #endif
634 }
635 
636 
637 /* --------------------------------------------------------------------------
638                             ACPI-based MP Configuration
639    -------------------------------------------------------------------------- */
640 
641 #ifdef CONFIG_ACPI_BOOT
642 
643 void __init mp_register_lapic_address (
644         u64                     address)
645 {
646         mp_lapic_addr = (unsigned long) address;
647 
648         set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
649 
650         if (boot_cpu_id == -1U)
651                 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
652 
653         Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
654 }
655 
656 
657 void __init mp_register_lapic (
658         u8                      id, 
659         u8                      enabled)
660 {
661         struct mpc_config_processor processor;
662         int                     boot_cpu = 0;
663         
664         if (id >= MAX_APICS) {
665                 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
666                         id, MAX_APICS);
667                 return;
668         }
669 
670         if (id == boot_cpu_physical_apicid)
671                 boot_cpu = 1;
672 
673         processor.mpc_type = MP_PROCESSOR;
674         processor.mpc_apicid = id;
675         processor.mpc_apicver = 0x10; /* TBD: lapic version */
676         processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
677         processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
678         processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 
679                 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
680         processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
681         processor.mpc_reserved[0] = 0;
682         processor.mpc_reserved[1] = 0;
683 
684         MP_processor_info(&processor);
685 }
686 
687 #ifdef CONFIG_X86_IO_APIC
688 
689 #define MP_ISA_BUS              0
690 #define MP_MAX_IOAPIC_PIN       127
691 
692 struct mp_ioapic_routing {
693         int                     apic_id;
694         int                     irq_start;
695         int                     irq_end;
696         u32                     pin_programmed[4];
697 } mp_ioapic_routing[MAX_IO_APICS];
698 
699 
700 static int __init mp_find_ioapic (
701         int                     irq)
702 {
703         int                     i = 0;
704 
705         /* Find the IOAPIC that manages this IRQ. */
706         for (i = 0; i < nr_ioapics; i++) {
707                 if ((irq >= mp_ioapic_routing[i].irq_start)
708                         && (irq <= mp_ioapic_routing[i].irq_end))
709                         return i;
710         }
711 
712         printk(KERN_ERR "ERROR: Unable to locate IOAPIC for IRQ %d\n", irq);
713 
714         return -1;
715 }
716         
717 
718 void __init mp_register_ioapic (
719         u8                      id, 
720         u32                     address,
721         u32                     irq_base)
722 {
723         int                     idx = 0;
724 
725         if (nr_ioapics >= MAX_IO_APICS) {
726                 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
727                         "(found %d)\n", MAX_IO_APICS, nr_ioapics);
728                 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
729         }
730         if (!address) {
731                 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
732                         " found in MADT table, skipping!\n");
733                 return;
734         }
735 
736         idx = nr_ioapics++;
737 
738         mp_ioapics[idx].mpc_type = MP_IOAPIC;
739         mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
740         mp_ioapics[idx].mpc_apicaddr = address;
741 
742         set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
743         mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
744         mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
745         
746         /* 
747          * Build basic IRQ lookup table to facilitate irq->io_apic lookups
748          * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
749          */
750         mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
751         mp_ioapic_routing[idx].irq_start = irq_base;
752         mp_ioapic_routing[idx].irq_end = irq_base + 
753                 io_apic_get_redir_entries(idx);
754 
755         printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
756                 "IRQ %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 
757                 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
758                 mp_ioapic_routing[idx].irq_start,
759                 mp_ioapic_routing[idx].irq_end);
760 
761         return;
762 }
763 
764 
765 void __init mp_override_legacy_irq (
766         u8                      bus_irq,
767         u8                      polarity, 
768         u8                      trigger, 
769         u32                     global_irq)
770 {
771         struct mpc_config_intsrc intsrc;
772         int                     i = 0;
773         int                     found = 0;
774         int                     ioapic = -1;
775         int                     pin = -1;
776 
777         /* 
778          * Convert 'global_irq' to 'ioapic.pin'.
779          */
780         ioapic = mp_find_ioapic(global_irq);
781         if (ioapic < 0)
782                 return;
783         pin = global_irq - mp_ioapic_routing[ioapic].irq_start;
784 
785         /*
786          * TBD: This check is for faulty timer entries, where the override
787          *      erroneously sets the trigger to level, resulting in a HUGE 
788          *      increase of timer interrupts!
789          */
790         if ((bus_irq == 0) && (global_irq == 2) && (trigger == 3))
791                 trigger = 1;
792 
793         intsrc.mpc_type = MP_INTSRC;
794         intsrc.mpc_irqtype = mp_INT;
795         intsrc.mpc_irqflag = (trigger << 2) | polarity;
796         intsrc.mpc_srcbus = MP_ISA_BUS;
797         intsrc.mpc_srcbusirq = bus_irq;                                /* IRQ */
798         intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;        /* APIC ID */
799         intsrc.mpc_dstirq = pin;                                    /* INTIN# */
800 
801         Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", 
802                 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 
803                 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
804                 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
805 
806         /* 
807          * If an existing [IOAPIC.PIN -> IRQ] routing entry exists we override it.
808          * Otherwise create a new entry (e.g. global_irq == 2).
809          */
810         for (i = 0; i < mp_irq_entries; i++) {
811                 if ((mp_irqs[i].mpc_dstapic == intsrc.mpc_dstapic) 
812                         && (mp_irqs[i].mpc_dstirq == intsrc.mpc_dstirq)) {
813                         mp_irqs[i] = intsrc;
814                         found = 1;
815                         break;
816                 }
817         }
818         if (!found) {
819                 mp_irqs[mp_irq_entries] = intsrc;
820                 if (++mp_irq_entries == MAX_IRQ_SOURCES)
821                         panic("Max # of irq sources exceeded!\n");
822         }
823 
824         return;
825 }
826 
827 
828 void __init mp_config_acpi_legacy_irqs (void)
829 {
830         struct mpc_config_intsrc intsrc;
831         int                     i = 0;
832         int                     ioapic = -1;
833 
834         /* 
835          * Fabricate the legacy ISA bus (bus #31).
836          */
837         mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
838         Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
839 
840         /* 
841          * Locate the IOAPIC that manages the ISA IRQs (0-15). 
842          */
843         ioapic = mp_find_ioapic(0);
844         if (ioapic < 0)
845                 return;
846 
847         intsrc.mpc_type = MP_INTSRC;
848         intsrc.mpc_irqflag = 0;                                 /* Conforming */
849         intsrc.mpc_srcbus = MP_ISA_BUS;
850         intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
851 
852         /* 
853          * Use the default configuration for the IRQs 0-15.  These may be
854          * overridden by (MADT) interrupt source override entries.
855          */
856         for (i = 0; i < 16; i++) {
857 
858                 if (i == 2) continue;                   /* Don't connect IRQ2 */
859 
860                 intsrc.mpc_irqtype = i ? mp_INT : mp_ExtINT;   /* 8259A to #0 */
861                 intsrc.mpc_srcbusirq = i;                  /* Identity mapped */
862                 intsrc.mpc_dstirq = i;
863 
864                 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
865                         "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 
866                         (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
867                         intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, 
868                         intsrc.mpc_dstirq);
869 
870                 mp_irqs[mp_irq_entries] = intsrc;
871                 if (++mp_irq_entries == MAX_IRQ_SOURCES)
872                         panic("Max # of irq sources exceeded!\n");
873         }
874 
875         return;
876 }
877 
878 #ifdef CONFIG_ACPI_PCI
879 
880 void __init mp_parse_prt (void)
881 {
882         struct list_head        *node = NULL;
883         struct acpi_prt_entry   *entry = NULL;
884         int                     vector = 0;
885         int                     ioapic = -1;
886         int                     ioapic_pin = 0;
887         int                     irq = 0;
888         int                     idx, bit = 0;
889         int                     edge_level = 0;
890         int                     active_high_low = 0;
891 
892         /*
893          * Parsing through the PCI Interrupt Routing Table (PRT) and program
894          * routing for all static (IOAPIC-direct) entries.
895          */
896         list_for_each(node, &acpi_prt.entries) {
897                 entry = list_entry(node, struct acpi_prt_entry, node);
898 
899                 /* Need to get irq for dynamic entry */
900                 if (entry->link.handle) {
901                         irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low);
902                         if (!irq)
903                                 continue;
904                 } else {
905                         /* Hardwired IRQ. Assume PCI standard settings */
906                         irq = entry->link.index;
907                         edge_level = 1;
908                         active_high_low = 1;
909                 }
910 
911                 /* Don't set up the ACPI SCI because it's already set up */
912                 if (acpi_fadt.sci_int == irq)
913                         continue;
914 
915                 ioapic = mp_find_ioapic(irq);
916                 if (ioapic < 0)
917                         continue;
918                 ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start;
919 
920                 /* 
921                  * Avoid pin reprogramming.  PRTs typically include entries  
922                  * with redundant pin->irq mappings (but unique PCI devices);
923                  * we only only program the IOAPIC on the first.
924                  */
925                 bit = ioapic_pin % 32;
926                 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
927                 if (idx > 3) {
928                         printk(KERN_ERR "Invalid reference to IOAPIC pin "
929                                 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 
930                                 ioapic_pin);
931                         continue;
932                 }
933                 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
934                         printk(KERN_DEBUG "Pin %d-%d already programmed\n",
935                                 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
936                         entry->irq = irq;
937                         continue;
938                 }
939 
940                 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
941 
942                 vector = io_apic_set_pci_routing(ioapic, ioapic_pin, irq, edge_level, active_high_low);
943                 if (vector)
944                         entry->irq = irq;
945 
946                 printk(KERN_DEBUG "%02x:%02x:%02x[%c] -> %d-%d -> vector 0x%02x"
947                         " -> IRQ %d\n", entry->id.segment, entry->id.bus, 
948                         entry->id.device, ('A' + entry->pin), 
949                         mp_ioapic_routing[ioapic].apic_id, ioapic_pin, vector, 
950                         entry->irq);
951         }
952         
953         return;
954 }
955 
956 #endif /*CONFIG_ACPI_PCI*/
957 
958 #endif /*CONFIG_X86_IO_APIC*/
959 
960 #endif /*CONFIG_ACPI_BOOT*/
961 

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