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Linux/arch/x86_64/kernel/smp.c

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  1 /*
  2  *      Intel SMP support routines.
  3  *
  4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  5  *      (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
  6  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
  7  *
  8  *      This code is released under the GNU General Public License version 2 or
  9  *      later.
 10  */
 11 
 12 #include <linux/init.h>
 13 
 14 #include <linux/mm.h>
 15 #include <linux/irq.h>
 16 #include <linux/delay.h>
 17 #include <linux/spinlock.h>
 18 #include <linux/smp_lock.h>
 19 #include <linux/smp.h>
 20 #include <linux/kernel_stat.h>
 21 #include <linux/mc146818rtc.h>
 22 #include <linux/interrupt.h>
 23 
 24 #include <asm/mtrr.h>
 25 #include <asm/pgalloc.h>
 26 #include <asm/tlbflush.h>
 27 
 28 /*
 29  * the following functions deal with sending IPIs between CPUs.
 30  *
 31  * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
 32  */
 33 
 34 static inline unsigned int __prepare_ICR (unsigned int shortcut, int vector)
 35 {
 36         unsigned int icr =  APIC_DM_FIXED | shortcut | vector | APIC_DEST_LOGICAL;
 37         if (vector == KDB_VECTOR) 
 38                 icr = (icr & (~APIC_VECTOR_MASK)) | APIC_DM_NMI;                
 39         return icr;
 40 }
 41 
 42 static inline int __prepare_ICR2 (unsigned int mask)
 43 {
 44         return SET_APIC_DEST_FIELD(mask);
 45 }
 46 
 47 static inline void __send_IPI_shortcut(unsigned int shortcut, int vector)
 48 {
 49         /*
 50          * Subtle. In the case of the 'never do double writes' workaround
 51          * we have to lock out interrupts to be safe.  As we don't care
 52          * of the value read we use an atomic rmw access to avoid costly
 53          * cli/sti.  Otherwise we use an even cheaper single atomic write
 54          * to the APIC.
 55          */
 56         unsigned int cfg;
 57 
 58         /*
 59          * Wait for idle.
 60          */
 61         apic_wait_icr_idle();
 62 
 63         /*
 64          * No need to touch the target chip field
 65          */
 66         cfg = __prepare_ICR(shortcut, vector);
 67 
 68         /*
 69          * Send the IPI. The write to APIC_ICR fires this off.
 70          */
 71         apic_write_around(APIC_ICR, cfg);
 72 }
 73 
 74 static inline void send_IPI_allbutself(int vector)
 75 {
 76         /*
 77          * if there are no other CPUs in the system then
 78          * we get an APIC send error if we try to broadcast.
 79          * thus we have to avoid sending IPIs in this case.
 80          */
 81         if (num_online_cpus() > 1)
 82                 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
 83 }
 84 
 85 static inline void send_IPI_all(int vector)
 86 {
 87         __send_IPI_shortcut(APIC_DEST_ALLINC, vector);
 88 }
 89 
 90 void send_IPI_self(int vector)
 91 {
 92         __send_IPI_shortcut(APIC_DEST_SELF, vector);
 93 }
 94 
 95 static inline void send_IPI_mask(cpumask_t cpumask, int vector)
 96 {
 97         unsigned long mask = cpus_coerce(cpumask);
 98         unsigned long cfg;
 99         unsigned long flags;
100 
101         local_save_flags(flags);
102         local_irq_disable();
103 
104         /*
105          * Wait for idle.
106          */
107         apic_wait_icr_idle();
108 
109         /*
110          * prepare target chip field
111          */
112         cfg = __prepare_ICR2(mask);
113         apic_write_around(APIC_ICR2, cfg);
114 
115         /*
116          * program the ICR 
117          */
118         cfg = __prepare_ICR(0, vector);
119         
120         /*
121          * Send the IPI. The write to APIC_ICR fires this off.
122          */
123         apic_write_around(APIC_ICR, cfg);
124         local_irq_restore(flags);
125 }
126 
127 /*
128  *      Smarter SMP flushing macros. 
129  *              c/o Linus Torvalds.
130  *
131  *      These mean you can really definitely utterly forget about
132  *      writing to user space from interrupts. (Its not allowed anyway).
133  *
134  *      Optimizations Manfred Spraul <manfred@colorfullife.com>
135  */
136 
137 static cpumask_t flush_cpumask;
138 static struct mm_struct * flush_mm;
139 static unsigned long flush_va;
140 static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
141 #define FLUSH_ALL       0xffffffff
142 
143 /*
144  * We cannot call mmdrop() because we are in interrupt context, 
145  * instead update mm->cpu_vm_mask.
146  */
147 static inline void leave_mm (unsigned long cpu)
148 {
149         if (read_pda(mmu_state) == TLBSTATE_OK)
150                 BUG();
151         clear_bit(cpu, &read_pda(active_mm)->cpu_vm_mask);
152         __flush_tlb();
153 }
154 
155 /*
156  *
157  * The flush IPI assumes that a thread switch happens in this order:
158  * [cpu0: the cpu that switches]
159  * 1) switch_mm() either 1a) or 1b)
160  * 1a) thread switch to a different mm
161  * 1a1) clear_bit(cpu, &old_mm->cpu_vm_mask);
162  *      Stop ipi delivery for the old mm. This is not synchronized with
163  *      the other cpus, but smp_invalidate_interrupt ignore flush ipis
164  *      for the wrong mm, and in the worst case we perform a superfluous
165  *      tlb flush.
166  * 1a2) set cpu mmu_state to TLBSTATE_OK
167  *      Now the smp_invalidate_interrupt won't call leave_mm if cpu0
168  *      was in lazy tlb mode.
169  * 1a3) update cpu active_mm
170  *      Now cpu0 accepts tlb flushes for the new mm.
171  * 1a4) set_bit(cpu, &new_mm->cpu_vm_mask);
172  *      Now the other cpus will send tlb flush ipis.
173  * 1a4) change cr3.
174  * 1b) thread switch without mm change
175  *      cpu active_mm is correct, cpu0 already handles
176  *      flush ipis.
177  * 1b1) set cpu mmu_state to TLBSTATE_OK
178  * 1b2) test_and_set the cpu bit in cpu_vm_mask.
179  *      Atomically set the bit [other cpus will start sending flush ipis],
180  *      and test the bit.
181  * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
182  * 2) switch %%esp, ie current
183  *
184  * The interrupt must handle 2 special cases:
185  * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
186  * - the cpu performs speculative tlb reads, i.e. even if the cpu only
187  *   runs in kernel space, the cpu could load tlb entries for user space
188  *   pages.
189  *
190  * The good news is that cpu mmu_state is local to each cpu, no
191  * write/read ordering problems.
192  */
193 
194 /*
195  * TLB flush IPI:
196  *
197  * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
198  * 2) Leave the mm if we are in the lazy tlb mode.
199  */
200 
201 asmlinkage void smp_invalidate_interrupt (void)
202 {
203         unsigned long cpu;
204 
205         cpu = get_cpu();
206 
207         if (!cpu_isset(cpu, flush_cpumask))
208                 goto out;
209                 /* 
210                  * This was a BUG() but until someone can quote me the
211                  * line from the intel manual that guarantees an IPI to
212                  * multiple CPUs is retried _only_ on the erroring CPUs
213                  * its staying as a return
214                  *
215                  * BUG();
216                  */
217                  
218         if (flush_mm == read_pda(active_mm)) {
219                 if (read_pda(mmu_state) == TLBSTATE_OK) {
220                         if (flush_va == FLUSH_ALL)
221                                 local_flush_tlb();
222                         else
223                                 __flush_tlb_one(flush_va);
224                 } else
225                         leave_mm(cpu);
226         }
227         ack_APIC_irq();
228         cpu_clear(cpu, flush_cpumask);
229 
230 out:
231         put_cpu_no_resched();
232 }
233 
234 static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
235                                                 unsigned long va)
236 {
237         cpumask_t tmp;
238         /*
239          * A couple of (to be removed) sanity checks:
240          *
241          * - we do not send IPIs to not-yet booted CPUs.
242          * - current CPU must not be in mask
243          * - mask must exist :)
244          */
245         BUG_ON(cpus_empty(cpumask));
246         cpus_and(tmp, cpumask, cpu_online_map);
247         BUG_ON(!cpus_equal(tmp, cpumask));
248         BUG_ON(cpu_isset(smp_processor_id(), cpumask));
249         if (!mm)
250                 BUG();
251 
252         /*
253          * I'm not happy about this global shared spinlock in the
254          * MM hot path, but we'll see how contended it is.
255          * Temporarily this turns IRQs off, so that lockups are
256          * detected by the NMI watchdog.
257          */
258         spin_lock(&tlbstate_lock);
259         
260         flush_mm = mm;
261         flush_va = va;
262         cpus_or(flush_cpumask, cpumask, flush_cpumask);
263 
264         /*
265          * We have to send the IPI only to
266          * CPUs affected.
267          */
268         send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
269 
270         while (!cpus_empty(flush_cpumask))
271                 mb();   /* nothing. lockup detection does not belong here */;
272 
273         flush_mm = NULL;
274         flush_va = 0;
275         spin_unlock(&tlbstate_lock);
276 }
277         
278 void flush_tlb_current_task(void)
279 {
280         struct mm_struct *mm = current->mm;
281         cpumask_t cpu_mask;
282 
283         preempt_disable();
284         cpu_mask = mm->cpu_vm_mask;
285         cpu_clear(smp_processor_id(), cpu_mask);
286 
287         local_flush_tlb();
288         if (!cpus_empty(cpu_mask))
289                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
290         preempt_enable();
291 }
292 
293 void flush_tlb_mm (struct mm_struct * mm)
294 {
295         cpumask_t cpu_mask;
296 
297         preempt_disable();
298         cpu_mask = mm->cpu_vm_mask;
299         cpu_clear(smp_processor_id(), cpu_mask);
300 
301         if (current->active_mm == mm) {
302                 if (current->mm)
303                         local_flush_tlb();
304                 else
305                         leave_mm(smp_processor_id());
306         }
307         if (!cpus_empty(cpu_mask))
308                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
309 
310         preempt_enable();
311 }
312 
313 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
314 {
315         struct mm_struct *mm = vma->vm_mm;
316         cpumask_t cpu_mask;
317 
318         preempt_disable();
319         cpu_mask = mm->cpu_vm_mask;
320         cpu_clear(smp_processor_id(), cpu_mask);
321 
322         if (current->active_mm == mm) {
323                 if(current->mm)
324                         __flush_tlb_one(va);
325                  else
326                         leave_mm(smp_processor_id());
327         }
328 
329         if (!cpus_empty(cpu_mask))
330                 flush_tlb_others(cpu_mask, mm, va);
331 
332         preempt_enable();
333 }
334 
335 static void do_flush_tlb_all(void* info)
336 {
337         unsigned long cpu = smp_processor_id();
338 
339         __flush_tlb_all();
340         if (read_pda(mmu_state) == TLBSTATE_LAZY)
341                 leave_mm(cpu);
342 }
343 
344 void flush_tlb_all(void)
345 {
346         on_each_cpu(do_flush_tlb_all, 0, 1, 1);
347 }
348 
349 void smp_kdb_stop(void)
350 {
351         send_IPI_allbutself(KDB_VECTOR);
352 }
353 
354 /*
355  * this function sends a 'reschedule' IPI to another CPU.
356  * it goes straight through and wastes no time serializing
357  * anything. Worst case is that we lose a reschedule ...
358  */
359 
360 void smp_send_reschedule(int cpu)
361 {
362         send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
363 }
364 
365 /*
366  * Structure and data for smp_call_function(). This is designed to minimise
367  * static memory requirements. It also looks cleaner.
368  */
369 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
370 
371 struct call_data_struct {
372         void (*func) (void *info);
373         void *info;
374         atomic_t started;
375         atomic_t finished;
376         int wait;
377 };
378 
379 static struct call_data_struct * call_data;
380 
381 /*
382  * this function sends a 'generic call function' IPI to all other CPUs
383  * in the system.
384  */
385 
386 int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
387                         int wait)
388 /*
389  * [SUMMARY] Run a function on all other CPUs.
390  * <func> The function to run. This must be fast and non-blocking.
391  * <info> An arbitrary pointer to pass to the function.
392  * <nonatomic> currently unused.
393  * <wait> If true, wait (atomically) until function has completed on other CPUs.
394  * [RETURNS] 0 on success, else a negative status code. Does not return until
395  * remote CPUs are nearly ready to execute <<func>> or are or have executed.
396  *
397  * You must not call this function with disabled interrupts or from a
398  * hardware interrupt handler or from a bottom half handler.
399  */
400 {
401         struct call_data_struct data;
402         int cpus = num_online_cpus()-1;
403 
404         if (!cpus)
405                 return 0;
406 
407         data.func = func;
408         data.info = info;
409         atomic_set(&data.started, 0);
410         data.wait = wait;
411         if (wait)
412                 atomic_set(&data.finished, 0);
413 
414         spin_lock(&call_lock);
415         call_data = &data;
416         wmb();
417         /* Send a message to all other CPUs and wait for them to respond */
418         send_IPI_allbutself(CALL_FUNCTION_VECTOR);
419 
420         /* Wait for response */
421         while (atomic_read(&data.started) != cpus)
422                 barrier();
423 
424         if (wait)
425                 while (atomic_read(&data.finished) != cpus)
426                         barrier();
427         spin_unlock(&call_lock);
428 
429         return 0;
430 }
431 
432 void smp_stop_cpu(void)
433 {
434         /*
435          * Remove this CPU:
436          */
437         cpu_clear(smp_processor_id(), cpu_online_map);
438         local_irq_disable();
439         disable_local_APIC();
440         local_irq_enable(); 
441 }
442 
443 static void smp_really_stop_cpu(void *dummy)
444 {
445         smp_stop_cpu(); 
446         for (;;) 
447                 asm("hlt"); 
448 } 
449 
450 void smp_send_stop(void)
451 {
452         smp_call_function(smp_really_stop_cpu, NULL, 1, 0);
453         smp_stop_cpu();
454 }
455 
456 /*
457  * Reschedule call back. Nothing to do,
458  * all the work is done automatically when
459  * we return from the interrupt.
460  */
461 asmlinkage void smp_reschedule_interrupt(void)
462 {
463         ack_APIC_irq();
464 }
465 
466 asmlinkage void smp_call_function_interrupt(void)
467 {
468         void (*func) (void *info) = call_data->func;
469         void *info = call_data->info;
470         int wait = call_data->wait;
471 
472         ack_APIC_irq();
473         /*
474          * Notify initiating CPU that I've grabbed the data and am
475          * about to execute the function
476          */
477         mb();
478         atomic_inc(&call_data->started);
479         /*
480          * At this point the info structure may be out of scope unless wait==1
481          */
482         irq_enter();
483         (*func)(info);
484         irq_exit();
485         if (wait) {
486                 mb();
487                 atomic_inc(&call_data->finished);
488         }
489 }
490 

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