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Linux/arch/xtensa/include/asm/processor.h

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  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2001 - 2008 Tensilica Inc.
  7  * Copyright (C) 2015 Cadence Design Systems Inc.
  8  */
  9 
 10 #ifndef _XTENSA_PROCESSOR_H
 11 #define _XTENSA_PROCESSOR_H
 12 
 13 #include <variant/core.h>
 14 #include <platform/hardware.h>
 15 
 16 #include <linux/compiler.h>
 17 #include <asm/ptrace.h>
 18 #include <asm/types.h>
 19 #include <asm/regs.h>
 20 
 21 /* Assertions. */
 22 
 23 #if (XCHAL_HAVE_WINDOWED != 1)
 24 # error Linux requires the Xtensa Windowed Registers Option.
 25 #endif
 26 
 27 #define ARCH_SLAB_MINALIGN      XCHAL_DATA_WIDTH
 28 
 29 /*
 30  * User space process size: 1 GB.
 31  * Windowed call ABI requires caller and callee to be located within the same
 32  * 1 GB region. The C compiler places trampoline code on the stack for sources
 33  * that take the address of a nested C function (a feature used by glibc), so
 34  * the 1 GB requirement applies to the stack as well.
 35  */
 36 
 37 #ifdef CONFIG_MMU
 38 #define TASK_SIZE       __XTENSA_UL_CONST(0x40000000)
 39 #else
 40 #define TASK_SIZE       __XTENSA_UL_CONST(0xffffffff)
 41 #endif
 42 
 43 #define STACK_TOP       TASK_SIZE
 44 #define STACK_TOP_MAX   STACK_TOP
 45 
 46 /*
 47  * General exception cause assigned to fake NMI. Fake NMI needs to be handled
 48  * differently from other interrupts, but it uses common kernel entry/exit
 49  * code.
 50  */
 51 
 52 #define EXCCAUSE_MAPPED_NMI     62
 53 
 54 /*
 55  * General exception cause assigned to debug exceptions. Debug exceptions go
 56  * to their own vector, rather than the general exception vectors (user,
 57  * kernel, double); and their specific causes are reported via DEBUGCAUSE
 58  * rather than EXCCAUSE.  However it is sometimes convenient to redirect debug
 59  * exceptions to the general exception mechanism.  To do this, an otherwise
 60  * unused EXCCAUSE value was assigned to debug exceptions for this purpose.
 61  */
 62 
 63 #define EXCCAUSE_MAPPED_DEBUG   63
 64 
 65 /*
 66  * We use DEPC also as a flag to distinguish between double and regular
 67  * exceptions. For performance reasons, DEPC might contain the value of
 68  * EXCCAUSE for regular exceptions, so we use this definition to mark a
 69  * valid double exception address.
 70  * (Note: We use it in bgeui, so it should be 64, 128, or 256)
 71  */
 72 
 73 #define VALID_DOUBLE_EXCEPTION_ADDRESS  64
 74 
 75 #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno)
 76 #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL
 77 
 78 #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
 79 #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
 80 
 81 #define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l)
 82 #define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK)
 83 
 84 #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
 85 
 86 /* LOCKLEVEL defines the interrupt level that masks all
 87  * general-purpose interrupts.
 88  */
 89 #if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT)
 90 #define LOCKLEVEL (PROFILING_INTLEVEL - 1)
 91 #else
 92 #define LOCKLEVEL XCHAL_EXCM_LEVEL
 93 #endif
 94 
 95 #define TOPLEVEL XCHAL_EXCM_LEVEL
 96 #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
 97 
 98 /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE
 99  * registers
100  */
101 #define WSBITS  (XCHAL_NUM_AREGS / 4)      /* width of WINDOWSTART in bits */
102 #define WBBITS  (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */
103 
104 #ifndef __ASSEMBLY__
105 
106 /* Build a valid return address for the specified call winsize.
107  * winsize must be 1 (call4), 2 (call8), or 3 (call12)
108  */
109 #define MAKE_RA_FOR_CALL(ra,ws)   (((ra) & 0x3fffffff) | (ws) << 30)
110 
111 /* Convert return address to a valid pc
112  * Note: We assume that the stack pointer is in the same 1GB ranges as the ra
113  */
114 #define MAKE_PC_FROM_RA(ra,sp)    (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
115 
116 typedef struct {
117         unsigned long seg;
118 } mm_segment_t;
119 
120 struct thread_struct {
121 
122         /* kernel's return address and stack pointer for context switching */
123         unsigned long ra; /* kernel's a0: return address and window call size */
124         unsigned long sp; /* kernel's a1: stack pointer */
125 
126         mm_segment_t current_ds;    /* see uaccess.h for example uses */
127 
128         /* struct xtensa_cpuinfo info; */
129 
130         unsigned long bad_vaddr; /* last user fault */
131         unsigned long bad_uaddr; /* last kernel fault accessing user space */
132         unsigned long error_code;
133 #ifdef CONFIG_HAVE_HW_BREAKPOINT
134         struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK];
135         struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
136 #endif
137         /* Make structure 16 bytes aligned. */
138         int align[0] __attribute__ ((aligned(16)));
139 };
140 
141 
142 /*
143  * Default implementation of macro that returns current
144  * instruction pointer ("program counter").
145  */
146 #define current_text_addr()  ({ __label__ _l; _l: &&_l;})
147 
148 
149 /* This decides where the kernel will search for a free chunk of vm
150  * space during mmap's.
151  */
152 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 2)
153 
154 #define INIT_THREAD  \
155 {                                                                       \
156         ra:             0,                                              \
157         sp:             sizeof(init_stack) + (long) &init_stack,        \
158         current_ds:     {0},                                            \
159         /*info:         {0}, */                                         \
160         bad_vaddr:      0,                                              \
161         bad_uaddr:      0,                                              \
162         error_code:     0,                                              \
163 }
164 
165 
166 /*
167  * Do necessary setup to start up a newly executed thread.
168  * Note: We set-up ps as if we did a call4 to the new pc.
169  *       set_thread_state in signal.c depends on it.
170  */
171 #define USER_PS_VALUE ((1 << PS_WOE_BIT) |                              \
172                        (1 << PS_CALLINC_SHIFT) |                        \
173                        (USER_RING << PS_RING_SHIFT) |                   \
174                        (1 << PS_UM_BIT) |                               \
175                        (1 << PS_EXCM_BIT))
176 
177 /* Clearing a0 terminates the backtrace. */
178 #define start_thread(regs, new_pc, new_sp) \
179         memset(regs, 0, sizeof(*regs)); \
180         regs->pc = new_pc; \
181         regs->ps = USER_PS_VALUE; \
182         regs->areg[1] = new_sp; \
183         regs->areg[0] = 0; \
184         regs->wmask = 1; \
185         regs->depc = 0; \
186         regs->windowbase = 0; \
187         regs->windowstart = 1;
188 
189 /* Forward declaration */
190 struct task_struct;
191 struct mm_struct;
192 
193 /* Free all resources held by a thread. */
194 #define release_thread(thread) do { } while(0)
195 
196 /* Copy and release all segment info associated with a VM */
197 #define copy_segments(p, mm)    do { } while(0)
198 #define release_segments(mm)    do { } while(0)
199 #define forget_segments()       do { } while (0)
200 
201 #define thread_saved_pc(tsk)    (task_pt_regs(tsk)->pc)
202 
203 extern unsigned long get_wchan(struct task_struct *p);
204 
205 #define KSTK_EIP(tsk)           (task_pt_regs(tsk)->pc)
206 #define KSTK_ESP(tsk)           (task_pt_regs(tsk)->areg[1])
207 
208 #define cpu_relax()  barrier()
209 
210 /* Special register access. */
211 
212 #define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
213 #define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
214 
215 #define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
216 #define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
217 
218 #ifndef XCHAL_HAVE_EXTERN_REGS
219 #define XCHAL_HAVE_EXTERN_REGS 0
220 #endif
221 
222 #if XCHAL_HAVE_EXTERN_REGS
223 
224 static inline void set_er(unsigned long value, unsigned long addr)
225 {
226         asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory");
227 }
228 
229 static inline unsigned long get_er(unsigned long addr)
230 {
231         register unsigned long value;
232         asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory");
233         return value;
234 }
235 
236 #endif /* XCHAL_HAVE_EXTERN_REGS */
237 
238 #endif  /* __ASSEMBLY__ */
239 #endif  /* _XTENSA_PROCESSOR_H */
240 

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