1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001 - 2007 Tensilica Inc.
7 *
8 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
9 * Chris Zankel <chris@zankel.net>
10 * Scott Foehner<sfoehner@yahoo.com>,
11 * Kevin Chea
12 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
13 */
14
15 #include <linux/errno.h>
16 #include <linux/hw_breakpoint.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/perf_event.h>
20 #include <linux/ptrace.h>
21 #include <linux/sched.h>
22 #include <linux/sched/task_stack.h>
23 #include <linux/security.h>
24 #include <linux/signal.h>
25 #include <linux/smp.h>
26 #include <linux/tracehook.h>
27 #include <linux/uaccess.h>
28
29 #include <asm/coprocessor.h>
30 #include <asm/elf.h>
31 #include <asm/page.h>
32 #include <asm/pgtable.h>
33 #include <asm/ptrace.h>
34
35
36 void user_enable_single_step(struct task_struct *child)
37 {
38 child->ptrace |= PT_SINGLESTEP;
39 }
40
41 void user_disable_single_step(struct task_struct *child)
42 {
43 child->ptrace &= ~PT_SINGLESTEP;
44 }
45
46 /*
47 * Called by kernel/ptrace.c when detaching to disable single stepping.
48 */
49
50 void ptrace_disable(struct task_struct *child)
51 {
52 /* Nothing to do.. */
53 }
54
55 static int ptrace_getregs(struct task_struct *child, void __user *uregs)
56 {
57 struct pt_regs *regs = task_pt_regs(child);
58 xtensa_gregset_t __user *gregset = uregs;
59 unsigned long wb = regs->windowbase;
60 int i;
61
62 if (!access_ok(VERIFY_WRITE, uregs, sizeof(xtensa_gregset_t)))
63 return -EIO;
64
65 __put_user(regs->pc, &gregset->pc);
66 __put_user(regs->ps & ~(1 << PS_EXCM_BIT), &gregset->ps);
67 __put_user(regs->lbeg, &gregset->lbeg);
68 __put_user(regs->lend, &gregset->lend);
69 __put_user(regs->lcount, &gregset->lcount);
70 __put_user(regs->windowstart, &gregset->windowstart);
71 __put_user(regs->windowbase, &gregset->windowbase);
72 __put_user(regs->threadptr, &gregset->threadptr);
73
74 for (i = 0; i < XCHAL_NUM_AREGS; i++)
75 __put_user(regs->areg[i],
76 gregset->a + ((wb * 4 + i) % XCHAL_NUM_AREGS));
77
78 return 0;
79 }
80
81 static int ptrace_setregs(struct task_struct *child, void __user *uregs)
82 {
83 struct pt_regs *regs = task_pt_regs(child);
84 xtensa_gregset_t *gregset = uregs;
85 const unsigned long ps_mask = PS_CALLINC_MASK | PS_OWB_MASK;
86 unsigned long ps;
87 unsigned long wb, ws;
88
89 if (!access_ok(VERIFY_WRITE, uregs, sizeof(xtensa_gregset_t)))
90 return -EIO;
91
92 __get_user(regs->pc, &gregset->pc);
93 __get_user(ps, &gregset->ps);
94 __get_user(regs->lbeg, &gregset->lbeg);
95 __get_user(regs->lend, &gregset->lend);
96 __get_user(regs->lcount, &gregset->lcount);
97 __get_user(ws, &gregset->windowstart);
98 __get_user(wb, &gregset->windowbase);
99 __get_user(regs->threadptr, &gregset->threadptr);
100
101 regs->ps = (regs->ps & ~ps_mask) | (ps & ps_mask) | (1 << PS_EXCM_BIT);
102
103 if (wb >= XCHAL_NUM_AREGS / 4)
104 return -EFAULT;
105
106 if (wb != regs->windowbase || ws != regs->windowstart) {
107 unsigned long rotws, wmask;
108
109 rotws = (((ws | (ws << WSBITS)) >> wb) &
110 ((1 << WSBITS) - 1)) & ~1;
111 wmask = ((rotws ? WSBITS + 1 - ffs(rotws) : 0) << 4) |
112 (rotws & 0xF) | 1;
113 regs->windowbase = wb;
114 regs->windowstart = ws;
115 regs->wmask = wmask;
116 }
117
118 if (wb != 0 && __copy_from_user(regs->areg + XCHAL_NUM_AREGS - wb * 4,
119 gregset->a, wb * 16))
120 return -EFAULT;
121
122 if (__copy_from_user(regs->areg, gregset->a + wb * 4,
123 (WSBITS - wb) * 16))
124 return -EFAULT;
125
126 return 0;
127 }
128
129
130 static int ptrace_getxregs(struct task_struct *child, void __user *uregs)
131 {
132 struct pt_regs *regs = task_pt_regs(child);
133 struct thread_info *ti = task_thread_info(child);
134 elf_xtregs_t __user *xtregs = uregs;
135 int ret = 0;
136
137 if (!access_ok(VERIFY_WRITE, uregs, sizeof(elf_xtregs_t)))
138 return -EIO;
139
140 #if XTENSA_HAVE_COPROCESSORS
141 /* Flush all coprocessor registers to memory. */
142 coprocessor_flush_all(ti);
143 ret |= __copy_to_user(&xtregs->cp0, &ti->xtregs_cp,
144 sizeof(xtregs_coprocessor_t));
145 #endif
146 ret |= __copy_to_user(&xtregs->opt, ®s->xtregs_opt,
147 sizeof(xtregs->opt));
148 ret |= __copy_to_user(&xtregs->user,&ti->xtregs_user,
149 sizeof(xtregs->user));
150
151 return ret ? -EFAULT : 0;
152 }
153
154 static int ptrace_setxregs(struct task_struct *child, void __user *uregs)
155 {
156 struct thread_info *ti = task_thread_info(child);
157 struct pt_regs *regs = task_pt_regs(child);
158 elf_xtregs_t *xtregs = uregs;
159 int ret = 0;
160
161 if (!access_ok(VERIFY_READ, uregs, sizeof(elf_xtregs_t)))
162 return -EFAULT;
163
164 #if XTENSA_HAVE_COPROCESSORS
165 /* Flush all coprocessors before we overwrite them. */
166 coprocessor_flush_all(ti);
167 coprocessor_release_all(ti);
168
169 ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0,
170 sizeof(xtregs_coprocessor_t));
171 #endif
172 ret |= __copy_from_user(®s->xtregs_opt, &xtregs->opt,
173 sizeof(xtregs->opt));
174 ret |= __copy_from_user(&ti->xtregs_user, &xtregs->user,
175 sizeof(xtregs->user));
176
177 return ret ? -EFAULT : 0;
178 }
179
180 static int ptrace_peekusr(struct task_struct *child, long regno,
181 long __user *ret)
182 {
183 struct pt_regs *regs;
184 unsigned long tmp;
185
186 regs = task_pt_regs(child);
187 tmp = 0; /* Default return value. */
188
189 switch(regno) {
190 case REG_AR_BASE ... REG_AR_BASE + XCHAL_NUM_AREGS - 1:
191 tmp = regs->areg[regno - REG_AR_BASE];
192 break;
193
194 case REG_A_BASE ... REG_A_BASE + 15:
195 tmp = regs->areg[regno - REG_A_BASE];
196 break;
197
198 case REG_PC:
199 tmp = regs->pc;
200 break;
201
202 case REG_PS:
203 /* Note: PS.EXCM is not set while user task is running;
204 * its being set in regs is for exception handling
205 * convenience.
206 */
207 tmp = (regs->ps & ~(1 << PS_EXCM_BIT));
208 break;
209
210 case REG_WB:
211 break; /* tmp = 0 */
212
213 case REG_WS:
214 {
215 unsigned long wb = regs->windowbase;
216 unsigned long ws = regs->windowstart;
217 tmp = ((ws >> wb) | (ws << (WSBITS - wb))) &
218 ((1 << WSBITS) - 1);
219 break;
220 }
221 case REG_LBEG:
222 tmp = regs->lbeg;
223 break;
224
225 case REG_LEND:
226 tmp = regs->lend;
227 break;
228
229 case REG_LCOUNT:
230 tmp = regs->lcount;
231 break;
232
233 case REG_SAR:
234 tmp = regs->sar;
235 break;
236
237 case SYSCALL_NR:
238 tmp = regs->syscall;
239 break;
240
241 default:
242 return -EIO;
243 }
244 return put_user(tmp, ret);
245 }
246
247 static int ptrace_pokeusr(struct task_struct *child, long regno, long val)
248 {
249 struct pt_regs *regs;
250 regs = task_pt_regs(child);
251
252 switch (regno) {
253 case REG_AR_BASE ... REG_AR_BASE + XCHAL_NUM_AREGS - 1:
254 regs->areg[regno - REG_AR_BASE] = val;
255 break;
256
257 case REG_A_BASE ... REG_A_BASE + 15:
258 regs->areg[regno - REG_A_BASE] = val;
259 break;
260
261 case REG_PC:
262 regs->pc = val;
263 break;
264
265 case SYSCALL_NR:
266 regs->syscall = val;
267 break;
268
269 default:
270 return -EIO;
271 }
272 return 0;
273 }
274
275 #ifdef CONFIG_HAVE_HW_BREAKPOINT
276 static void ptrace_hbptriggered(struct perf_event *bp,
277 struct perf_sample_data *data,
278 struct pt_regs *regs)
279 {
280 int i;
281 siginfo_t info;
282 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
283
284 if (bp->attr.bp_type & HW_BREAKPOINT_X) {
285 for (i = 0; i < XCHAL_NUM_IBREAK; ++i)
286 if (current->thread.ptrace_bp[i] == bp)
287 break;
288 i <<= 1;
289 } else {
290 for (i = 0; i < XCHAL_NUM_DBREAK; ++i)
291 if (current->thread.ptrace_wp[i] == bp)
292 break;
293 i = (i << 1) | 1;
294 }
295
296 info.si_signo = SIGTRAP;
297 info.si_errno = i;
298 info.si_code = TRAP_HWBKPT;
299 info.si_addr = (void __user *)bkpt->address;
300
301 force_sig_info(SIGTRAP, &info, current);
302 }
303
304 static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
305 {
306 struct perf_event_attr attr;
307
308 ptrace_breakpoint_init(&attr);
309
310 /* Initialise fields to sane defaults. */
311 attr.bp_addr = 0;
312 attr.bp_len = 1;
313 attr.bp_type = type;
314 attr.disabled = 1;
315
316 return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
317 tsk);
318 }
319
320 /*
321 * Address bit 0 choose instruction (0) or data (1) break register, bits
322 * 31..1 are the register number.
323 * Both PTRACE_GETHBPREGS and PTRACE_SETHBPREGS transfer two 32-bit words:
324 * address (0) and control (1).
325 * Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
326 * Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
327 * 'trigger on load, bits 29..0 are length. Length 0 is used to clear a
328 * breakpoint. To set a breakpoint length must be a power of 2 in the range
329 * 1..64 and the address must be length-aligned.
330 */
331
332 static long ptrace_gethbpregs(struct task_struct *child, long addr,
333 long __user *datap)
334 {
335 struct perf_event *bp;
336 u32 user_data[2] = {0};
337 bool dbreak = addr & 1;
338 unsigned idx = addr >> 1;
339
340 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
341 (dbreak && idx >= XCHAL_NUM_DBREAK))
342 return -EINVAL;
343
344 if (dbreak)
345 bp = child->thread.ptrace_wp[idx];
346 else
347 bp = child->thread.ptrace_bp[idx];
348
349 if (bp) {
350 user_data[0] = bp->attr.bp_addr;
351 user_data[1] = bp->attr.disabled ? 0 : bp->attr.bp_len;
352 if (dbreak) {
353 if (bp->attr.bp_type & HW_BREAKPOINT_R)
354 user_data[1] |= DBREAKC_LOAD_MASK;
355 if (bp->attr.bp_type & HW_BREAKPOINT_W)
356 user_data[1] |= DBREAKC_STOR_MASK;
357 }
358 }
359
360 if (copy_to_user(datap, user_data, sizeof(user_data)))
361 return -EFAULT;
362
363 return 0;
364 }
365
366 static long ptrace_sethbpregs(struct task_struct *child, long addr,
367 long __user *datap)
368 {
369 struct perf_event *bp;
370 struct perf_event_attr attr;
371 u32 user_data[2];
372 bool dbreak = addr & 1;
373 unsigned idx = addr >> 1;
374 int bp_type = 0;
375
376 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
377 (dbreak && idx >= XCHAL_NUM_DBREAK))
378 return -EINVAL;
379
380 if (copy_from_user(user_data, datap, sizeof(user_data)))
381 return -EFAULT;
382
383 if (dbreak) {
384 bp = child->thread.ptrace_wp[idx];
385 if (user_data[1] & DBREAKC_LOAD_MASK)
386 bp_type |= HW_BREAKPOINT_R;
387 if (user_data[1] & DBREAKC_STOR_MASK)
388 bp_type |= HW_BREAKPOINT_W;
389 } else {
390 bp = child->thread.ptrace_bp[idx];
391 bp_type = HW_BREAKPOINT_X;
392 }
393
394 if (!bp) {
395 bp = ptrace_hbp_create(child,
396 bp_type ? bp_type : HW_BREAKPOINT_RW);
397 if (IS_ERR(bp))
398 return PTR_ERR(bp);
399 if (dbreak)
400 child->thread.ptrace_wp[idx] = bp;
401 else
402 child->thread.ptrace_bp[idx] = bp;
403 }
404
405 attr = bp->attr;
406 attr.bp_addr = user_data[0];
407 attr.bp_len = user_data[1] & ~(DBREAKC_LOAD_MASK | DBREAKC_STOR_MASK);
408 attr.bp_type = bp_type;
409 attr.disabled = !attr.bp_len;
410
411 return modify_user_hw_breakpoint(bp, &attr);
412 }
413 #endif
414
415 long arch_ptrace(struct task_struct *child, long request,
416 unsigned long addr, unsigned long data)
417 {
418 int ret = -EPERM;
419 void __user *datap = (void __user *) data;
420
421 switch (request) {
422 case PTRACE_PEEKTEXT: /* read word at location addr. */
423 case PTRACE_PEEKDATA:
424 ret = generic_ptrace_peekdata(child, addr, data);
425 break;
426
427 case PTRACE_PEEKUSR: /* read register specified by addr. */
428 ret = ptrace_peekusr(child, addr, datap);
429 break;
430
431 case PTRACE_POKETEXT: /* write the word at location addr. */
432 case PTRACE_POKEDATA:
433 ret = generic_ptrace_pokedata(child, addr, data);
434 break;
435
436 case PTRACE_POKEUSR: /* write register specified by addr. */
437 ret = ptrace_pokeusr(child, addr, data);
438 break;
439
440 case PTRACE_GETREGS:
441 ret = ptrace_getregs(child, datap);
442 break;
443
444 case PTRACE_SETREGS:
445 ret = ptrace_setregs(child, datap);
446 break;
447
448 case PTRACE_GETXTREGS:
449 ret = ptrace_getxregs(child, datap);
450 break;
451
452 case PTRACE_SETXTREGS:
453 ret = ptrace_setxregs(child, datap);
454 break;
455 #ifdef CONFIG_HAVE_HW_BREAKPOINT
456 case PTRACE_GETHBPREGS:
457 ret = ptrace_gethbpregs(child, addr, datap);
458 break;
459
460 case PTRACE_SETHBPREGS:
461 ret = ptrace_sethbpregs(child, addr, datap);
462 break;
463 #endif
464 default:
465 ret = ptrace_request(child, request, addr, data);
466 break;
467 }
468
469 return ret;
470 }
471
472 unsigned long do_syscall_trace_enter(struct pt_regs *regs)
473 {
474 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
475 tracehook_report_syscall_entry(regs))
476 return -1;
477
478 return regs->areg[2];
479 }
480
481 void do_syscall_trace_leave(struct pt_regs *regs)
482 {
483 int step;
484
485 step = test_thread_flag(TIF_SINGLESTEP);
486
487 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
488 tracehook_report_syscall_exit(regs, step);
489 }
490
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