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Linux/arch/xtensa/variants/dc233c/include/variant/tie-asm.h

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  1 /* 
  2  * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
  3  *
  4  *  NOTE:  This header file is not meant to be included directly.
  5  */
  6 
  7 /* This header file contains assembly-language definitions (assembly
  8    macros, etc.) for this specific Xtensa processor's TIE extensions
  9    and options.  It is customized to this Xtensa processor configuration.
 10 
 11    Copyright (c) 1999-2010 Tensilica Inc.
 12 
 13    Permission is hereby granted, free of charge, to any person obtaining
 14    a copy of this software and associated documentation files (the
 15    "Software"), to deal in the Software without restriction, including
 16    without limitation the rights to use, copy, modify, merge, publish,
 17    distribute, sublicense, and/or sell copies of the Software, and to
 18    permit persons to whom the Software is furnished to do so, subject to
 19    the following conditions:
 20 
 21    The above copyright notice and this permission notice shall be included
 22    in all copies or substantial portions of the Software.
 23 
 24    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 25    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 26    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 27    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
 28    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 29    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 30    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 31 
 32 #ifndef _XTENSA_CORE_TIE_ASM_H
 33 #define _XTENSA_CORE_TIE_ASM_H
 34 
 35 /*  Selection parameter values for save-area save/restore macros:  */
 36 /*  Option vs. TIE:  */
 37 #define XTHAL_SAS_TIE   0x0001  /* custom extension or coprocessor */
 38 #define XTHAL_SAS_OPT   0x0002  /* optional (and not a coprocessor) */
 39 #define XTHAL_SAS_ANYOT 0x0003  /* both of the above */
 40 /*  Whether used automatically by compiler:  */
 41 #define XTHAL_SAS_NOCC  0x0004  /* not used by compiler w/o special opts/code */
 42 #define XTHAL_SAS_CC    0x0008  /* used by compiler without special opts/code */
 43 #define XTHAL_SAS_ANYCC 0x000C  /* both of the above */
 44 /*  ABI handling across function calls:  */
 45 #define XTHAL_SAS_CALR  0x0010  /* caller-saved */
 46 #define XTHAL_SAS_CALE  0x0020  /* callee-saved */
 47 #define XTHAL_SAS_GLOB  0x0040  /* global across function calls (in thread) */
 48 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
 49 /*  Misc  */
 50 #define XTHAL_SAS_ALL   0xFFFF  /* include all default NCP contents */
 51 #define XTHAL_SAS3(optie,ccuse,abi)     ( ((optie) & XTHAL_SAS_ANYOT)  \
 52                                         | ((ccuse) & XTHAL_SAS_ANYCC)  \
 53                                         | ((abi)   & XTHAL_SAS_ANYABI) )
 54 
 55 
 56 
 57     /*
 58      *  Macro to save all non-coprocessor (extra) custom TIE and optional state
 59      *  (not including zero-overhead loop registers).
 60      *  Required parameters:
 61      *      ptr         Save area pointer address register (clobbered)
 62      *                  (register must contain a 4 byte aligned address).
 63      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
 64      *                  registers are clobbered, the remaining are unused).
 65      *  Optional parameters:
 66      *      continue    If macro invoked as part of a larger store sequence, set to 1
 67      *                  if this is not the first in the sequence.  Defaults to 0.
 68      *      ofs         Offset from start of larger sequence (from value of first ptr
 69      *                  in sequence) at which to store.  Defaults to next available space
 70      *                  (or 0 if <continue> is 0).
 71      *      select      Select what category(ies) of registers to store, as a bitmask
 72      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
 73      *      alloc       Select what category(ies) of registers to allocate; if any
 74      *                  category is selected here that is not in <select>, space for
 75      *                  the corresponding registers is skipped without doing any store.
 76      */
 77     .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
 78         xchal_sa_start  \continue, \ofs
 79         // Optional global register used by default by the compiler:
 80         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
 81         xchal_sa_align  \ptr, 0, 1020, 4, 4
 82         rur.THREADPTR   \at1            // threadptr option
 83         s32i    \at1, \ptr, .Lxchal_ofs_+0
 84         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 85         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
 86         xchal_sa_align  \ptr, 0, 1020, 4, 4
 87         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 88         .endif
 89         // Optional caller-saved registers used by default by the compiler:
 90         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
 91         xchal_sa_align  \ptr, 0, 1016, 4, 4
 92         rsr     \at1, ACCLO                     // MAC16 option
 93         s32i    \at1, \ptr, .Lxchal_ofs_+0
 94         rsr     \at1, ACCHI                     // MAC16 option
 95         s32i    \at1, \ptr, .Lxchal_ofs_+4
 96         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 97         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 98         xchal_sa_align  \ptr, 0, 1016, 4, 4
 99         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
100         .endif
101         // Optional caller-saved registers not used by default by the compiler:
102         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
103         xchal_sa_align  \ptr, 0, 1004, 4, 4
104         rsr     \at1, M0                        // MAC16 option
105         s32i    \at1, \ptr, .Lxchal_ofs_+0
106         rsr     \at1, M1                        // MAC16 option
107         s32i    \at1, \ptr, .Lxchal_ofs_+4
108         rsr     \at1, M2                        // MAC16 option
109         s32i    \at1, \ptr, .Lxchal_ofs_+8
110         rsr     \at1, M3                        // MAC16 option
111         s32i    \at1, \ptr, .Lxchal_ofs_+12
112         rsr     \at1, SCOMPARE1                 // conditional store option
113         s32i    \at1, \ptr, .Lxchal_ofs_+16
114         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
115         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
116         xchal_sa_align  \ptr, 0, 1004, 4, 4
117         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
118         .endif
119     .endm       // xchal_ncp_store
120 
121     /*
122      *  Macro to restore all non-coprocessor (extra) custom TIE and optional state
123      *  (not including zero-overhead loop registers).
124      *  Required parameters:
125      *      ptr         Save area pointer address register (clobbered)
126      *                  (register must contain a 4 byte aligned address).
127      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
128      *                  registers are clobbered, the remaining are unused).
129      *  Optional parameters:
130      *      continue    If macro invoked as part of a larger load sequence, set to 1
131      *                  if this is not the first in the sequence.  Defaults to 0.
132      *      ofs         Offset from start of larger sequence (from value of first ptr
133      *                  in sequence) at which to load.  Defaults to next available space
134      *                  (or 0 if <continue> is 0).
135      *      select      Select what category(ies) of registers to load, as a bitmask
136      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
137      *      alloc       Select what category(ies) of registers to allocate; if any
138      *                  category is selected here that is not in <select>, space for
139      *                  the corresponding registers is skipped without doing any load.
140      */
141     .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
142         xchal_sa_start  \continue, \ofs
143         // Optional global register used by default by the compiler:
144         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
145         xchal_sa_align  \ptr, 0, 1020, 4, 4
146         l32i    \at1, \ptr, .Lxchal_ofs_+0
147         wur.THREADPTR   \at1            // threadptr option
148         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
149         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
150         xchal_sa_align  \ptr, 0, 1020, 4, 4
151         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
152         .endif
153         // Optional caller-saved registers used by default by the compiler:
154         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
155         xchal_sa_align  \ptr, 0, 1016, 4, 4
156         l32i    \at1, \ptr, .Lxchal_ofs_+0
157         wsr     \at1, ACCLO                     // MAC16 option
158         l32i    \at1, \ptr, .Lxchal_ofs_+4
159         wsr     \at1, ACCHI                     // MAC16 option
160         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
161         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
162         xchal_sa_align  \ptr, 0, 1016, 4, 4
163         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
164         .endif
165         // Optional caller-saved registers not used by default by the compiler:
166         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
167         xchal_sa_align  \ptr, 0, 1004, 4, 4
168         l32i    \at1, \ptr, .Lxchal_ofs_+0
169         wsr     \at1, M0                        // MAC16 option
170         l32i    \at1, \ptr, .Lxchal_ofs_+4
171         wsr     \at1, M1                        // MAC16 option
172         l32i    \at1, \ptr, .Lxchal_ofs_+8
173         wsr     \at1, M2                        // MAC16 option
174         l32i    \at1, \ptr, .Lxchal_ofs_+12
175         wsr     \at1, M3                        // MAC16 option
176         l32i    \at1, \ptr, .Lxchal_ofs_+16
177         wsr     \at1, SCOMPARE1                 // conditional store option
178         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
179         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
180         xchal_sa_align  \ptr, 0, 1004, 4, 4
181         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
182         .endif
183     .endm       // xchal_ncp_load
184 
185 
186 #define XCHAL_NCP_NUM_ATMPS     1
187 
188 
189 
190 #define XCHAL_SA_NUM_ATMPS      1
191 
192 #endif /*_XTENSA_CORE_TIE_ASM_H*/
193 
194 

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