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Linux/arch/xtensa/variants/de212/include/variant/tie-asm.h

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  1 /* 
  2  * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
  3  *
  4  *  NOTE:  This header file is not meant to be included directly.
  5  */
  6 
  7 /* This header file contains assembly-language definitions (assembly
  8    macros, etc.) for this specific Xtensa processor's TIE extensions
  9    and options.  It is customized to this Xtensa processor configuration.
 10 
 11    Copyright (c) 1999-2015 Cadence Design Systems Inc.
 12 
 13    Permission is hereby granted, free of charge, to any person obtaining
 14    a copy of this software and associated documentation files (the
 15    "Software"), to deal in the Software without restriction, including
 16    without limitation the rights to use, copy, modify, merge, publish,
 17    distribute, sublicense, and/or sell copies of the Software, and to
 18    permit persons to whom the Software is furnished to do so, subject to
 19    the following conditions:
 20 
 21    The above copyright notice and this permission notice shall be included
 22    in all copies or substantial portions of the Software.
 23 
 24    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 25    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 26    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 27    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
 28    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 29    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 30    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 31 
 32 #ifndef _XTENSA_CORE_TIE_ASM_H
 33 #define _XTENSA_CORE_TIE_ASM_H
 34 
 35 /*  Selection parameter values for save-area save/restore macros:  */
 36 /*  Option vs. TIE:  */
 37 #define XTHAL_SAS_TIE   0x0001  /* custom extension or coprocessor */
 38 #define XTHAL_SAS_OPT   0x0002  /* optional (and not a coprocessor) */
 39 #define XTHAL_SAS_ANYOT 0x0003  /* both of the above */
 40 /*  Whether used automatically by compiler:  */
 41 #define XTHAL_SAS_NOCC  0x0004  /* not used by compiler w/o special opts/code */
 42 #define XTHAL_SAS_CC    0x0008  /* used by compiler without special opts/code */
 43 #define XTHAL_SAS_ANYCC 0x000C  /* both of the above */
 44 /*  ABI handling across function calls:  */
 45 #define XTHAL_SAS_CALR  0x0010  /* caller-saved */
 46 #define XTHAL_SAS_CALE  0x0020  /* callee-saved */
 47 #define XTHAL_SAS_GLOB  0x0040  /* global across function calls (in thread) */
 48 #define XTHAL_SAS_ANYABI        0x0070  /* all of the above three */
 49 /*  Misc  */
 50 #define XTHAL_SAS_ALL   0xFFFF  /* include all default NCP contents */
 51 #define XTHAL_SAS3(optie,ccuse,abi)     ( ((optie) & XTHAL_SAS_ANYOT)  \
 52                                         | ((ccuse) & XTHAL_SAS_ANYCC)  \
 53                                         | ((abi)   & XTHAL_SAS_ANYABI) )
 54 
 55 
 56     /*
 57       *  Macro to store all non-coprocessor (extra) custom TIE and optional state
 58       *  (not including zero-overhead loop registers).
 59       *  Required parameters:
 60       *      ptr         Save area pointer address register (clobbered)
 61       *                  (register must contain a 4 byte aligned address).
 62       *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
 63       *                  registers are clobbered, the remaining are unused).
 64       *  Optional parameters:
 65       *      continue    If macro invoked as part of a larger store sequence, set to 1
 66       *                  if this is not the first in the sequence.  Defaults to 0.
 67       *      ofs         Offset from start of larger sequence (from value of first ptr
 68       *                  in sequence) at which to store.  Defaults to next available space
 69       *                  (or 0 if <continue> is 0).
 70       *      select      Select what category(ies) of registers to store, as a bitmask
 71       *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
 72       *      alloc       Select what category(ies) of registers to allocate; if any
 73       *                  category is selected here that is not in <select>, space for
 74       *                  the corresponding registers is skipped without doing any store.
 75       */
 76     .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
 77         xchal_sa_start  \continue, \ofs
 78         // Optional caller-saved registers used by default by the compiler:
 79         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
 80         xchal_sa_align  \ptr, 0, 1016, 4, 4
 81         rsr.ACCLO       \at1            // MAC16 option
 82         s32i    \at1, \ptr, .Lxchal_ofs_+0
 83         rsr.ACCHI       \at1            // MAC16 option
 84         s32i    \at1, \ptr, .Lxchal_ofs_+4
 85         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 86         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 87         xchal_sa_align  \ptr, 0, 1016, 4, 4
 88         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 89         .endif
 90         // Optional caller-saved registers not used by default by the compiler:
 91         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
 92         xchal_sa_align  \ptr, 0, 1004, 4, 4
 93         rsr.SCOMPARE1   \at1            // conditional store option
 94         s32i    \at1, \ptr, .Lxchal_ofs_+0
 95         rsr.M0  \at1            // MAC16 option
 96         s32i    \at1, \ptr, .Lxchal_ofs_+4
 97         rsr.M1  \at1            // MAC16 option
 98         s32i    \at1, \ptr, .Lxchal_ofs_+8
 99         rsr.M2  \at1            // MAC16 option
100         s32i    \at1, \ptr, .Lxchal_ofs_+12
101         rsr.M3  \at1            // MAC16 option
102         s32i    \at1, \ptr, .Lxchal_ofs_+16
103         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
104         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
105         xchal_sa_align  \ptr, 0, 1004, 4, 4
106         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
107         .endif
108     .endm       // xchal_ncp_store
109 
110     /*
111       *  Macro to load all non-coprocessor (extra) custom TIE and optional state
112       *  (not including zero-overhead loop registers).
113       *  Required parameters:
114       *      ptr         Save area pointer address register (clobbered)
115       *                  (register must contain a 4 byte aligned address).
116       *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
117       *                  registers are clobbered, the remaining are unused).
118       *  Optional parameters:
119       *      continue    If macro invoked as part of a larger load sequence, set to 1
120       *                  if this is not the first in the sequence.  Defaults to 0.
121       *      ofs         Offset from start of larger sequence (from value of first ptr
122       *                  in sequence) at which to load.  Defaults to next available space
123       *                  (or 0 if <continue> is 0).
124       *      select      Select what category(ies) of registers to load, as a bitmask
125       *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
126       *      alloc       Select what category(ies) of registers to allocate; if any
127       *                  category is selected here that is not in <select>, space for
128       *                  the corresponding registers is skipped without doing any load.
129       */
130     .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
131         xchal_sa_start  \continue, \ofs
132         // Optional caller-saved registers used by default by the compiler:
133         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
134         xchal_sa_align  \ptr, 0, 1016, 4, 4
135         l32i    \at1, \ptr, .Lxchal_ofs_+0
136         wsr.ACCLO       \at1            // MAC16 option
137         l32i    \at1, \ptr, .Lxchal_ofs_+4
138         wsr.ACCHI       \at1            // MAC16 option
139         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
140         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
141         xchal_sa_align  \ptr, 0, 1016, 4, 4
142         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
143         .endif
144         // Optional caller-saved registers not used by default by the compiler:
145         .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
146         xchal_sa_align  \ptr, 0, 1004, 4, 4
147         l32i    \at1, \ptr, .Lxchal_ofs_+0
148         wsr.SCOMPARE1   \at1            // conditional store option
149         l32i    \at1, \ptr, .Lxchal_ofs_+4
150         wsr.M0  \at1            // MAC16 option
151         l32i    \at1, \ptr, .Lxchal_ofs_+8
152         wsr.M1  \at1            // MAC16 option
153         l32i    \at1, \ptr, .Lxchal_ofs_+12
154         wsr.M2  \at1            // MAC16 option
155         l32i    \at1, \ptr, .Lxchal_ofs_+16
156         wsr.M3  \at1            // MAC16 option
157         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
158         .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
159         xchal_sa_align  \ptr, 0, 1004, 4, 4
160         .set    .Lxchal_ofs_, .Lxchal_ofs_ + 20
161         .endif
162     .endm       // xchal_ncp_load
163 
164 
165 #define XCHAL_NCP_NUM_ATMPS     1
166 
167 #define XCHAL_SA_NUM_ATMPS      1
168 
169 #endif /*_XTENSA_CORE_TIE_ASM_H*/
170 
171 

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