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TOMOYO Linux Cross Reference
Linux/include/asm-ia64/sn/pci/pcibr.h

Version: ~ [ linux-5.0-rc6 ] ~ [ linux-4.20.10 ] ~ [ linux-4.19.23 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.101 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.158 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.174 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.134 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.63 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* $Id$
  2  *
  3  * This file is subject to the terms and conditions of the GNU General Public
  4  * License.  See the file "COPYING" in the main directory of this archive
  5  * for more details.
  6  *
  7  * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
  8  */
  9 #ifndef _ASM_SN_PCI_PCIBR_H
 10 #define _ASM_SN_PCI_PCIBR_H
 11 
 12 #if defined(__KERNEL__)
 13 
 14 #include <linux/config.h>
 15 #include <asm/sn/dmamap.h>
 16 #include <asm/sn/driver.h>
 17 #include <asm/sn/pio.h>
 18 
 19 #include <asm/sn/pci/pciio.h>
 20 #include <asm/sn/pci/bridge.h>
 21 
 22 /* =====================================================================
 23  *    symbolic constants used by pcibr's xtalk bus provider
 24  */
 25 
 26 #define PCIBR_PIOMAP_BUSY               0x80000000
 27 
 28 #define PCIBR_DMAMAP_BUSY               0x80000000
 29 #define PCIBR_DMAMAP_SSRAM              0x40000000
 30 
 31 #define PCIBR_INTR_BLOCKED              0x40000000
 32 #define PCIBR_INTR_BUSY                 0x80000000
 33 
 34 #ifndef __ASSEMBLY__
 35 
 36 /* =====================================================================
 37  *    opaque types used by pcibr's xtalk bus provider
 38  */
 39 
 40 typedef struct pcibr_piomap_s *pcibr_piomap_t;
 41 typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
 42 typedef struct pcibr_intr_s *pcibr_intr_t;
 43 
 44 /* =====================================================================
 45  *    primary entry points: Bridge (pcibr) device driver
 46  *
 47  *      These functions are normal device driver entry points
 48  *      and are called along with the similar entry points from
 49  *      other device drivers. They are included here as documentation
 50  *      of their existence and purpose.
 51  *
 52  *      pcibr_init() is called to inform us that there is a pcibr driver
 53  *      configured into the kernel; it is responsible for registering
 54  *      as a crosstalk widget and providing a routine to be called
 55  *      when a widget with the proper part number is observed.
 56  *
 57  *      pcibr_attach() is called for each vertex in the hardware graph
 58  *      corresponding to a crosstalk widget with the manufacturer
 59  *      code and part number registered by pcibr_init().
 60  */
 61 
 62 extern int              pcibr_attach(vertex_hdl_t);
 63 
 64 /* =====================================================================
 65  *    bus provider function table
 66  *
 67  *      Normally, this table is only handed off explicitly
 68  *      during provider initialization, and the PCI generic
 69  *      layer will stash a pointer to it in the vertex; however,
 70  *      exporting it explicitly enables a performance hack in
 71  *      the generic PCI provider where if we know at compile
 72  *      time that the only possible PCI provider is a
 73  *      pcibr, we can go directly to this ops table.
 74  */
 75 
 76 extern pciio_provider_t pcibr_provider;
 77 extern pciio_provider_t pci_pic_provider;
 78 
 79 /* =====================================================================
 80  *    secondary entry points: pcibr PCI bus provider
 81  *
 82  *      These functions are normally exported explicitly by
 83  *      a direct call from the pcibr initialization routine
 84  *      into the generic crosstalk provider; they are included
 85  *      here to enable a more aggressive performance hack in
 86  *      the generic crosstalk layer, where if we know that the
 87  *      only possible crosstalk provider is pcibr, and we can
 88  *      guarantee that all entry points are properly named, and
 89  *      we can deal with the implicit casting properly, then
 90  *      we can turn many of the generic provider routines into
 91  *      plain brances, or even eliminate them (given sufficient
 92  *      smarts on the part of the compilation system).
 93  */
 94 
 95 extern pcibr_piomap_t   pcibr_piomap_alloc(vertex_hdl_t dev,
 96                                            device_desc_t dev_desc,
 97                                            pciio_space_t space,
 98                                            iopaddr_t pci_addr,
 99                                            size_t byte_count,
100                                            size_t byte_count_max,
101                                            unsigned flags);
102 
103 extern void             pcibr_piomap_free(pcibr_piomap_t piomap);
104 
105 extern caddr_t          pcibr_piomap_addr(pcibr_piomap_t piomap,
106                                           iopaddr_t xtalk_addr,
107                                           size_t byte_count);
108 
109 extern void             pcibr_piomap_done(pcibr_piomap_t piomap);
110 
111 extern caddr_t          pcibr_piotrans_addr(vertex_hdl_t dev,
112                                             device_desc_t dev_desc,
113                                             pciio_space_t space,
114                                             iopaddr_t pci_addr,
115                                             size_t byte_count,
116                                             unsigned flags);
117 
118 extern iopaddr_t        pcibr_piospace_alloc(vertex_hdl_t dev,
119                                              device_desc_t dev_desc,
120                                              pciio_space_t space,
121                                              size_t byte_count,
122                                              size_t alignment);
123 extern void             pcibr_piospace_free(vertex_hdl_t dev,
124                                             pciio_space_t space,
125                                             iopaddr_t pciaddr,
126                                             size_t byte_count);
127 
128 extern pcibr_dmamap_t   pcibr_dmamap_alloc(vertex_hdl_t dev,
129                                            device_desc_t dev_desc,
130                                            size_t byte_count_max,
131                                            unsigned flags);
132 
133 extern void             pcibr_dmamap_free(pcibr_dmamap_t dmamap);
134 
135 extern iopaddr_t        pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
136                                           paddr_t paddr,
137                                           size_t byte_count);
138 
139 extern alenlist_t       pcibr_dmamap_list(pcibr_dmamap_t dmamap,
140                                           alenlist_t palenlist,
141                                           unsigned flags);
142 
143 extern void             pcibr_dmamap_done(pcibr_dmamap_t dmamap);
144 
145 /*
146  * pcibr_get_dmatrans_node() will return the compact node id to which  
147  * all 32-bit Direct Mapping memory accesses will be directed.
148  * (This node id can be different for each PCI bus.) 
149  */
150 
151 extern cnodeid_t        pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl);
152 
153 extern iopaddr_t        pcibr_dmatrans_addr(vertex_hdl_t dev,
154                                             device_desc_t dev_desc,
155                                             paddr_t paddr,
156                                             size_t byte_count,
157                                             unsigned flags);
158 
159 extern alenlist_t       pcibr_dmatrans_list(vertex_hdl_t dev,
160                                             device_desc_t dev_desc,
161                                             alenlist_t palenlist,
162                                             unsigned flags);
163 
164 extern void             pcibr_dmamap_drain(pcibr_dmamap_t map);
165 
166 extern void             pcibr_dmaaddr_drain(vertex_hdl_t vhdl,
167                                             paddr_t addr,
168                                             size_t bytes);
169 
170 extern void             pcibr_dmalist_drain(vertex_hdl_t vhdl,
171                                             alenlist_t list);
172 
173 typedef unsigned        pcibr_intr_ibit_f(pciio_info_t info,
174                                           pciio_intr_line_t lines);
175 
176 extern void             pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *);
177 
178 extern pcibr_intr_t     pcibr_intr_alloc(vertex_hdl_t dev,
179                                          device_desc_t dev_desc,
180                                          pciio_intr_line_t lines,
181                                          vertex_hdl_t owner_dev);
182 
183 extern void             pcibr_intr_free(pcibr_intr_t intr);
184 
185 extern int              pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t);
186 
187 extern void             pcibr_intr_disconnect(pcibr_intr_t intr);
188 
189 extern vertex_hdl_t     pcibr_intr_cpu_get(pcibr_intr_t intr);
190 
191 extern void             pcibr_provider_startup(vertex_hdl_t pcibr);
192 
193 extern void             pcibr_provider_shutdown(vertex_hdl_t pcibr);
194 
195 extern int              pcibr_reset(vertex_hdl_t dev);
196 
197 extern int              pcibr_write_gather_flush(vertex_hdl_t dev);
198 
199 extern pciio_endian_t   pcibr_endian_set(vertex_hdl_t dev,
200                                          pciio_endian_t device_end,
201                                          pciio_endian_t desired_end);
202 
203 extern pciio_priority_t pcibr_priority_set(vertex_hdl_t dev,
204                                            pciio_priority_t device_prio);
205 
206 extern uint64_t         pcibr_config_get(vertex_hdl_t conn,
207                                          unsigned reg,
208                                          unsigned size);
209 
210 extern void             pcibr_config_set(vertex_hdl_t conn,
211                                          unsigned reg,
212                                          unsigned size,
213                                          uint64_t value);
214 
215 extern int              pcibr_error_devenable(vertex_hdl_t pconn_vhdl,
216                                               int error_code);
217 
218 extern int              pcibr_wrb_flush(vertex_hdl_t pconn_vhdl);
219 extern int              pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
220                                         int *count_vchan0,
221                                         int *count_vchan1,
222                                         int *count_reserved,
223                                         int *count_pool);
224 
225 extern int              pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd,
226                                              int dev_1_rrbs, int virt1,
227                                              int dev_2_rrbs, int virt2,
228                                              int dev_3_rrbs, int virt3,
229                                              int dev_4_rrbs, int virt4);
230 
231 typedef void
232 rrb_alloc_funct_f       (vertex_hdl_t xconn_vhdl,
233                          int *vendor_list);
234 
235 typedef rrb_alloc_funct_f      *rrb_alloc_funct_t;
236 
237 void                    pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
238                                                rrb_alloc_funct_f *func);
239 
240 extern int              pcibr_device_unregister(vertex_hdl_t);
241 extern int              pcibr_dma_enabled(vertex_hdl_t);
242 /*
243  * Bridge-specific flags that can be set via pcibr_device_flags_set
244  * and cleared via pcibr_device_flags_clear.  Other flags are
245  * more generic and are maniuplated through PCI-generic interfaces.
246  *
247  * Note that all PCI implementation-specific flags (Bridge flags, in
248  * this case) are in bits 15-31.  The lower 15 bits are reserved
249  * for PCI-generic flags.
250  *
251  * Some of these flags have been "promoted" to the
252  * generic layer, so they can be used without having
253  * to "know" that the PCI bus is hosted by a Bridge.
254  *
255  * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when 
256  * allocating ATE's. ATE count computation will assume that the
257  * address to be mapped will start on a page boundary.
258  */
259 #define PCIBR_NO_ATE_ROUNDUP    0x00008000
260 #define PCIBR_WRITE_GATHER      0x00010000      /* please use PCIIO version */
261 #define PCIBR_NOWRITE_GATHER    0x00020000      /* please use PCIIO version */
262 #define PCIBR_PREFETCH          0x00040000      /* please use PCIIO version */
263 #define PCIBR_NOPREFETCH        0x00080000      /* please use PCIIO version */
264 #define PCIBR_PRECISE           0x00100000
265 #define PCIBR_NOPRECISE         0x00200000
266 #define PCIBR_BARRIER           0x00400000
267 #define PCIBR_NOBARRIER         0x00800000
268 #define PCIBR_VCHAN0            0x01000000
269 #define PCIBR_VCHAN1            0x02000000
270 #define PCIBR_64BIT             0x04000000
271 #define PCIBR_NO64BIT           0x08000000
272 #define PCIBR_SWAP              0x10000000
273 #define PCIBR_NOSWAP            0x20000000
274 
275 #define PCIBR_EXTERNAL_ATES     0x40000000      /* uses external ATEs */
276 #define PCIBR_ACTIVE            0x80000000      /* need a "done" */
277 
278 /* Flags that have meaning to pcibr_device_flags_{set,clear} */
279 #define PCIBR_DEVICE_FLAGS (    \
280         PCIBR_WRITE_GATHER      |\
281         PCIBR_NOWRITE_GATHER    |\
282         PCIBR_PREFETCH          |\
283         PCIBR_NOPREFETCH        |\
284         PCIBR_PRECISE           |\
285         PCIBR_NOPRECISE         |\
286         PCIBR_BARRIER           |\
287         PCIBR_NOBARRIER         \
288 )
289 
290 /* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
291 #define PCIBR_DMA_FLAGS (       \
292         PCIBR_PREFETCH          |\
293         PCIBR_NOPREFETCH        |\
294         PCIBR_PRECISE           |\
295         PCIBR_NOPRECISE         |\
296         PCIBR_BARRIER           |\
297         PCIBR_NOBARRIER         |\
298         PCIBR_VCHAN0            |\
299         PCIBR_VCHAN1            \
300 )
301 
302 typedef int             pcibr_device_flags_t;
303 
304 /*
305  * Set bits in the Bridge Device(x) register for this device.
306  * "flags" are defined above. NOTE: this includes turning
307  * things *OFF* as well as turning them *ON* ...
308  */
309 extern int              pcibr_device_flags_set(vertex_hdl_t dev,
310                                              pcibr_device_flags_t flags);
311 
312 /*
313  * Allocate Read Response Buffers for use by the specified device.
314  * count_vchan0 is the total number of buffers desired for the
315  * "normal" channel.  count_vchan1 is the total number of buffers
316  * desired for the "virtual" channel.  Returns 0 on success, or
317  * <0 on failure, which occurs when we're unable to allocate any
318  * buffers to a channel that desires at least one buffer.
319  */
320 extern int              pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
321                                         int *count_vchan0,
322                                         int *count_vchan1);
323 
324 /*
325  * Get the starting PCIbus address out of the given DMA map.
326  * This function is supposed to be used by a close friend of PCI bridge
327  * since it relies on the fact that the starting address of the map is fixed at
328  * the allocation time in the current implementation of PCI bridge.
329  */
330 extern iopaddr_t        pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
331 
332 extern xwidget_intr_preset_f pcibr_xintr_preset;
333 
334 extern void             pcibr_hints_fix_rrbs(vertex_hdl_t);
335 extern void             pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t);
336 extern void             pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong);
337 extern void             pcibr_hints_handsoff(vertex_hdl_t);
338 
339 typedef unsigned        pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int);
340 extern void             pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *);
341 
342 extern int              pcibr_asic_rev(vertex_hdl_t);
343 
344 #endif  /* __ASSEMBLY__ */
345 #endif  /* #if defined(__KERNEL__) */
346 /* 
347  * Some useful ioctls into the pcibr driver
348  */
349 #define PCIBR                   'p'
350 #define _PCIBR(x)               ((PCIBR << 8) | (x))
351 
352 #define PCIBR_SLOT_STARTUP      _PCIBR(1)
353 #define PCIBR_SLOT_SHUTDOWN     _PCIBR(2)
354 #define PCIBR_SLOT_QUERY        _PCIBR(3)
355 
356 /*
357  * Bit defintions for variable slot_status in struct
358  * pcibr_soft_slot_s.  They are here so that both
359  * the pcibr driver and the pciconfig command can
360  * reference them.
361  */
362 #define SLOT_STARTUP_CMPLT      0x01
363 #define SLOT_STARTUP_INCMPLT    0x02
364 #define SLOT_SHUTDOWN_CMPLT     0x04
365 #define SLOT_SHUTDOWN_INCMPLT   0x08
366 #define SLOT_POWER_UP           0x10
367 #define SLOT_POWER_DOWN         0x20
368 #define SLOT_IS_SYS_CRITICAL    0x40
369 
370 #define SLOT_STATUS_MASK        (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \
371                                  SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT)
372 #define SLOT_POWER_MASK         (SLOT_POWER_UP | SLOT_POWER_DOWN)
373 
374 /*
375  * Bit definitions for variable resp_f_staus.
376  * They are here so that both the pcibr driver
377  * and the pciconfig command can reference them.
378  */
379 #define FUNC_IS_VALID           0x01
380 #define FUNC_IS_SYS_CRITICAL    0x02
381 
382 /*
383  * Structures for requesting PCI bridge information and receiving a response
384  */
385 typedef struct pcibr_slot_req_s *pcibr_slot_req_t;
386 typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t;
387 typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t;
388 typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
389 typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
390 
391 #define L1_QSIZE                128      /* our L1 message buffer size */
392 struct pcibr_slot_req_s {
393     int                      req_slot;
394     union {
395         pcibr_slot_up_resp_t     up;
396         pcibr_slot_down_resp_t   down;
397         pcibr_slot_info_resp_t   query;
398         void                    *any;
399     }                       req_respp;
400     int                     req_size;
401 };
402 
403 struct pcibr_slot_up_resp_s {
404     int                     resp_sub_errno;
405     char                    resp_l1_msg[L1_QSIZE + 1];
406 };
407 
408 struct pcibr_slot_down_resp_s {
409     int                     resp_sub_errno;
410     char                    resp_l1_msg[L1_QSIZE + 1];
411 };
412 
413 struct pcibr_slot_info_resp_s {
414     short                   resp_bs_bridge_type;
415     short                   resp_bs_bridge_mode;
416     int                     resp_has_host;
417     char                    resp_host_slot;
418     vertex_hdl_t            resp_slot_conn;
419     char                    resp_slot_conn_name[MAXDEVNAME];
420     int                     resp_slot_status;
421     int                     resp_l1_bus_num;
422     int                     resp_bss_ninfo;
423     char                    resp_bss_devio_bssd_space[16];
424     iopaddr_t               resp_bss_devio_bssd_base; 
425     bridgereg_t             resp_bss_device;
426     int                     resp_bss_pmu_uctr;
427     int                     resp_bss_d32_uctr;
428     int                     resp_bss_d64_uctr;
429     iopaddr_t               resp_bss_d64_base;
430     unsigned                resp_bss_d64_flags;
431     iopaddr_t               resp_bss_d32_base;
432     unsigned                resp_bss_d32_flags;
433     atomic_t                resp_bss_ext_ates_active;
434     volatile unsigned      *resp_bss_cmd_pointer;
435     unsigned                resp_bss_cmd_shadow;
436     int                     resp_bs_rrb_valid;
437     int                     resp_bs_rrb_valid_v1;
438     int                     resp_bs_rrb_valid_v2;
439     int                     resp_bs_rrb_valid_v3;
440     int                     resp_bs_rrb_res;
441     bridgereg_t             resp_b_resp;
442     bridgereg_t             resp_b_int_device;
443     bridgereg_t             resp_b_int_enable;
444     bridgereg_t             resp_b_int_host;
445     picreg_t                resp_p_int_enable;
446     picreg_t                resp_p_int_host;
447     struct pcibr_slot_func_info_resp_s {
448         int                     resp_f_status;
449         char                    resp_f_slot_name[MAXDEVNAME];
450         char                    resp_f_bus;
451         char                    resp_f_slot;
452         char                    resp_f_func;
453         char                    resp_f_master_name[MAXDEVNAME];
454         void                   *resp_f_pops;
455         error_handler_f        *resp_f_efunc;
456         error_handler_arg_t     resp_f_einfo;
457         int                     resp_f_vendor;
458         int                     resp_f_device;
459 
460         struct {
461             char                    resp_w_space[16];
462             iopaddr_t               resp_w_base;
463             size_t                  resp_w_size;
464         } resp_f_window[6];
465 
466         unsigned                resp_f_rbase;
467         unsigned                resp_f_rsize;
468         int                     resp_f_ibit[4];
469         int                     resp_f_att_det_error;
470 
471     } resp_func[8];
472 };
473 
474 
475 /*
476  * PCI specific errors, interpreted by pciconfig command
477  */
478 
479 /* EPERM                          1    */
480 #define PCI_SLOT_ALREADY_UP       2     /* slot already up */
481 #define PCI_SLOT_ALREADY_DOWN     3     /* slot already down */
482 #define PCI_IS_SYS_CRITICAL       4     /* slot is system critical */
483 /* EIO                            5    */
484 /* ENXIO                          6    */
485 #define PCI_L1_ERR                7     /* L1 console command error */
486 #define PCI_NOT_A_BRIDGE          8     /* device is not a bridge */
487 #define PCI_SLOT_IN_SHOEHORN      9     /* slot is in a shorhorn */
488 #define PCI_NOT_A_SLOT           10     /* slot is invalid */
489 #define PCI_RESP_AREA_TOO_SMALL  11     /* slot is invalid */
490 /* ENOMEM                        12    */
491 #define PCI_NO_DRIVER            13     /* no driver for device */
492 /* EFAULT                        14    */
493 #define PCI_EMPTY_33MHZ          15     /* empty 33 MHz bus */
494 /* EBUSY                         16    */
495 #define PCI_SLOT_RESET_ERR       17     /* slot reset error */
496 #define PCI_SLOT_INFO_INIT_ERR   18     /* slot info init error */
497 /* ENODEV                        19    */
498 #define PCI_SLOT_ADDR_INIT_ERR   20     /* slot addr space init error */
499 #define PCI_SLOT_DEV_INIT_ERR    21     /* slot device init error */
500 /* EINVAL                        22    */
501 #define PCI_SLOT_GUEST_INIT_ERR  23     /* slot guest info init error */
502 #define PCI_SLOT_RRB_ALLOC_ERR   24     /* slot initial rrb alloc error */
503 #define PCI_SLOT_DRV_ATTACH_ERR  25     /* driver attach error */
504 #define PCI_SLOT_DRV_DETACH_ERR  26     /* driver detach error */
505 /* EFBIG                         27    */
506 #define PCI_MULTI_FUNC_ERR       28     /* multi-function card error */
507 #define PCI_SLOT_RBAR_ALLOC_ERR  29     /* slot PCI-X RBAR alloc error */
508 /* ERANGE                        34    */
509 /* EUNATCH                       42    */
510 
511 #endif                          /* _ASM_SN_PCI_PCIBR_H */
512 

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