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TOMOYO Linux Cross Reference
Linux/include/drm/drm_edid.h

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  1 /*
  2  * Copyright © 2007-2008 Intel Corporation
  3  *   Jesse Barnes <jesse.barnes@intel.com>
  4  *
  5  * Permission is hereby granted, free of charge, to any person obtaining a
  6  * copy of this software and associated documentation files (the "Software"),
  7  * to deal in the Software without restriction, including without limitation
  8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9  * and/or sell copies of the Software, and to permit persons to whom the
 10  * Software is furnished to do so, subject to the following conditions:
 11  *
 12  * The above copyright notice and this permission notice shall be included in
 13  * all copies or substantial portions of the Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21  * OTHER DEALINGS IN THE SOFTWARE.
 22  */
 23 #ifndef __DRM_EDID_H__
 24 #define __DRM_EDID_H__
 25 
 26 #include <linux/types.h>
 27 #include <linux/hdmi.h>
 28 
 29 struct drm_device;
 30 struct i2c_adapter;
 31 
 32 #define EDID_LENGTH 128
 33 #define DDC_ADDR 0x50
 34 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
 35 
 36 #define CEA_EXT     0x02
 37 #define VTB_EXT     0x10
 38 #define DI_EXT      0x40
 39 #define LS_EXT      0x50
 40 #define MI_EXT      0x60
 41 #define DISPLAYID_EXT 0x70
 42 
 43 struct est_timings {
 44         u8 t1;
 45         u8 t2;
 46         u8 mfg_rsvd;
 47 } __attribute__((packed));
 48 
 49 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
 50 #define EDID_TIMING_ASPECT_SHIFT 6
 51 #define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
 52 
 53 /* need to add 60 */
 54 #define EDID_TIMING_VFREQ_SHIFT  0
 55 #define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
 56 
 57 struct std_timing {
 58         u8 hsize; /* need to multiply by 8 then add 248 */
 59         u8 vfreq_aspect;
 60 } __attribute__((packed));
 61 
 62 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
 63 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
 64 #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
 65 #define DRM_EDID_PT_STEREO         (1 << 5)
 66 #define DRM_EDID_PT_INTERLACED     (1 << 7)
 67 
 68 /* If detailed data is pixel timing */
 69 struct detailed_pixel_timing {
 70         u8 hactive_lo;
 71         u8 hblank_lo;
 72         u8 hactive_hblank_hi;
 73         u8 vactive_lo;
 74         u8 vblank_lo;
 75         u8 vactive_vblank_hi;
 76         u8 hsync_offset_lo;
 77         u8 hsync_pulse_width_lo;
 78         u8 vsync_offset_pulse_width_lo;
 79         u8 hsync_vsync_offset_pulse_width_hi;
 80         u8 width_mm_lo;
 81         u8 height_mm_lo;
 82         u8 width_height_mm_hi;
 83         u8 hborder;
 84         u8 vborder;
 85         u8 misc;
 86 } __attribute__((packed));
 87 
 88 /* If it's not pixel timing, it'll be one of the below */
 89 struct detailed_data_string {
 90         u8 str[13];
 91 } __attribute__((packed));
 92 
 93 struct detailed_data_monitor_range {
 94         u8 min_vfreq;
 95         u8 max_vfreq;
 96         u8 min_hfreq_khz;
 97         u8 max_hfreq_khz;
 98         u8 pixel_clock_mhz; /* need to multiply by 10 */
 99         u8 flags;
100         union {
101                 struct {
102                         u8 reserved;
103                         u8 hfreq_start_khz; /* need to multiply by 2 */
104                         u8 c; /* need to divide by 2 */
105                         __le16 m;
106                         u8 k;
107                         u8 j; /* need to divide by 2 */
108                 } __attribute__((packed)) gtf2;
109                 struct {
110                         u8 version;
111                         u8 data1; /* high 6 bits: extra clock resolution */
112                         u8 data2; /* plus low 2 of above: max hactive */
113                         u8 supported_aspects;
114                         u8 flags; /* preferred aspect and blanking support */
115                         u8 supported_scalings;
116                         u8 preferred_refresh;
117                 } __attribute__((packed)) cvt;
118         } formula;
119 } __attribute__((packed));
120 
121 struct detailed_data_wpindex {
122         u8 white_yx_lo; /* Lower 2 bits each */
123         u8 white_x_hi;
124         u8 white_y_hi;
125         u8 gamma; /* need to divide by 100 then add 1 */
126 } __attribute__((packed));
127 
128 struct detailed_data_color_point {
129         u8 windex1;
130         u8 wpindex1[3];
131         u8 windex2;
132         u8 wpindex2[3];
133 } __attribute__((packed));
134 
135 struct cvt_timing {
136         u8 code[3];
137 } __attribute__((packed));
138 
139 struct detailed_non_pixel {
140         u8 pad1;
141         u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
142                     fb=color point data, fa=standard timing data,
143                     f9=undefined, f8=mfg. reserved */
144         u8 pad2;
145         union {
146                 struct detailed_data_string str;
147                 struct detailed_data_monitor_range range;
148                 struct detailed_data_wpindex color;
149                 struct std_timing timings[6];
150                 struct cvt_timing cvt[4];
151         } data;
152 } __attribute__((packed));
153 
154 #define EDID_DETAIL_EST_TIMINGS 0xf7
155 #define EDID_DETAIL_CVT_3BYTE 0xf8
156 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
157 #define EDID_DETAIL_STD_MODES 0xfa
158 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
159 #define EDID_DETAIL_MONITOR_NAME 0xfc
160 #define EDID_DETAIL_MONITOR_RANGE 0xfd
161 #define EDID_DETAIL_MONITOR_STRING 0xfe
162 #define EDID_DETAIL_MONITOR_SERIAL 0xff
163 
164 struct detailed_timing {
165         __le16 pixel_clock; /* need to multiply by 10 KHz */
166         union {
167                 struct detailed_pixel_timing pixel_data;
168                 struct detailed_non_pixel other_data;
169         } data;
170 } __attribute__((packed));
171 
172 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
173 #define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
174 #define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
175 #define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
176 #define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
177 #define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
178 #define DRM_EDID_INPUT_DIGITAL         (1 << 7)
179 #define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
180 #define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
181 #define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
182 #define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
183 #define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
184 #define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
185 #define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
186 #define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
187 #define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
188 #define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
189 #define DRM_EDID_DIGITAL_TYPE_DVI      (1)
190 #define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
191 #define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
192 #define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
193 #define DRM_EDID_DIGITAL_TYPE_DP       (5)
194 
195 #define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
196 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
197 #define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
198 /* If analog */
199 #define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
200 /* If digital */
201 #define DRM_EDID_FEATURE_COLOR_MASK       (3 << 3)
202 #define DRM_EDID_FEATURE_RGB              (0 << 3)
203 #define DRM_EDID_FEATURE_RGB_YCRCB444     (1 << 3)
204 #define DRM_EDID_FEATURE_RGB_YCRCB422     (2 << 3)
205 #define DRM_EDID_FEATURE_RGB_YCRCB        (3 << 3) /* both 4:4:4 and 4:2:2 */
206 
207 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
208 #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
209 #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
210 
211 #define DRM_EDID_HDMI_DC_48               (1 << 6)
212 #define DRM_EDID_HDMI_DC_36               (1 << 5)
213 #define DRM_EDID_HDMI_DC_30               (1 << 4)
214 #define DRM_EDID_HDMI_DC_Y444             (1 << 3)
215 
216 /* YCBCR 420 deep color modes */
217 #define DRM_EDID_YCBCR420_DC_48           (1 << 2)
218 #define DRM_EDID_YCBCR420_DC_36           (1 << 1)
219 #define DRM_EDID_YCBCR420_DC_30           (1 << 0)
220 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
221                                     DRM_EDID_YCBCR420_DC_36 | \
222                                     DRM_EDID_YCBCR420_DC_30)
223 
224 /* ELD Header Block */
225 #define DRM_ELD_HEADER_BLOCK_SIZE       4
226 
227 #define DRM_ELD_VER                     0
228 # define DRM_ELD_VER_SHIFT              3
229 # define DRM_ELD_VER_MASK               (0x1f << 3)
230 # define DRM_ELD_VER_CEA861D            (2 << 3) /* supports 861D or below */
231 # define DRM_ELD_VER_CANNED             (0x1f << 3)
232 
233 #define DRM_ELD_BASELINE_ELD_LEN        2       /* in dwords! */
234 
235 /* ELD Baseline Block for ELD_Ver == 2 */
236 #define DRM_ELD_CEA_EDID_VER_MNL        4
237 # define DRM_ELD_CEA_EDID_VER_SHIFT     5
238 # define DRM_ELD_CEA_EDID_VER_MASK      (7 << 5)
239 # define DRM_ELD_CEA_EDID_VER_NONE      (0 << 5)
240 # define DRM_ELD_CEA_EDID_VER_CEA861    (1 << 5)
241 # define DRM_ELD_CEA_EDID_VER_CEA861A   (2 << 5)
242 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
243 # define DRM_ELD_MNL_SHIFT              0
244 # define DRM_ELD_MNL_MASK               (0x1f << 0)
245 
246 #define DRM_ELD_SAD_COUNT_CONN_TYPE     5
247 # define DRM_ELD_SAD_COUNT_SHIFT        4
248 # define DRM_ELD_SAD_COUNT_MASK         (0xf << 4)
249 # define DRM_ELD_CONN_TYPE_SHIFT        2
250 # define DRM_ELD_CONN_TYPE_MASK         (3 << 2)
251 # define DRM_ELD_CONN_TYPE_HDMI         (0 << 2)
252 # define DRM_ELD_CONN_TYPE_DP           (1 << 2)
253 # define DRM_ELD_SUPPORTS_AI            (1 << 1)
254 # define DRM_ELD_SUPPORTS_HDCP          (1 << 0)
255 
256 #define DRM_ELD_AUD_SYNCH_DELAY         6       /* in units of 2 ms */
257 # define DRM_ELD_AUD_SYNCH_DELAY_MAX    0xfa    /* 500 ms */
258 
259 #define DRM_ELD_SPEAKER                 7
260 # define DRM_ELD_SPEAKER_MASK           0x7f
261 # define DRM_ELD_SPEAKER_RLRC           (1 << 6)
262 # define DRM_ELD_SPEAKER_FLRC           (1 << 5)
263 # define DRM_ELD_SPEAKER_RC             (1 << 4)
264 # define DRM_ELD_SPEAKER_RLR            (1 << 3)
265 # define DRM_ELD_SPEAKER_FC             (1 << 2)
266 # define DRM_ELD_SPEAKER_LFE            (1 << 1)
267 # define DRM_ELD_SPEAKER_FLR            (1 << 0)
268 
269 #define DRM_ELD_PORT_ID                 8       /* offsets 8..15 inclusive */
270 # define DRM_ELD_PORT_ID_LEN            8
271 
272 #define DRM_ELD_MANUFACTURER_NAME0      16
273 #define DRM_ELD_MANUFACTURER_NAME1      17
274 
275 #define DRM_ELD_PRODUCT_CODE0           18
276 #define DRM_ELD_PRODUCT_CODE1           19
277 
278 #define DRM_ELD_MONITOR_NAME_STRING     20      /* offsets 20..(20+mnl-1) inclusive */
279 
280 #define DRM_ELD_CEA_SAD(mnl, sad)       (20 + (mnl) + 3 * (sad))
281 
282 struct edid {
283         u8 header[8];
284         /* Vendor & product info */
285         u8 mfg_id[2];
286         u8 prod_code[2];
287         u32 serial; /* FIXME: byte order */
288         u8 mfg_week;
289         u8 mfg_year;
290         /* EDID version */
291         u8 version;
292         u8 revision;
293         /* Display info: */
294         u8 input;
295         u8 width_cm;
296         u8 height_cm;
297         u8 gamma;
298         u8 features;
299         /* Color characteristics */
300         u8 red_green_lo;
301         u8 black_white_lo;
302         u8 red_x;
303         u8 red_y;
304         u8 green_x;
305         u8 green_y;
306         u8 blue_x;
307         u8 blue_y;
308         u8 white_x;
309         u8 white_y;
310         /* Est. timings and mfg rsvd timings*/
311         struct est_timings established_timings;
312         /* Standard timings 1-8*/
313         struct std_timing standard_timings[8];
314         /* Detailing timings 1-4 */
315         struct detailed_timing detailed_timings[4];
316         /* Number of 128 byte ext. blocks */
317         u8 extensions;
318         /* Checksum */
319         u8 checksum;
320 } __attribute__((packed));
321 
322 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
323 
324 /* Short Audio Descriptor */
325 struct cea_sad {
326         u8 format;
327         u8 channels; /* max number of channels - 1 */
328         u8 freq;
329         u8 byte2; /* meaning depends on format */
330 };
331 
332 struct drm_encoder;
333 struct drm_connector;
334 struct drm_display_mode;
335 
336 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
337 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
338 int drm_av_sync_delay(struct drm_connector *connector,
339                       const struct drm_display_mode *mode);
340 
341 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
342 struct edid *drm_load_edid_firmware(struct drm_connector *connector);
343 int __drm_set_edid_firmware_path(const char *path);
344 int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
345 #else
346 static inline struct edid *
347 drm_load_edid_firmware(struct drm_connector *connector)
348 {
349         return ERR_PTR(-ENOENT);
350 }
351 #endif
352 
353 int
354 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
355                                          const struct drm_display_mode *mode,
356                                          bool is_hdmi2_sink);
357 int
358 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
359                                             struct drm_connector *connector,
360                                             const struct drm_display_mode *mode);
361 void
362 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
363                                    const struct drm_display_mode *mode,
364                                    enum hdmi_quantization_range rgb_quant_range,
365                                    bool rgb_quant_range_selectable,
366                                    bool is_hdmi2_sink);
367 
368 /**
369  * drm_eld_mnl - Get ELD monitor name length in bytes.
370  * @eld: pointer to an eld memory structure with mnl set
371  */
372 static inline int drm_eld_mnl(const uint8_t *eld)
373 {
374         return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
375 }
376 
377 /**
378  * drm_eld_sad - Get ELD SAD structures.
379  * @eld: pointer to an eld memory structure with sad_count set
380  */
381 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
382 {
383         unsigned int ver, mnl;
384 
385         ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
386         if (ver != 2 && ver != 31)
387                 return NULL;
388 
389         mnl = drm_eld_mnl(eld);
390         if (mnl > 16)
391                 return NULL;
392 
393         return eld + DRM_ELD_CEA_SAD(mnl, 0);
394 }
395 
396 /**
397  * drm_eld_sad_count - Get ELD SAD count.
398  * @eld: pointer to an eld memory structure with sad_count set
399  */
400 static inline int drm_eld_sad_count(const uint8_t *eld)
401 {
402         return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
403                 DRM_ELD_SAD_COUNT_SHIFT;
404 }
405 
406 /**
407  * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
408  * @eld: pointer to an eld memory structure with mnl and sad_count set
409  *
410  * This is a helper for determining the payload size of the baseline block, in
411  * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
412  */
413 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
414 {
415         return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
416                 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
417 }
418 
419 /**
420  * drm_eld_size - Get ELD size in bytes
421  * @eld: pointer to a complete eld memory structure
422  *
423  * The returned value does not include the vendor block. It's vendor specific,
424  * and comprises of the remaining bytes in the ELD memory buffer after
425  * drm_eld_size() bytes of header and baseline block.
426  *
427  * The returned value is guaranteed to be a multiple of 4.
428  */
429 static inline int drm_eld_size(const uint8_t *eld)
430 {
431         return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
432 }
433 
434 /**
435  * drm_eld_get_spk_alloc - Get speaker allocation
436  * @eld: pointer to an ELD memory structure
437  *
438  * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
439  * field definitions to identify speakers.
440  */
441 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
442 {
443         return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
444 }
445 
446 /**
447  * drm_eld_get_conn_type - Get device type hdmi/dp connected
448  * @eld: pointer to an ELD memory structure
449  *
450  * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
451  * identify the display type connected.
452  */
453 static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
454 {
455         return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
456 }
457 
458 bool drm_probe_ddc(struct i2c_adapter *adapter);
459 struct edid *drm_do_get_edid(struct drm_connector *connector,
460         int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
461                               size_t len),
462         void *data);
463 struct edid *drm_get_edid(struct drm_connector *connector,
464                           struct i2c_adapter *adapter);
465 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
466                                      struct i2c_adapter *adapter);
467 struct edid *drm_edid_duplicate(const struct edid *edid);
468 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
469 
470 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
471 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
472 bool drm_detect_hdmi_monitor(struct edid *edid);
473 bool drm_detect_monitor_audio(struct edid *edid);
474 bool drm_rgb_quant_range_selectable(struct edid *edid);
475 enum hdmi_quantization_range
476 drm_default_rgb_quant_range(const struct drm_display_mode *mode);
477 int drm_add_modes_noedid(struct drm_connector *connector,
478                          int hdisplay, int vdisplay);
479 void drm_set_preferred_mode(struct drm_connector *connector,
480                             int hpref, int vpref);
481 
482 int drm_edid_header_is_valid(const u8 *raw_edid);
483 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
484                           bool *edid_corrupt);
485 bool drm_edid_is_valid(struct edid *edid);
486 void drm_edid_get_monitor_name(struct edid *edid, char *name,
487                                int buflen);
488 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
489                                            int hsize, int vsize, int fresh,
490                                            bool rb);
491 #endif /* __DRM_EDID_H__ */
492 

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