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TOMOYO Linux Cross Reference
Linux/include/drm/i915_pciids.h

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  1 /*
  2  * Copyright 2013 Intel Corporation
  3  * All Rights Reserved.
  4  *
  5  * Permission is hereby granted, free of charge, to any person obtaining a
  6  * copy of this software and associated documentation files (the
  7  * "Software"), to deal in the Software without restriction, including
  8  * without limitation the rights to use, copy, modify, merge, publish,
  9  * distribute, sub license, and/or sell copies of the Software, and to
 10  * permit persons to whom the Software is furnished to do so, subject to
 11  * the following conditions:
 12  *
 13  * The above copyright notice and this permission notice (including the
 14  * next paragraph) shall be included in all copies or substantial portions
 15  * of the Software.
 16  *
 17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 23  * DEALINGS IN THE SOFTWARE.
 24  */
 25 #ifndef _I915_PCIIDS_H
 26 #define _I915_PCIIDS_H
 27 
 28 /*
 29  * A pci_device_id struct {
 30  *      __u32 vendor, device;
 31  *      __u32 subvendor, subdevice;
 32  *      __u32 class, class_mask;
 33  *      kernel_ulong_t driver_data;
 34  * };
 35  * Don't use C99 here because "class" is reserved and we want to
 36  * give userspace flexibility.
 37  */
 38 #define INTEL_VGA_DEVICE(id, info) {            \
 39         0x8086, id,                             \
 40         ~0, ~0,                                 \
 41         0x030000, 0xff0000,                     \
 42         (unsigned long) info }
 43 
 44 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
 45         0x8086, 0x16a,                          \
 46         0x152d, 0x8990,                         \
 47         0x030000, 0xff0000,                     \
 48         (unsigned long) info }
 49 
 50 #define INTEL_I810_IDS(info)                                    \
 51         INTEL_VGA_DEVICE(0x7121, info), /* I810 */              \
 52         INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */        \
 53         INTEL_VGA_DEVICE(0x7125, info)  /* I810_E */
 54 
 55 #define INTEL_I815_IDS(info)                                    \
 56         INTEL_VGA_DEVICE(0x1132, info)  /* I815*/
 57 
 58 #define INTEL_I830_IDS(info)                            \
 59         INTEL_VGA_DEVICE(0x3577, info)
 60 
 61 #define INTEL_I845G_IDS(info)                           \
 62         INTEL_VGA_DEVICE(0x2562, info)
 63 
 64 #define INTEL_I85X_IDS(info)                            \
 65         INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
 66         INTEL_VGA_DEVICE(0x358e, info)
 67 
 68 #define INTEL_I865G_IDS(info)                           \
 69         INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
 70 
 71 #define INTEL_I915G_IDS(info)                           \
 72         INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
 73         INTEL_VGA_DEVICE(0x258a, info)  /* E7221_G */
 74 
 75 #define INTEL_I915GM_IDS(info)                          \
 76         INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
 77 
 78 #define INTEL_I945G_IDS(info)                           \
 79         INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
 80 
 81 #define INTEL_I945GM_IDS(info)                          \
 82         INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
 83         INTEL_VGA_DEVICE(0x27ae, info)  /* I945_GME */
 84 
 85 #define INTEL_I965G_IDS(info)                           \
 86         INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */   \
 87         INTEL_VGA_DEVICE(0x2982, info), /* G35_G */     \
 88         INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */    \
 89         INTEL_VGA_DEVICE(0x29a2, info)  /* I965_G */
 90 
 91 #define INTEL_G33_IDS(info)                             \
 92         INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
 93         INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
 94         INTEL_VGA_DEVICE(0x29d2, info)  /* Q33_G */
 95 
 96 #define INTEL_I965GM_IDS(info)                          \
 97         INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
 98         INTEL_VGA_DEVICE(0x2a12, info)  /* I965_GME */
 99 
100 #define INTEL_GM45_IDS(info)                            \
101         INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
102 
103 #define INTEL_G45_IDS(info)                             \
104         INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
105         INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
106         INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
107         INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
108         INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
109         INTEL_VGA_DEVICE(0x2e92, info)  /* B43_G.1 */
110 
111 #define INTEL_PINEVIEW_G_IDS(info) \
112         INTEL_VGA_DEVICE(0xa001, info)
113 
114 #define INTEL_PINEVIEW_M_IDS(info) \
115         INTEL_VGA_DEVICE(0xa011, info)
116 
117 #define INTEL_IRONLAKE_D_IDS(info) \
118         INTEL_VGA_DEVICE(0x0042, info)
119 
120 #define INTEL_IRONLAKE_M_IDS(info) \
121         INTEL_VGA_DEVICE(0x0046, info)
122 
123 #define INTEL_SNB_D_GT1_IDS(info) \
124         INTEL_VGA_DEVICE(0x0102, info), \
125         INTEL_VGA_DEVICE(0x010A, info)
126 
127 #define INTEL_SNB_D_GT2_IDS(info) \
128         INTEL_VGA_DEVICE(0x0112, info), \
129         INTEL_VGA_DEVICE(0x0122, info)
130 
131 #define INTEL_SNB_D_IDS(info) \
132         INTEL_SNB_D_GT1_IDS(info), \
133         INTEL_SNB_D_GT2_IDS(info)
134 
135 #define INTEL_SNB_M_GT1_IDS(info) \
136         INTEL_VGA_DEVICE(0x0106, info)
137 
138 #define INTEL_SNB_M_GT2_IDS(info) \
139         INTEL_VGA_DEVICE(0x0116, info), \
140         INTEL_VGA_DEVICE(0x0126, info)
141 
142 #define INTEL_SNB_M_IDS(info) \
143         INTEL_SNB_M_GT1_IDS(info), \
144         INTEL_SNB_M_GT2_IDS(info)
145 
146 #define INTEL_IVB_M_GT1_IDS(info) \
147         INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
148 
149 #define INTEL_IVB_M_GT2_IDS(info) \
150         INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
151 
152 #define INTEL_IVB_M_IDS(info) \
153         INTEL_IVB_M_GT1_IDS(info), \
154         INTEL_IVB_M_GT2_IDS(info)
155 
156 #define INTEL_IVB_D_GT1_IDS(info) \
157         INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
158         INTEL_VGA_DEVICE(0x015a, info)  /* GT1 server */
159 
160 #define INTEL_IVB_D_GT2_IDS(info) \
161         INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
162         INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
163 
164 #define INTEL_IVB_D_IDS(info) \
165         INTEL_IVB_D_GT1_IDS(info), \
166         INTEL_IVB_D_GT2_IDS(info)
167 
168 #define INTEL_IVB_Q_IDS(info) \
169         INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
170 
171 #define INTEL_HSW_ULT_GT1_IDS(info) \
172         INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
173         INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
174         INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
175         INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
176 
177 #define INTEL_HSW_ULX_GT1_IDS(info) \
178         INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
179 
180 #define INTEL_HSW_GT1_IDS(info) \
181         INTEL_HSW_ULT_GT1_IDS(info), \
182         INTEL_HSW_ULX_GT1_IDS(info), \
183         INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
184         INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
185         INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
186         INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
187         INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
188         INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
189         INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
190         INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
191         INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
192         INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
193         INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
194         INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
195         INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
196         INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
197         INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
198 
199 #define INTEL_HSW_ULT_GT2_IDS(info) \
200         INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
201         INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
202         INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
203         INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
204 
205 #define INTEL_HSW_ULX_GT2_IDS(info) \
206         INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
207 
208 #define INTEL_HSW_GT2_IDS(info) \
209         INTEL_HSW_ULT_GT2_IDS(info), \
210         INTEL_HSW_ULX_GT2_IDS(info), \
211         INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
212         INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
213         INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
214         INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
215         INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
216         INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
217         INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
218         INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
219         INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
220         INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
221         INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
222         INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
223         INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
224         INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
225         INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
226         INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
227 
228 #define INTEL_HSW_ULT_GT3_IDS(info) \
229         INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
230         INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
231         INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
232         INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
233         INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */
234 
235 #define INTEL_HSW_GT3_IDS(info) \
236         INTEL_HSW_ULT_GT3_IDS(info), \
237         INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
238         INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
239         INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
240         INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
241         INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
242         INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
243         INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
244         INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
245         INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
246         INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
247         INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
248         INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
249         INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
250         INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
251 
252 #define INTEL_HSW_IDS(info) \
253         INTEL_HSW_GT1_IDS(info), \
254         INTEL_HSW_GT2_IDS(info), \
255         INTEL_HSW_GT3_IDS(info)
256 
257 #define INTEL_VLV_IDS(info) \
258         INTEL_VGA_DEVICE(0x0f30, info), \
259         INTEL_VGA_DEVICE(0x0f31, info), \
260         INTEL_VGA_DEVICE(0x0f32, info), \
261         INTEL_VGA_DEVICE(0x0f33, info), \
262         INTEL_VGA_DEVICE(0x0157, info), \
263         INTEL_VGA_DEVICE(0x0155, info)
264 
265 #define INTEL_BDW_ULT_GT1_IDS(info) \
266         INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
267         INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */
268 
269 #define INTEL_BDW_ULX_GT1_IDS(info) \
270         INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
271 
272 #define INTEL_BDW_GT1_IDS(info) \
273         INTEL_BDW_ULT_GT1_IDS(info), \
274         INTEL_BDW_ULX_GT1_IDS(info), \
275         INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
276         INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
277         INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
278 
279 #define INTEL_BDW_ULT_GT2_IDS(info) \
280         INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
281         INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */
282 
283 #define INTEL_BDW_ULX_GT2_IDS(info) \
284         INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
285 
286 #define INTEL_BDW_GT2_IDS(info) \
287         INTEL_BDW_ULT_GT2_IDS(info), \
288         INTEL_BDW_ULX_GT2_IDS(info), \
289         INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */  \
290         INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
291         INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
292 
293 #define INTEL_BDW_ULT_GT3_IDS(info) \
294         INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
295         INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
296 
297 #define INTEL_BDW_ULX_GT3_IDS(info) \
298         INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
299 
300 #define INTEL_BDW_GT3_IDS(info) \
301         INTEL_BDW_ULT_GT3_IDS(info), \
302         INTEL_BDW_ULX_GT3_IDS(info), \
303         INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
304         INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
305         INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
306 
307 #define INTEL_BDW_ULT_RSVD_IDS(info) \
308         INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
309         INTEL_VGA_DEVICE(0x163B, info)  /* Iris */
310 
311 #define INTEL_BDW_ULX_RSVD_IDS(info) \
312         INTEL_VGA_DEVICE(0x163E, info) /* ULX */
313 
314 #define INTEL_BDW_RSVD_IDS(info) \
315         INTEL_BDW_ULT_RSVD_IDS(info), \
316         INTEL_BDW_ULX_RSVD_IDS(info), \
317         INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
318         INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
319         INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
320 
321 #define INTEL_BDW_IDS(info) \
322         INTEL_BDW_GT1_IDS(info), \
323         INTEL_BDW_GT2_IDS(info), \
324         INTEL_BDW_GT3_IDS(info), \
325         INTEL_BDW_RSVD_IDS(info)
326 
327 #define INTEL_CHV_IDS(info) \
328         INTEL_VGA_DEVICE(0x22b0, info), \
329         INTEL_VGA_DEVICE(0x22b1, info), \
330         INTEL_VGA_DEVICE(0x22b2, info), \
331         INTEL_VGA_DEVICE(0x22b3, info)
332 
333 #define INTEL_SKL_ULT_GT1_IDS(info) \
334         INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
335 
336 #define INTEL_SKL_ULX_GT1_IDS(info) \
337         INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
338 
339 #define INTEL_SKL_GT1_IDS(info) \
340         INTEL_SKL_ULT_GT1_IDS(info), \
341         INTEL_SKL_ULX_GT1_IDS(info), \
342         INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
343         INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
344         INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
345 
346 #define INTEL_SKL_ULT_GT2_IDS(info) \
347         INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
348         INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */
349 
350 #define INTEL_SKL_ULX_GT2_IDS(info) \
351         INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
352 
353 #define INTEL_SKL_GT2_IDS(info) \
354         INTEL_SKL_ULT_GT2_IDS(info), \
355         INTEL_SKL_ULX_GT2_IDS(info), \
356         INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
357         INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
358         INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
359         INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
360 
361 #define INTEL_SKL_ULT_GT3_IDS(info) \
362         INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
363 
364 #define INTEL_SKL_GT3_IDS(info) \
365         INTEL_SKL_ULT_GT3_IDS(info), \
366         INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
367         INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
368         INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
369         INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
370 
371 #define INTEL_SKL_GT4_IDS(info) \
372         INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
373         INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
374         INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
375         INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
376         INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
377 
378 #define INTEL_SKL_IDS(info)      \
379         INTEL_SKL_GT1_IDS(info), \
380         INTEL_SKL_GT2_IDS(info), \
381         INTEL_SKL_GT3_IDS(info), \
382         INTEL_SKL_GT4_IDS(info)
383 
384 #define INTEL_BXT_IDS(info) \
385         INTEL_VGA_DEVICE(0x0A84, info), \
386         INTEL_VGA_DEVICE(0x1A84, info), \
387         INTEL_VGA_DEVICE(0x1A85, info), \
388         INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
389         INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
390 
391 #define INTEL_GLK_IDS(info) \
392         INTEL_VGA_DEVICE(0x3184, info), \
393         INTEL_VGA_DEVICE(0x3185, info)
394 
395 #define INTEL_KBL_ULT_GT1_IDS(info) \
396         INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
397         INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */
398 
399 #define INTEL_KBL_ULX_GT1_IDS(info) \
400         INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
401         INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */
402 
403 #define INTEL_KBL_GT1_IDS(info) \
404         INTEL_KBL_ULT_GT1_IDS(info), \
405         INTEL_KBL_ULX_GT1_IDS(info), \
406         INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
407         INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
408         INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
409         INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
410 
411 #define INTEL_KBL_ULT_GT2_IDS(info) \
412         INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
413         INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */
414 
415 #define INTEL_KBL_ULX_GT2_IDS(info) \
416         INTEL_VGA_DEVICE(0x591E, info)  /* ULX GT2 */
417 
418 #define INTEL_KBL_GT2_IDS(info) \
419         INTEL_KBL_ULT_GT2_IDS(info), \
420         INTEL_KBL_ULX_GT2_IDS(info), \
421         INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
422         INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
423         INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
424         INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
425         INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
426 
427 #define INTEL_KBL_ULT_GT3_IDS(info) \
428         INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
429 
430 #define INTEL_KBL_GT3_IDS(info) \
431         INTEL_KBL_ULT_GT3_IDS(info), \
432         INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
433         INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
434 
435 #define INTEL_KBL_GT4_IDS(info) \
436         INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
437 
438 /* AML/KBL Y GT2 */
439 #define INTEL_AML_KBL_GT2_IDS(info) \
440         INTEL_VGA_DEVICE(0x591C, info),  /* ULX GT2 */ \
441         INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
442 
443 /* AML/CFL Y GT2 */
444 #define INTEL_AML_CFL_GT2_IDS(info) \
445         INTEL_VGA_DEVICE(0x87CA, info)
446 
447 /* CML GT1 */
448 #define INTEL_CML_GT1_IDS(info) \
449         INTEL_VGA_DEVICE(0x9BA5, info), \
450         INTEL_VGA_DEVICE(0x9BA8, info), \
451         INTEL_VGA_DEVICE(0x9BA4, info), \
452         INTEL_VGA_DEVICE(0x9BA2, info)
453 
454 #define INTEL_CML_U_GT1_IDS(info) \
455         INTEL_VGA_DEVICE(0x9B21, info), \
456         INTEL_VGA_DEVICE(0x9BAA, info), \
457         INTEL_VGA_DEVICE(0x9BAC, info)
458 
459 /* CML GT2 */
460 #define INTEL_CML_GT2_IDS(info) \
461         INTEL_VGA_DEVICE(0x9BC5, info), \
462         INTEL_VGA_DEVICE(0x9BC8, info), \
463         INTEL_VGA_DEVICE(0x9BC4, info), \
464         INTEL_VGA_DEVICE(0x9BC2, info), \
465         INTEL_VGA_DEVICE(0x9BC6, info), \
466         INTEL_VGA_DEVICE(0x9BE6, info), \
467         INTEL_VGA_DEVICE(0x9BF6, info)
468 
469 #define INTEL_CML_U_GT2_IDS(info) \
470         INTEL_VGA_DEVICE(0x9B41, info), \
471         INTEL_VGA_DEVICE(0x9BCA, info), \
472         INTEL_VGA_DEVICE(0x9BCC, info)
473 
474 #define INTEL_KBL_IDS(info) \
475         INTEL_KBL_GT1_IDS(info), \
476         INTEL_KBL_GT2_IDS(info), \
477         INTEL_KBL_GT3_IDS(info), \
478         INTEL_KBL_GT4_IDS(info), \
479         INTEL_AML_KBL_GT2_IDS(info)
480 
481 /* CFL S */
482 #define INTEL_CFL_S_GT1_IDS(info) \
483         INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
484         INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
485         INTEL_VGA_DEVICE(0x3E99, info)  /* SRV GT1 */
486 
487 #define INTEL_CFL_S_GT2_IDS(info) \
488         INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
489         INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
490         INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
491         INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
492         INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */
493 
494 /* CFL H */
495 #define INTEL_CFL_H_GT1_IDS(info) \
496         INTEL_VGA_DEVICE(0x3E9C, info)
497 
498 #define INTEL_CFL_H_GT2_IDS(info) \
499         INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
500         INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
501 
502 /* CFL U GT2 */
503 #define INTEL_CFL_U_GT2_IDS(info) \
504         INTEL_VGA_DEVICE(0x3EA9, info)
505 
506 /* CFL U GT3 */
507 #define INTEL_CFL_U_GT3_IDS(info) \
508         INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
509         INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
510         INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
511         INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */
512 
513 /* WHL/CFL U GT1 */
514 #define INTEL_WHL_U_GT1_IDS(info) \
515         INTEL_VGA_DEVICE(0x3EA1, info), \
516         INTEL_VGA_DEVICE(0x3EA4, info)
517 
518 /* WHL/CFL U GT2 */
519 #define INTEL_WHL_U_GT2_IDS(info) \
520         INTEL_VGA_DEVICE(0x3EA0, info), \
521         INTEL_VGA_DEVICE(0x3EA3, info)
522 
523 /* WHL/CFL U GT3 */
524 #define INTEL_WHL_U_GT3_IDS(info) \
525         INTEL_VGA_DEVICE(0x3EA2, info)
526 
527 #define INTEL_CFL_IDS(info)        \
528         INTEL_CFL_S_GT1_IDS(info), \
529         INTEL_CFL_S_GT2_IDS(info), \
530         INTEL_CFL_H_GT1_IDS(info), \
531         INTEL_CFL_H_GT2_IDS(info), \
532         INTEL_CFL_U_GT2_IDS(info), \
533         INTEL_CFL_U_GT3_IDS(info), \
534         INTEL_WHL_U_GT1_IDS(info), \
535         INTEL_WHL_U_GT2_IDS(info), \
536         INTEL_WHL_U_GT3_IDS(info), \
537         INTEL_AML_CFL_GT2_IDS(info), \
538         INTEL_CML_GT1_IDS(info), \
539         INTEL_CML_GT2_IDS(info), \
540         INTEL_CML_U_GT1_IDS(info), \
541         INTEL_CML_U_GT2_IDS(info)
542 
543 /* CNL */
544 #define INTEL_CNL_PORT_F_IDS(info) \
545         INTEL_VGA_DEVICE(0x5A54, info), \
546         INTEL_VGA_DEVICE(0x5A5C, info), \
547         INTEL_VGA_DEVICE(0x5A44, info), \
548         INTEL_VGA_DEVICE(0x5A4C, info)
549 
550 #define INTEL_CNL_IDS(info) \
551         INTEL_CNL_PORT_F_IDS(info), \
552         INTEL_VGA_DEVICE(0x5A51, info), \
553         INTEL_VGA_DEVICE(0x5A59, info), \
554         INTEL_VGA_DEVICE(0x5A41, info), \
555         INTEL_VGA_DEVICE(0x5A49, info), \
556         INTEL_VGA_DEVICE(0x5A52, info), \
557         INTEL_VGA_DEVICE(0x5A5A, info), \
558         INTEL_VGA_DEVICE(0x5A42, info), \
559         INTEL_VGA_DEVICE(0x5A4A, info), \
560         INTEL_VGA_DEVICE(0x5A50, info), \
561         INTEL_VGA_DEVICE(0x5A40, info)
562 
563 /* ICL */
564 #define INTEL_ICL_PORT_F_IDS(info) \
565         INTEL_VGA_DEVICE(0x8A50, info), \
566         INTEL_VGA_DEVICE(0x8A5C, info), \
567         INTEL_VGA_DEVICE(0x8A59, info), \
568         INTEL_VGA_DEVICE(0x8A58, info), \
569         INTEL_VGA_DEVICE(0x8A52, info), \
570         INTEL_VGA_DEVICE(0x8A5A, info), \
571         INTEL_VGA_DEVICE(0x8A5B, info), \
572         INTEL_VGA_DEVICE(0x8A57, info), \
573         INTEL_VGA_DEVICE(0x8A56, info), \
574         INTEL_VGA_DEVICE(0x8A71, info), \
575         INTEL_VGA_DEVICE(0x8A70, info), \
576         INTEL_VGA_DEVICE(0x8A53, info), \
577         INTEL_VGA_DEVICE(0x8A54, info)
578 
579 #define INTEL_ICL_11_IDS(info) \
580         INTEL_ICL_PORT_F_IDS(info), \
581         INTEL_VGA_DEVICE(0x8A51, info), \
582         INTEL_VGA_DEVICE(0x8A5D, info)
583 
584 /* EHL/JSL */
585 #define INTEL_EHL_IDS(info) \
586         INTEL_VGA_DEVICE(0x4500, info), \
587         INTEL_VGA_DEVICE(0x4571, info), \
588         INTEL_VGA_DEVICE(0x4551, info), \
589         INTEL_VGA_DEVICE(0x4541, info), \
590         INTEL_VGA_DEVICE(0x4E71, info), \
591         INTEL_VGA_DEVICE(0x4557, info), \
592         INTEL_VGA_DEVICE(0x4555, info), \
593         INTEL_VGA_DEVICE(0x4E61, info), \
594         INTEL_VGA_DEVICE(0x4E57, info), \
595         INTEL_VGA_DEVICE(0x4E55, info), \
596         INTEL_VGA_DEVICE(0x4E51, info)
597 
598 /* TGL */
599 #define INTEL_TGL_12_IDS(info) \
600         INTEL_VGA_DEVICE(0x9A40, info), \
601         INTEL_VGA_DEVICE(0x9A49, info), \
602         INTEL_VGA_DEVICE(0x9A59, info), \
603         INTEL_VGA_DEVICE(0x9A60, info), \
604         INTEL_VGA_DEVICE(0x9A68, info), \
605         INTEL_VGA_DEVICE(0x9A70, info), \
606         INTEL_VGA_DEVICE(0x9A78, info), \
607         INTEL_VGA_DEVICE(0x9AC0, info), \
608         INTEL_VGA_DEVICE(0x9AC9, info), \
609         INTEL_VGA_DEVICE(0x9AD9, info), \
610         INTEL_VGA_DEVICE(0x9AF8, info)
611 
612 /* RKL */
613 #define INTEL_RKL_IDS(info) \
614         INTEL_VGA_DEVICE(0x4C80, info), \
615         INTEL_VGA_DEVICE(0x4C8A, info), \
616         INTEL_VGA_DEVICE(0x4C8B, info), \
617         INTEL_VGA_DEVICE(0x4C8C, info), \
618         INTEL_VGA_DEVICE(0x4C90, info), \
619         INTEL_VGA_DEVICE(0x4C9A, info)
620 
621 /* DG1 */
622 #define INTEL_DG1_IDS(info) \
623         INTEL_VGA_DEVICE(0x4905, info)
624 
625 #endif /* _I915_PCIIDS_H */
626 

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