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TOMOYO Linux Cross Reference
Linux/include/linux/alcor_pci.h

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  1 /* SPDX-License-Identifier: GPL-2.0+ */
  2 /*
  3  * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
  4  *
  5  * Driver for Alcor Micro AU6601 and AU6621 controllers
  6  */
  7 
  8 #ifndef __ALCOR_PCI_H
  9 #define __ALCOR_PCI_H
 10 
 11 #define ALCOR_SD_CARD 0
 12 #define ALCOR_MS_CARD 1
 13 
 14 #define DRV_NAME_ALCOR_PCI_SDMMC                "alcor_sdmmc"
 15 #define DRV_NAME_ALCOR_PCI_MS                   "alcor_ms"
 16 
 17 #define PCI_ID_ALCOR_MICRO                      0x1AEA
 18 #define PCI_ID_AU6601                           0x6601
 19 #define PCI_ID_AU6621                           0x6621
 20 
 21 #define MHZ_TO_HZ(freq)                         ((freq) * 1000 * 1000)
 22 
 23 #define AU6601_BASE_CLOCK                       31000000
 24 #define AU6601_MIN_CLOCK                        150000
 25 #define AU6601_MAX_CLOCK                        208000000
 26 #define AU6601_MAX_DMA_SEGMENTS                 64
 27 #define AU6601_MAX_PIO_SEGMENTS                 1
 28 #define AU6601_MAX_DMA_BLOCK_SIZE               0x1000
 29 #define AU6601_MAX_PIO_BLOCK_SIZE               0x200
 30 #define AU6601_MAX_DMA_BLOCKS                   1
 31 #define AU6601_DMA_LOCAL_SEGMENTS               1
 32 
 33 /* registers spotter by reverse engineering but still
 34  * with unknown functionality:
 35  * 0x10 - ADMA phy address. AU6621 only?
 36  * 0x51 - LED ctrl?
 37  * 0x52 - unknown
 38  * 0x61 - LED related? Always toggled BIT0
 39  * 0x63 - Same as 0x61?
 40  * 0x77 - unknown
 41  */
 42 
 43 /* SDMA phy address. Higher then 0x0800.0000?
 44  * The au6601 and au6621 have different DMA engines with different issues. One
 45  * For example au6621 engine is triggered by addr change. No other interaction
 46  * is needed. This means, if we get two buffers with same address, then engine
 47  * will stall.
 48  */
 49 #define AU6601_REG_SDMA_ADDR                    0x00
 50 #define AU6601_SDMA_MASK                        0xffffffff
 51 
 52 #define AU6601_DMA_BOUNDARY                     0x05
 53 #define AU6621_DMA_PAGE_CNT                     0x05
 54 /* PIO */
 55 #define AU6601_REG_BUFFER                       0x08
 56 /* ADMA ctrl? AU6621 only. */
 57 #define AU6621_DMA_CTRL                         0x0c
 58 #define AU6621_DMA_ENABLE                       BIT(0)
 59 /* CMD index */
 60 #define AU6601_REG_CMD_OPCODE                   0x23
 61 /* CMD parametr */
 62 #define AU6601_REG_CMD_ARG                      0x24
 63 /* CMD response 4x4 Bytes */
 64 #define AU6601_REG_CMD_RSP0                     0x30
 65 #define AU6601_REG_CMD_RSP1                     0x34
 66 #define AU6601_REG_CMD_RSP2                     0x38
 67 #define AU6601_REG_CMD_RSP3                     0x3C
 68 /* default timeout set to 125: 125 * 40ms = 5 sec
 69  * how exactly it is calculated?
 70  */
 71 #define AU6601_TIME_OUT_CTRL                    0x69
 72 /* Block size for SDMA or PIO */
 73 #define AU6601_REG_BLOCK_SIZE                   0x6c
 74 /* Some power related reg, used together with AU6601_OUTPUT_ENABLE */
 75 #define AU6601_POWER_CONTROL                    0x70
 76 
 77 /* PLL ctrl */
 78 #define AU6601_CLK_SELECT                       0x72
 79 #define AU6601_CLK_OVER_CLK                     0x80
 80 #define AU6601_CLK_384_MHZ                      0x30
 81 #define AU6601_CLK_125_MHZ                      0x20
 82 #define AU6601_CLK_48_MHZ                       0x10
 83 #define AU6601_CLK_EXT_PLL                      0x04
 84 #define AU6601_CLK_X2_MODE                      0x02
 85 #define AU6601_CLK_ENABLE                       0x01
 86 #define AU6601_CLK_31_25_MHZ                    0x00
 87 
 88 #define AU6601_CLK_DIVIDER                      0x73
 89 
 90 #define AU6601_INTERFACE_MODE_CTRL              0x74
 91 #define AU6601_DLINK_MODE                       0x80
 92 #define AU6601_INTERRUPT_DELAY_TIME             0x40
 93 #define AU6601_SIGNAL_REQ_CTRL                  0x30
 94 #define AU6601_MS_CARD_WP                       BIT(3)
 95 #define AU6601_SD_CARD_WP                       BIT(0)
 96 
 97 /* same register values are used for:
 98  *  - AU6601_OUTPUT_ENABLE
 99  *  - AU6601_POWER_CONTROL
100  */
101 #define AU6601_ACTIVE_CTRL                      0x75
102 #define AU6601_XD_CARD                          BIT(4)
103 /* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */
104 #define AU6601_MS_CARD                          BIT(3)
105 #define AU6601_SD_CARD                          BIT(0)
106 
107 /* card slot state. It should automatically detect type of
108  * the card
109  */
110 #define AU6601_DETECT_STATUS                    0x76
111 #define AU6601_DETECT_EN                        BIT(7)
112 #define AU6601_MS_DETECTED                      BIT(3)
113 #define AU6601_SD_DETECTED                      BIT(0)
114 #define AU6601_DETECT_STATUS_M                  0xf
115 
116 #define AU6601_REG_SW_RESET                     0x79
117 #define AU6601_BUF_CTRL_RESET                   BIT(7)
118 #define AU6601_RESET_DATA                       BIT(3)
119 #define AU6601_RESET_CMD                        BIT(0)
120 
121 #define AU6601_OUTPUT_ENABLE                    0x7a
122 
123 #define AU6601_PAD_DRIVE0                       0x7b
124 #define AU6601_PAD_DRIVE1                       0x7c
125 #define AU6601_PAD_DRIVE2                       0x7d
126 /* read EEPROM? */
127 #define AU6601_FUNCTION                         0x7f
128 
129 #define AU6601_CMD_XFER_CTRL                    0x81
130 #define AU6601_CMD_17_BYTE_CRC                  0xc0
131 #define AU6601_CMD_6_BYTE_WO_CRC                0x80
132 #define AU6601_CMD_6_BYTE_CRC                   0x40
133 #define AU6601_CMD_START_XFER                   0x20
134 #define AU6601_CMD_STOP_WAIT_RDY                0x10
135 #define AU6601_CMD_NO_RESP                      0x00
136 
137 #define AU6601_REG_BUS_CTRL                     0x82
138 #define AU6601_BUS_WIDTH_4BIT                   0x20
139 #define AU6601_BUS_WIDTH_8BIT                   0x10
140 #define AU6601_BUS_WIDTH_1BIT                   0x00
141 
142 #define AU6601_DATA_XFER_CTRL                   0x83
143 #define AU6601_DATA_WRITE                       BIT(7)
144 #define AU6601_DATA_DMA_MODE                    BIT(6)
145 #define AU6601_DATA_START_XFER                  BIT(0)
146 
147 #define AU6601_DATA_PIN_STATE                   0x84
148 #define AU6601_BUS_STAT_CMD                     BIT(15)
149 /* BIT(4) - BIT(7) are permanently 1.
150  * May be reserved or not attached DAT4-DAT7
151  */
152 #define AU6601_BUS_STAT_DAT3                    BIT(3)
153 #define AU6601_BUS_STAT_DAT2                    BIT(2)
154 #define AU6601_BUS_STAT_DAT1                    BIT(1)
155 #define AU6601_BUS_STAT_DAT0                    BIT(0)
156 #define AU6601_BUS_STAT_DAT_MASK                0xf
157 
158 #define AU6601_OPT                              0x85
159 #define AU6601_OPT_CMD_LINE_LEVEL               0x80
160 #define AU6601_OPT_NCRC_16_CLK                  BIT(4)
161 #define AU6601_OPT_CMD_NWT                      BIT(3)
162 #define AU6601_OPT_STOP_CLK                     BIT(2)
163 #define AU6601_OPT_DDR_MODE                     BIT(1)
164 #define AU6601_OPT_SD_18V                       BIT(0)
165 
166 #define AU6601_CLK_DELAY                        0x86
167 #define AU6601_CLK_DATA_POSITIVE_EDGE           0x80
168 #define AU6601_CLK_CMD_POSITIVE_EDGE            0x40
169 #define AU6601_CLK_POSITIVE_EDGE_ALL            (AU6601_CLK_CMD_POSITIVE_EDGE \
170                                                 | AU6601_CLK_DATA_POSITIVE_EDGE)
171 
172 
173 #define AU6601_REG_INT_STATUS                   0x90
174 #define AU6601_REG_INT_ENABLE                   0x94
175 #define AU6601_INT_DATA_END_BIT_ERR             BIT(22)
176 #define AU6601_INT_DATA_CRC_ERR                 BIT(21)
177 #define AU6601_INT_DATA_TIMEOUT_ERR             BIT(20)
178 #define AU6601_INT_CMD_INDEX_ERR                BIT(19)
179 #define AU6601_INT_CMD_END_BIT_ERR              BIT(18)
180 #define AU6601_INT_CMD_CRC_ERR                  BIT(17)
181 #define AU6601_INT_CMD_TIMEOUT_ERR              BIT(16)
182 #define AU6601_INT_ERROR                        BIT(15)
183 #define AU6601_INT_OVER_CURRENT_ERR             BIT(8)
184 #define AU6601_INT_CARD_INSERT                  BIT(7)
185 #define AU6601_INT_CARD_REMOVE                  BIT(6)
186 #define AU6601_INT_READ_BUF_RDY                 BIT(5)
187 #define AU6601_INT_WRITE_BUF_RDY                BIT(4)
188 #define AU6601_INT_DMA_END                      BIT(3)
189 #define AU6601_INT_DATA_END                     BIT(1)
190 #define AU6601_INT_CMD_END                      BIT(0)
191 
192 #define AU6601_INT_NORMAL_MASK                  0x00007FFF
193 #define AU6601_INT_ERROR_MASK                   0xFFFF8000
194 
195 #define AU6601_INT_CMD_MASK     (AU6601_INT_CMD_END | \
196                 AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \
197                 AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR)
198 #define AU6601_INT_DATA_MASK    (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \
199                 AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \
200                 AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \
201                 AU6601_INT_DATA_END_BIT_ERR)
202 #define AU6601_INT_ALL_MASK                     ((u32)-1)
203 
204 /* MS_CARD mode registers */
205 
206 #define AU6601_MS_STATUS                        0xa0
207 
208 #define AU6601_MS_BUS_MODE_CTRL                 0xa1
209 #define AU6601_MS_BUS_8BIT_MODE                 0x03
210 #define AU6601_MS_BUS_4BIT_MODE                 0x01
211 #define AU6601_MS_BUS_1BIT_MODE                 0x00
212 
213 #define AU6601_MS_TPC_CMD                       0xa2
214 #define AU6601_MS_TPC_READ_PAGE_DATA            0x02
215 #define AU6601_MS_TPC_READ_REG                  0x04
216 #define AU6601_MS_TPC_GET_INT                   0x07
217 #define AU6601_MS_TPC_WRITE_PAGE_DATA           0x0D
218 #define AU6601_MS_TPC_WRITE_REG                 0x0B
219 #define AU6601_MS_TPC_SET_RW_REG_ADRS           0x08
220 #define AU6601_MS_TPC_SET_CMD                   0x0E
221 #define AU6601_MS_TPC_EX_SET_CMD                0x09
222 #define AU6601_MS_TPC_READ_SHORT_DATA           0x03
223 #define AU6601_MS_TPC_WRITE_SHORT_DATA          0x0C
224 
225 #define AU6601_MS_TRANSFER_MODE                 0xa3
226 #define AU6601_MS_XFER_INT_TIMEOUT_CHK          BIT(2)
227 #define AU6601_MS_XFER_DMA_ENABLE               BIT(1)
228 #define AU6601_MS_XFER_START                    BIT(0)
229 
230 #define AU6601_MS_DATA_PIN_STATE                0xa4
231 
232 #define AU6601_MS_INT_STATUS                    0xb0
233 #define AU6601_MS_INT_ENABLE                    0xb4
234 #define AU6601_MS_INT_OVER_CURRENT_ERROR        BIT(23)
235 #define AU6601_MS_INT_DATA_CRC_ERROR            BIT(21)
236 #define AU6601_MS_INT_INT_TIMEOUT               BIT(20)
237 #define AU6601_MS_INT_INT_RESP_ERROR            BIT(19)
238 #define AU6601_MS_INT_CED_ERROR                 BIT(18)
239 #define AU6601_MS_INT_TPC_TIMEOUT               BIT(16)
240 #define AU6601_MS_INT_ERROR                     BIT(15)
241 #define AU6601_MS_INT_CARD_INSERT               BIT(7)
242 #define AU6601_MS_INT_CARD_REMOVE               BIT(6)
243 #define AU6601_MS_INT_BUF_READ_RDY              BIT(5)
244 #define AU6601_MS_INT_BUF_WRITE_RDY             BIT(4)
245 #define AU6601_MS_INT_DMA_END                   BIT(3)
246 #define AU6601_MS_INT_TPC_END                   BIT(1)
247 
248 #define AU6601_MS_INT_DATA_MASK                 0x00000038
249 #define AU6601_MS_INT_TPC_MASK                  0x003d8002
250 #define AU6601_MS_INT_TPC_ERROR                 0x003d0000
251 
252 #define ALCOR_PCIE_LINK_CTRL_OFFSET             0x10
253 #define ALCOR_PCIE_LINK_CAP_OFFSET              0x0c
254 #define ALCOR_CAP_START_OFFSET                  0x34
255 
256 struct alcor_dev_cfg {
257         u8      dma;
258 };
259 
260 struct alcor_pci_priv {
261         struct pci_dev *pdev;
262         struct pci_dev *parent_pdev;
263         struct  device *dev;
264         void __iomem *iobase;
265         unsigned int irq;
266 
267         unsigned long id; /* idr id */
268 
269         struct alcor_dev_cfg    *cfg;
270 
271         /* PCI ASPM related vars */
272         int pdev_cap_off;
273         u8  pdev_aspm_cap;
274         int parent_cap_off;
275         u8  parent_aspm_cap;
276         u8 ext_config_dev_aspm;
277 };
278 
279 void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr);
280 void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr);
281 void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
282 void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
283 u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr);
284 u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr);
285 u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr);
286 #endif
287 

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