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Linux/include/linux/amba/clcd.h

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  1 /*
  2  * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
  3  *
  4  * David A Rusling
  5  *
  6  * Copyright (C) 2001 ARM Limited
  7  *
  8  * This file is subject to the terms and conditions of the GNU General Public
  9  * License.  See the file COPYING in the main directory of this archive
 10  * for more details.
 11  */
 12 #include <linux/fb.h>
 13 #include <linux/amba/clcd-regs.h>
 14 
 15 enum {
 16         /* individual formats */
 17         CLCD_CAP_RGB444         = (1 << 0),
 18         CLCD_CAP_RGB5551        = (1 << 1),
 19         CLCD_CAP_RGB565         = (1 << 2),
 20         CLCD_CAP_RGB888         = (1 << 3),
 21         CLCD_CAP_BGR444         = (1 << 4),
 22         CLCD_CAP_BGR5551        = (1 << 5),
 23         CLCD_CAP_BGR565         = (1 << 6),
 24         CLCD_CAP_BGR888         = (1 << 7),
 25 
 26         /* connection layouts */
 27         CLCD_CAP_444            = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
 28         CLCD_CAP_5551           = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
 29         CLCD_CAP_565            = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
 30         CLCD_CAP_888            = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
 31 
 32         /* red/blue ordering */
 33         CLCD_CAP_RGB            = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
 34                                   CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
 35         CLCD_CAP_BGR            = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
 36                                   CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
 37 
 38         CLCD_CAP_ALL            = CLCD_CAP_BGR | CLCD_CAP_RGB,
 39 };
 40 
 41 struct backlight_device;
 42 
 43 struct clcd_panel {
 44         struct fb_videomode     mode;
 45         signed short            width;  /* width in mm */
 46         signed short            height; /* height in mm */
 47         u32                     tim2;
 48         u32                     tim3;
 49         u32                     cntl;
 50         u32                     caps;
 51         unsigned int            bpp:8,
 52                                 fixedtimings:1,
 53                                 grayscale:1;
 54         unsigned int            connector;
 55         struct backlight_device *backlight;
 56         /*
 57          * If the B/R lines are switched between the CLCD
 58          * and the panel we need to know this and not try to
 59          * compensate with the BGR bit in the control register.
 60          */
 61         bool                    bgr_connection;
 62 };
 63 
 64 struct clcd_regs {
 65         u32                     tim0;
 66         u32                     tim1;
 67         u32                     tim2;
 68         u32                     tim3;
 69         u32                     cntl;
 70         unsigned long           pixclock;
 71 };
 72 
 73 struct clcd_fb;
 74 
 75 /*
 76  * the board-type specific routines
 77  */
 78 struct clcd_board {
 79         const char *name;
 80 
 81         /*
 82          * Optional.  Hardware capability flags.
 83          */
 84         u32     caps;
 85 
 86         /*
 87          * Optional.  Check whether the var structure is acceptable
 88          * for this display.
 89          */
 90         int     (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
 91 
 92         /*
 93          * Compulsory.  Decode fb->fb.var into regs->*.  In the case of
 94          * fixed timing, set regs->* to the register values required.
 95          */
 96         void    (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
 97 
 98         /*
 99          * Optional.  Disable any extra display hardware.
100          */
101         void    (*disable)(struct clcd_fb *);
102 
103         /*
104          * Optional.  Enable any extra display hardware.
105          */
106         void    (*enable)(struct clcd_fb *);
107 
108         /*
109          * Setup platform specific parts of CLCD driver
110          */
111         int     (*setup)(struct clcd_fb *);
112 
113         /*
114          * mmap the framebuffer memory
115          */
116         int     (*mmap)(struct clcd_fb *, struct vm_area_struct *);
117 
118         /*
119          * Remove platform specific parts of CLCD driver
120          */
121         void    (*remove)(struct clcd_fb *);
122 };
123 
124 struct amba_device;
125 struct clk;
126 
127 /**
128  * struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
129  * variant information
130  *
131  * @clock_timregs: the CLCD needs to be clocked when accessing the
132  * timer registers, or the hardware will hang.
133  * @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
134  * so that RGB accesses 3 bytes at a time, not just on even 32bit
135  * boundaries, packing the pixel data in memory. ST Microelectronics
136  * have this.
137  * @st_bitmux_control: ST Microelectronics have implemented output
138  * bit line multiplexing into the CLCD control register. This indicates
139  * that we need to use this.
140  * @init_board: custom board init function for this variant
141  * @init_panel: custom panel init function for this variant
142  */
143 struct clcd_vendor_data {
144         bool    clock_timregs;
145         bool    packed_24_bit_pixels;
146         bool    st_bitmux_control;
147         int     (*init_board)(struct amba_device *adev,
148                               struct clcd_board *board);
149         int     (*init_panel)(struct clcd_fb *fb,
150                               struct device_node *panel);
151 };
152 
153 /* this data structure describes each frame buffer device we find */
154 struct clcd_fb {
155         struct fb_info          fb;
156         struct amba_device      *dev;
157         struct clk              *clk;
158         struct clcd_vendor_data *vendor;
159         struct clcd_panel       *panel;
160         struct clcd_board       *board;
161         void                    *board_data;
162         void __iomem            *regs;
163         u16                     off_ienb;
164         u16                     off_cntl;
165         u32                     clcd_cntl;
166         u32                     cmap[16];
167         bool                    clk_enabled;
168 };
169 
170 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
171 {
172         struct fb_var_screeninfo *var = &fb->fb.var;
173         u32 val, cpl;
174 
175         /*
176          * Program the CLCD controller registers and start the CLCD
177          */
178         val = ((var->xres / 16) - 1) << 2;
179         val |= (var->hsync_len - 1) << 8;
180         val |= (var->right_margin - 1) << 16;
181         val |= (var->left_margin - 1) << 24;
182         regs->tim0 = val;
183 
184         val = var->yres;
185         if (fb->panel->cntl & CNTL_LCDDUAL)
186                 val /= 2;
187         val -= 1;
188         val |= (var->vsync_len - 1) << 10;
189         val |= var->lower_margin << 16;
190         val |= var->upper_margin << 24;
191         regs->tim1 = val;
192 
193         val = fb->panel->tim2;
194         val |= var->sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
195         val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
196 
197         cpl = var->xres_virtual;
198         if (fb->panel->cntl & CNTL_LCDTFT)        /* TFT */
199                 /* / 1 */;
200         else if (!var->grayscale)                 /* STN color */
201                 cpl = cpl * 8 / 3;
202         else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
203                 cpl /= 8;
204         else                                      /* STN monochrome, 4bit */
205                 cpl /= 4;
206 
207         regs->tim2 = val | ((cpl - 1) << 16);
208 
209         regs->tim3 = fb->panel->tim3;
210 
211         val = fb->panel->cntl;
212         if (var->grayscale)
213                 val |= CNTL_LCDBW;
214 
215         if (fb->panel->caps && fb->board->caps && var->bits_per_pixel >= 16) {
216                 /*
217                  * if board and panel supply capabilities, we can support
218                  * changing BGR/RGB depending on supplied parameters. Here
219                  * we switch to what the framebuffer is providing if need
220                  * be, so if the framebuffer is BGR but the display connection
221                  * is RGB (first case) we switch it around. Vice versa mutatis
222                  * mutandis if the framebuffer is RGB but the display connection
223                  * is BGR, we flip it around.
224                  */
225                 if (var->red.offset == 0)
226                         val &= ~CNTL_BGR;
227                 else
228                         val |= CNTL_BGR;
229                 if (fb->panel->bgr_connection)
230                         val ^= CNTL_BGR;
231         }
232 
233         switch (var->bits_per_pixel) {
234         case 1:
235                 val |= CNTL_LCDBPP1;
236                 break;
237         case 2:
238                 val |= CNTL_LCDBPP2;
239                 break;
240         case 4:
241                 val |= CNTL_LCDBPP4;
242                 break;
243         case 8:
244                 val |= CNTL_LCDBPP8;
245                 break;
246         case 16:
247                 /*
248                  * PL110 cannot choose between 5551 and 565 modes in its
249                  * control register.  It is possible to use 565 with
250                  * custom external wiring.
251                  */
252                 if (amba_part(fb->dev) == 0x110 ||
253                     var->green.length == 5)
254                         val |= CNTL_LCDBPP16;
255                 else if (var->green.length == 6)
256                         val |= CNTL_LCDBPP16_565;
257                 else
258                         val |= CNTL_LCDBPP16_444;
259                 break;
260         case 24:
261                 /* Modified variant supporting 24 bit packed pixels */
262                 val |= CNTL_ST_LCDBPP24_PACKED;
263                 break;
264         case 32:
265                 val |= CNTL_LCDBPP24;
266                 break;
267         }
268 
269         regs->cntl = val;
270         regs->pixclock = var->pixclock;
271 }
272 
273 static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
274 {
275         var->xres_virtual = var->xres = (var->xres + 15) & ~15;
276         var->yres_virtual = var->yres = (var->yres + 1) & ~1;
277 
278 #define CHECK(e,l,h) (var->e < l || var->e > h)
279         if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
280             CHECK(left_margin, (5+1), 256) ||   /* front porch */
281             CHECK(hsync_len, (5+1), 256) ||
282             var->xres > 4096 ||
283             var->lower_margin > 255 ||          /* back porch */
284             var->upper_margin > 255 ||          /* front porch */
285             var->vsync_len > 32 ||
286             var->yres > 1024)
287                 return -EINVAL;
288 #undef CHECK
289 
290         /* single panel mode: PCD = max(PCD, 1) */
291         /* dual panel mode: PCD = max(PCD, 5) */
292 
293         /*
294          * You can't change the grayscale setting, and
295          * we can only do non-interlaced video.
296          */
297         if (var->grayscale != fb->fb.var.grayscale ||
298             (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
299                 return -EINVAL;
300 
301 #define CHECK(e) (var->e != fb->fb.var.e)
302         if (fb->panel->fixedtimings &&
303             (CHECK(xres)                ||
304              CHECK(yres)                ||
305              CHECK(bits_per_pixel)      ||
306              CHECK(pixclock)            ||
307              CHECK(left_margin)         ||
308              CHECK(right_margin)        ||
309              CHECK(upper_margin)        ||
310              CHECK(lower_margin)        ||
311              CHECK(hsync_len)           ||
312              CHECK(vsync_len)           ||
313              CHECK(sync)))
314                 return -EINVAL;
315 #undef CHECK
316 
317         var->nonstd = 0;
318         var->accel_flags = 0;
319 
320         return 0;
321 }
322 

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