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TOMOYO Linux Cross Reference
Linux/include/linux/cyclades.h

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  1 /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
  2  * linux/include/linux/cyclades.h
  3  *
  4  * This file was initially written by
  5  * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
  6  * Ivan Passos <ivan@cyclades.com>.
  7  *
  8  * This file contains the general definitions for the cyclades.c driver
  9  *$Log: cyclades.h,v $
 10  *Revision 3.1  2002/01/29 11:36:16  henrique
 11  *added throttle field on struct cyclades_port to indicate whether the
 12  *port is throttled or not
 13  *
 14  *Revision 3.1  2000/04/19 18:52:52  ivan
 15  *converted address fields to unsigned long and added fields for physical
 16  *addresses on cyclades_card structure;
 17  *
 18  *Revision 3.0  1998/11/02 14:20:59  ivan
 19  *added nports field on cyclades_card structure;
 20  *
 21  *Revision 2.5  1998/08/03 16:57:01  ivan
 22  *added cyclades_idle_stats structure;
 23  * 
 24  *Revision 2.4  1998/06/01 12:09:53  ivan
 25  *removed closing_wait2 from cyclades_port structure;
 26  *
 27  *Revision 2.3  1998/03/16 18:01:12  ivan
 28  *changes in the cyclades_port structure to get it closer to the 
 29  *standard serial port structure;
 30  *added constants for new ioctls;
 31  *
 32  *Revision 2.2  1998/02/17 16:50:00  ivan
 33  *changes in the cyclades_port structure (addition of shutdown_wait and 
 34  *chip_rev variables);
 35  *added constants for new ioctls and for CD1400 rev. numbers.
 36  *
 37  *Revision 2.1  1997/10/24 16:03:00  ivan
 38  *added rflow (which allows enabling the CD1400 special flow control 
 39  *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to 
 40  *cyclades_port structure;
 41  *added Alpha support
 42  *
 43  *Revision 2.0  1997/06/30 10:30:00  ivan
 44  *added some new doorbell command constants related to IOCTLW and
 45  *UART error signaling
 46  *
 47  *Revision 1.8  1997/06/03 15:30:00  ivan
 48  *added constant ZFIRM_HLT
 49  *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
 50  *
 51  *Revision 1.7  1997/03/26 10:30:00  daniel
 52  *new entries at the end of cyclades_port struct to reallocate
 53  *variables illegally allocated within card memory.
 54  *
 55  *Revision 1.6  1996/09/09 18:35:30  bentson
 56  *fold in changes for Cyclom-Z -- including structures for
 57  *communicating with board as well modest changes to original
 58  *structures to support new features.
 59  *
 60  *Revision 1.5  1995/11/13 21:13:31  bentson
 61  *changes suggested by Michael Chastain <mec@duracef.shout.net>
 62  *to support use of this file in non-kernel applications
 63  *
 64  *
 65  */
 66 #ifndef _LINUX_CYCLADES_H
 67 #define _LINUX_CYCLADES_H
 68 
 69 #include <uapi/linux/cyclades.h>
 70 
 71 
 72 /* Per card data structure */
 73 struct cyclades_card {
 74         void __iomem *base_addr;
 75         union {
 76                 void __iomem *p9050;
 77                 struct RUNTIME_9060 __iomem *p9060;
 78         } ctl_addr;
 79         struct BOARD_CTRL __iomem *board_ctrl;  /* cyz specific */
 80         int irq;
 81         unsigned int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */
 82         unsigned int first_line;        /* minor number of first channel on card */
 83         unsigned int nports;    /* Number of ports in the card */
 84         int bus_index;          /* address shift - 0 for ISA, 1 for PCI */
 85         int intr_enabled;               /* FW Interrupt flag - 0 disabled, 1 enabled */
 86         u32 hw_ver;
 87         spinlock_t card_lock;
 88         struct cyclades_port *ports;
 89 };
 90 
 91 /***************************************
 92  * Memory access functions/macros      *
 93  * (required to support Alpha systems) *
 94  ***************************************/
 95 
 96 #define cy_writeb(port,val)     do { writeb((val), (port)); mb(); } while (0)
 97 #define cy_writew(port,val)     do { writew((val), (port)); mb(); } while (0)
 98 #define cy_writel(port,val)     do { writel((val), (port)); mb(); } while (0)
 99 
100 /*
101  * Statistics counters
102  */
103 struct cyclades_icount {
104         __u32   cts, dsr, rng, dcd, tx, rx;
105         __u32   frame, parity, overrun, brk;
106         __u32   buf_overrun;
107 };
108 
109 /*
110  * This is our internal structure for each serial port's state.
111  * 
112  * Many fields are paralleled by the structure used by the serial_struct
113  * structure.
114  *
115  * For definitions of the flags field, see tty.h
116  */
117 
118 struct cyclades_port {
119         int                     magic;
120         struct tty_port         port;
121         struct cyclades_card    *card;
122         union {
123                 struct {
124                         void __iomem *base_addr;
125                 } cyy;
126                 struct {
127                         struct CH_CTRL __iomem  *ch_ctrl;
128                         struct BUF_CTRL __iomem *buf_ctrl;
129                 } cyz;
130         } u;
131         int                     line;
132         int                     flags;          /* defined in tty.h */
133         int                     type;           /* UART type */
134         int                     read_status_mask;
135         int                     ignore_status_mask;
136         int                     timeout;
137         int                     xmit_fifo_size;
138         int                     cor1,cor2,cor3,cor4,cor5;
139         int                     tbpr,tco,rbpr,rco;
140         int                     baud;
141         int                     rflow;
142         int                     rtsdtr_inv;
143         int                     chip_rev;
144         int                     custom_divisor;
145         u8                      x_char; /* to be pushed out ASAP */
146         int                     breakon;
147         int                     breakoff;
148         int                     xmit_head;
149         int                     xmit_tail;
150         int                     xmit_cnt;
151         int                     default_threshold;
152         int                     default_timeout;
153         unsigned long           rflush_count;
154         struct cyclades_monitor mon;
155         struct cyclades_idle_stats      idle_stats;
156         struct cyclades_icount  icount;
157         struct completion       shutdown_wait;
158         int throttle;
159 };
160 
161 #define CLOSING_WAIT_DELAY      30*HZ
162 #define CY_CLOSING_WAIT_NONE    ASYNC_CLOSING_WAIT_NONE
163 #define CY_CLOSING_WAIT_INF     ASYNC_CLOSING_WAIT_INF
164 
165 
166 #define CyMAX_CHIPS_PER_CARD    8
167 #define CyMAX_CHAR_FIFO         12
168 #define CyPORTS_PER_CHIP        4
169 #define CD1400_MAX_SPEED        115200
170 
171 #define CyISA_Ywin      0x2000
172 
173 #define CyPCI_Ywin      0x4000
174 #define CyPCI_Yctl      0x80
175 #define CyPCI_Zctl      CTRL_WINDOW_SIZE
176 #define CyPCI_Zwin      0x80000
177 #define CyPCI_Ze_win    (2 * CyPCI_Zwin)
178 
179 #define PCI_DEVICE_ID_MASK      0x06
180 
181 /**** CD1400 registers ****/
182 
183 #define CD1400_REV_G    0x46
184 #define CD1400_REV_J    0x48
185 
186 #define CyRegSize       0x0400
187 #define Cy_HwReset      0x1400
188 #define Cy_ClrIntr      0x1800
189 #define Cy_EpldRev      0x1e00
190 
191 /* Global Registers */
192 
193 #define CyGFRCR         (0x40*2)
194 #define      CyRevE             (44)
195 #define CyCAR           (0x68*2)
196 #define      CyCHAN_0           (0x00)
197 #define      CyCHAN_1           (0x01)
198 #define      CyCHAN_2           (0x02)
199 #define      CyCHAN_3           (0x03)
200 #define CyGCR           (0x4B*2)
201 #define      CyCH0_SERIAL       (0x00)
202 #define      CyCH0_PARALLEL     (0x80)
203 #define CySVRR          (0x67*2)
204 #define      CySRModem          (0x04)
205 #define      CySRTransmit       (0x02)
206 #define      CySRReceive        (0x01)
207 #define CyRICR          (0x44*2)
208 #define CyTICR          (0x45*2)
209 #define CyMICR          (0x46*2)
210 #define      CyICR0             (0x00)
211 #define      CyICR1             (0x01)
212 #define      CyICR2             (0x02)
213 #define      CyICR3             (0x03)
214 #define CyRIR           (0x6B*2)
215 #define CyTIR           (0x6A*2)
216 #define CyMIR           (0x69*2)
217 #define      CyIRDirEq          (0x80)
218 #define      CyIRBusy           (0x40)
219 #define      CyIRUnfair         (0x20)
220 #define      CyIRContext        (0x1C)
221 #define      CyIRChannel        (0x03)
222 #define CyPPR           (0x7E*2)
223 #define      CyCLOCK_20_1MS     (0x27)
224 #define      CyCLOCK_25_1MS     (0x31)
225 #define      CyCLOCK_25_5MS     (0xf4)
226 #define      CyCLOCK_60_1MS     (0x75)
227 #define      CyCLOCK_60_2MS     (0xea)
228 
229 /* Virtual Registers */
230 
231 #define CyRIVR          (0x43*2)
232 #define CyTIVR          (0x42*2)
233 #define CyMIVR          (0x41*2)
234 #define      CyIVRMask (0x07)
235 #define      CyIVRRxEx (0x07)
236 #define      CyIVRRxOK (0x03)
237 #define      CyIVRTxOK (0x02)
238 #define      CyIVRMdmOK (0x01)
239 #define CyTDR           (0x63*2)
240 #define CyRDSR          (0x62*2)
241 #define      CyTIMEOUT          (0x80)
242 #define      CySPECHAR          (0x70)
243 #define      CyBREAK            (0x08)
244 #define      CyPARITY           (0x04)
245 #define      CyFRAME            (0x02)
246 #define      CyOVERRUN          (0x01)
247 #define CyMISR          (0x4C*2)
248 /* see CyMCOR_ and CyMSVR_ for bits*/
249 #define CyEOSRR         (0x60*2)
250 
251 /* Channel Registers */
252 
253 #define CyLIVR          (0x18*2)
254 #define      CyMscsr            (0x01)
255 #define      CyTdsr             (0x02)
256 #define      CyRgdsr            (0x03)
257 #define      CyRedsr            (0x07)
258 #define CyCCR           (0x05*2)
259 /* Format 1 */
260 #define      CyCHAN_RESET       (0x80)
261 #define      CyCHIP_RESET       (0x81)
262 #define      CyFlushTransFIFO   (0x82)
263 /* Format 2 */
264 #define      CyCOR_CHANGE       (0x40)
265 #define      CyCOR1ch           (0x02)
266 #define      CyCOR2ch           (0x04)
267 #define      CyCOR3ch           (0x08)
268 /* Format 3 */
269 #define      CySEND_SPEC_1      (0x21)
270 #define      CySEND_SPEC_2      (0x22)
271 #define      CySEND_SPEC_3      (0x23)
272 #define      CySEND_SPEC_4      (0x24)
273 /* Format 4 */
274 #define      CyCHAN_CTL         (0x10)
275 #define      CyDIS_RCVR         (0x01)
276 #define      CyENB_RCVR         (0x02)
277 #define      CyDIS_XMTR         (0x04)
278 #define      CyENB_XMTR         (0x08)
279 #define CySRER          (0x06*2)
280 #define      CyMdmCh            (0x80)
281 #define      CyRxData           (0x10)
282 #define      CyTxRdy            (0x04)
283 #define      CyTxMpty           (0x02)
284 #define      CyNNDT             (0x01)
285 #define CyCOR1          (0x08*2)
286 #define      CyPARITY_NONE      (0x00)
287 #define      CyPARITY_0         (0x20)
288 #define      CyPARITY_1         (0xA0)
289 #define      CyPARITY_E         (0x40)
290 #define      CyPARITY_O         (0xC0)
291 #define      Cy_1_STOP          (0x00)
292 #define      Cy_1_5_STOP        (0x04)
293 #define      Cy_2_STOP          (0x08)
294 #define      Cy_5_BITS          (0x00)
295 #define      Cy_6_BITS          (0x01)
296 #define      Cy_7_BITS          (0x02)
297 #define      Cy_8_BITS          (0x03)
298 #define CyCOR2          (0x09*2)
299 #define      CyIXM              (0x80)
300 #define      CyTxIBE            (0x40)
301 #define      CyETC              (0x20)
302 #define      CyAUTO_TXFL        (0x60)
303 #define      CyLLM              (0x10)
304 #define      CyRLM              (0x08)
305 #define      CyRtsAO            (0x04)
306 #define      CyCtsAE            (0x02)
307 #define      CyDsrAE            (0x01)
308 #define CyCOR3          (0x0A*2)
309 #define      CySPL_CH_DRANGE    (0x80)  /* special character detect range */
310 #define      CySPL_CH_DET1      (0x40)  /* enable special character detection
311                                                                on SCHR4-SCHR3 */
312 #define      CyFL_CTRL_TRNSP    (0x20)  /* Flow Control Transparency */
313 #define      CySPL_CH_DET2      (0x10)  /* Enable special character detection
314                                                                on SCHR2-SCHR1 */
315 #define      CyREC_FIFO         (0x0F)  /* Receive FIFO threshold */
316 #define CyCOR4          (0x1E*2)
317 #define CyCOR5          (0x1F*2)
318 #define CyCCSR          (0x0B*2)
319 #define      CyRxEN             (0x80)
320 #define      CyRxFloff          (0x40)
321 #define      CyRxFlon           (0x20)
322 #define      CyTxEN             (0x08)
323 #define      CyTxFloff          (0x04)
324 #define      CyTxFlon           (0x02)
325 #define CyRDCR          (0x0E*2)
326 #define CySCHR1         (0x1A*2)
327 #define CySCHR2         (0x1B*2)
328 #define CySCHR3         (0x1C*2)
329 #define CySCHR4         (0x1D*2)
330 #define CySCRL          (0x22*2)
331 #define CySCRH          (0x23*2)
332 #define CyLNC           (0x24*2)
333 #define CyMCOR1         (0x15*2)
334 #define CyMCOR2         (0x16*2)
335 #define CyRTPR          (0x21*2)
336 #define CyMSVR1         (0x6C*2)
337 #define CyMSVR2         (0x6D*2)
338 #define      CyANY_DELTA        (0xF0)
339 #define      CyDSR              (0x80)
340 #define      CyCTS              (0x40)
341 #define      CyRI               (0x20)
342 #define      CyDCD              (0x10)
343 #define      CyDTR              (0x02)
344 #define      CyRTS              (0x01)
345 #define CyPVSR          (0x6F*2)
346 #define CyRBPR          (0x78*2)
347 #define CyRCOR          (0x7C*2)
348 #define CyTBPR          (0x72*2)
349 #define CyTCOR          (0x76*2)
350 
351 /* Custom Registers */
352 
353 #define CyPLX_VER       (0x3400)
354 #define PLX_9050        0x0b
355 #define PLX_9060        0x0c
356 #define PLX_9080        0x0d
357 
358 /***************************************************************************/
359 
360 #endif /* _LINUX_CYCLADES_H */
361 

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