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Linux/include/linux/dmaengine.h

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  1 /* SPDX-License-Identifier: GPL-2.0-or-later */
  2 /*
  3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  4  */
  5 #ifndef LINUX_DMAENGINE_H
  6 #define LINUX_DMAENGINE_H
  7 
  8 #include <linux/device.h>
  9 #include <linux/err.h>
 10 #include <linux/uio.h>
 11 #include <linux/bug.h>
 12 #include <linux/scatterlist.h>
 13 #include <linux/bitmap.h>
 14 #include <linux/types.h>
 15 #include <asm/page.h>
 16 
 17 /**
 18  * typedef dma_cookie_t - an opaque DMA cookie
 19  *
 20  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 21  */
 22 typedef s32 dma_cookie_t;
 23 #define DMA_MIN_COOKIE  1
 24 
 25 static inline int dma_submit_error(dma_cookie_t cookie)
 26 {
 27         return cookie < 0 ? cookie : 0;
 28 }
 29 
 30 /**
 31  * enum dma_status - DMA transaction status
 32  * @DMA_COMPLETE: transaction completed
 33  * @DMA_IN_PROGRESS: transaction not yet processed
 34  * @DMA_PAUSED: transaction is paused
 35  * @DMA_ERROR: transaction failed
 36  */
 37 enum dma_status {
 38         DMA_COMPLETE,
 39         DMA_IN_PROGRESS,
 40         DMA_PAUSED,
 41         DMA_ERROR,
 42 };
 43 
 44 /**
 45  * enum dma_transaction_type - DMA transaction types/indexes
 46  *
 47  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 48  * automatically set as dma devices are registered.
 49  */
 50 enum dma_transaction_type {
 51         DMA_MEMCPY,
 52         DMA_XOR,
 53         DMA_PQ,
 54         DMA_XOR_VAL,
 55         DMA_PQ_VAL,
 56         DMA_MEMSET,
 57         DMA_MEMSET_SG,
 58         DMA_INTERRUPT,
 59         DMA_PRIVATE,
 60         DMA_ASYNC_TX,
 61         DMA_SLAVE,
 62         DMA_CYCLIC,
 63         DMA_INTERLEAVE,
 64 /* last transaction type for creation of the capabilities mask */
 65         DMA_TX_TYPE_END,
 66 };
 67 
 68 /**
 69  * enum dma_transfer_direction - dma transfer mode and direction indicator
 70  * @DMA_MEM_TO_MEM: Async/Memcpy mode
 71  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 72  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 73  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 74  */
 75 enum dma_transfer_direction {
 76         DMA_MEM_TO_MEM,
 77         DMA_MEM_TO_DEV,
 78         DMA_DEV_TO_MEM,
 79         DMA_DEV_TO_DEV,
 80         DMA_TRANS_NONE,
 81 };
 82 
 83 /**
 84  * Interleaved Transfer Request
 85  * ----------------------------
 86  * A chunk is collection of contiguous bytes to be transferred.
 87  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
 88  * ICGs may or may not change between chunks.
 89  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
 90  *  that when repeated an integral number of times, specifies the transfer.
 91  * A transfer template is specification of a Frame, the number of times
 92  *  it is to be repeated and other per-transfer attributes.
 93  *
 94  * Practically, a client driver would have ready a template for each
 95  *  type of transfer it is going to need during its lifetime and
 96  *  set only 'src_start' and 'dst_start' before submitting the requests.
 97  *
 98  *
 99  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
100  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
101  *
102  *    ==  Chunk size
103  *    ... ICG
104  */
105 
106 /**
107  * struct data_chunk - Element of scatter-gather list that makes a frame.
108  * @size: Number of bytes to read from source.
109  *        size_dst := fn(op, size_src), so doesn't mean much for destination.
110  * @icg: Number of bytes to jump after last src/dst address of this
111  *       chunk and before first src/dst address for next chunk.
112  *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
113  *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
114  * @dst_icg: Number of bytes to jump after last dst address of this
115  *       chunk and before the first dst address for next chunk.
116  *       Ignored if dst_inc is true and dst_sgl is false.
117  * @src_icg: Number of bytes to jump after last src address of this
118  *       chunk and before the first src address for next chunk.
119  *       Ignored if src_inc is true and src_sgl is false.
120  */
121 struct data_chunk {
122         size_t size;
123         size_t icg;
124         size_t dst_icg;
125         size_t src_icg;
126 };
127 
128 /**
129  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
130  *       and attributes.
131  * @src_start: Bus address of source for the first chunk.
132  * @dst_start: Bus address of destination for the first chunk.
133  * @dir: Specifies the type of Source and Destination.
134  * @src_inc: If the source address increments after reading from it.
135  * @dst_inc: If the destination address increments after writing to it.
136  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
137  *              Otherwise, source is read contiguously (icg ignored).
138  *              Ignored if src_inc is false.
139  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
140  *              Otherwise, destination is filled contiguously (icg ignored).
141  *              Ignored if dst_inc is false.
142  * @numf: Number of frames in this template.
143  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
144  * @sgl: Array of {chunk,icg} pairs that make up a frame.
145  */
146 struct dma_interleaved_template {
147         dma_addr_t src_start;
148         dma_addr_t dst_start;
149         enum dma_transfer_direction dir;
150         bool src_inc;
151         bool dst_inc;
152         bool src_sgl;
153         bool dst_sgl;
154         size_t numf;
155         size_t frame_size;
156         struct data_chunk sgl[];
157 };
158 
159 /**
160  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
161  *  control completion, and communicate status.
162  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
163  *  this transaction
164  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
165  *  acknowledges receipt, i.e. has has a chance to establish any dependency
166  *  chains
167  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
168  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
169  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
170  *  sources that were the result of a previous operation, in the case of a PQ
171  *  operation it continues the calculation with new sources
172  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
173  *  on the result of this operation
174  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
175  *  cleared or freed
176  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
177  *  data and the descriptor should be in different format from normal
178  *  data descriptors.
179  */
180 enum dma_ctrl_flags {
181         DMA_PREP_INTERRUPT = (1 << 0),
182         DMA_CTRL_ACK = (1 << 1),
183         DMA_PREP_PQ_DISABLE_P = (1 << 2),
184         DMA_PREP_PQ_DISABLE_Q = (1 << 3),
185         DMA_PREP_CONTINUE = (1 << 4),
186         DMA_PREP_FENCE = (1 << 5),
187         DMA_CTRL_REUSE = (1 << 6),
188         DMA_PREP_CMD = (1 << 7),
189 };
190 
191 /**
192  * enum sum_check_bits - bit position of pq_check_flags
193  */
194 enum sum_check_bits {
195         SUM_CHECK_P = 0,
196         SUM_CHECK_Q = 1,
197 };
198 
199 /**
200  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
201  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
202  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
203  */
204 enum sum_check_flags {
205         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
206         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
207 };
208 
209 
210 /**
211  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
212  * See linux/cpumask.h
213  */
214 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
215 
216 /**
217  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
218  * @memcpy_count: transaction counter
219  * @bytes_transferred: byte counter
220  */
221 
222 /**
223  * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
224  * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
225  *  client driver and it is attached (via the dmaengine_desc_attach_metadata()
226  *  helper) to the descriptor.
227  *
228  * Client drivers interested to use this mode can follow:
229  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
230  *   1. prepare the descriptor (dmaengine_prep_*)
231  *      construct the metadata in the client's buffer
232  *   2. use dmaengine_desc_attach_metadata() to attach the buffer to the
233  *      descriptor
234  *   3. submit the transfer
235  * - DMA_DEV_TO_MEM:
236  *   1. prepare the descriptor (dmaengine_prep_*)
237  *   2. use dmaengine_desc_attach_metadata() to attach the buffer to the
238  *      descriptor
239  *   3. submit the transfer
240  *   4. when the transfer is completed, the metadata should be available in the
241  *      attached buffer
242  *
243  * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
244  *  driver. The client driver can ask for the pointer, maximum size and the
245  *  currently used size of the metadata and can directly update or read it.
246  *  dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
247  *  provided as helper functions.
248  *
249  *  Note: the metadata area for the descriptor is no longer valid after the
250  *  transfer has been completed (valid up to the point when the completion
251  *  callback returns if used).
252  *
253  * Client drivers interested to use this mode can follow:
254  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
255  *   1. prepare the descriptor (dmaengine_prep_*)
256  *   2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
257  *      metadata area
258  *   3. update the metadata at the pointer
259  *   4. use dmaengine_desc_set_metadata_len()  to tell the DMA engine the amount
260  *      of data the client has placed into the metadata buffer
261  *   5. submit the transfer
262  * - DMA_DEV_TO_MEM:
263  *   1. prepare the descriptor (dmaengine_prep_*)
264  *   2. submit the transfer
265  *   3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
266  *      pointer to the engine's metadata area
267  *   4. Read out the metadata from the pointer
268  *
269  * Note: the two mode is not compatible and clients must use one mode for a
270  * descriptor.
271  */
272 enum dma_desc_metadata_mode {
273         DESC_METADATA_NONE = 0,
274         DESC_METADATA_CLIENT = BIT(0),
275         DESC_METADATA_ENGINE = BIT(1),
276 };
277 
278 struct dma_chan_percpu {
279         /* stats */
280         unsigned long memcpy_count;
281         unsigned long bytes_transferred;
282 };
283 
284 /**
285  * struct dma_router - DMA router structure
286  * @dev: pointer to the DMA router device
287  * @route_free: function to be called when the route can be disconnected
288  */
289 struct dma_router {
290         struct device *dev;
291         void (*route_free)(struct device *dev, void *route_data);
292 };
293 
294 /**
295  * struct dma_chan - devices supply DMA channels, clients use them
296  * @device: ptr to the dma device who supplies this channel, always !%NULL
297  * @slave: ptr to the device using this channel
298  * @cookie: last cookie value returned to client
299  * @completed_cookie: last completed cookie for this channel
300  * @chan_id: channel ID for sysfs
301  * @dev: class device for sysfs
302  * @name: backlink name for sysfs
303  * @dbg_client_name: slave name for debugfs in format:
304  *      dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
305  * @device_node: used to add this to the device chan list
306  * @local: per-cpu pointer to a struct dma_chan_percpu
307  * @client_count: how many clients are using this channel
308  * @table_count: number of appearances in the mem-to-mem allocation table
309  * @router: pointer to the DMA router structure
310  * @route_data: channel specific data for the router
311  * @private: private data for certain client-channel associations
312  */
313 struct dma_chan {
314         struct dma_device *device;
315         struct device *slave;
316         dma_cookie_t cookie;
317         dma_cookie_t completed_cookie;
318 
319         /* sysfs */
320         int chan_id;
321         struct dma_chan_dev *dev;
322         const char *name;
323 #ifdef CONFIG_DEBUG_FS
324         char *dbg_client_name;
325 #endif
326 
327         struct list_head device_node;
328         struct dma_chan_percpu __percpu *local;
329         int client_count;
330         int table_count;
331 
332         /* DMA router */
333         struct dma_router *router;
334         void *route_data;
335 
336         void *private;
337 };
338 
339 /**
340  * struct dma_chan_dev - relate sysfs device node to backing channel device
341  * @chan: driver channel device
342  * @device: sysfs device
343  * @dev_id: parent dma_device dev_id
344  */
345 struct dma_chan_dev {
346         struct dma_chan *chan;
347         struct device device;
348         int dev_id;
349 };
350 
351 /**
352  * enum dma_slave_buswidth - defines bus width of the DMA slave
353  * device, source or target buses
354  */
355 enum dma_slave_buswidth {
356         DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
357         DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
358         DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
359         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
360         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
361         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
362         DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
363         DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
364         DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
365 };
366 
367 /**
368  * struct dma_slave_config - dma slave channel runtime config
369  * @direction: whether the data shall go in or out on this slave
370  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
371  * legal values. DEPRECATED, drivers should use the direction argument
372  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
373  * the dir field in the dma_interleaved_template structure.
374  * @src_addr: this is the physical address where DMA slave data
375  * should be read (RX), if the source is memory this argument is
376  * ignored.
377  * @dst_addr: this is the physical address where DMA slave data
378  * should be written (TX), if the source is memory this argument
379  * is ignored.
380  * @src_addr_width: this is the width in bytes of the source (RX)
381  * register where DMA data shall be read. If the source
382  * is memory this may be ignored depending on architecture.
383  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
384  * @dst_addr_width: same as src_addr_width but for destination
385  * target (TX) mutatis mutandis.
386  * @src_maxburst: the maximum number of words (note: words, as in
387  * units of the src_addr_width member, not bytes) that can be sent
388  * in one burst to the device. Typically something like half the
389  * FIFO depth on I/O peripherals so you don't overflow it. This
390  * may or may not be applicable on memory sources.
391  * @dst_maxburst: same as src_maxburst but for destination target
392  * mutatis mutandis.
393  * @src_port_window_size: The length of the register area in words the data need
394  * to be accessed on the device side. It is only used for devices which is using
395  * an area instead of a single register to receive the data. Typically the DMA
396  * loops in this area in order to transfer the data.
397  * @dst_port_window_size: same as src_port_window_size but for the destination
398  * port.
399  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
400  * with 'true' if peripheral should be flow controller. Direction will be
401  * selected at Runtime.
402  * @slave_id: Slave requester id. Only valid for slave channels. The dma
403  * slave peripheral will have unique id as dma requester which need to be
404  * pass as slave config.
405  *
406  * This struct is passed in as configuration data to a DMA engine
407  * in order to set up a certain channel for DMA transport at runtime.
408  * The DMA device/engine has to provide support for an additional
409  * callback in the dma_device structure, device_config and this struct
410  * will then be passed in as an argument to the function.
411  *
412  * The rationale for adding configuration information to this struct is as
413  * follows: if it is likely that more than one DMA slave controllers in
414  * the world will support the configuration option, then make it generic.
415  * If not: if it is fixed so that it be sent in static from the platform
416  * data, then prefer to do that.
417  */
418 struct dma_slave_config {
419         enum dma_transfer_direction direction;
420         phys_addr_t src_addr;
421         phys_addr_t dst_addr;
422         enum dma_slave_buswidth src_addr_width;
423         enum dma_slave_buswidth dst_addr_width;
424         u32 src_maxburst;
425         u32 dst_maxburst;
426         u32 src_port_window_size;
427         u32 dst_port_window_size;
428         bool device_fc;
429         unsigned int slave_id;
430 };
431 
432 /**
433  * enum dma_residue_granularity - Granularity of the reported transfer residue
434  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
435  *  DMA channel is only able to tell whether a descriptor has been completed or
436  *  not, which means residue reporting is not supported by this channel. The
437  *  residue field of the dma_tx_state field will always be 0.
438  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
439  *  completed segment of the transfer (For cyclic transfers this is after each
440  *  period). This is typically implemented by having the hardware generate an
441  *  interrupt after each transferred segment and then the drivers updates the
442  *  outstanding residue by the size of the segment. Another possibility is if
443  *  the hardware supports scatter-gather and the segment descriptor has a field
444  *  which gets set after the segment has been completed. The driver then counts
445  *  the number of segments without the flag set to compute the residue.
446  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
447  *  burst. This is typically only supported if the hardware has a progress
448  *  register of some sort (E.g. a register with the current read/write address
449  *  or a register with the amount of bursts/beats/bytes that have been
450  *  transferred or still need to be transferred).
451  */
452 enum dma_residue_granularity {
453         DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
454         DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
455         DMA_RESIDUE_GRANULARITY_BURST = 2,
456 };
457 
458 /**
459  * struct dma_slave_caps - expose capabilities of a slave channel only
460  * @src_addr_widths: bit mask of src addr widths the channel supports.
461  *      Width is specified in bytes, e.g. for a channel supporting
462  *      a width of 4 the mask should have BIT(4) set.
463  * @dst_addr_widths: bit mask of dst addr widths the channel supports
464  * @directions: bit mask of slave directions the channel supports.
465  *      Since the enum dma_transfer_direction is not defined as bit flag for
466  *      each type, the dma controller should set BIT(<TYPE>) and same
467  *      should be checked by controller as well
468  * @max_burst: max burst capability per-transfer
469  * @cmd_pause: true, if pause is supported (i.e. for reading residue or
470  *             for resume later)
471  * @cmd_resume: true, if resume is supported
472  * @cmd_terminate: true, if terminate cmd is supported
473  * @residue_granularity: granularity of the reported transfer residue
474  * @descriptor_reuse: if a descriptor can be reused by client and
475  * resubmitted multiple times
476  */
477 struct dma_slave_caps {
478         u32 src_addr_widths;
479         u32 dst_addr_widths;
480         u32 directions;
481         u32 max_burst;
482         bool cmd_pause;
483         bool cmd_resume;
484         bool cmd_terminate;
485         enum dma_residue_granularity residue_granularity;
486         bool descriptor_reuse;
487 };
488 
489 static inline const char *dma_chan_name(struct dma_chan *chan)
490 {
491         return dev_name(&chan->dev->device);
492 }
493 
494 void dma_chan_cleanup(struct kref *kref);
495 
496 /**
497  * typedef dma_filter_fn - callback filter for dma_request_channel
498  * @chan: channel to be reviewed
499  * @filter_param: opaque parameter passed through dma_request_channel
500  *
501  * When this optional parameter is specified in a call to dma_request_channel a
502  * suitable channel is passed to this routine for further dispositioning before
503  * being returned.  Where 'suitable' indicates a non-busy channel that
504  * satisfies the given capability mask.  It returns 'true' to indicate that the
505  * channel is suitable.
506  */
507 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
508 
509 typedef void (*dma_async_tx_callback)(void *dma_async_param);
510 
511 enum dmaengine_tx_result {
512         DMA_TRANS_NOERROR = 0,          /* SUCCESS */
513         DMA_TRANS_READ_FAILED,          /* Source DMA read failed */
514         DMA_TRANS_WRITE_FAILED,         /* Destination DMA write failed */
515         DMA_TRANS_ABORTED,              /* Op never submitted / aborted */
516 };
517 
518 struct dmaengine_result {
519         enum dmaengine_tx_result result;
520         u32 residue;
521 };
522 
523 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
524                                 const struct dmaengine_result *result);
525 
526 struct dmaengine_unmap_data {
527 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
528         u16 map_cnt;
529 #else
530         u8 map_cnt;
531 #endif
532         u8 to_cnt;
533         u8 from_cnt;
534         u8 bidi_cnt;
535         struct device *dev;
536         struct kref kref;
537         size_t len;
538         dma_addr_t addr[];
539 };
540 
541 struct dma_async_tx_descriptor;
542 
543 struct dma_descriptor_metadata_ops {
544         int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
545                       size_t len);
546 
547         void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
548                          size_t *payload_len, size_t *max_len);
549         int (*set_len)(struct dma_async_tx_descriptor *desc,
550                        size_t payload_len);
551 };
552 
553 /**
554  * struct dma_async_tx_descriptor - async transaction descriptor
555  * ---dma generic offload fields---
556  * @cookie: tracking cookie for this transaction, set to -EBUSY if
557  *      this tx is sitting on a dependency list
558  * @flags: flags to augment operation preparation, control completion, and
559  *      communicate status
560  * @phys: physical address of the descriptor
561  * @chan: target channel for this operation
562  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
563  * descriptor pending. To be pushed on .issue_pending() call
564  * @callback: routine to call after this operation is complete
565  * @callback_param: general parameter to pass to the callback routine
566  * @desc_metadata_mode: core managed metadata mode to protect mixed use of
567  *      DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
568  *      DESC_METADATA_NONE
569  * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
570  *      DMA driver if metadata mode is supported with the descriptor
571  * ---async_tx api specific fields---
572  * @next: at completion submit this descriptor
573  * @parent: pointer to the next level up in the dependency chain
574  * @lock: protect the parent and next pointers
575  */
576 struct dma_async_tx_descriptor {
577         dma_cookie_t cookie;
578         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
579         dma_addr_t phys;
580         struct dma_chan *chan;
581         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
582         int (*desc_free)(struct dma_async_tx_descriptor *tx);
583         dma_async_tx_callback callback;
584         dma_async_tx_callback_result callback_result;
585         void *callback_param;
586         struct dmaengine_unmap_data *unmap;
587         enum dma_desc_metadata_mode desc_metadata_mode;
588         struct dma_descriptor_metadata_ops *metadata_ops;
589 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
590         struct dma_async_tx_descriptor *next;
591         struct dma_async_tx_descriptor *parent;
592         spinlock_t lock;
593 #endif
594 };
595 
596 #ifdef CONFIG_DMA_ENGINE
597 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
598                                  struct dmaengine_unmap_data *unmap)
599 {
600         kref_get(&unmap->kref);
601         tx->unmap = unmap;
602 }
603 
604 struct dmaengine_unmap_data *
605 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
606 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
607 #else
608 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
609                                  struct dmaengine_unmap_data *unmap)
610 {
611 }
612 static inline struct dmaengine_unmap_data *
613 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
614 {
615         return NULL;
616 }
617 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
618 {
619 }
620 #endif
621 
622 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
623 {
624         if (!tx->unmap)
625                 return;
626 
627         dmaengine_unmap_put(tx->unmap);
628         tx->unmap = NULL;
629 }
630 
631 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
632 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
633 {
634 }
635 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
636 {
637 }
638 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
639 {
640         BUG();
641 }
642 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
643 {
644 }
645 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
646 {
647 }
648 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
649 {
650         return NULL;
651 }
652 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
653 {
654         return NULL;
655 }
656 
657 #else
658 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
659 {
660         spin_lock_bh(&txd->lock);
661 }
662 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
663 {
664         spin_unlock_bh(&txd->lock);
665 }
666 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
667 {
668         txd->next = next;
669         next->parent = txd;
670 }
671 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
672 {
673         txd->parent = NULL;
674 }
675 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
676 {
677         txd->next = NULL;
678 }
679 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
680 {
681         return txd->parent;
682 }
683 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
684 {
685         return txd->next;
686 }
687 #endif
688 
689 /**
690  * struct dma_tx_state - filled in to report the status of
691  * a transfer.
692  * @last: last completed DMA cookie
693  * @used: last issued DMA cookie (i.e. the one in progress)
694  * @residue: the remaining number of bytes left to transmit
695  *      on the selected transfer for states DMA_IN_PROGRESS and
696  *      DMA_PAUSED if this is implemented in the driver, else 0
697  * @in_flight_bytes: amount of data in bytes cached by the DMA.
698  */
699 struct dma_tx_state {
700         dma_cookie_t last;
701         dma_cookie_t used;
702         u32 residue;
703         u32 in_flight_bytes;
704 };
705 
706 /**
707  * enum dmaengine_alignment - defines alignment of the DMA async tx
708  * buffers
709  */
710 enum dmaengine_alignment {
711         DMAENGINE_ALIGN_1_BYTE = 0,
712         DMAENGINE_ALIGN_2_BYTES = 1,
713         DMAENGINE_ALIGN_4_BYTES = 2,
714         DMAENGINE_ALIGN_8_BYTES = 3,
715         DMAENGINE_ALIGN_16_BYTES = 4,
716         DMAENGINE_ALIGN_32_BYTES = 5,
717         DMAENGINE_ALIGN_64_BYTES = 6,
718 };
719 
720 /**
721  * struct dma_slave_map - associates slave device and it's slave channel with
722  * parameter to be used by a filter function
723  * @devname: name of the device
724  * @slave: slave channel name
725  * @param: opaque parameter to pass to struct dma_filter.fn
726  */
727 struct dma_slave_map {
728         const char *devname;
729         const char *slave;
730         void *param;
731 };
732 
733 /**
734  * struct dma_filter - information for slave device/channel to filter_fn/param
735  * mapping
736  * @fn: filter function callback
737  * @mapcnt: number of slave device/channel in the map
738  * @map: array of channel to filter mapping data
739  */
740 struct dma_filter {
741         dma_filter_fn fn;
742         int mapcnt;
743         const struct dma_slave_map *map;
744 };
745 
746 /**
747  * struct dma_device - info on the entity supplying DMA services
748  * @chancnt: how many DMA channels are supported
749  * @privatecnt: how many DMA channels are requested by dma_request_channel
750  * @channels: the list of struct dma_chan
751  * @global_node: list_head for global dma_device_list
752  * @filter: information for device/slave to filter function/param mapping
753  * @cap_mask: one or more dma_capability flags
754  * @desc_metadata_modes: supported metadata modes by the DMA device
755  * @max_xor: maximum number of xor sources, 0 if no capability
756  * @max_pq: maximum number of PQ sources and PQ-continue capability
757  * @copy_align: alignment shift for memcpy operations
758  * @xor_align: alignment shift for xor operations
759  * @pq_align: alignment shift for pq operations
760  * @fill_align: alignment shift for memset operations
761  * @dev_id: unique device ID
762  * @dev: struct device reference for dma mapping api
763  * @owner: owner module (automatically set based on the provided dev)
764  * @src_addr_widths: bit mask of src addr widths the device supports
765  *      Width is specified in bytes, e.g. for a device supporting
766  *      a width of 4 the mask should have BIT(4) set.
767  * @dst_addr_widths: bit mask of dst addr widths the device supports
768  * @directions: bit mask of slave directions the device supports.
769  *      Since the enum dma_transfer_direction is not defined as bit flag for
770  *      each type, the dma controller should set BIT(<TYPE>) and same
771  *      should be checked by controller as well
772  * @max_burst: max burst capability per-transfer
773  * @residue_granularity: granularity of the transfer residue reported
774  *      by tx_status
775  * @device_alloc_chan_resources: allocate resources and return the
776  *      number of allocated descriptors
777  * @device_free_chan_resources: release DMA channel's resources
778  * @device_prep_dma_memcpy: prepares a memcpy operation
779  * @device_prep_dma_xor: prepares a xor operation
780  * @device_prep_dma_xor_val: prepares a xor validation operation
781  * @device_prep_dma_pq: prepares a pq operation
782  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
783  * @device_prep_dma_memset: prepares a memset operation
784  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
785  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
786  * @device_prep_slave_sg: prepares a slave dma operation
787  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
788  *      The function takes a buffer of size buf_len. The callback function will
789  *      be called after period_len bytes have been transferred.
790  * @device_prep_interleaved_dma: Transfer expression in a generic way.
791  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
792  * @device_config: Pushes a new configuration to a channel, return 0 or an error
793  *      code
794  * @device_pause: Pauses any transfer happening on a channel. Returns
795  *      0 or an error code
796  * @device_resume: Resumes any transfer on a channel previously
797  *      paused. Returns 0 or an error code
798  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
799  *      or an error code
800  * @device_synchronize: Synchronizes the termination of a transfers to the
801  *  current context.
802  * @device_tx_status: poll for transaction completion, the optional
803  *      txstate parameter can be supplied with a pointer to get a
804  *      struct with auxiliary transfer status information, otherwise the call
805  *      will just return a simple status code
806  * @device_issue_pending: push pending transactions to hardware
807  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
808  * @device_release: called sometime atfer dma_async_device_unregister() is
809  *     called and there are no further references to this structure. This
810  *     must be implemented to free resources however many existing drivers
811  *     do not and are therefore not safe to unbind while in use.
812  * @dbg_summary_show: optional routine to show contents in debugfs; default code
813  *     will be used when this is omitted, but custom code can show extra,
814  *     controller specific information.
815  */
816 struct dma_device {
817         struct kref ref;
818         unsigned int chancnt;
819         unsigned int privatecnt;
820         struct list_head channels;
821         struct list_head global_node;
822         struct dma_filter filter;
823         dma_cap_mask_t  cap_mask;
824         enum dma_desc_metadata_mode desc_metadata_modes;
825         unsigned short max_xor;
826         unsigned short max_pq;
827         enum dmaengine_alignment copy_align;
828         enum dmaengine_alignment xor_align;
829         enum dmaengine_alignment pq_align;
830         enum dmaengine_alignment fill_align;
831         #define DMA_HAS_PQ_CONTINUE (1 << 15)
832 
833         int dev_id;
834         struct device *dev;
835         struct module *owner;
836         struct ida chan_ida;
837         struct mutex chan_mutex;        /* to protect chan_ida */
838 
839         u32 src_addr_widths;
840         u32 dst_addr_widths;
841         u32 directions;
842         u32 max_burst;
843         bool descriptor_reuse;
844         enum dma_residue_granularity residue_granularity;
845 
846         int (*device_alloc_chan_resources)(struct dma_chan *chan);
847         void (*device_free_chan_resources)(struct dma_chan *chan);
848 
849         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
850                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
851                 size_t len, unsigned long flags);
852         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
853                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
854                 unsigned int src_cnt, size_t len, unsigned long flags);
855         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
856                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
857                 size_t len, enum sum_check_flags *result, unsigned long flags);
858         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
859                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
860                 unsigned int src_cnt, const unsigned char *scf,
861                 size_t len, unsigned long flags);
862         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
863                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
864                 unsigned int src_cnt, const unsigned char *scf, size_t len,
865                 enum sum_check_flags *pqres, unsigned long flags);
866         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
867                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
868                 unsigned long flags);
869         struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
870                 struct dma_chan *chan, struct scatterlist *sg,
871                 unsigned int nents, int value, unsigned long flags);
872         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
873                 struct dma_chan *chan, unsigned long flags);
874 
875         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
876                 struct dma_chan *chan, struct scatterlist *sgl,
877                 unsigned int sg_len, enum dma_transfer_direction direction,
878                 unsigned long flags, void *context);
879         struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
880                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
881                 size_t period_len, enum dma_transfer_direction direction,
882                 unsigned long flags);
883         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
884                 struct dma_chan *chan, struct dma_interleaved_template *xt,
885                 unsigned long flags);
886         struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
887                 struct dma_chan *chan, dma_addr_t dst, u64 data,
888                 unsigned long flags);
889 
890         int (*device_config)(struct dma_chan *chan,
891                              struct dma_slave_config *config);
892         int (*device_pause)(struct dma_chan *chan);
893         int (*device_resume)(struct dma_chan *chan);
894         int (*device_terminate_all)(struct dma_chan *chan);
895         void (*device_synchronize)(struct dma_chan *chan);
896 
897         enum dma_status (*device_tx_status)(struct dma_chan *chan,
898                                             dma_cookie_t cookie,
899                                             struct dma_tx_state *txstate);
900         void (*device_issue_pending)(struct dma_chan *chan);
901         void (*device_release)(struct dma_device *dev);
902         /* debugfs support */
903 #ifdef CONFIG_DEBUG_FS
904         void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
905         struct dentry *dbg_dev_root;
906 #endif
907 };
908 
909 static inline int dmaengine_slave_config(struct dma_chan *chan,
910                                           struct dma_slave_config *config)
911 {
912         if (chan->device->device_config)
913                 return chan->device->device_config(chan, config);
914 
915         return -ENOSYS;
916 }
917 
918 static inline bool is_slave_direction(enum dma_transfer_direction direction)
919 {
920         return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
921 }
922 
923 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
924         struct dma_chan *chan, dma_addr_t buf, size_t len,
925         enum dma_transfer_direction dir, unsigned long flags)
926 {
927         struct scatterlist sg;
928         sg_init_table(&sg, 1);
929         sg_dma_address(&sg) = buf;
930         sg_dma_len(&sg) = len;
931 
932         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
933                 return NULL;
934 
935         return chan->device->device_prep_slave_sg(chan, &sg, 1,
936                                                   dir, flags, NULL);
937 }
938 
939 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
940         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
941         enum dma_transfer_direction dir, unsigned long flags)
942 {
943         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
944                 return NULL;
945 
946         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
947                                                   dir, flags, NULL);
948 }
949 
950 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
951 struct rio_dma_ext;
952 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
953         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
954         enum dma_transfer_direction dir, unsigned long flags,
955         struct rio_dma_ext *rio_ext)
956 {
957         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
958                 return NULL;
959 
960         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
961                                                   dir, flags, rio_ext);
962 }
963 #endif
964 
965 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
966                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
967                 size_t period_len, enum dma_transfer_direction dir,
968                 unsigned long flags)
969 {
970         if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
971                 return NULL;
972 
973         return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
974                                                 period_len, dir, flags);
975 }
976 
977 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
978                 struct dma_chan *chan, struct dma_interleaved_template *xt,
979                 unsigned long flags)
980 {
981         if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
982                 return NULL;
983 
984         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
985 }
986 
987 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
988                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
989                 unsigned long flags)
990 {
991         if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
992                 return NULL;
993 
994         return chan->device->device_prep_dma_memset(chan, dest, value,
995                                                     len, flags);
996 }
997 
998 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
999                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1000                 size_t len, unsigned long flags)
1001 {
1002         if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
1003                 return NULL;
1004 
1005         return chan->device->device_prep_dma_memcpy(chan, dest, src,
1006                                                     len, flags);
1007 }
1008 
1009 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
1010                 enum dma_desc_metadata_mode mode)
1011 {
1012         if (!chan)
1013                 return false;
1014 
1015         return !!(chan->device->desc_metadata_modes & mode);
1016 }
1017 
1018 #ifdef CONFIG_DMA_ENGINE
1019 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
1020                                    void *data, size_t len);
1021 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
1022                                       size_t *payload_len, size_t *max_len);
1023 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
1024                                     size_t payload_len);
1025 #else /* CONFIG_DMA_ENGINE */
1026 static inline int dmaengine_desc_attach_metadata(
1027                 struct dma_async_tx_descriptor *desc, void *data, size_t len)
1028 {
1029         return -EINVAL;
1030 }
1031 static inline void *dmaengine_desc_get_metadata_ptr(
1032                 struct dma_async_tx_descriptor *desc, size_t *payload_len,
1033                 size_t *max_len)
1034 {
1035         return NULL;
1036 }
1037 static inline int dmaengine_desc_set_metadata_len(
1038                 struct dma_async_tx_descriptor *desc, size_t payload_len)
1039 {
1040         return -EINVAL;
1041 }
1042 #endif /* CONFIG_DMA_ENGINE */
1043 
1044 /**
1045  * dmaengine_terminate_all() - Terminate all active DMA transfers
1046  * @chan: The channel for which to terminate the transfers
1047  *
1048  * This function is DEPRECATED use either dmaengine_terminate_sync() or
1049  * dmaengine_terminate_async() instead.
1050  */
1051 static inline int dmaengine_terminate_all(struct dma_chan *chan)
1052 {
1053         if (chan->device->device_terminate_all)
1054                 return chan->device->device_terminate_all(chan);
1055 
1056         return -ENOSYS;
1057 }
1058 
1059 /**
1060  * dmaengine_terminate_async() - Terminate all active DMA transfers
1061  * @chan: The channel for which to terminate the transfers
1062  *
1063  * Calling this function will terminate all active and pending descriptors
1064  * that have previously been submitted to the channel. It is not guaranteed
1065  * though that the transfer for the active descriptor has stopped when the
1066  * function returns. Furthermore it is possible the complete callback of a
1067  * submitted transfer is still running when this function returns.
1068  *
1069  * dmaengine_synchronize() needs to be called before it is safe to free
1070  * any memory that is accessed by previously submitted descriptors or before
1071  * freeing any resources accessed from within the completion callback of any
1072  * previously submitted descriptors.
1073  *
1074  * This function can be called from atomic context as well as from within a
1075  * complete callback of a descriptor submitted on the same channel.
1076  *
1077  * If none of the two conditions above apply consider using
1078  * dmaengine_terminate_sync() instead.
1079  */
1080 static inline int dmaengine_terminate_async(struct dma_chan *chan)
1081 {
1082         if (chan->device->device_terminate_all)
1083                 return chan->device->device_terminate_all(chan);
1084 
1085         return -EINVAL;
1086 }
1087 
1088 /**
1089  * dmaengine_synchronize() - Synchronize DMA channel termination
1090  * @chan: The channel to synchronize
1091  *
1092  * Synchronizes to the DMA channel termination to the current context. When this
1093  * function returns it is guaranteed that all transfers for previously issued
1094  * descriptors have stopped and it is safe to free the memory associated
1095  * with them. Furthermore it is guaranteed that all complete callback functions
1096  * for a previously submitted descriptor have finished running and it is safe to
1097  * free resources accessed from within the complete callbacks.
1098  *
1099  * The behavior of this function is undefined if dma_async_issue_pending() has
1100  * been called between dmaengine_terminate_async() and this function.
1101  *
1102  * This function must only be called from non-atomic context and must not be
1103  * called from within a complete callback of a descriptor submitted on the same
1104  * channel.
1105  */
1106 static inline void dmaengine_synchronize(struct dma_chan *chan)
1107 {
1108         might_sleep();
1109 
1110         if (chan->device->device_synchronize)
1111                 chan->device->device_synchronize(chan);
1112 }
1113 
1114 /**
1115  * dmaengine_terminate_sync() - Terminate all active DMA transfers
1116  * @chan: The channel for which to terminate the transfers
1117  *
1118  * Calling this function will terminate all active and pending transfers
1119  * that have previously been submitted to the channel. It is similar to
1120  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1121  * stopped and that all complete callbacks have finished running when the
1122  * function returns.
1123  *
1124  * This function must only be called from non-atomic context and must not be
1125  * called from within a complete callback of a descriptor submitted on the same
1126  * channel.
1127  */
1128 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1129 {
1130         int ret;
1131 
1132         ret = dmaengine_terminate_async(chan);
1133         if (ret)
1134                 return ret;
1135 
1136         dmaengine_synchronize(chan);
1137 
1138         return 0;
1139 }
1140 
1141 static inline int dmaengine_pause(struct dma_chan *chan)
1142 {
1143         if (chan->device->device_pause)
1144                 return chan->device->device_pause(chan);
1145 
1146         return -ENOSYS;
1147 }
1148 
1149 static inline int dmaengine_resume(struct dma_chan *chan)
1150 {
1151         if (chan->device->device_resume)
1152                 return chan->device->device_resume(chan);
1153 
1154         return -ENOSYS;
1155 }
1156 
1157 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1158         dma_cookie_t cookie, struct dma_tx_state *state)
1159 {
1160         return chan->device->device_tx_status(chan, cookie, state);
1161 }
1162 
1163 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1164 {
1165         return desc->tx_submit(desc);
1166 }
1167 
1168 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1169                                          size_t off1, size_t off2, size_t len)
1170 {
1171         return !(((1 << align) - 1) & (off1 | off2 | len));
1172 }
1173 
1174 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1175                                        size_t off2, size_t len)
1176 {
1177         return dmaengine_check_align(dev->copy_align, off1, off2, len);
1178 }
1179 
1180 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1181                                       size_t off2, size_t len)
1182 {
1183         return dmaengine_check_align(dev->xor_align, off1, off2, len);
1184 }
1185 
1186 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1187                                      size_t off2, size_t len)
1188 {
1189         return dmaengine_check_align(dev->pq_align, off1, off2, len);
1190 }
1191 
1192 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1193                                        size_t off2, size_t len)
1194 {
1195         return dmaengine_check_align(dev->fill_align, off1, off2, len);
1196 }
1197 
1198 static inline void
1199 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1200 {
1201         dma->max_pq = maxpq;
1202         if (has_pq_continue)
1203                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1204 }
1205 
1206 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1207 {
1208         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1209 }
1210 
1211 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1212 {
1213         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1214 
1215         return (flags & mask) == mask;
1216 }
1217 
1218 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1219 {
1220         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1221 }
1222 
1223 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1224 {
1225         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1226 }
1227 
1228 /* dma_maxpq - reduce maxpq in the face of continued operations
1229  * @dma - dma device with PQ capability
1230  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1231  *
1232  * When an engine does not support native continuation we need 3 extra
1233  * source slots to reuse P and Q with the following coefficients:
1234  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1235  * 2/ {01} * Q : use Q to continue Q' calculation
1236  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1237  *
1238  * In the case where P is disabled we only need 1 extra source:
1239  * 1/ {01} * Q : use Q to continue Q' calculation
1240  */
1241 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1242 {
1243         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1244                 return dma_dev_to_maxpq(dma);
1245         if (dmaf_p_disabled_continue(flags))
1246                 return dma_dev_to_maxpq(dma) - 1;
1247         if (dmaf_continue(flags))
1248                 return dma_dev_to_maxpq(dma) - 3;
1249         BUG();
1250 }
1251 
1252 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1253                                       size_t dir_icg)
1254 {
1255         if (inc) {
1256                 if (dir_icg)
1257                         return dir_icg;
1258                 if (sgl)
1259                         return icg;
1260         }
1261 
1262         return 0;
1263 }
1264 
1265 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1266                                            struct data_chunk *chunk)
1267 {
1268         return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1269                                  chunk->icg, chunk->dst_icg);
1270 }
1271 
1272 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1273                                            struct data_chunk *chunk)
1274 {
1275         return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1276                                  chunk->icg, chunk->src_icg);
1277 }
1278 
1279 /* --- public DMA engine API --- */
1280 
1281 #ifdef CONFIG_DMA_ENGINE
1282 void dmaengine_get(void);
1283 void dmaengine_put(void);
1284 #else
1285 static inline void dmaengine_get(void)
1286 {
1287 }
1288 static inline void dmaengine_put(void)
1289 {
1290 }
1291 #endif
1292 
1293 #ifdef CONFIG_ASYNC_TX_DMA
1294 #define async_dmaengine_get()   dmaengine_get()
1295 #define async_dmaengine_put()   dmaengine_put()
1296 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1297 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1298 #else
1299 #define async_dma_find_channel(type) dma_find_channel(type)
1300 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1301 #else
1302 static inline void async_dmaengine_get(void)
1303 {
1304 }
1305 static inline void async_dmaengine_put(void)
1306 {
1307 }
1308 static inline struct dma_chan *
1309 async_dma_find_channel(enum dma_transaction_type type)
1310 {
1311         return NULL;
1312 }
1313 #endif /* CONFIG_ASYNC_TX_DMA */
1314 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1315                                   struct dma_chan *chan);
1316 
1317 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1318 {
1319         tx->flags |= DMA_CTRL_ACK;
1320 }
1321 
1322 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1323 {
1324         tx->flags &= ~DMA_CTRL_ACK;
1325 }
1326 
1327 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1328 {
1329         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1330 }
1331 
1332 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1333 static inline void
1334 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1335 {
1336         set_bit(tx_type, dstp->bits);
1337 }
1338 
1339 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1340 static inline void
1341 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1342 {
1343         clear_bit(tx_type, dstp->bits);
1344 }
1345 
1346 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1347 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1348 {
1349         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1350 }
1351 
1352 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1353 static inline int
1354 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1355 {
1356         return test_bit(tx_type, srcp->bits);
1357 }
1358 
1359 #define for_each_dma_cap_mask(cap, mask) \
1360         for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1361 
1362 /**
1363  * dma_async_issue_pending - flush pending transactions to HW
1364  * @chan: target DMA channel
1365  *
1366  * This allows drivers to push copies to HW in batches,
1367  * reducing MMIO writes where possible.
1368  */
1369 static inline void dma_async_issue_pending(struct dma_chan *chan)
1370 {
1371         chan->device->device_issue_pending(chan);
1372 }
1373 
1374 /**
1375  * dma_async_is_tx_complete - poll for transaction completion
1376  * @chan: DMA channel
1377  * @cookie: transaction identifier to check status of
1378  * @last: returns last completed cookie, can be NULL
1379  * @used: returns last issued cookie, can be NULL
1380  *
1381  * If @last and @used are passed in, upon return they reflect the driver
1382  * internal state and can be used with dma_async_is_complete() to check
1383  * the status of multiple cookies without re-checking hardware state.
1384  */
1385 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1386         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1387 {
1388         struct dma_tx_state state;
1389         enum dma_status status;
1390 
1391         status = chan->device->device_tx_status(chan, cookie, &state);
1392         if (last)
1393                 *last = state.last;
1394         if (used)
1395                 *used = state.used;
1396         return status;
1397 }
1398 
1399 /**
1400  * dma_async_is_complete - test a cookie against chan state
1401  * @cookie: transaction identifier to test status of
1402  * @last_complete: last know completed transaction
1403  * @last_used: last cookie value handed out
1404  *
1405  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1406  * the test logic is separated for lightweight testing of multiple cookies
1407  */
1408 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1409                         dma_cookie_t last_complete, dma_cookie_t last_used)
1410 {
1411         if (last_complete <= last_used) {
1412                 if ((cookie <= last_complete) || (cookie > last_used))
1413                         return DMA_COMPLETE;
1414         } else {
1415                 if ((cookie <= last_complete) && (cookie > last_used))
1416                         return DMA_COMPLETE;
1417         }
1418         return DMA_IN_PROGRESS;
1419 }
1420 
1421 static inline void
1422 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1423 {
1424         if (!st)
1425                 return;
1426 
1427         st->last = last;
1428         st->used = used;
1429         st->residue = residue;
1430 }
1431 
1432 #ifdef CONFIG_DMA_ENGINE
1433 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1434 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1435 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1436 void dma_issue_pending_all(void);
1437 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1438                                        dma_filter_fn fn, void *fn_param,
1439                                        struct device_node *np);
1440 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1441 
1442 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1443 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1444 
1445 void dma_release_channel(struct dma_chan *chan);
1446 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1447 #else
1448 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1449 {
1450         return NULL;
1451 }
1452 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1453 {
1454         return DMA_COMPLETE;
1455 }
1456 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1457 {
1458         return DMA_COMPLETE;
1459 }
1460 static inline void dma_issue_pending_all(void)
1461 {
1462 }
1463 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1464                                                      dma_filter_fn fn,
1465                                                      void *fn_param,
1466                                                      struct device_node *np)
1467 {
1468         return NULL;
1469 }
1470 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1471                                                          const char *name)
1472 {
1473         return NULL;
1474 }
1475 static inline struct dma_chan *dma_request_chan(struct device *dev,
1476                                                 const char *name)
1477 {
1478         return ERR_PTR(-ENODEV);
1479 }
1480 static inline struct dma_chan *dma_request_chan_by_mask(
1481                                                 const dma_cap_mask_t *mask)
1482 {
1483         return ERR_PTR(-ENODEV);
1484 }
1485 static inline void dma_release_channel(struct dma_chan *chan)
1486 {
1487 }
1488 static inline int dma_get_slave_caps(struct dma_chan *chan,
1489                                      struct dma_slave_caps *caps)
1490 {
1491         return -ENXIO;
1492 }
1493 #endif
1494 
1495 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1496 
1497 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1498 {
1499         struct dma_slave_caps caps;
1500         int ret;
1501 
1502         ret = dma_get_slave_caps(tx->chan, &caps);
1503         if (ret)
1504                 return ret;
1505 
1506         if (!caps.descriptor_reuse)
1507                 return -EPERM;
1508 
1509         tx->flags |= DMA_CTRL_REUSE;
1510         return 0;
1511 }
1512 
1513 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1514 {
1515         tx->flags &= ~DMA_CTRL_REUSE;
1516 }
1517 
1518 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1519 {
1520         return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1521 }
1522 
1523 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1524 {
1525         /* this is supported for reusable desc, so check that */
1526         if (!dmaengine_desc_test_reuse(desc))
1527                 return -EPERM;
1528 
1529         return desc->desc_free(desc);
1530 }
1531 
1532 /* --- DMA device --- */
1533 
1534 int dma_async_device_register(struct dma_device *device);
1535 int dmaenginem_async_device_register(struct dma_device *device);
1536 void dma_async_device_unregister(struct dma_device *device);
1537 int dma_async_device_channel_register(struct dma_device *device,
1538                                       struct dma_chan *chan);
1539 void dma_async_device_channel_unregister(struct dma_device *device,
1540                                          struct dma_chan *chan);
1541 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1542 #define dma_request_channel(mask, x, y) \
1543         __dma_request_channel(&(mask), x, y, NULL)
1544 
1545 static inline struct dma_chan
1546 *dma_request_slave_channel_compat(const dma_cap_mask_t mask,
1547                                   dma_filter_fn fn, void *fn_param,
1548                                   struct device *dev, const char *name)
1549 {
1550         struct dma_chan *chan;
1551 
1552         chan = dma_request_slave_channel(dev, name);
1553         if (chan)
1554                 return chan;
1555 
1556         if (!fn || !fn_param)
1557                 return NULL;
1558 
1559         return __dma_request_channel(&mask, fn, fn_param, NULL);
1560 }
1561 
1562 static inline char *
1563 dmaengine_get_direction_text(enum dma_transfer_direction dir)
1564 {
1565         switch (dir) {
1566         case DMA_DEV_TO_MEM:
1567                 return "DEV_TO_MEM";
1568         case DMA_MEM_TO_DEV:
1569                 return "MEM_TO_DEV";
1570         case DMA_MEM_TO_MEM:
1571                 return "MEM_TO_MEM";
1572         case DMA_DEV_TO_DEV:
1573                 return "DEV_TO_DEV";
1574         default:
1575                 return "invalid";
1576         }
1577 }
1578 #endif /* DMAENGINE_H */
1579 

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