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TOMOYO Linux Cross Reference
Linux/include/linux/dmaengine.h

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  1 /*
  2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms of the GNU General Public License as published by the Free
  6  * Software Foundation; either version 2 of the License, or (at your option)
  7  * any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * The full GNU General Public License is included in this distribution in the
 15  * file called COPYING.
 16  */
 17 #ifndef LINUX_DMAENGINE_H
 18 #define LINUX_DMAENGINE_H
 19 
 20 #include <linux/device.h>
 21 #include <linux/err.h>
 22 #include <linux/uio.h>
 23 #include <linux/bug.h>
 24 #include <linux/scatterlist.h>
 25 #include <linux/bitmap.h>
 26 #include <linux/types.h>
 27 #include <asm/page.h>
 28 
 29 /**
 30  * typedef dma_cookie_t - an opaque DMA cookie
 31  *
 32  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 33  */
 34 typedef s32 dma_cookie_t;
 35 #define DMA_MIN_COOKIE  1
 36 
 37 static inline int dma_submit_error(dma_cookie_t cookie)
 38 {
 39         return cookie < 0 ? cookie : 0;
 40 }
 41 
 42 /**
 43  * enum dma_status - DMA transaction status
 44  * @DMA_COMPLETE: transaction completed
 45  * @DMA_IN_PROGRESS: transaction not yet processed
 46  * @DMA_PAUSED: transaction is paused
 47  * @DMA_ERROR: transaction failed
 48  */
 49 enum dma_status {
 50         DMA_COMPLETE,
 51         DMA_IN_PROGRESS,
 52         DMA_PAUSED,
 53         DMA_ERROR,
 54 };
 55 
 56 /**
 57  * enum dma_transaction_type - DMA transaction types/indexes
 58  *
 59  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 60  * automatically set as dma devices are registered.
 61  */
 62 enum dma_transaction_type {
 63         DMA_MEMCPY,
 64         DMA_XOR,
 65         DMA_PQ,
 66         DMA_XOR_VAL,
 67         DMA_PQ_VAL,
 68         DMA_MEMSET,
 69         DMA_MEMSET_SG,
 70         DMA_INTERRUPT,
 71         DMA_PRIVATE,
 72         DMA_ASYNC_TX,
 73         DMA_SLAVE,
 74         DMA_CYCLIC,
 75         DMA_INTERLEAVE,
 76 /* last transaction type for creation of the capabilities mask */
 77         DMA_TX_TYPE_END,
 78 };
 79 
 80 /**
 81  * enum dma_transfer_direction - dma transfer mode and direction indicator
 82  * @DMA_MEM_TO_MEM: Async/Memcpy mode
 83  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 84  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 85  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 86  */
 87 enum dma_transfer_direction {
 88         DMA_MEM_TO_MEM,
 89         DMA_MEM_TO_DEV,
 90         DMA_DEV_TO_MEM,
 91         DMA_DEV_TO_DEV,
 92         DMA_TRANS_NONE,
 93 };
 94 
 95 /**
 96  * Interleaved Transfer Request
 97  * ----------------------------
 98  * A chunk is collection of contiguous bytes to be transfered.
 99  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100  * ICGs may or maynot change between chunks.
101  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102  *  that when repeated an integral number of times, specifies the transfer.
103  * A transfer template is specification of a Frame, the number of times
104  *  it is to be repeated and other per-transfer attributes.
105  *
106  * Practically, a client driver would have ready a template for each
107  *  type of transfer it is going to need during its lifetime and
108  *  set only 'src_start' and 'dst_start' before submitting the requests.
109  *
110  *
111  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
112  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
113  *
114  *    ==  Chunk size
115  *    ... ICG
116  */
117 
118 /**
119  * struct data_chunk - Element of scatter-gather list that makes a frame.
120  * @size: Number of bytes to read from source.
121  *        size_dst := fn(op, size_src), so doesn't mean much for destination.
122  * @icg: Number of bytes to jump after last src/dst address of this
123  *       chunk and before first src/dst address for next chunk.
124  *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125  *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
126  * @dst_icg: Number of bytes to jump after last dst address of this
127  *       chunk and before the first dst address for next chunk.
128  *       Ignored if dst_inc is true and dst_sgl is false.
129  * @src_icg: Number of bytes to jump after last src address of this
130  *       chunk and before the first src address for next chunk.
131  *       Ignored if src_inc is true and src_sgl is false.
132  */
133 struct data_chunk {
134         size_t size;
135         size_t icg;
136         size_t dst_icg;
137         size_t src_icg;
138 };
139 
140 /**
141  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
142  *       and attributes.
143  * @src_start: Bus address of source for the first chunk.
144  * @dst_start: Bus address of destination for the first chunk.
145  * @dir: Specifies the type of Source and Destination.
146  * @src_inc: If the source address increments after reading from it.
147  * @dst_inc: If the destination address increments after writing to it.
148  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
149  *              Otherwise, source is read contiguously (icg ignored).
150  *              Ignored if src_inc is false.
151  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
152  *              Otherwise, destination is filled contiguously (icg ignored).
153  *              Ignored if dst_inc is false.
154  * @numf: Number of frames in this template.
155  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
156  * @sgl: Array of {chunk,icg} pairs that make up a frame.
157  */
158 struct dma_interleaved_template {
159         dma_addr_t src_start;
160         dma_addr_t dst_start;
161         enum dma_transfer_direction dir;
162         bool src_inc;
163         bool dst_inc;
164         bool src_sgl;
165         bool dst_sgl;
166         size_t numf;
167         size_t frame_size;
168         struct data_chunk sgl[0];
169 };
170 
171 /**
172  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
173  *  control completion, and communicate status.
174  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
175  *  this transaction
176  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
177  *  acknowledges receipt, i.e. has has a chance to establish any dependency
178  *  chains
179  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
180  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
181  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
182  *  sources that were the result of a previous operation, in the case of a PQ
183  *  operation it continues the calculation with new sources
184  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
185  *  on the result of this operation
186  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
187  *  cleared or freed
188  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
189  *  data and the descriptor should be in different format from normal
190  *  data descriptors.
191  */
192 enum dma_ctrl_flags {
193         DMA_PREP_INTERRUPT = (1 << 0),
194         DMA_CTRL_ACK = (1 << 1),
195         DMA_PREP_PQ_DISABLE_P = (1 << 2),
196         DMA_PREP_PQ_DISABLE_Q = (1 << 3),
197         DMA_PREP_CONTINUE = (1 << 4),
198         DMA_PREP_FENCE = (1 << 5),
199         DMA_CTRL_REUSE = (1 << 6),
200         DMA_PREP_CMD = (1 << 7),
201 };
202 
203 /**
204  * enum sum_check_bits - bit position of pq_check_flags
205  */
206 enum sum_check_bits {
207         SUM_CHECK_P = 0,
208         SUM_CHECK_Q = 1,
209 };
210 
211 /**
212  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
213  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
214  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
215  */
216 enum sum_check_flags {
217         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
218         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
219 };
220 
221 
222 /**
223  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
224  * See linux/cpumask.h
225  */
226 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
227 
228 /**
229  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
230  * @memcpy_count: transaction counter
231  * @bytes_transferred: byte counter
232  */
233 
234 struct dma_chan_percpu {
235         /* stats */
236         unsigned long memcpy_count;
237         unsigned long bytes_transferred;
238 };
239 
240 /**
241  * struct dma_router - DMA router structure
242  * @dev: pointer to the DMA router device
243  * @route_free: function to be called when the route can be disconnected
244  */
245 struct dma_router {
246         struct device *dev;
247         void (*route_free)(struct device *dev, void *route_data);
248 };
249 
250 /**
251  * struct dma_chan - devices supply DMA channels, clients use them
252  * @device: ptr to the dma device who supplies this channel, always !%NULL
253  * @cookie: last cookie value returned to client
254  * @completed_cookie: last completed cookie for this channel
255  * @chan_id: channel ID for sysfs
256  * @dev: class device for sysfs
257  * @device_node: used to add this to the device chan list
258  * @local: per-cpu pointer to a struct dma_chan_percpu
259  * @client_count: how many clients are using this channel
260  * @table_count: number of appearances in the mem-to-mem allocation table
261  * @router: pointer to the DMA router structure
262  * @route_data: channel specific data for the router
263  * @private: private data for certain client-channel associations
264  */
265 struct dma_chan {
266         struct dma_device *device;
267         dma_cookie_t cookie;
268         dma_cookie_t completed_cookie;
269 
270         /* sysfs */
271         int chan_id;
272         struct dma_chan_dev *dev;
273 
274         struct list_head device_node;
275         struct dma_chan_percpu __percpu *local;
276         int client_count;
277         int table_count;
278 
279         /* DMA router */
280         struct dma_router *router;
281         void *route_data;
282 
283         void *private;
284 };
285 
286 /**
287  * struct dma_chan_dev - relate sysfs device node to backing channel device
288  * @chan: driver channel device
289  * @device: sysfs device
290  * @dev_id: parent dma_device dev_id
291  * @idr_ref: reference count to gate release of dma_device dev_id
292  */
293 struct dma_chan_dev {
294         struct dma_chan *chan;
295         struct device device;
296         int dev_id;
297         atomic_t *idr_ref;
298 };
299 
300 /**
301  * enum dma_slave_buswidth - defines bus width of the DMA slave
302  * device, source or target buses
303  */
304 enum dma_slave_buswidth {
305         DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
306         DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
307         DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
308         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
309         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
310         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
311         DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
312         DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
313         DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
314 };
315 
316 /**
317  * struct dma_slave_config - dma slave channel runtime config
318  * @direction: whether the data shall go in or out on this slave
319  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
320  * legal values. DEPRECATED, drivers should use the direction argument
321  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
322  * the dir field in the dma_interleaved_template structure.
323  * @src_addr: this is the physical address where DMA slave data
324  * should be read (RX), if the source is memory this argument is
325  * ignored.
326  * @dst_addr: this is the physical address where DMA slave data
327  * should be written (TX), if the source is memory this argument
328  * is ignored.
329  * @src_addr_width: this is the width in bytes of the source (RX)
330  * register where DMA data shall be read. If the source
331  * is memory this may be ignored depending on architecture.
332  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
333  * @dst_addr_width: same as src_addr_width but for destination
334  * target (TX) mutatis mutandis.
335  * @src_maxburst: the maximum number of words (note: words, as in
336  * units of the src_addr_width member, not bytes) that can be sent
337  * in one burst to the device. Typically something like half the
338  * FIFO depth on I/O peripherals so you don't overflow it. This
339  * may or may not be applicable on memory sources.
340  * @dst_maxburst: same as src_maxburst but for destination target
341  * mutatis mutandis.
342  * @src_port_window_size: The length of the register area in words the data need
343  * to be accessed on the device side. It is only used for devices which is using
344  * an area instead of a single register to receive the data. Typically the DMA
345  * loops in this area in order to transfer the data.
346  * @dst_port_window_size: same as src_port_window_size but for the destination
347  * port.
348  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
349  * with 'true' if peripheral should be flow controller. Direction will be
350  * selected at Runtime.
351  * @slave_id: Slave requester id. Only valid for slave channels. The dma
352  * slave peripheral will have unique id as dma requester which need to be
353  * pass as slave config.
354  *
355  * This struct is passed in as configuration data to a DMA engine
356  * in order to set up a certain channel for DMA transport at runtime.
357  * The DMA device/engine has to provide support for an additional
358  * callback in the dma_device structure, device_config and this struct
359  * will then be passed in as an argument to the function.
360  *
361  * The rationale for adding configuration information to this struct is as
362  * follows: if it is likely that more than one DMA slave controllers in
363  * the world will support the configuration option, then make it generic.
364  * If not: if it is fixed so that it be sent in static from the platform
365  * data, then prefer to do that.
366  */
367 struct dma_slave_config {
368         enum dma_transfer_direction direction;
369         phys_addr_t src_addr;
370         phys_addr_t dst_addr;
371         enum dma_slave_buswidth src_addr_width;
372         enum dma_slave_buswidth dst_addr_width;
373         u32 src_maxburst;
374         u32 dst_maxburst;
375         u32 src_port_window_size;
376         u32 dst_port_window_size;
377         bool device_fc;
378         unsigned int slave_id;
379 };
380 
381 /**
382  * enum dma_residue_granularity - Granularity of the reported transfer residue
383  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
384  *  DMA channel is only able to tell whether a descriptor has been completed or
385  *  not, which means residue reporting is not supported by this channel. The
386  *  residue field of the dma_tx_state field will always be 0.
387  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
388  *  completed segment of the transfer (For cyclic transfers this is after each
389  *  period). This is typically implemented by having the hardware generate an
390  *  interrupt after each transferred segment and then the drivers updates the
391  *  outstanding residue by the size of the segment. Another possibility is if
392  *  the hardware supports scatter-gather and the segment descriptor has a field
393  *  which gets set after the segment has been completed. The driver then counts
394  *  the number of segments without the flag set to compute the residue.
395  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
396  *  burst. This is typically only supported if the hardware has a progress
397  *  register of some sort (E.g. a register with the current read/write address
398  *  or a register with the amount of bursts/beats/bytes that have been
399  *  transferred or still need to be transferred).
400  */
401 enum dma_residue_granularity {
402         DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
403         DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
404         DMA_RESIDUE_GRANULARITY_BURST = 2,
405 };
406 
407 /**
408  * struct dma_slave_caps - expose capabilities of a slave channel only
409  * @src_addr_widths: bit mask of src addr widths the channel supports.
410  *      Width is specified in bytes, e.g. for a channel supporting
411  *      a width of 4 the mask should have BIT(4) set.
412  * @dst_addr_widths: bit mask of dst addr widths the channel supports
413  * @directions: bit mask of slave directions the channel supports.
414  *      Since the enum dma_transfer_direction is not defined as bit flag for
415  *      each type, the dma controller should set BIT(<TYPE>) and same
416  *      should be checked by controller as well
417  * @max_burst: max burst capability per-transfer
418  * @cmd_pause: true, if pause is supported (i.e. for reading residue or
419  *             for resume later)
420  * @cmd_resume: true, if resume is supported
421  * @cmd_terminate: true, if terminate cmd is supported
422  * @residue_granularity: granularity of the reported transfer residue
423  * @descriptor_reuse: if a descriptor can be reused by client and
424  * resubmitted multiple times
425  */
426 struct dma_slave_caps {
427         u32 src_addr_widths;
428         u32 dst_addr_widths;
429         u32 directions;
430         u32 max_burst;
431         bool cmd_pause;
432         bool cmd_resume;
433         bool cmd_terminate;
434         enum dma_residue_granularity residue_granularity;
435         bool descriptor_reuse;
436 };
437 
438 static inline const char *dma_chan_name(struct dma_chan *chan)
439 {
440         return dev_name(&chan->dev->device);
441 }
442 
443 void dma_chan_cleanup(struct kref *kref);
444 
445 /**
446  * typedef dma_filter_fn - callback filter for dma_request_channel
447  * @chan: channel to be reviewed
448  * @filter_param: opaque parameter passed through dma_request_channel
449  *
450  * When this optional parameter is specified in a call to dma_request_channel a
451  * suitable channel is passed to this routine for further dispositioning before
452  * being returned.  Where 'suitable' indicates a non-busy channel that
453  * satisfies the given capability mask.  It returns 'true' to indicate that the
454  * channel is suitable.
455  */
456 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
457 
458 typedef void (*dma_async_tx_callback)(void *dma_async_param);
459 
460 enum dmaengine_tx_result {
461         DMA_TRANS_NOERROR = 0,          /* SUCCESS */
462         DMA_TRANS_READ_FAILED,          /* Source DMA read failed */
463         DMA_TRANS_WRITE_FAILED,         /* Destination DMA write failed */
464         DMA_TRANS_ABORTED,              /* Op never submitted / aborted */
465 };
466 
467 struct dmaengine_result {
468         enum dmaengine_tx_result result;
469         u32 residue;
470 };
471 
472 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
473                                 const struct dmaengine_result *result);
474 
475 struct dmaengine_unmap_data {
476 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
477         u16 map_cnt;
478 #else
479         u8 map_cnt;
480 #endif
481         u8 to_cnt;
482         u8 from_cnt;
483         u8 bidi_cnt;
484         struct device *dev;
485         struct kref kref;
486         size_t len;
487         dma_addr_t addr[0];
488 };
489 
490 /**
491  * struct dma_async_tx_descriptor - async transaction descriptor
492  * ---dma generic offload fields---
493  * @cookie: tracking cookie for this transaction, set to -EBUSY if
494  *      this tx is sitting on a dependency list
495  * @flags: flags to augment operation preparation, control completion, and
496  *      communicate status
497  * @phys: physical address of the descriptor
498  * @chan: target channel for this operation
499  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
500  * descriptor pending. To be pushed on .issue_pending() call
501  * @callback: routine to call after this operation is complete
502  * @callback_param: general parameter to pass to the callback routine
503  * ---async_tx api specific fields---
504  * @next: at completion submit this descriptor
505  * @parent: pointer to the next level up in the dependency chain
506  * @lock: protect the parent and next pointers
507  */
508 struct dma_async_tx_descriptor {
509         dma_cookie_t cookie;
510         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
511         dma_addr_t phys;
512         struct dma_chan *chan;
513         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
514         int (*desc_free)(struct dma_async_tx_descriptor *tx);
515         dma_async_tx_callback callback;
516         dma_async_tx_callback_result callback_result;
517         void *callback_param;
518         struct dmaengine_unmap_data *unmap;
519 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
520         struct dma_async_tx_descriptor *next;
521         struct dma_async_tx_descriptor *parent;
522         spinlock_t lock;
523 #endif
524 };
525 
526 #ifdef CONFIG_DMA_ENGINE
527 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
528                                  struct dmaengine_unmap_data *unmap)
529 {
530         kref_get(&unmap->kref);
531         tx->unmap = unmap;
532 }
533 
534 struct dmaengine_unmap_data *
535 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
536 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
537 #else
538 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
539                                  struct dmaengine_unmap_data *unmap)
540 {
541 }
542 static inline struct dmaengine_unmap_data *
543 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
544 {
545         return NULL;
546 }
547 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
548 {
549 }
550 #endif
551 
552 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
553 {
554         if (tx->unmap) {
555                 dmaengine_unmap_put(tx->unmap);
556                 tx->unmap = NULL;
557         }
558 }
559 
560 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
561 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
562 {
563 }
564 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
565 {
566 }
567 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
568 {
569         BUG();
570 }
571 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
572 {
573 }
574 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
575 {
576 }
577 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
578 {
579         return NULL;
580 }
581 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
582 {
583         return NULL;
584 }
585 
586 #else
587 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
588 {
589         spin_lock_bh(&txd->lock);
590 }
591 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
592 {
593         spin_unlock_bh(&txd->lock);
594 }
595 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
596 {
597         txd->next = next;
598         next->parent = txd;
599 }
600 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
601 {
602         txd->parent = NULL;
603 }
604 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
605 {
606         txd->next = NULL;
607 }
608 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
609 {
610         return txd->parent;
611 }
612 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
613 {
614         return txd->next;
615 }
616 #endif
617 
618 /**
619  * struct dma_tx_state - filled in to report the status of
620  * a transfer.
621  * @last: last completed DMA cookie
622  * @used: last issued DMA cookie (i.e. the one in progress)
623  * @residue: the remaining number of bytes left to transmit
624  *      on the selected transfer for states DMA_IN_PROGRESS and
625  *      DMA_PAUSED if this is implemented in the driver, else 0
626  */
627 struct dma_tx_state {
628         dma_cookie_t last;
629         dma_cookie_t used;
630         u32 residue;
631 };
632 
633 /**
634  * enum dmaengine_alignment - defines alignment of the DMA async tx
635  * buffers
636  */
637 enum dmaengine_alignment {
638         DMAENGINE_ALIGN_1_BYTE = 0,
639         DMAENGINE_ALIGN_2_BYTES = 1,
640         DMAENGINE_ALIGN_4_BYTES = 2,
641         DMAENGINE_ALIGN_8_BYTES = 3,
642         DMAENGINE_ALIGN_16_BYTES = 4,
643         DMAENGINE_ALIGN_32_BYTES = 5,
644         DMAENGINE_ALIGN_64_BYTES = 6,
645 };
646 
647 /**
648  * struct dma_slave_map - associates slave device and it's slave channel with
649  * parameter to be used by a filter function
650  * @devname: name of the device
651  * @slave: slave channel name
652  * @param: opaque parameter to pass to struct dma_filter.fn
653  */
654 struct dma_slave_map {
655         const char *devname;
656         const char *slave;
657         void *param;
658 };
659 
660 /**
661  * struct dma_filter - information for slave device/channel to filter_fn/param
662  * mapping
663  * @fn: filter function callback
664  * @mapcnt: number of slave device/channel in the map
665  * @map: array of channel to filter mapping data
666  */
667 struct dma_filter {
668         dma_filter_fn fn;
669         int mapcnt;
670         const struct dma_slave_map *map;
671 };
672 
673 /**
674  * struct dma_device - info on the entity supplying DMA services
675  * @chancnt: how many DMA channels are supported
676  * @privatecnt: how many DMA channels are requested by dma_request_channel
677  * @channels: the list of struct dma_chan
678  * @global_node: list_head for global dma_device_list
679  * @filter: information for device/slave to filter function/param mapping
680  * @cap_mask: one or more dma_capability flags
681  * @max_xor: maximum number of xor sources, 0 if no capability
682  * @max_pq: maximum number of PQ sources and PQ-continue capability
683  * @copy_align: alignment shift for memcpy operations
684  * @xor_align: alignment shift for xor operations
685  * @pq_align: alignment shift for pq operations
686  * @fill_align: alignment shift for memset operations
687  * @dev_id: unique device ID
688  * @dev: struct device reference for dma mapping api
689  * @src_addr_widths: bit mask of src addr widths the device supports
690  *      Width is specified in bytes, e.g. for a device supporting
691  *      a width of 4 the mask should have BIT(4) set.
692  * @dst_addr_widths: bit mask of dst addr widths the device supports
693  * @directions: bit mask of slave directions the device supports.
694  *      Since the enum dma_transfer_direction is not defined as bit flag for
695  *      each type, the dma controller should set BIT(<TYPE>) and same
696  *      should be checked by controller as well
697  * @max_burst: max burst capability per-transfer
698  * @residue_granularity: granularity of the transfer residue reported
699  *      by tx_status
700  * @device_alloc_chan_resources: allocate resources and return the
701  *      number of allocated descriptors
702  * @device_free_chan_resources: release DMA channel's resources
703  * @device_prep_dma_memcpy: prepares a memcpy operation
704  * @device_prep_dma_xor: prepares a xor operation
705  * @device_prep_dma_xor_val: prepares a xor validation operation
706  * @device_prep_dma_pq: prepares a pq operation
707  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
708  * @device_prep_dma_memset: prepares a memset operation
709  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
710  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
711  * @device_prep_slave_sg: prepares a slave dma operation
712  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
713  *      The function takes a buffer of size buf_len. The callback function will
714  *      be called after period_len bytes have been transferred.
715  * @device_prep_interleaved_dma: Transfer expression in a generic way.
716  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
717  * @device_config: Pushes a new configuration to a channel, return 0 or an error
718  *      code
719  * @device_pause: Pauses any transfer happening on a channel. Returns
720  *      0 or an error code
721  * @device_resume: Resumes any transfer on a channel previously
722  *      paused. Returns 0 or an error code
723  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
724  *      or an error code
725  * @device_synchronize: Synchronizes the termination of a transfers to the
726  *  current context.
727  * @device_tx_status: poll for transaction completion, the optional
728  *      txstate parameter can be supplied with a pointer to get a
729  *      struct with auxiliary transfer status information, otherwise the call
730  *      will just return a simple status code
731  * @device_issue_pending: push pending transactions to hardware
732  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
733  */
734 struct dma_device {
735 
736         unsigned int chancnt;
737         unsigned int privatecnt;
738         struct list_head channels;
739         struct list_head global_node;
740         struct dma_filter filter;
741         dma_cap_mask_t  cap_mask;
742         unsigned short max_xor;
743         unsigned short max_pq;
744         enum dmaengine_alignment copy_align;
745         enum dmaengine_alignment xor_align;
746         enum dmaengine_alignment pq_align;
747         enum dmaengine_alignment fill_align;
748         #define DMA_HAS_PQ_CONTINUE (1 << 15)
749 
750         int dev_id;
751         struct device *dev;
752 
753         u32 src_addr_widths;
754         u32 dst_addr_widths;
755         u32 directions;
756         u32 max_burst;
757         bool descriptor_reuse;
758         enum dma_residue_granularity residue_granularity;
759 
760         int (*device_alloc_chan_resources)(struct dma_chan *chan);
761         void (*device_free_chan_resources)(struct dma_chan *chan);
762 
763         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
764                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
765                 size_t len, unsigned long flags);
766         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
767                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
768                 unsigned int src_cnt, size_t len, unsigned long flags);
769         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
770                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
771                 size_t len, enum sum_check_flags *result, unsigned long flags);
772         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
773                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
774                 unsigned int src_cnt, const unsigned char *scf,
775                 size_t len, unsigned long flags);
776         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
777                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
778                 unsigned int src_cnt, const unsigned char *scf, size_t len,
779                 enum sum_check_flags *pqres, unsigned long flags);
780         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
781                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
782                 unsigned long flags);
783         struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
784                 struct dma_chan *chan, struct scatterlist *sg,
785                 unsigned int nents, int value, unsigned long flags);
786         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
787                 struct dma_chan *chan, unsigned long flags);
788 
789         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
790                 struct dma_chan *chan, struct scatterlist *sgl,
791                 unsigned int sg_len, enum dma_transfer_direction direction,
792                 unsigned long flags, void *context);
793         struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
794                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
795                 size_t period_len, enum dma_transfer_direction direction,
796                 unsigned long flags);
797         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
798                 struct dma_chan *chan, struct dma_interleaved_template *xt,
799                 unsigned long flags);
800         struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
801                 struct dma_chan *chan, dma_addr_t dst, u64 data,
802                 unsigned long flags);
803 
804         int (*device_config)(struct dma_chan *chan,
805                              struct dma_slave_config *config);
806         int (*device_pause)(struct dma_chan *chan);
807         int (*device_resume)(struct dma_chan *chan);
808         int (*device_terminate_all)(struct dma_chan *chan);
809         void (*device_synchronize)(struct dma_chan *chan);
810 
811         enum dma_status (*device_tx_status)(struct dma_chan *chan,
812                                             dma_cookie_t cookie,
813                                             struct dma_tx_state *txstate);
814         void (*device_issue_pending)(struct dma_chan *chan);
815 };
816 
817 static inline int dmaengine_slave_config(struct dma_chan *chan,
818                                           struct dma_slave_config *config)
819 {
820         if (chan->device->device_config)
821                 return chan->device->device_config(chan, config);
822 
823         return -ENOSYS;
824 }
825 
826 static inline bool is_slave_direction(enum dma_transfer_direction direction)
827 {
828         return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
829 }
830 
831 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
832         struct dma_chan *chan, dma_addr_t buf, size_t len,
833         enum dma_transfer_direction dir, unsigned long flags)
834 {
835         struct scatterlist sg;
836         sg_init_table(&sg, 1);
837         sg_dma_address(&sg) = buf;
838         sg_dma_len(&sg) = len;
839 
840         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
841                 return NULL;
842 
843         return chan->device->device_prep_slave_sg(chan, &sg, 1,
844                                                   dir, flags, NULL);
845 }
846 
847 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
848         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
849         enum dma_transfer_direction dir, unsigned long flags)
850 {
851         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
852                 return NULL;
853 
854         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
855                                                   dir, flags, NULL);
856 }
857 
858 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
859 struct rio_dma_ext;
860 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
861         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
862         enum dma_transfer_direction dir, unsigned long flags,
863         struct rio_dma_ext *rio_ext)
864 {
865         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
866                 return NULL;
867 
868         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
869                                                   dir, flags, rio_ext);
870 }
871 #endif
872 
873 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
874                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
875                 size_t period_len, enum dma_transfer_direction dir,
876                 unsigned long flags)
877 {
878         if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
879                 return NULL;
880 
881         return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
882                                                 period_len, dir, flags);
883 }
884 
885 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
886                 struct dma_chan *chan, struct dma_interleaved_template *xt,
887                 unsigned long flags)
888 {
889         if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
890                 return NULL;
891 
892         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
893 }
894 
895 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
896                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
897                 unsigned long flags)
898 {
899         if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
900                 return NULL;
901 
902         return chan->device->device_prep_dma_memset(chan, dest, value,
903                                                     len, flags);
904 }
905 
906 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
907                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
908                 size_t len, unsigned long flags)
909 {
910         if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
911                 return NULL;
912 
913         return chan->device->device_prep_dma_memcpy(chan, dest, src,
914                                                     len, flags);
915 }
916 
917 /**
918  * dmaengine_terminate_all() - Terminate all active DMA transfers
919  * @chan: The channel for which to terminate the transfers
920  *
921  * This function is DEPRECATED use either dmaengine_terminate_sync() or
922  * dmaengine_terminate_async() instead.
923  */
924 static inline int dmaengine_terminate_all(struct dma_chan *chan)
925 {
926         if (chan->device->device_terminate_all)
927                 return chan->device->device_terminate_all(chan);
928 
929         return -ENOSYS;
930 }
931 
932 /**
933  * dmaengine_terminate_async() - Terminate all active DMA transfers
934  * @chan: The channel for which to terminate the transfers
935  *
936  * Calling this function will terminate all active and pending descriptors
937  * that have previously been submitted to the channel. It is not guaranteed
938  * though that the transfer for the active descriptor has stopped when the
939  * function returns. Furthermore it is possible the complete callback of a
940  * submitted transfer is still running when this function returns.
941  *
942  * dmaengine_synchronize() needs to be called before it is safe to free
943  * any memory that is accessed by previously submitted descriptors or before
944  * freeing any resources accessed from within the completion callback of any
945  * perviously submitted descriptors.
946  *
947  * This function can be called from atomic context as well as from within a
948  * complete callback of a descriptor submitted on the same channel.
949  *
950  * If none of the two conditions above apply consider using
951  * dmaengine_terminate_sync() instead.
952  */
953 static inline int dmaengine_terminate_async(struct dma_chan *chan)
954 {
955         if (chan->device->device_terminate_all)
956                 return chan->device->device_terminate_all(chan);
957 
958         return -EINVAL;
959 }
960 
961 /**
962  * dmaengine_synchronize() - Synchronize DMA channel termination
963  * @chan: The channel to synchronize
964  *
965  * Synchronizes to the DMA channel termination to the current context. When this
966  * function returns it is guaranteed that all transfers for previously issued
967  * descriptors have stopped and and it is safe to free the memory assoicated
968  * with them. Furthermore it is guaranteed that all complete callback functions
969  * for a previously submitted descriptor have finished running and it is safe to
970  * free resources accessed from within the complete callbacks.
971  *
972  * The behavior of this function is undefined if dma_async_issue_pending() has
973  * been called between dmaengine_terminate_async() and this function.
974  *
975  * This function must only be called from non-atomic context and must not be
976  * called from within a complete callback of a descriptor submitted on the same
977  * channel.
978  */
979 static inline void dmaengine_synchronize(struct dma_chan *chan)
980 {
981         might_sleep();
982 
983         if (chan->device->device_synchronize)
984                 chan->device->device_synchronize(chan);
985 }
986 
987 /**
988  * dmaengine_terminate_sync() - Terminate all active DMA transfers
989  * @chan: The channel for which to terminate the transfers
990  *
991  * Calling this function will terminate all active and pending transfers
992  * that have previously been submitted to the channel. It is similar to
993  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
994  * stopped and that all complete callbacks have finished running when the
995  * function returns.
996  *
997  * This function must only be called from non-atomic context and must not be
998  * called from within a complete callback of a descriptor submitted on the same
999  * channel.
1000  */
1001 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1002 {
1003         int ret;
1004 
1005         ret = dmaengine_terminate_async(chan);
1006         if (ret)
1007                 return ret;
1008 
1009         dmaengine_synchronize(chan);
1010 
1011         return 0;
1012 }
1013 
1014 static inline int dmaengine_pause(struct dma_chan *chan)
1015 {
1016         if (chan->device->device_pause)
1017                 return chan->device->device_pause(chan);
1018 
1019         return -ENOSYS;
1020 }
1021 
1022 static inline int dmaengine_resume(struct dma_chan *chan)
1023 {
1024         if (chan->device->device_resume)
1025                 return chan->device->device_resume(chan);
1026 
1027         return -ENOSYS;
1028 }
1029 
1030 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1031         dma_cookie_t cookie, struct dma_tx_state *state)
1032 {
1033         return chan->device->device_tx_status(chan, cookie, state);
1034 }
1035 
1036 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1037 {
1038         return desc->tx_submit(desc);
1039 }
1040 
1041 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1042                                          size_t off1, size_t off2, size_t len)
1043 {
1044         size_t mask;
1045 
1046         if (!align)
1047                 return true;
1048         mask = (1 << align) - 1;
1049         if (mask & (off1 | off2 | len))
1050                 return false;
1051         return true;
1052 }
1053 
1054 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1055                                        size_t off2, size_t len)
1056 {
1057         return dmaengine_check_align(dev->copy_align, off1, off2, len);
1058 }
1059 
1060 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1061                                       size_t off2, size_t len)
1062 {
1063         return dmaengine_check_align(dev->xor_align, off1, off2, len);
1064 }
1065 
1066 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1067                                      size_t off2, size_t len)
1068 {
1069         return dmaengine_check_align(dev->pq_align, off1, off2, len);
1070 }
1071 
1072 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1073                                        size_t off2, size_t len)
1074 {
1075         return dmaengine_check_align(dev->fill_align, off1, off2, len);
1076 }
1077 
1078 static inline void
1079 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1080 {
1081         dma->max_pq = maxpq;
1082         if (has_pq_continue)
1083                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1084 }
1085 
1086 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1087 {
1088         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1089 }
1090 
1091 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1092 {
1093         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1094 
1095         return (flags & mask) == mask;
1096 }
1097 
1098 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1099 {
1100         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1101 }
1102 
1103 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1104 {
1105         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1106 }
1107 
1108 /* dma_maxpq - reduce maxpq in the face of continued operations
1109  * @dma - dma device with PQ capability
1110  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1111  *
1112  * When an engine does not support native continuation we need 3 extra
1113  * source slots to reuse P and Q with the following coefficients:
1114  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1115  * 2/ {01} * Q : use Q to continue Q' calculation
1116  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1117  *
1118  * In the case where P is disabled we only need 1 extra source:
1119  * 1/ {01} * Q : use Q to continue Q' calculation
1120  */
1121 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1122 {
1123         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1124                 return dma_dev_to_maxpq(dma);
1125         else if (dmaf_p_disabled_continue(flags))
1126                 return dma_dev_to_maxpq(dma) - 1;
1127         else if (dmaf_continue(flags))
1128                 return dma_dev_to_maxpq(dma) - 3;
1129         BUG();
1130 }
1131 
1132 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1133                                       size_t dir_icg)
1134 {
1135         if (inc) {
1136                 if (dir_icg)
1137                         return dir_icg;
1138                 else if (sgl)
1139                         return icg;
1140         }
1141 
1142         return 0;
1143 }
1144 
1145 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1146                                            struct data_chunk *chunk)
1147 {
1148         return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1149                                  chunk->icg, chunk->dst_icg);
1150 }
1151 
1152 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1153                                            struct data_chunk *chunk)
1154 {
1155         return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1156                                  chunk->icg, chunk->src_icg);
1157 }
1158 
1159 /* --- public DMA engine API --- */
1160 
1161 #ifdef CONFIG_DMA_ENGINE
1162 void dmaengine_get(void);
1163 void dmaengine_put(void);
1164 #else
1165 static inline void dmaengine_get(void)
1166 {
1167 }
1168 static inline void dmaengine_put(void)
1169 {
1170 }
1171 #endif
1172 
1173 #ifdef CONFIG_ASYNC_TX_DMA
1174 #define async_dmaengine_get()   dmaengine_get()
1175 #define async_dmaengine_put()   dmaengine_put()
1176 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1177 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1178 #else
1179 #define async_dma_find_channel(type) dma_find_channel(type)
1180 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1181 #else
1182 static inline void async_dmaengine_get(void)
1183 {
1184 }
1185 static inline void async_dmaengine_put(void)
1186 {
1187 }
1188 static inline struct dma_chan *
1189 async_dma_find_channel(enum dma_transaction_type type)
1190 {
1191         return NULL;
1192 }
1193 #endif /* CONFIG_ASYNC_TX_DMA */
1194 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1195                                   struct dma_chan *chan);
1196 
1197 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1198 {
1199         tx->flags |= DMA_CTRL_ACK;
1200 }
1201 
1202 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1203 {
1204         tx->flags &= ~DMA_CTRL_ACK;
1205 }
1206 
1207 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1208 {
1209         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1210 }
1211 
1212 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1213 static inline void
1214 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1215 {
1216         set_bit(tx_type, dstp->bits);
1217 }
1218 
1219 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1220 static inline void
1221 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1222 {
1223         clear_bit(tx_type, dstp->bits);
1224 }
1225 
1226 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1227 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1228 {
1229         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1230 }
1231 
1232 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1233 static inline int
1234 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1235 {
1236         return test_bit(tx_type, srcp->bits);
1237 }
1238 
1239 #define for_each_dma_cap_mask(cap, mask) \
1240         for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1241 
1242 /**
1243  * dma_async_issue_pending - flush pending transactions to HW
1244  * @chan: target DMA channel
1245  *
1246  * This allows drivers to push copies to HW in batches,
1247  * reducing MMIO writes where possible.
1248  */
1249 static inline void dma_async_issue_pending(struct dma_chan *chan)
1250 {
1251         chan->device->device_issue_pending(chan);
1252 }
1253 
1254 /**
1255  * dma_async_is_tx_complete - poll for transaction completion
1256  * @chan: DMA channel
1257  * @cookie: transaction identifier to check status of
1258  * @last: returns last completed cookie, can be NULL
1259  * @used: returns last issued cookie, can be NULL
1260  *
1261  * If @last and @used are passed in, upon return they reflect the driver
1262  * internal state and can be used with dma_async_is_complete() to check
1263  * the status of multiple cookies without re-checking hardware state.
1264  */
1265 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1266         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1267 {
1268         struct dma_tx_state state;
1269         enum dma_status status;
1270 
1271         status = chan->device->device_tx_status(chan, cookie, &state);
1272         if (last)
1273                 *last = state.last;
1274         if (used)
1275                 *used = state.used;
1276         return status;
1277 }
1278 
1279 /**
1280  * dma_async_is_complete - test a cookie against chan state
1281  * @cookie: transaction identifier to test status of
1282  * @last_complete: last know completed transaction
1283  * @last_used: last cookie value handed out
1284  *
1285  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1286  * the test logic is separated for lightweight testing of multiple cookies
1287  */
1288 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1289                         dma_cookie_t last_complete, dma_cookie_t last_used)
1290 {
1291         if (last_complete <= last_used) {
1292                 if ((cookie <= last_complete) || (cookie > last_used))
1293                         return DMA_COMPLETE;
1294         } else {
1295                 if ((cookie <= last_complete) && (cookie > last_used))
1296                         return DMA_COMPLETE;
1297         }
1298         return DMA_IN_PROGRESS;
1299 }
1300 
1301 static inline void
1302 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1303 {
1304         if (st) {
1305                 st->last = last;
1306                 st->used = used;
1307                 st->residue = residue;
1308         }
1309 }
1310 
1311 #ifdef CONFIG_DMA_ENGINE
1312 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1313 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1314 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1315 void dma_issue_pending_all(void);
1316 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1317                                         dma_filter_fn fn, void *fn_param);
1318 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1319 
1320 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1321 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1322 
1323 void dma_release_channel(struct dma_chan *chan);
1324 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1325 #else
1326 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1327 {
1328         return NULL;
1329 }
1330 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1331 {
1332         return DMA_COMPLETE;
1333 }
1334 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1335 {
1336         return DMA_COMPLETE;
1337 }
1338 static inline void dma_issue_pending_all(void)
1339 {
1340 }
1341 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1342                                               dma_filter_fn fn, void *fn_param)
1343 {
1344         return NULL;
1345 }
1346 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1347                                                          const char *name)
1348 {
1349         return NULL;
1350 }
1351 static inline struct dma_chan *dma_request_chan(struct device *dev,
1352                                                 const char *name)
1353 {
1354         return ERR_PTR(-ENODEV);
1355 }
1356 static inline struct dma_chan *dma_request_chan_by_mask(
1357                                                 const dma_cap_mask_t *mask)
1358 {
1359         return ERR_PTR(-ENODEV);
1360 }
1361 static inline void dma_release_channel(struct dma_chan *chan)
1362 {
1363 }
1364 static inline int dma_get_slave_caps(struct dma_chan *chan,
1365                                      struct dma_slave_caps *caps)
1366 {
1367         return -ENXIO;
1368 }
1369 #endif
1370 
1371 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1372 
1373 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1374 {
1375         struct dma_slave_caps caps;
1376 
1377         dma_get_slave_caps(tx->chan, &caps);
1378 
1379         if (caps.descriptor_reuse) {
1380                 tx->flags |= DMA_CTRL_REUSE;
1381                 return 0;
1382         } else {
1383                 return -EPERM;
1384         }
1385 }
1386 
1387 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1388 {
1389         tx->flags &= ~DMA_CTRL_REUSE;
1390 }
1391 
1392 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1393 {
1394         return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1395 }
1396 
1397 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1398 {
1399         /* this is supported for reusable desc, so check that */
1400         if (dmaengine_desc_test_reuse(desc))
1401                 return desc->desc_free(desc);
1402         else
1403                 return -EPERM;
1404 }
1405 
1406 /* --- DMA device --- */
1407 
1408 int dma_async_device_register(struct dma_device *device);
1409 int dmaenginem_async_device_register(struct dma_device *device);
1410 void dma_async_device_unregister(struct dma_device *device);
1411 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1412 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1413 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1414 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1415 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1416         __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1417 
1418 static inline struct dma_chan
1419 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1420                                   dma_filter_fn fn, void *fn_param,
1421                                   struct device *dev, const char *name)
1422 {
1423         struct dma_chan *chan;
1424 
1425         chan = dma_request_slave_channel(dev, name);
1426         if (chan)
1427                 return chan;
1428 
1429         if (!fn || !fn_param)
1430                 return NULL;
1431 
1432         return __dma_request_channel(mask, fn, fn_param);
1433 }
1434 #endif /* DMAENGINE_H */
1435 

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