1 /* 2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef LINUX_DMAENGINE_H 22 #define LINUX_DMAENGINE_H 23 24 #include <linux/device.h> 25 #include <linux/uio.h> 26 #include <linux/bug.h> 27 #include <linux/scatterlist.h> 28 #include <linux/bitmap.h> 29 #include <linux/types.h> 30 #include <asm/page.h> 31 32 /** 33 * typedef dma_cookie_t - an opaque DMA cookie 34 * 35 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 36 */ 37 typedef s32 dma_cookie_t; 38 #define DMA_MIN_COOKIE 1 39 #define DMA_MAX_COOKIE INT_MAX 40 41 static inline int dma_submit_error(dma_cookie_t cookie) 42 { 43 return cookie < 0 ? cookie : 0; 44 } 45 46 /** 47 * enum dma_status - DMA transaction status 48 * @DMA_SUCCESS: transaction completed successfully 49 * @DMA_IN_PROGRESS: transaction not yet processed 50 * @DMA_PAUSED: transaction is paused 51 * @DMA_ERROR: transaction failed 52 */ 53 enum dma_status { 54 DMA_SUCCESS, 55 DMA_IN_PROGRESS, 56 DMA_PAUSED, 57 DMA_ERROR, 58 }; 59 60 /** 61 * enum dma_transaction_type - DMA transaction types/indexes 62 * 63 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 64 * automatically set as dma devices are registered. 65 */ 66 enum dma_transaction_type { 67 DMA_MEMCPY, 68 DMA_XOR, 69 DMA_PQ, 70 DMA_XOR_VAL, 71 DMA_PQ_VAL, 72 DMA_INTERRUPT, 73 DMA_SG, 74 DMA_PRIVATE, 75 DMA_ASYNC_TX, 76 DMA_SLAVE, 77 DMA_CYCLIC, 78 DMA_INTERLEAVE, 79 /* last transaction type for creation of the capabilities mask */ 80 DMA_TX_TYPE_END, 81 }; 82 83 /** 84 * enum dma_transfer_direction - dma transfer mode and direction indicator 85 * @DMA_MEM_TO_MEM: Async/Memcpy mode 86 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 87 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 88 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 89 */ 90 enum dma_transfer_direction { 91 DMA_MEM_TO_MEM, 92 DMA_MEM_TO_DEV, 93 DMA_DEV_TO_MEM, 94 DMA_DEV_TO_DEV, 95 DMA_TRANS_NONE, 96 }; 97 98 /** 99 * Interleaved Transfer Request 100 * ---------------------------- 101 * A chunk is collection of contiguous bytes to be transfered. 102 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 103 * ICGs may or maynot change between chunks. 104 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 105 * that when repeated an integral number of times, specifies the transfer. 106 * A transfer template is specification of a Frame, the number of times 107 * it is to be repeated and other per-transfer attributes. 108 * 109 * Practically, a client driver would have ready a template for each 110 * type of transfer it is going to need during its lifetime and 111 * set only 'src_start' and 'dst_start' before submitting the requests. 112 * 113 * 114 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 115 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 116 * 117 * == Chunk size 118 * ... ICG 119 */ 120 121 /** 122 * struct data_chunk - Element of scatter-gather list that makes a frame. 123 * @size: Number of bytes to read from source. 124 * size_dst := fn(op, size_src), so doesn't mean much for destination. 125 * @icg: Number of bytes to jump after last src/dst address of this 126 * chunk and before first src/dst address for next chunk. 127 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 128 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 129 */ 130 struct data_chunk { 131 size_t size; 132 size_t icg; 133 }; 134 135 /** 136 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 137 * and attributes. 138 * @src_start: Bus address of source for the first chunk. 139 * @dst_start: Bus address of destination for the first chunk. 140 * @dir: Specifies the type of Source and Destination. 141 * @src_inc: If the source address increments after reading from it. 142 * @dst_inc: If the destination address increments after writing to it. 143 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 144 * Otherwise, source is read contiguously (icg ignored). 145 * Ignored if src_inc is false. 146 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 147 * Otherwise, destination is filled contiguously (icg ignored). 148 * Ignored if dst_inc is false. 149 * @numf: Number of frames in this template. 150 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 151 * @sgl: Array of {chunk,icg} pairs that make up a frame. 152 */ 153 struct dma_interleaved_template { 154 dma_addr_t src_start; 155 dma_addr_t dst_start; 156 enum dma_transfer_direction dir; 157 bool src_inc; 158 bool dst_inc; 159 bool src_sgl; 160 bool dst_sgl; 161 size_t numf; 162 size_t frame_size; 163 struct data_chunk sgl[0]; 164 }; 165 166 /** 167 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 168 * control completion, and communicate status. 169 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 170 * this transaction 171 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 172 * acknowledges receipt, i.e. has has a chance to establish any dependency 173 * chains 174 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) 175 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) 176 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single 177 * (if not set, do the source dma-unmapping as page) 178 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single 179 * (if not set, do the destination dma-unmapping as page) 180 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 181 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 182 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 183 * sources that were the result of a previous operation, in the case of a PQ 184 * operation it continues the calculation with new sources 185 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 186 * on the result of this operation 187 */ 188 enum dma_ctrl_flags { 189 DMA_PREP_INTERRUPT = (1 << 0), 190 DMA_CTRL_ACK = (1 << 1), 191 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), 192 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), 193 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), 194 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), 195 DMA_PREP_PQ_DISABLE_P = (1 << 6), 196 DMA_PREP_PQ_DISABLE_Q = (1 << 7), 197 DMA_PREP_CONTINUE = (1 << 8), 198 DMA_PREP_FENCE = (1 << 9), 199 }; 200 201 /** 202 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised 203 * on a running channel. 204 * @DMA_TERMINATE_ALL: terminate all ongoing transfers 205 * @DMA_PAUSE: pause ongoing transfers 206 * @DMA_RESUME: resume paused transfer 207 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers 208 * that need to runtime reconfigure the slave channels (as opposed to passing 209 * configuration data in statically from the platform). An additional 210 * argument of struct dma_slave_config must be passed in with this 211 * command. 212 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller 213 * into external start mode. 214 */ 215 enum dma_ctrl_cmd { 216 DMA_TERMINATE_ALL, 217 DMA_PAUSE, 218 DMA_RESUME, 219 DMA_SLAVE_CONFIG, 220 FSLDMA_EXTERNAL_START, 221 }; 222 223 /** 224 * enum sum_check_bits - bit position of pq_check_flags 225 */ 226 enum sum_check_bits { 227 SUM_CHECK_P = 0, 228 SUM_CHECK_Q = 1, 229 }; 230 231 /** 232 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 233 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 234 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 235 */ 236 enum sum_check_flags { 237 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 238 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 239 }; 240 241 242 /** 243 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 244 * See linux/cpumask.h 245 */ 246 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 247 248 /** 249 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 250 * @memcpy_count: transaction counter 251 * @bytes_transferred: byte counter 252 */ 253 254 struct dma_chan_percpu { 255 /* stats */ 256 unsigned long memcpy_count; 257 unsigned long bytes_transferred; 258 }; 259 260 /** 261 * struct dma_chan - devices supply DMA channels, clients use them 262 * @device: ptr to the dma device who supplies this channel, always !%NULL 263 * @cookie: last cookie value returned to client 264 * @completed_cookie: last completed cookie for this channel 265 * @chan_id: channel ID for sysfs 266 * @dev: class device for sysfs 267 * @device_node: used to add this to the device chan list 268 * @local: per-cpu pointer to a struct dma_chan_percpu 269 * @client-count: how many clients are using this channel 270 * @table_count: number of appearances in the mem-to-mem allocation table 271 * @private: private data for certain client-channel associations 272 */ 273 struct dma_chan { 274 struct dma_device *device; 275 dma_cookie_t cookie; 276 dma_cookie_t completed_cookie; 277 278 /* sysfs */ 279 int chan_id; 280 struct dma_chan_dev *dev; 281 282 struct list_head device_node; 283 struct dma_chan_percpu __percpu *local; 284 int client_count; 285 int table_count; 286 void *private; 287 }; 288 289 /** 290 * struct dma_chan_dev - relate sysfs device node to backing channel device 291 * @chan - driver channel device 292 * @device - sysfs device 293 * @dev_id - parent dma_device dev_id 294 * @idr_ref - reference count to gate release of dma_device dev_id 295 */ 296 struct dma_chan_dev { 297 struct dma_chan *chan; 298 struct device device; 299 int dev_id; 300 atomic_t *idr_ref; 301 }; 302 303 /** 304 * enum dma_slave_buswidth - defines bus with of the DMA slave 305 * device, source or target buses 306 */ 307 enum dma_slave_buswidth { 308 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 309 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 310 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 311 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 312 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 313 }; 314 315 /** 316 * struct dma_slave_config - dma slave channel runtime config 317 * @direction: whether the data shall go in or out on this slave 318 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are 319 * legal values, DMA_BIDIRECTIONAL is not acceptable since we 320 * need to differentiate source and target addresses. 321 * @src_addr: this is the physical address where DMA slave data 322 * should be read (RX), if the source is memory this argument is 323 * ignored. 324 * @dst_addr: this is the physical address where DMA slave data 325 * should be written (TX), if the source is memory this argument 326 * is ignored. 327 * @src_addr_width: this is the width in bytes of the source (RX) 328 * register where DMA data shall be read. If the source 329 * is memory this may be ignored depending on architecture. 330 * Legal values: 1, 2, 4, 8. 331 * @dst_addr_width: same as src_addr_width but for destination 332 * target (TX) mutatis mutandis. 333 * @src_maxburst: the maximum number of words (note: words, as in 334 * units of the src_addr_width member, not bytes) that can be sent 335 * in one burst to the device. Typically something like half the 336 * FIFO depth on I/O peripherals so you don't overflow it. This 337 * may or may not be applicable on memory sources. 338 * @dst_maxburst: same as src_maxburst but for destination target 339 * mutatis mutandis. 340 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 341 * with 'true' if peripheral should be flow controller. Direction will be 342 * selected at Runtime. 343 * @slave_id: Slave requester id. Only valid for slave channels. The dma 344 * slave peripheral will have unique id as dma requester which need to be 345 * pass as slave config. 346 * 347 * This struct is passed in as configuration data to a DMA engine 348 * in order to set up a certain channel for DMA transport at runtime. 349 * The DMA device/engine has to provide support for an additional 350 * command in the channel config interface, DMA_SLAVE_CONFIG 351 * and this struct will then be passed in as an argument to the 352 * DMA engine device_control() function. 353 * 354 * The rationale for adding configuration information to this struct 355 * is as follows: if it is likely that most DMA slave controllers in 356 * the world will support the configuration option, then make it 357 * generic. If not: if it is fixed so that it be sent in static from 358 * the platform data, then prefer to do that. Else, if it is neither 359 * fixed at runtime, nor generic enough (such as bus mastership on 360 * some CPU family and whatnot) then create a custom slave config 361 * struct and pass that, then make this config a member of that 362 * struct, if applicable. 363 */ 364 struct dma_slave_config { 365 enum dma_transfer_direction direction; 366 dma_addr_t src_addr; 367 dma_addr_t dst_addr; 368 enum dma_slave_buswidth src_addr_width; 369 enum dma_slave_buswidth dst_addr_width; 370 u32 src_maxburst; 371 u32 dst_maxburst; 372 bool device_fc; 373 unsigned int slave_id; 374 }; 375 376 /* struct dma_slave_caps - expose capabilities of a slave channel only 377 * 378 * @src_addr_widths: bit mask of src addr widths the channel supports 379 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports 380 * @directions: bit mask of slave direction the channel supported 381 * since the enum dma_transfer_direction is not defined as bits for each 382 * type of direction, the dma controller should fill (1 << <TYPE>) and same 383 * should be checked by controller as well 384 * @cmd_pause: true, if pause and thereby resume is supported 385 * @cmd_terminate: true, if terminate cmd is supported 386 */ 387 struct dma_slave_caps { 388 u32 src_addr_widths; 389 u32 dstn_addr_widths; 390 u32 directions; 391 bool cmd_pause; 392 bool cmd_terminate; 393 }; 394 395 static inline const char *dma_chan_name(struct dma_chan *chan) 396 { 397 return dev_name(&chan->dev->device); 398 } 399 400 void dma_chan_cleanup(struct kref *kref); 401 402 /** 403 * typedef dma_filter_fn - callback filter for dma_request_channel 404 * @chan: channel to be reviewed 405 * @filter_param: opaque parameter passed through dma_request_channel 406 * 407 * When this optional parameter is specified in a call to dma_request_channel a 408 * suitable channel is passed to this routine for further dispositioning before 409 * being returned. Where 'suitable' indicates a non-busy channel that 410 * satisfies the given capability mask. It returns 'true' to indicate that the 411 * channel is suitable. 412 */ 413 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 414 415 typedef void (*dma_async_tx_callback)(void *dma_async_param); 416 /** 417 * struct dma_async_tx_descriptor - async transaction descriptor 418 * ---dma generic offload fields--- 419 * @cookie: tracking cookie for this transaction, set to -EBUSY if 420 * this tx is sitting on a dependency list 421 * @flags: flags to augment operation preparation, control completion, and 422 * communicate status 423 * @phys: physical address of the descriptor 424 * @chan: target channel for this operation 425 * @tx_submit: set the prepared descriptor(s) to be executed by the engine 426 * @callback: routine to call after this operation is complete 427 * @callback_param: general parameter to pass to the callback routine 428 * ---async_tx api specific fields--- 429 * @next: at completion submit this descriptor 430 * @parent: pointer to the next level up in the dependency chain 431 * @lock: protect the parent and next pointers 432 */ 433 struct dma_async_tx_descriptor { 434 dma_cookie_t cookie; 435 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 436 dma_addr_t phys; 437 struct dma_chan *chan; 438 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 439 dma_async_tx_callback callback; 440 void *callback_param; 441 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 442 struct dma_async_tx_descriptor *next; 443 struct dma_async_tx_descriptor *parent; 444 spinlock_t lock; 445 #endif 446 }; 447 448 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 449 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 450 { 451 } 452 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 453 { 454 } 455 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 456 { 457 BUG(); 458 } 459 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 460 { 461 } 462 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 463 { 464 } 465 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 466 { 467 return NULL; 468 } 469 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 470 { 471 return NULL; 472 } 473 474 #else 475 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 476 { 477 spin_lock_bh(&txd->lock); 478 } 479 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 480 { 481 spin_unlock_bh(&txd->lock); 482 } 483 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 484 { 485 txd->next = next; 486 next->parent = txd; 487 } 488 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 489 { 490 txd->parent = NULL; 491 } 492 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 493 { 494 txd->next = NULL; 495 } 496 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 497 { 498 return txd->parent; 499 } 500 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 501 { 502 return txd->next; 503 } 504 #endif 505 506 /** 507 * struct dma_tx_state - filled in to report the status of 508 * a transfer. 509 * @last: last completed DMA cookie 510 * @used: last issued DMA cookie (i.e. the one in progress) 511 * @residue: the remaining number of bytes left to transmit 512 * on the selected transfer for states DMA_IN_PROGRESS and 513 * DMA_PAUSED if this is implemented in the driver, else 0 514 */ 515 struct dma_tx_state { 516 dma_cookie_t last; 517 dma_cookie_t used; 518 u32 residue; 519 }; 520 521 /** 522 * struct dma_device - info on the entity supplying DMA services 523 * @chancnt: how many DMA channels are supported 524 * @privatecnt: how many DMA channels are requested by dma_request_channel 525 * @channels: the list of struct dma_chan 526 * @global_node: list_head for global dma_device_list 527 * @cap_mask: one or more dma_capability flags 528 * @max_xor: maximum number of xor sources, 0 if no capability 529 * @max_pq: maximum number of PQ sources and PQ-continue capability 530 * @copy_align: alignment shift for memcpy operations 531 * @xor_align: alignment shift for xor operations 532 * @pq_align: alignment shift for pq operations 533 * @fill_align: alignment shift for memset operations 534 * @dev_id: unique device ID 535 * @dev: struct device reference for dma mapping api 536 * @device_alloc_chan_resources: allocate resources and return the 537 * number of allocated descriptors 538 * @device_free_chan_resources: release DMA channel's resources 539 * @device_prep_dma_memcpy: prepares a memcpy operation 540 * @device_prep_dma_xor: prepares a xor operation 541 * @device_prep_dma_xor_val: prepares a xor validation operation 542 * @device_prep_dma_pq: prepares a pq operation 543 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 544 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 545 * @device_prep_slave_sg: prepares a slave dma operation 546 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 547 * The function takes a buffer of size buf_len. The callback function will 548 * be called after period_len bytes have been transferred. 549 * @device_prep_interleaved_dma: Transfer expression in a generic way. 550 * @device_control: manipulate all pending operations on a channel, returns 551 * zero or error code 552 * @device_tx_status: poll for transaction completion, the optional 553 * txstate parameter can be supplied with a pointer to get a 554 * struct with auxiliary transfer status information, otherwise the call 555 * will just return a simple status code 556 * @device_issue_pending: push pending transactions to hardware 557 * @device_slave_caps: return the slave channel capabilities 558 */ 559 struct dma_device { 560 561 unsigned int chancnt; 562 unsigned int privatecnt; 563 struct list_head channels; 564 struct list_head global_node; 565 dma_cap_mask_t cap_mask; 566 unsigned short max_xor; 567 unsigned short max_pq; 568 u8 copy_align; 569 u8 xor_align; 570 u8 pq_align; 571 u8 fill_align; 572 #define DMA_HAS_PQ_CONTINUE (1 << 15) 573 574 int dev_id; 575 struct device *dev; 576 577 int (*device_alloc_chan_resources)(struct dma_chan *chan); 578 void (*device_free_chan_resources)(struct dma_chan *chan); 579 580 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 581 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 582 size_t len, unsigned long flags); 583 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 584 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 585 unsigned int src_cnt, size_t len, unsigned long flags); 586 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 587 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 588 size_t len, enum sum_check_flags *result, unsigned long flags); 589 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 590 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 591 unsigned int src_cnt, const unsigned char *scf, 592 size_t len, unsigned long flags); 593 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 594 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 595 unsigned int src_cnt, const unsigned char *scf, size_t len, 596 enum sum_check_flags *pqres, unsigned long flags); 597 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 598 struct dma_chan *chan, unsigned long flags); 599 struct dma_async_tx_descriptor *(*device_prep_dma_sg)( 600 struct dma_chan *chan, 601 struct scatterlist *dst_sg, unsigned int dst_nents, 602 struct scatterlist *src_sg, unsigned int src_nents, 603 unsigned long flags); 604 605 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 606 struct dma_chan *chan, struct scatterlist *sgl, 607 unsigned int sg_len, enum dma_transfer_direction direction, 608 unsigned long flags, void *context); 609 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 610 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 611 size_t period_len, enum dma_transfer_direction direction, 612 unsigned long flags, void *context); 613 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 614 struct dma_chan *chan, struct dma_interleaved_template *xt, 615 unsigned long flags); 616 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 617 unsigned long arg); 618 619 enum dma_status (*device_tx_status)(struct dma_chan *chan, 620 dma_cookie_t cookie, 621 struct dma_tx_state *txstate); 622 void (*device_issue_pending)(struct dma_chan *chan); 623 int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); 624 }; 625 626 static inline int dmaengine_device_control(struct dma_chan *chan, 627 enum dma_ctrl_cmd cmd, 628 unsigned long arg) 629 { 630 if (chan->device->device_control) 631 return chan->device->device_control(chan, cmd, arg); 632 633 return -ENOSYS; 634 } 635 636 static inline int dmaengine_slave_config(struct dma_chan *chan, 637 struct dma_slave_config *config) 638 { 639 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, 640 (unsigned long)config); 641 } 642 643 static inline bool is_slave_direction(enum dma_transfer_direction direction) 644 { 645 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); 646 } 647 648 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 649 struct dma_chan *chan, dma_addr_t buf, size_t len, 650 enum dma_transfer_direction dir, unsigned long flags) 651 { 652 struct scatterlist sg; 653 sg_init_table(&sg, 1); 654 sg_dma_address(&sg) = buf; 655 sg_dma_len(&sg) = len; 656 657 return chan->device->device_prep_slave_sg(chan, &sg, 1, 658 dir, flags, NULL); 659 } 660 661 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 662 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 663 enum dma_transfer_direction dir, unsigned long flags) 664 { 665 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 666 dir, flags, NULL); 667 } 668 669 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 670 struct rio_dma_ext; 671 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 672 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 673 enum dma_transfer_direction dir, unsigned long flags, 674 struct rio_dma_ext *rio_ext) 675 { 676 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 677 dir, flags, rio_ext); 678 } 679 #endif 680 681 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 682 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 683 size_t period_len, enum dma_transfer_direction dir, 684 unsigned long flags) 685 { 686 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 687 period_len, dir, flags, NULL); 688 } 689 690 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 691 struct dma_chan *chan, struct dma_interleaved_template *xt, 692 unsigned long flags) 693 { 694 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 695 } 696 697 static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) 698 { 699 if (!chan || !caps) 700 return -EINVAL; 701 702 /* check if the channel supports slave transactions */ 703 if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits)) 704 return -ENXIO; 705 706 if (chan->device->device_slave_caps) 707 return chan->device->device_slave_caps(chan, caps); 708 709 return -ENXIO; 710 } 711 712 static inline int dmaengine_terminate_all(struct dma_chan *chan) 713 { 714 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); 715 } 716 717 static inline int dmaengine_pause(struct dma_chan *chan) 718 { 719 return dmaengine_device_control(chan, DMA_PAUSE, 0); 720 } 721 722 static inline int dmaengine_resume(struct dma_chan *chan) 723 { 724 return dmaengine_device_control(chan, DMA_RESUME, 0); 725 } 726 727 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 728 dma_cookie_t cookie, struct dma_tx_state *state) 729 { 730 return chan->device->device_tx_status(chan, cookie, state); 731 } 732 733 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 734 { 735 return desc->tx_submit(desc); 736 } 737 738 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) 739 { 740 size_t mask; 741 742 if (!align) 743 return true; 744 mask = (1 << align) - 1; 745 if (mask & (off1 | off2 | len)) 746 return false; 747 return true; 748 } 749 750 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 751 size_t off2, size_t len) 752 { 753 return dmaengine_check_align(dev->copy_align, off1, off2, len); 754 } 755 756 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 757 size_t off2, size_t len) 758 { 759 return dmaengine_check_align(dev->xor_align, off1, off2, len); 760 } 761 762 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 763 size_t off2, size_t len) 764 { 765 return dmaengine_check_align(dev->pq_align, off1, off2, len); 766 } 767 768 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 769 size_t off2, size_t len) 770 { 771 return dmaengine_check_align(dev->fill_align, off1, off2, len); 772 } 773 774 static inline void 775 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 776 { 777 dma->max_pq = maxpq; 778 if (has_pq_continue) 779 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 780 } 781 782 static inline bool dmaf_continue(enum dma_ctrl_flags flags) 783 { 784 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 785 } 786 787 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 788 { 789 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 790 791 return (flags & mask) == mask; 792 } 793 794 static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 795 { 796 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 797 } 798 799 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 800 { 801 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 802 } 803 804 /* dma_maxpq - reduce maxpq in the face of continued operations 805 * @dma - dma device with PQ capability 806 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 807 * 808 * When an engine does not support native continuation we need 3 extra 809 * source slots to reuse P and Q with the following coefficients: 810 * 1/ {00} * P : remove P from Q', but use it as a source for P' 811 * 2/ {01} * Q : use Q to continue Q' calculation 812 * 3/ {00} * Q : subtract Q from P' to cancel (2) 813 * 814 * In the case where P is disabled we only need 1 extra source: 815 * 1/ {01} * Q : use Q to continue Q' calculation 816 */ 817 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 818 { 819 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 820 return dma_dev_to_maxpq(dma); 821 else if (dmaf_p_disabled_continue(flags)) 822 return dma_dev_to_maxpq(dma) - 1; 823 else if (dmaf_continue(flags)) 824 return dma_dev_to_maxpq(dma) - 3; 825 BUG(); 826 } 827 828 /* --- public DMA engine API --- */ 829 830 #ifdef CONFIG_DMA_ENGINE 831 void dmaengine_get(void); 832 void dmaengine_put(void); 833 #else 834 static inline void dmaengine_get(void) 835 { 836 } 837 static inline void dmaengine_put(void) 838 { 839 } 840 #endif 841 842 #ifdef CONFIG_NET_DMA 843 #define net_dmaengine_get() dmaengine_get() 844 #define net_dmaengine_put() dmaengine_put() 845 #else 846 static inline void net_dmaengine_get(void) 847 { 848 } 849 static inline void net_dmaengine_put(void) 850 { 851 } 852 #endif 853 854 #ifdef CONFIG_ASYNC_TX_DMA 855 #define async_dmaengine_get() dmaengine_get() 856 #define async_dmaengine_put() dmaengine_put() 857 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 858 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 859 #else 860 #define async_dma_find_channel(type) dma_find_channel(type) 861 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 862 #else 863 static inline void async_dmaengine_get(void) 864 { 865 } 866 static inline void async_dmaengine_put(void) 867 { 868 } 869 static inline struct dma_chan * 870 async_dma_find_channel(enum dma_transaction_type type) 871 { 872 return NULL; 873 } 874 #endif /* CONFIG_ASYNC_TX_DMA */ 875 876 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, 877 void *dest, void *src, size_t len); 878 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, 879 struct page *page, unsigned int offset, void *kdata, size_t len); 880 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, 881 struct page *dest_pg, unsigned int dest_off, struct page *src_pg, 882 unsigned int src_off, size_t len); 883 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 884 struct dma_chan *chan); 885 886 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 887 { 888 tx->flags |= DMA_CTRL_ACK; 889 } 890 891 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 892 { 893 tx->flags &= ~DMA_CTRL_ACK; 894 } 895 896 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 897 { 898 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 899 } 900 901 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 902 static inline void 903 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 904 { 905 set_bit(tx_type, dstp->bits); 906 } 907 908 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 909 static inline void 910 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 911 { 912 clear_bit(tx_type, dstp->bits); 913 } 914 915 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 916 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 917 { 918 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 919 } 920 921 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 922 static inline int 923 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 924 { 925 return test_bit(tx_type, srcp->bits); 926 } 927 928 #define for_each_dma_cap_mask(cap, mask) \ 929 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 930 931 /** 932 * dma_async_issue_pending - flush pending transactions to HW 933 * @chan: target DMA channel 934 * 935 * This allows drivers to push copies to HW in batches, 936 * reducing MMIO writes where possible. 937 */ 938 static inline void dma_async_issue_pending(struct dma_chan *chan) 939 { 940 chan->device->device_issue_pending(chan); 941 } 942 943 /** 944 * dma_async_is_tx_complete - poll for transaction completion 945 * @chan: DMA channel 946 * @cookie: transaction identifier to check status of 947 * @last: returns last completed cookie, can be NULL 948 * @used: returns last issued cookie, can be NULL 949 * 950 * If @last and @used are passed in, upon return they reflect the driver 951 * internal state and can be used with dma_async_is_complete() to check 952 * the status of multiple cookies without re-checking hardware state. 953 */ 954 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 955 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 956 { 957 struct dma_tx_state state; 958 enum dma_status status; 959 960 status = chan->device->device_tx_status(chan, cookie, &state); 961 if (last) 962 *last = state.last; 963 if (used) 964 *used = state.used; 965 return status; 966 } 967 968 /** 969 * dma_async_is_complete - test a cookie against chan state 970 * @cookie: transaction identifier to test status of 971 * @last_complete: last know completed transaction 972 * @last_used: last cookie value handed out 973 * 974 * dma_async_is_complete() is used in dma_async_is_tx_complete() 975 * the test logic is separated for lightweight testing of multiple cookies 976 */ 977 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 978 dma_cookie_t last_complete, dma_cookie_t last_used) 979 { 980 if (last_complete <= last_used) { 981 if ((cookie <= last_complete) || (cookie > last_used)) 982 return DMA_SUCCESS; 983 } else { 984 if ((cookie <= last_complete) && (cookie > last_used)) 985 return DMA_SUCCESS; 986 } 987 return DMA_IN_PROGRESS; 988 } 989 990 static inline void 991 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 992 { 993 if (st) { 994 st->last = last; 995 st->used = used; 996 st->residue = residue; 997 } 998 } 999 1000 #ifdef CONFIG_DMA_ENGINE 1001 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1002 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1003 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1004 void dma_issue_pending_all(void); 1005 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1006 dma_filter_fn fn, void *fn_param); 1007 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1008 void dma_release_channel(struct dma_chan *chan); 1009 #else 1010 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1011 { 1012 return NULL; 1013 } 1014 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1015 { 1016 return DMA_SUCCESS; 1017 } 1018 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1019 { 1020 return DMA_SUCCESS; 1021 } 1022 static inline void dma_issue_pending_all(void) 1023 { 1024 } 1025 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1026 dma_filter_fn fn, void *fn_param) 1027 { 1028 return NULL; 1029 } 1030 static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1031 const char *name) 1032 { 1033 return NULL; 1034 } 1035 static inline void dma_release_channel(struct dma_chan *chan) 1036 { 1037 } 1038 #endif 1039 1040 /* --- DMA device --- */ 1041 1042 int dma_async_device_register(struct dma_device *device); 1043 void dma_async_device_unregister(struct dma_device *device); 1044 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1045 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); 1046 struct dma_chan *net_dma_find_channel(void); 1047 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 1048 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ 1049 __dma_request_slave_channel_compat(&(mask), x, y, dev, name) 1050 1051 static inline struct dma_chan 1052 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, 1053 dma_filter_fn fn, void *fn_param, 1054 struct device *dev, char *name) 1055 { 1056 struct dma_chan *chan; 1057 1058 chan = dma_request_slave_channel(dev, name); 1059 if (chan) 1060 return chan; 1061 1062 return __dma_request_channel(mask, fn, fn_param); 1063 } 1064 1065 /* --- Helper iov-locking functions --- */ 1066 1067 struct dma_page_list { 1068 char __user *base_address; 1069 int nr_pages; 1070 struct page **pages; 1071 }; 1072 1073 struct dma_pinned_list { 1074 int nr_iovecs; 1075 struct dma_page_list page_list[0]; 1076 }; 1077 1078 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); 1079 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); 1080 1081 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, 1082 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); 1083 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, 1084 struct dma_pinned_list *pinned_list, struct page *page, 1085 unsigned int offset, size_t len); 1086 1087 #endif /* DMAENGINE_H */ 1088
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