~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/include/linux/dmaengine.h

Version: ~ [ linux-5.2 ] ~ [ linux-5.1.16 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.57 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.132 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.184 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.184 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.69 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms of the GNU General Public License as published by the Free
  6  * Software Foundation; either version 2 of the License, or (at your option)
  7  * any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * The full GNU General Public License is included in this distribution in the
 15  * file called COPYING.
 16  */
 17 #ifndef LINUX_DMAENGINE_H
 18 #define LINUX_DMAENGINE_H
 19 
 20 #include <linux/device.h>
 21 #include <linux/err.h>
 22 #include <linux/uio.h>
 23 #include <linux/bug.h>
 24 #include <linux/scatterlist.h>
 25 #include <linux/bitmap.h>
 26 #include <linux/types.h>
 27 #include <asm/page.h>
 28 
 29 /**
 30  * typedef dma_cookie_t - an opaque DMA cookie
 31  *
 32  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 33  */
 34 typedef s32 dma_cookie_t;
 35 #define DMA_MIN_COOKIE  1
 36 
 37 static inline int dma_submit_error(dma_cookie_t cookie)
 38 {
 39         return cookie < 0 ? cookie : 0;
 40 }
 41 
 42 /**
 43  * enum dma_status - DMA transaction status
 44  * @DMA_COMPLETE: transaction completed
 45  * @DMA_IN_PROGRESS: transaction not yet processed
 46  * @DMA_PAUSED: transaction is paused
 47  * @DMA_ERROR: transaction failed
 48  */
 49 enum dma_status {
 50         DMA_COMPLETE,
 51         DMA_IN_PROGRESS,
 52         DMA_PAUSED,
 53         DMA_ERROR,
 54 };
 55 
 56 /**
 57  * enum dma_transaction_type - DMA transaction types/indexes
 58  *
 59  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 60  * automatically set as dma devices are registered.
 61  */
 62 enum dma_transaction_type {
 63         DMA_MEMCPY,
 64         DMA_XOR,
 65         DMA_PQ,
 66         DMA_XOR_VAL,
 67         DMA_PQ_VAL,
 68         DMA_MEMSET,
 69         DMA_MEMSET_SG,
 70         DMA_INTERRUPT,
 71         DMA_PRIVATE,
 72         DMA_ASYNC_TX,
 73         DMA_SLAVE,
 74         DMA_CYCLIC,
 75         DMA_INTERLEAVE,
 76 /* last transaction type for creation of the capabilities mask */
 77         DMA_TX_TYPE_END,
 78 };
 79 
 80 /**
 81  * enum dma_transfer_direction - dma transfer mode and direction indicator
 82  * @DMA_MEM_TO_MEM: Async/Memcpy mode
 83  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 84  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 85  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 86  */
 87 enum dma_transfer_direction {
 88         DMA_MEM_TO_MEM,
 89         DMA_MEM_TO_DEV,
 90         DMA_DEV_TO_MEM,
 91         DMA_DEV_TO_DEV,
 92         DMA_TRANS_NONE,
 93 };
 94 
 95 /**
 96  * Interleaved Transfer Request
 97  * ----------------------------
 98  * A chunk is collection of contiguous bytes to be transfered.
 99  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100  * ICGs may or maynot change between chunks.
101  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102  *  that when repeated an integral number of times, specifies the transfer.
103  * A transfer template is specification of a Frame, the number of times
104  *  it is to be repeated and other per-transfer attributes.
105  *
106  * Practically, a client driver would have ready a template for each
107  *  type of transfer it is going to need during its lifetime and
108  *  set only 'src_start' and 'dst_start' before submitting the requests.
109  *
110  *
111  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
112  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
113  *
114  *    ==  Chunk size
115  *    ... ICG
116  */
117 
118 /**
119  * struct data_chunk - Element of scatter-gather list that makes a frame.
120  * @size: Number of bytes to read from source.
121  *        size_dst := fn(op, size_src), so doesn't mean much for destination.
122  * @icg: Number of bytes to jump after last src/dst address of this
123  *       chunk and before first src/dst address for next chunk.
124  *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125  *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
126  * @dst_icg: Number of bytes to jump after last dst address of this
127  *       chunk and before the first dst address for next chunk.
128  *       Ignored if dst_inc is true and dst_sgl is false.
129  * @src_icg: Number of bytes to jump after last src address of this
130  *       chunk and before the first src address for next chunk.
131  *       Ignored if src_inc is true and src_sgl is false.
132  */
133 struct data_chunk {
134         size_t size;
135         size_t icg;
136         size_t dst_icg;
137         size_t src_icg;
138 };
139 
140 /**
141  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
142  *       and attributes.
143  * @src_start: Bus address of source for the first chunk.
144  * @dst_start: Bus address of destination for the first chunk.
145  * @dir: Specifies the type of Source and Destination.
146  * @src_inc: If the source address increments after reading from it.
147  * @dst_inc: If the destination address increments after writing to it.
148  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
149  *              Otherwise, source is read contiguously (icg ignored).
150  *              Ignored if src_inc is false.
151  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
152  *              Otherwise, destination is filled contiguously (icg ignored).
153  *              Ignored if dst_inc is false.
154  * @numf: Number of frames in this template.
155  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
156  * @sgl: Array of {chunk,icg} pairs that make up a frame.
157  */
158 struct dma_interleaved_template {
159         dma_addr_t src_start;
160         dma_addr_t dst_start;
161         enum dma_transfer_direction dir;
162         bool src_inc;
163         bool dst_inc;
164         bool src_sgl;
165         bool dst_sgl;
166         size_t numf;
167         size_t frame_size;
168         struct data_chunk sgl[0];
169 };
170 
171 /**
172  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
173  *  control completion, and communicate status.
174  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
175  *  this transaction
176  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
177  *  acknowledges receipt, i.e. has has a chance to establish any dependency
178  *  chains
179  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
180  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
181  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
182  *  sources that were the result of a previous operation, in the case of a PQ
183  *  operation it continues the calculation with new sources
184  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
185  *  on the result of this operation
186  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
187  *  cleared or freed
188  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
189  *  data and the descriptor should be in different format from normal
190  *  data descriptors.
191  */
192 enum dma_ctrl_flags {
193         DMA_PREP_INTERRUPT = (1 << 0),
194         DMA_CTRL_ACK = (1 << 1),
195         DMA_PREP_PQ_DISABLE_P = (1 << 2),
196         DMA_PREP_PQ_DISABLE_Q = (1 << 3),
197         DMA_PREP_CONTINUE = (1 << 4),
198         DMA_PREP_FENCE = (1 << 5),
199         DMA_CTRL_REUSE = (1 << 6),
200         DMA_PREP_CMD = (1 << 7),
201 };
202 
203 /**
204  * enum sum_check_bits - bit position of pq_check_flags
205  */
206 enum sum_check_bits {
207         SUM_CHECK_P = 0,
208         SUM_CHECK_Q = 1,
209 };
210 
211 /**
212  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
213  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
214  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
215  */
216 enum sum_check_flags {
217         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
218         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
219 };
220 
221 
222 /**
223  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
224  * See linux/cpumask.h
225  */
226 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
227 
228 /**
229  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
230  * @memcpy_count: transaction counter
231  * @bytes_transferred: byte counter
232  */
233 
234 struct dma_chan_percpu {
235         /* stats */
236         unsigned long memcpy_count;
237         unsigned long bytes_transferred;
238 };
239 
240 /**
241  * struct dma_router - DMA router structure
242  * @dev: pointer to the DMA router device
243  * @route_free: function to be called when the route can be disconnected
244  */
245 struct dma_router {
246         struct device *dev;
247         void (*route_free)(struct device *dev, void *route_data);
248 };
249 
250 /**
251  * struct dma_chan - devices supply DMA channels, clients use them
252  * @device: ptr to the dma device who supplies this channel, always !%NULL
253  * @cookie: last cookie value returned to client
254  * @completed_cookie: last completed cookie for this channel
255  * @chan_id: channel ID for sysfs
256  * @dev: class device for sysfs
257  * @device_node: used to add this to the device chan list
258  * @local: per-cpu pointer to a struct dma_chan_percpu
259  * @client_count: how many clients are using this channel
260  * @table_count: number of appearances in the mem-to-mem allocation table
261  * @router: pointer to the DMA router structure
262  * @route_data: channel specific data for the router
263  * @private: private data for certain client-channel associations
264  */
265 struct dma_chan {
266         struct dma_device *device;
267         dma_cookie_t cookie;
268         dma_cookie_t completed_cookie;
269 
270         /* sysfs */
271         int chan_id;
272         struct dma_chan_dev *dev;
273 
274         struct list_head device_node;
275         struct dma_chan_percpu __percpu *local;
276         int client_count;
277         int table_count;
278 
279         /* DMA router */
280         struct dma_router *router;
281         void *route_data;
282 
283         void *private;
284 };
285 
286 /**
287  * struct dma_chan_dev - relate sysfs device node to backing channel device
288  * @chan: driver channel device
289  * @device: sysfs device
290  * @dev_id: parent dma_device dev_id
291  * @idr_ref: reference count to gate release of dma_device dev_id
292  */
293 struct dma_chan_dev {
294         struct dma_chan *chan;
295         struct device device;
296         int dev_id;
297         atomic_t *idr_ref;
298 };
299 
300 /**
301  * enum dma_slave_buswidth - defines bus width of the DMA slave
302  * device, source or target buses
303  */
304 enum dma_slave_buswidth {
305         DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
306         DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
307         DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
308         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
309         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
310         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
311         DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
312         DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
313         DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
314 };
315 
316 /**
317  * struct dma_slave_config - dma slave channel runtime config
318  * @direction: whether the data shall go in or out on this slave
319  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
320  * legal values. DEPRECATED, drivers should use the direction argument
321  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
322  * the dir field in the dma_interleaved_template structure.
323  * @src_addr: this is the physical address where DMA slave data
324  * should be read (RX), if the source is memory this argument is
325  * ignored.
326  * @dst_addr: this is the physical address where DMA slave data
327  * should be written (TX), if the source is memory this argument
328  * is ignored.
329  * @src_addr_width: this is the width in bytes of the source (RX)
330  * register where DMA data shall be read. If the source
331  * is memory this may be ignored depending on architecture.
332  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
333  * @dst_addr_width: same as src_addr_width but for destination
334  * target (TX) mutatis mutandis.
335  * @src_maxburst: the maximum number of words (note: words, as in
336  * units of the src_addr_width member, not bytes) that can be sent
337  * in one burst to the device. Typically something like half the
338  * FIFO depth on I/O peripherals so you don't overflow it. This
339  * may or may not be applicable on memory sources.
340  * @dst_maxburst: same as src_maxburst but for destination target
341  * mutatis mutandis.
342  * @src_port_window_size: The length of the register area in words the data need
343  * to be accessed on the device side. It is only used for devices which is using
344  * an area instead of a single register to receive the data. Typically the DMA
345  * loops in this area in order to transfer the data.
346  * @dst_port_window_size: same as src_port_window_size but for the destination
347  * port.
348  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
349  * with 'true' if peripheral should be flow controller. Direction will be
350  * selected at Runtime.
351  * @slave_id: Slave requester id. Only valid for slave channels. The dma
352  * slave peripheral will have unique id as dma requester which need to be
353  * pass as slave config.
354  *
355  * This struct is passed in as configuration data to a DMA engine
356  * in order to set up a certain channel for DMA transport at runtime.
357  * The DMA device/engine has to provide support for an additional
358  * callback in the dma_device structure, device_config and this struct
359  * will then be passed in as an argument to the function.
360  *
361  * The rationale for adding configuration information to this struct is as
362  * follows: if it is likely that more than one DMA slave controllers in
363  * the world will support the configuration option, then make it generic.
364  * If not: if it is fixed so that it be sent in static from the platform
365  * data, then prefer to do that.
366  */
367 struct dma_slave_config {
368         enum dma_transfer_direction direction;
369         phys_addr_t src_addr;
370         phys_addr_t dst_addr;
371         enum dma_slave_buswidth src_addr_width;
372         enum dma_slave_buswidth dst_addr_width;
373         u32 src_maxburst;
374         u32 dst_maxburst;
375         u32 src_port_window_size;
376         u32 dst_port_window_size;
377         bool device_fc;
378         unsigned int slave_id;
379 };
380 
381 /**
382  * enum dma_residue_granularity - Granularity of the reported transfer residue
383  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
384  *  DMA channel is only able to tell whether a descriptor has been completed or
385  *  not, which means residue reporting is not supported by this channel. The
386  *  residue field of the dma_tx_state field will always be 0.
387  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
388  *  completed segment of the transfer (For cyclic transfers this is after each
389  *  period). This is typically implemented by having the hardware generate an
390  *  interrupt after each transferred segment and then the drivers updates the
391  *  outstanding residue by the size of the segment. Another possibility is if
392  *  the hardware supports scatter-gather and the segment descriptor has a field
393  *  which gets set after the segment has been completed. The driver then counts
394  *  the number of segments without the flag set to compute the residue.
395  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
396  *  burst. This is typically only supported if the hardware has a progress
397  *  register of some sort (E.g. a register with the current read/write address
398  *  or a register with the amount of bursts/beats/bytes that have been
399  *  transferred or still need to be transferred).
400  */
401 enum dma_residue_granularity {
402         DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
403         DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
404         DMA_RESIDUE_GRANULARITY_BURST = 2,
405 };
406 
407 /**
408  * struct dma_slave_caps - expose capabilities of a slave channel only
409  * @src_addr_widths: bit mask of src addr widths the channel supports.
410  *      Width is specified in bytes, e.g. for a channel supporting
411  *      a width of 4 the mask should have BIT(4) set.
412  * @dst_addr_widths: bit mask of dst addr widths the channel supports
413  * @directions: bit mask of slave directions the channel supports.
414  *      Since the enum dma_transfer_direction is not defined as bit flag for
415  *      each type, the dma controller should set BIT(<TYPE>) and same
416  *      should be checked by controller as well
417  * @max_burst: max burst capability per-transfer
418  * @cmd_pause: true, if pause and thereby resume is supported
419  * @cmd_terminate: true, if terminate cmd is supported
420  * @residue_granularity: granularity of the reported transfer residue
421  * @descriptor_reuse: if a descriptor can be reused by client and
422  * resubmitted multiple times
423  */
424 struct dma_slave_caps {
425         u32 src_addr_widths;
426         u32 dst_addr_widths;
427         u32 directions;
428         u32 max_burst;
429         bool cmd_pause;
430         bool cmd_terminate;
431         enum dma_residue_granularity residue_granularity;
432         bool descriptor_reuse;
433 };
434 
435 static inline const char *dma_chan_name(struct dma_chan *chan)
436 {
437         return dev_name(&chan->dev->device);
438 }
439 
440 void dma_chan_cleanup(struct kref *kref);
441 
442 /**
443  * typedef dma_filter_fn - callback filter for dma_request_channel
444  * @chan: channel to be reviewed
445  * @filter_param: opaque parameter passed through dma_request_channel
446  *
447  * When this optional parameter is specified in a call to dma_request_channel a
448  * suitable channel is passed to this routine for further dispositioning before
449  * being returned.  Where 'suitable' indicates a non-busy channel that
450  * satisfies the given capability mask.  It returns 'true' to indicate that the
451  * channel is suitable.
452  */
453 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
454 
455 typedef void (*dma_async_tx_callback)(void *dma_async_param);
456 
457 enum dmaengine_tx_result {
458         DMA_TRANS_NOERROR = 0,          /* SUCCESS */
459         DMA_TRANS_READ_FAILED,          /* Source DMA read failed */
460         DMA_TRANS_WRITE_FAILED,         /* Destination DMA write failed */
461         DMA_TRANS_ABORTED,              /* Op never submitted / aborted */
462 };
463 
464 struct dmaengine_result {
465         enum dmaengine_tx_result result;
466         u32 residue;
467 };
468 
469 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
470                                 const struct dmaengine_result *result);
471 
472 struct dmaengine_unmap_data {
473         u8 map_cnt;
474         u8 to_cnt;
475         u8 from_cnt;
476         u8 bidi_cnt;
477         struct device *dev;
478         struct kref kref;
479         size_t len;
480         dma_addr_t addr[0];
481 };
482 
483 /**
484  * struct dma_async_tx_descriptor - async transaction descriptor
485  * ---dma generic offload fields---
486  * @cookie: tracking cookie for this transaction, set to -EBUSY if
487  *      this tx is sitting on a dependency list
488  * @flags: flags to augment operation preparation, control completion, and
489  *      communicate status
490  * @phys: physical address of the descriptor
491  * @chan: target channel for this operation
492  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
493  * descriptor pending. To be pushed on .issue_pending() call
494  * @callback: routine to call after this operation is complete
495  * @callback_param: general parameter to pass to the callback routine
496  * ---async_tx api specific fields---
497  * @next: at completion submit this descriptor
498  * @parent: pointer to the next level up in the dependency chain
499  * @lock: protect the parent and next pointers
500  */
501 struct dma_async_tx_descriptor {
502         dma_cookie_t cookie;
503         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
504         dma_addr_t phys;
505         struct dma_chan *chan;
506         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
507         int (*desc_free)(struct dma_async_tx_descriptor *tx);
508         dma_async_tx_callback callback;
509         dma_async_tx_callback_result callback_result;
510         void *callback_param;
511         struct dmaengine_unmap_data *unmap;
512 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
513         struct dma_async_tx_descriptor *next;
514         struct dma_async_tx_descriptor *parent;
515         spinlock_t lock;
516 #endif
517 };
518 
519 #ifdef CONFIG_DMA_ENGINE
520 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
521                                  struct dmaengine_unmap_data *unmap)
522 {
523         kref_get(&unmap->kref);
524         tx->unmap = unmap;
525 }
526 
527 struct dmaengine_unmap_data *
528 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
529 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
530 #else
531 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
532                                  struct dmaengine_unmap_data *unmap)
533 {
534 }
535 static inline struct dmaengine_unmap_data *
536 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
537 {
538         return NULL;
539 }
540 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
541 {
542 }
543 #endif
544 
545 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
546 {
547         if (tx->unmap) {
548                 dmaengine_unmap_put(tx->unmap);
549                 tx->unmap = NULL;
550         }
551 }
552 
553 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
554 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
555 {
556 }
557 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
558 {
559 }
560 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
561 {
562         BUG();
563 }
564 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
565 {
566 }
567 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
568 {
569 }
570 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
571 {
572         return NULL;
573 }
574 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
575 {
576         return NULL;
577 }
578 
579 #else
580 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
581 {
582         spin_lock_bh(&txd->lock);
583 }
584 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
585 {
586         spin_unlock_bh(&txd->lock);
587 }
588 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
589 {
590         txd->next = next;
591         next->parent = txd;
592 }
593 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
594 {
595         txd->parent = NULL;
596 }
597 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
598 {
599         txd->next = NULL;
600 }
601 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
602 {
603         return txd->parent;
604 }
605 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
606 {
607         return txd->next;
608 }
609 #endif
610 
611 /**
612  * struct dma_tx_state - filled in to report the status of
613  * a transfer.
614  * @last: last completed DMA cookie
615  * @used: last issued DMA cookie (i.e. the one in progress)
616  * @residue: the remaining number of bytes left to transmit
617  *      on the selected transfer for states DMA_IN_PROGRESS and
618  *      DMA_PAUSED if this is implemented in the driver, else 0
619  */
620 struct dma_tx_state {
621         dma_cookie_t last;
622         dma_cookie_t used;
623         u32 residue;
624 };
625 
626 /**
627  * enum dmaengine_alignment - defines alignment of the DMA async tx
628  * buffers
629  */
630 enum dmaengine_alignment {
631         DMAENGINE_ALIGN_1_BYTE = 0,
632         DMAENGINE_ALIGN_2_BYTES = 1,
633         DMAENGINE_ALIGN_4_BYTES = 2,
634         DMAENGINE_ALIGN_8_BYTES = 3,
635         DMAENGINE_ALIGN_16_BYTES = 4,
636         DMAENGINE_ALIGN_32_BYTES = 5,
637         DMAENGINE_ALIGN_64_BYTES = 6,
638 };
639 
640 /**
641  * struct dma_slave_map - associates slave device and it's slave channel with
642  * parameter to be used by a filter function
643  * @devname: name of the device
644  * @slave: slave channel name
645  * @param: opaque parameter to pass to struct dma_filter.fn
646  */
647 struct dma_slave_map {
648         const char *devname;
649         const char *slave;
650         void *param;
651 };
652 
653 /**
654  * struct dma_filter - information for slave device/channel to filter_fn/param
655  * mapping
656  * @fn: filter function callback
657  * @mapcnt: number of slave device/channel in the map
658  * @map: array of channel to filter mapping data
659  */
660 struct dma_filter {
661         dma_filter_fn fn;
662         int mapcnt;
663         const struct dma_slave_map *map;
664 };
665 
666 /**
667  * struct dma_device - info on the entity supplying DMA services
668  * @chancnt: how many DMA channels are supported
669  * @privatecnt: how many DMA channels are requested by dma_request_channel
670  * @channels: the list of struct dma_chan
671  * @global_node: list_head for global dma_device_list
672  * @filter: information for device/slave to filter function/param mapping
673  * @cap_mask: one or more dma_capability flags
674  * @max_xor: maximum number of xor sources, 0 if no capability
675  * @max_pq: maximum number of PQ sources and PQ-continue capability
676  * @copy_align: alignment shift for memcpy operations
677  * @xor_align: alignment shift for xor operations
678  * @pq_align: alignment shift for pq operations
679  * @fill_align: alignment shift for memset operations
680  * @dev_id: unique device ID
681  * @dev: struct device reference for dma mapping api
682  * @src_addr_widths: bit mask of src addr widths the device supports
683  *      Width is specified in bytes, e.g. for a device supporting
684  *      a width of 4 the mask should have BIT(4) set.
685  * @dst_addr_widths: bit mask of dst addr widths the device supports
686  * @directions: bit mask of slave directions the device supports.
687  *      Since the enum dma_transfer_direction is not defined as bit flag for
688  *      each type, the dma controller should set BIT(<TYPE>) and same
689  *      should be checked by controller as well
690  * @max_burst: max burst capability per-transfer
691  * @residue_granularity: granularity of the transfer residue reported
692  *      by tx_status
693  * @device_alloc_chan_resources: allocate resources and return the
694  *      number of allocated descriptors
695  * @device_free_chan_resources: release DMA channel's resources
696  * @device_prep_dma_memcpy: prepares a memcpy operation
697  * @device_prep_dma_xor: prepares a xor operation
698  * @device_prep_dma_xor_val: prepares a xor validation operation
699  * @device_prep_dma_pq: prepares a pq operation
700  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
701  * @device_prep_dma_memset: prepares a memset operation
702  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
703  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
704  * @device_prep_slave_sg: prepares a slave dma operation
705  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
706  *      The function takes a buffer of size buf_len. The callback function will
707  *      be called after period_len bytes have been transferred.
708  * @device_prep_interleaved_dma: Transfer expression in a generic way.
709  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
710  * @device_config: Pushes a new configuration to a channel, return 0 or an error
711  *      code
712  * @device_pause: Pauses any transfer happening on a channel. Returns
713  *      0 or an error code
714  * @device_resume: Resumes any transfer on a channel previously
715  *      paused. Returns 0 or an error code
716  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
717  *      or an error code
718  * @device_synchronize: Synchronizes the termination of a transfers to the
719  *  current context.
720  * @device_tx_status: poll for transaction completion, the optional
721  *      txstate parameter can be supplied with a pointer to get a
722  *      struct with auxiliary transfer status information, otherwise the call
723  *      will just return a simple status code
724  * @device_issue_pending: push pending transactions to hardware
725  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
726  */
727 struct dma_device {
728 
729         unsigned int chancnt;
730         unsigned int privatecnt;
731         struct list_head channels;
732         struct list_head global_node;
733         struct dma_filter filter;
734         dma_cap_mask_t  cap_mask;
735         unsigned short max_xor;
736         unsigned short max_pq;
737         enum dmaengine_alignment copy_align;
738         enum dmaengine_alignment xor_align;
739         enum dmaengine_alignment pq_align;
740         enum dmaengine_alignment fill_align;
741         #define DMA_HAS_PQ_CONTINUE (1 << 15)
742 
743         int dev_id;
744         struct device *dev;
745 
746         u32 src_addr_widths;
747         u32 dst_addr_widths;
748         u32 directions;
749         u32 max_burst;
750         bool descriptor_reuse;
751         enum dma_residue_granularity residue_granularity;
752 
753         int (*device_alloc_chan_resources)(struct dma_chan *chan);
754         void (*device_free_chan_resources)(struct dma_chan *chan);
755 
756         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
757                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
758                 size_t len, unsigned long flags);
759         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
760                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
761                 unsigned int src_cnt, size_t len, unsigned long flags);
762         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
763                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
764                 size_t len, enum sum_check_flags *result, unsigned long flags);
765         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
766                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
767                 unsigned int src_cnt, const unsigned char *scf,
768                 size_t len, unsigned long flags);
769         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
770                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
771                 unsigned int src_cnt, const unsigned char *scf, size_t len,
772                 enum sum_check_flags *pqres, unsigned long flags);
773         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
774                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
775                 unsigned long flags);
776         struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
777                 struct dma_chan *chan, struct scatterlist *sg,
778                 unsigned int nents, int value, unsigned long flags);
779         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
780                 struct dma_chan *chan, unsigned long flags);
781 
782         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
783                 struct dma_chan *chan, struct scatterlist *sgl,
784                 unsigned int sg_len, enum dma_transfer_direction direction,
785                 unsigned long flags, void *context);
786         struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
787                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
788                 size_t period_len, enum dma_transfer_direction direction,
789                 unsigned long flags);
790         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
791                 struct dma_chan *chan, struct dma_interleaved_template *xt,
792                 unsigned long flags);
793         struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
794                 struct dma_chan *chan, dma_addr_t dst, u64 data,
795                 unsigned long flags);
796 
797         int (*device_config)(struct dma_chan *chan,
798                              struct dma_slave_config *config);
799         int (*device_pause)(struct dma_chan *chan);
800         int (*device_resume)(struct dma_chan *chan);
801         int (*device_terminate_all)(struct dma_chan *chan);
802         void (*device_synchronize)(struct dma_chan *chan);
803 
804         enum dma_status (*device_tx_status)(struct dma_chan *chan,
805                                             dma_cookie_t cookie,
806                                             struct dma_tx_state *txstate);
807         void (*device_issue_pending)(struct dma_chan *chan);
808 };
809 
810 static inline int dmaengine_slave_config(struct dma_chan *chan,
811                                           struct dma_slave_config *config)
812 {
813         if (chan->device->device_config)
814                 return chan->device->device_config(chan, config);
815 
816         return -ENOSYS;
817 }
818 
819 static inline bool is_slave_direction(enum dma_transfer_direction direction)
820 {
821         return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
822 }
823 
824 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
825         struct dma_chan *chan, dma_addr_t buf, size_t len,
826         enum dma_transfer_direction dir, unsigned long flags)
827 {
828         struct scatterlist sg;
829         sg_init_table(&sg, 1);
830         sg_dma_address(&sg) = buf;
831         sg_dma_len(&sg) = len;
832 
833         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
834                 return NULL;
835 
836         return chan->device->device_prep_slave_sg(chan, &sg, 1,
837                                                   dir, flags, NULL);
838 }
839 
840 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
841         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
842         enum dma_transfer_direction dir, unsigned long flags)
843 {
844         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
845                 return NULL;
846 
847         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
848                                                   dir, flags, NULL);
849 }
850 
851 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
852 struct rio_dma_ext;
853 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
854         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
855         enum dma_transfer_direction dir, unsigned long flags,
856         struct rio_dma_ext *rio_ext)
857 {
858         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
859                 return NULL;
860 
861         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
862                                                   dir, flags, rio_ext);
863 }
864 #endif
865 
866 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
867                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
868                 size_t period_len, enum dma_transfer_direction dir,
869                 unsigned long flags)
870 {
871         if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
872                 return NULL;
873 
874         return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
875                                                 period_len, dir, flags);
876 }
877 
878 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
879                 struct dma_chan *chan, struct dma_interleaved_template *xt,
880                 unsigned long flags)
881 {
882         if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
883                 return NULL;
884 
885         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
886 }
887 
888 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
889                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
890                 unsigned long flags)
891 {
892         if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
893                 return NULL;
894 
895         return chan->device->device_prep_dma_memset(chan, dest, value,
896                                                     len, flags);
897 }
898 
899 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
900                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
901                 size_t len, unsigned long flags)
902 {
903         if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
904                 return NULL;
905 
906         return chan->device->device_prep_dma_memcpy(chan, dest, src,
907                                                     len, flags);
908 }
909 
910 /**
911  * dmaengine_terminate_all() - Terminate all active DMA transfers
912  * @chan: The channel for which to terminate the transfers
913  *
914  * This function is DEPRECATED use either dmaengine_terminate_sync() or
915  * dmaengine_terminate_async() instead.
916  */
917 static inline int dmaengine_terminate_all(struct dma_chan *chan)
918 {
919         if (chan->device->device_terminate_all)
920                 return chan->device->device_terminate_all(chan);
921 
922         return -ENOSYS;
923 }
924 
925 /**
926  * dmaengine_terminate_async() - Terminate all active DMA transfers
927  * @chan: The channel for which to terminate the transfers
928  *
929  * Calling this function will terminate all active and pending descriptors
930  * that have previously been submitted to the channel. It is not guaranteed
931  * though that the transfer for the active descriptor has stopped when the
932  * function returns. Furthermore it is possible the complete callback of a
933  * submitted transfer is still running when this function returns.
934  *
935  * dmaengine_synchronize() needs to be called before it is safe to free
936  * any memory that is accessed by previously submitted descriptors or before
937  * freeing any resources accessed from within the completion callback of any
938  * perviously submitted descriptors.
939  *
940  * This function can be called from atomic context as well as from within a
941  * complete callback of a descriptor submitted on the same channel.
942  *
943  * If none of the two conditions above apply consider using
944  * dmaengine_terminate_sync() instead.
945  */
946 static inline int dmaengine_terminate_async(struct dma_chan *chan)
947 {
948         if (chan->device->device_terminate_all)
949                 return chan->device->device_terminate_all(chan);
950 
951         return -EINVAL;
952 }
953 
954 /**
955  * dmaengine_synchronize() - Synchronize DMA channel termination
956  * @chan: The channel to synchronize
957  *
958  * Synchronizes to the DMA channel termination to the current context. When this
959  * function returns it is guaranteed that all transfers for previously issued
960  * descriptors have stopped and and it is safe to free the memory assoicated
961  * with them. Furthermore it is guaranteed that all complete callback functions
962  * for a previously submitted descriptor have finished running and it is safe to
963  * free resources accessed from within the complete callbacks.
964  *
965  * The behavior of this function is undefined if dma_async_issue_pending() has
966  * been called between dmaengine_terminate_async() and this function.
967  *
968  * This function must only be called from non-atomic context and must not be
969  * called from within a complete callback of a descriptor submitted on the same
970  * channel.
971  */
972 static inline void dmaengine_synchronize(struct dma_chan *chan)
973 {
974         might_sleep();
975 
976         if (chan->device->device_synchronize)
977                 chan->device->device_synchronize(chan);
978 }
979 
980 /**
981  * dmaengine_terminate_sync() - Terminate all active DMA transfers
982  * @chan: The channel for which to terminate the transfers
983  *
984  * Calling this function will terminate all active and pending transfers
985  * that have previously been submitted to the channel. It is similar to
986  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
987  * stopped and that all complete callbacks have finished running when the
988  * function returns.
989  *
990  * This function must only be called from non-atomic context and must not be
991  * called from within a complete callback of a descriptor submitted on the same
992  * channel.
993  */
994 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
995 {
996         int ret;
997 
998         ret = dmaengine_terminate_async(chan);
999         if (ret)
1000                 return ret;
1001 
1002         dmaengine_synchronize(chan);
1003 
1004         return 0;
1005 }
1006 
1007 static inline int dmaengine_pause(struct dma_chan *chan)
1008 {
1009         if (chan->device->device_pause)
1010                 return chan->device->device_pause(chan);
1011 
1012         return -ENOSYS;
1013 }
1014 
1015 static inline int dmaengine_resume(struct dma_chan *chan)
1016 {
1017         if (chan->device->device_resume)
1018                 return chan->device->device_resume(chan);
1019 
1020         return -ENOSYS;
1021 }
1022 
1023 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1024         dma_cookie_t cookie, struct dma_tx_state *state)
1025 {
1026         return chan->device->device_tx_status(chan, cookie, state);
1027 }
1028 
1029 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1030 {
1031         return desc->tx_submit(desc);
1032 }
1033 
1034 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1035                                          size_t off1, size_t off2, size_t len)
1036 {
1037         size_t mask;
1038 
1039         if (!align)
1040                 return true;
1041         mask = (1 << align) - 1;
1042         if (mask & (off1 | off2 | len))
1043                 return false;
1044         return true;
1045 }
1046 
1047 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1048                                        size_t off2, size_t len)
1049 {
1050         return dmaengine_check_align(dev->copy_align, off1, off2, len);
1051 }
1052 
1053 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1054                                       size_t off2, size_t len)
1055 {
1056         return dmaengine_check_align(dev->xor_align, off1, off2, len);
1057 }
1058 
1059 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1060                                      size_t off2, size_t len)
1061 {
1062         return dmaengine_check_align(dev->pq_align, off1, off2, len);
1063 }
1064 
1065 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1066                                        size_t off2, size_t len)
1067 {
1068         return dmaengine_check_align(dev->fill_align, off1, off2, len);
1069 }
1070 
1071 static inline void
1072 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1073 {
1074         dma->max_pq = maxpq;
1075         if (has_pq_continue)
1076                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1077 }
1078 
1079 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1080 {
1081         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1082 }
1083 
1084 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1085 {
1086         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1087 
1088         return (flags & mask) == mask;
1089 }
1090 
1091 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1092 {
1093         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1094 }
1095 
1096 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1097 {
1098         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1099 }
1100 
1101 /* dma_maxpq - reduce maxpq in the face of continued operations
1102  * @dma - dma device with PQ capability
1103  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1104  *
1105  * When an engine does not support native continuation we need 3 extra
1106  * source slots to reuse P and Q with the following coefficients:
1107  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1108  * 2/ {01} * Q : use Q to continue Q' calculation
1109  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1110  *
1111  * In the case where P is disabled we only need 1 extra source:
1112  * 1/ {01} * Q : use Q to continue Q' calculation
1113  */
1114 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1115 {
1116         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1117                 return dma_dev_to_maxpq(dma);
1118         else if (dmaf_p_disabled_continue(flags))
1119                 return dma_dev_to_maxpq(dma) - 1;
1120         else if (dmaf_continue(flags))
1121                 return dma_dev_to_maxpq(dma) - 3;
1122         BUG();
1123 }
1124 
1125 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1126                                       size_t dir_icg)
1127 {
1128         if (inc) {
1129                 if (dir_icg)
1130                         return dir_icg;
1131                 else if (sgl)
1132                         return icg;
1133         }
1134 
1135         return 0;
1136 }
1137 
1138 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1139                                            struct data_chunk *chunk)
1140 {
1141         return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1142                                  chunk->icg, chunk->dst_icg);
1143 }
1144 
1145 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1146                                            struct data_chunk *chunk)
1147 {
1148         return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1149                                  chunk->icg, chunk->src_icg);
1150 }
1151 
1152 /* --- public DMA engine API --- */
1153 
1154 #ifdef CONFIG_DMA_ENGINE
1155 void dmaengine_get(void);
1156 void dmaengine_put(void);
1157 #else
1158 static inline void dmaengine_get(void)
1159 {
1160 }
1161 static inline void dmaengine_put(void)
1162 {
1163 }
1164 #endif
1165 
1166 #ifdef CONFIG_ASYNC_TX_DMA
1167 #define async_dmaengine_get()   dmaengine_get()
1168 #define async_dmaengine_put()   dmaengine_put()
1169 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1170 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1171 #else
1172 #define async_dma_find_channel(type) dma_find_channel(type)
1173 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1174 #else
1175 static inline void async_dmaengine_get(void)
1176 {
1177 }
1178 static inline void async_dmaengine_put(void)
1179 {
1180 }
1181 static inline struct dma_chan *
1182 async_dma_find_channel(enum dma_transaction_type type)
1183 {
1184         return NULL;
1185 }
1186 #endif /* CONFIG_ASYNC_TX_DMA */
1187 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1188                                   struct dma_chan *chan);
1189 
1190 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1191 {
1192         tx->flags |= DMA_CTRL_ACK;
1193 }
1194 
1195 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1196 {
1197         tx->flags &= ~DMA_CTRL_ACK;
1198 }
1199 
1200 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1201 {
1202         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1203 }
1204 
1205 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1206 static inline void
1207 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1208 {
1209         set_bit(tx_type, dstp->bits);
1210 }
1211 
1212 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1213 static inline void
1214 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1215 {
1216         clear_bit(tx_type, dstp->bits);
1217 }
1218 
1219 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1220 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1221 {
1222         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1223 }
1224 
1225 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1226 static inline int
1227 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1228 {
1229         return test_bit(tx_type, srcp->bits);
1230 }
1231 
1232 #define for_each_dma_cap_mask(cap, mask) \
1233         for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1234 
1235 /**
1236  * dma_async_issue_pending - flush pending transactions to HW
1237  * @chan: target DMA channel
1238  *
1239  * This allows drivers to push copies to HW in batches,
1240  * reducing MMIO writes where possible.
1241  */
1242 static inline void dma_async_issue_pending(struct dma_chan *chan)
1243 {
1244         chan->device->device_issue_pending(chan);
1245 }
1246 
1247 /**
1248  * dma_async_is_tx_complete - poll for transaction completion
1249  * @chan: DMA channel
1250  * @cookie: transaction identifier to check status of
1251  * @last: returns last completed cookie, can be NULL
1252  * @used: returns last issued cookie, can be NULL
1253  *
1254  * If @last and @used are passed in, upon return they reflect the driver
1255  * internal state and can be used with dma_async_is_complete() to check
1256  * the status of multiple cookies without re-checking hardware state.
1257  */
1258 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1259         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1260 {
1261         struct dma_tx_state state;
1262         enum dma_status status;
1263 
1264         status = chan->device->device_tx_status(chan, cookie, &state);
1265         if (last)
1266                 *last = state.last;
1267         if (used)
1268                 *used = state.used;
1269         return status;
1270 }
1271 
1272 /**
1273  * dma_async_is_complete - test a cookie against chan state
1274  * @cookie: transaction identifier to test status of
1275  * @last_complete: last know completed transaction
1276  * @last_used: last cookie value handed out
1277  *
1278  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1279  * the test logic is separated for lightweight testing of multiple cookies
1280  */
1281 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1282                         dma_cookie_t last_complete, dma_cookie_t last_used)
1283 {
1284         if (last_complete <= last_used) {
1285                 if ((cookie <= last_complete) || (cookie > last_used))
1286                         return DMA_COMPLETE;
1287         } else {
1288                 if ((cookie <= last_complete) && (cookie > last_used))
1289                         return DMA_COMPLETE;
1290         }
1291         return DMA_IN_PROGRESS;
1292 }
1293 
1294 static inline void
1295 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1296 {
1297         if (st) {
1298                 st->last = last;
1299                 st->used = used;
1300                 st->residue = residue;
1301         }
1302 }
1303 
1304 #ifdef CONFIG_DMA_ENGINE
1305 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1306 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1307 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1308 void dma_issue_pending_all(void);
1309 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1310                                         dma_filter_fn fn, void *fn_param);
1311 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1312 
1313 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1314 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1315 
1316 void dma_release_channel(struct dma_chan *chan);
1317 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1318 #else
1319 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1320 {
1321         return NULL;
1322 }
1323 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1324 {
1325         return DMA_COMPLETE;
1326 }
1327 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1328 {
1329         return DMA_COMPLETE;
1330 }
1331 static inline void dma_issue_pending_all(void)
1332 {
1333 }
1334 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1335                                               dma_filter_fn fn, void *fn_param)
1336 {
1337         return NULL;
1338 }
1339 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1340                                                          const char *name)
1341 {
1342         return NULL;
1343 }
1344 static inline struct dma_chan *dma_request_chan(struct device *dev,
1345                                                 const char *name)
1346 {
1347         return ERR_PTR(-ENODEV);
1348 }
1349 static inline struct dma_chan *dma_request_chan_by_mask(
1350                                                 const dma_cap_mask_t *mask)
1351 {
1352         return ERR_PTR(-ENODEV);
1353 }
1354 static inline void dma_release_channel(struct dma_chan *chan)
1355 {
1356 }
1357 static inline int dma_get_slave_caps(struct dma_chan *chan,
1358                                      struct dma_slave_caps *caps)
1359 {
1360         return -ENXIO;
1361 }
1362 #endif
1363 
1364 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1365 
1366 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1367 {
1368         struct dma_slave_caps caps;
1369 
1370         dma_get_slave_caps(tx->chan, &caps);
1371 
1372         if (caps.descriptor_reuse) {
1373                 tx->flags |= DMA_CTRL_REUSE;
1374                 return 0;
1375         } else {
1376                 return -EPERM;
1377         }
1378 }
1379 
1380 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1381 {
1382         tx->flags &= ~DMA_CTRL_REUSE;
1383 }
1384 
1385 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1386 {
1387         return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1388 }
1389 
1390 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1391 {
1392         /* this is supported for reusable desc, so check that */
1393         if (dmaengine_desc_test_reuse(desc))
1394                 return desc->desc_free(desc);
1395         else
1396                 return -EPERM;
1397 }
1398 
1399 /* --- DMA device --- */
1400 
1401 int dma_async_device_register(struct dma_device *device);
1402 void dma_async_device_unregister(struct dma_device *device);
1403 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1404 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1405 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1406 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1407 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1408         __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1409 
1410 static inline struct dma_chan
1411 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1412                                   dma_filter_fn fn, void *fn_param,
1413                                   struct device *dev, const char *name)
1414 {
1415         struct dma_chan *chan;
1416 
1417         chan = dma_request_slave_channel(dev, name);
1418         if (chan)
1419                 return chan;
1420 
1421         if (!fn || !fn_param)
1422                 return NULL;
1423 
1424         return __dma_request_channel(mask, fn, fn_param);
1425 }
1426 #endif /* DMAENGINE_H */
1427 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp