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TOMOYO Linux Cross Reference
Linux/include/linux/dmaengine.h

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  1 /*
  2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms of the GNU General Public License as published by the Free
  6  * Software Foundation; either version 2 of the License, or (at your option)
  7  * any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * The full GNU General Public License is included in this distribution in the
 15  * file called COPYING.
 16  */
 17 #ifndef LINUX_DMAENGINE_H
 18 #define LINUX_DMAENGINE_H
 19 
 20 #include <linux/device.h>
 21 #include <linux/err.h>
 22 #include <linux/uio.h>
 23 #include <linux/bug.h>
 24 #include <linux/scatterlist.h>
 25 #include <linux/bitmap.h>
 26 #include <linux/types.h>
 27 #include <asm/page.h>
 28 
 29 /**
 30  * typedef dma_cookie_t - an opaque DMA cookie
 31  *
 32  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 33  */
 34 typedef s32 dma_cookie_t;
 35 #define DMA_MIN_COOKIE  1
 36 
 37 static inline int dma_submit_error(dma_cookie_t cookie)
 38 {
 39         return cookie < 0 ? cookie : 0;
 40 }
 41 
 42 /**
 43  * enum dma_status - DMA transaction status
 44  * @DMA_COMPLETE: transaction completed
 45  * @DMA_IN_PROGRESS: transaction not yet processed
 46  * @DMA_PAUSED: transaction is paused
 47  * @DMA_ERROR: transaction failed
 48  */
 49 enum dma_status {
 50         DMA_COMPLETE,
 51         DMA_IN_PROGRESS,
 52         DMA_PAUSED,
 53         DMA_ERROR,
 54 };
 55 
 56 /**
 57  * enum dma_transaction_type - DMA transaction types/indexes
 58  *
 59  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 60  * automatically set as dma devices are registered.
 61  */
 62 enum dma_transaction_type {
 63         DMA_MEMCPY,
 64         DMA_XOR,
 65         DMA_PQ,
 66         DMA_XOR_VAL,
 67         DMA_PQ_VAL,
 68         DMA_MEMSET,
 69         DMA_MEMSET_SG,
 70         DMA_INTERRUPT,
 71         DMA_PRIVATE,
 72         DMA_ASYNC_TX,
 73         DMA_SLAVE,
 74         DMA_CYCLIC,
 75         DMA_INTERLEAVE,
 76 /* last transaction type for creation of the capabilities mask */
 77         DMA_TX_TYPE_END,
 78 };
 79 
 80 /**
 81  * enum dma_transfer_direction - dma transfer mode and direction indicator
 82  * @DMA_MEM_TO_MEM: Async/Memcpy mode
 83  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 84  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 85  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 86  */
 87 enum dma_transfer_direction {
 88         DMA_MEM_TO_MEM,
 89         DMA_MEM_TO_DEV,
 90         DMA_DEV_TO_MEM,
 91         DMA_DEV_TO_DEV,
 92         DMA_TRANS_NONE,
 93 };
 94 
 95 /**
 96  * Interleaved Transfer Request
 97  * ----------------------------
 98  * A chunk is collection of contiguous bytes to be transfered.
 99  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100  * ICGs may or maynot change between chunks.
101  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102  *  that when repeated an integral number of times, specifies the transfer.
103  * A transfer template is specification of a Frame, the number of times
104  *  it is to be repeated and other per-transfer attributes.
105  *
106  * Practically, a client driver would have ready a template for each
107  *  type of transfer it is going to need during its lifetime and
108  *  set only 'src_start' and 'dst_start' before submitting the requests.
109  *
110  *
111  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
112  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
113  *
114  *    ==  Chunk size
115  *    ... ICG
116  */
117 
118 /**
119  * struct data_chunk - Element of scatter-gather list that makes a frame.
120  * @size: Number of bytes to read from source.
121  *        size_dst := fn(op, size_src), so doesn't mean much for destination.
122  * @icg: Number of bytes to jump after last src/dst address of this
123  *       chunk and before first src/dst address for next chunk.
124  *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125  *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
126  * @dst_icg: Number of bytes to jump after last dst address of this
127  *       chunk and before the first dst address for next chunk.
128  *       Ignored if dst_inc is true and dst_sgl is false.
129  * @src_icg: Number of bytes to jump after last src address of this
130  *       chunk and before the first src address for next chunk.
131  *       Ignored if src_inc is true and src_sgl is false.
132  */
133 struct data_chunk {
134         size_t size;
135         size_t icg;
136         size_t dst_icg;
137         size_t src_icg;
138 };
139 
140 /**
141  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
142  *       and attributes.
143  * @src_start: Bus address of source for the first chunk.
144  * @dst_start: Bus address of destination for the first chunk.
145  * @dir: Specifies the type of Source and Destination.
146  * @src_inc: If the source address increments after reading from it.
147  * @dst_inc: If the destination address increments after writing to it.
148  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
149  *              Otherwise, source is read contiguously (icg ignored).
150  *              Ignored if src_inc is false.
151  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
152  *              Otherwise, destination is filled contiguously (icg ignored).
153  *              Ignored if dst_inc is false.
154  * @numf: Number of frames in this template.
155  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
156  * @sgl: Array of {chunk,icg} pairs that make up a frame.
157  */
158 struct dma_interleaved_template {
159         dma_addr_t src_start;
160         dma_addr_t dst_start;
161         enum dma_transfer_direction dir;
162         bool src_inc;
163         bool dst_inc;
164         bool src_sgl;
165         bool dst_sgl;
166         size_t numf;
167         size_t frame_size;
168         struct data_chunk sgl[0];
169 };
170 
171 /**
172  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
173  *  control completion, and communicate status.
174  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
175  *  this transaction
176  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
177  *  acknowledges receipt, i.e. has has a chance to establish any dependency
178  *  chains
179  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
180  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
181  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
182  *  sources that were the result of a previous operation, in the case of a PQ
183  *  operation it continues the calculation with new sources
184  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
185  *  on the result of this operation
186  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
187  *  cleared or freed
188  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
189  *  data and the descriptor should be in different format from normal
190  *  data descriptors.
191  */
192 enum dma_ctrl_flags {
193         DMA_PREP_INTERRUPT = (1 << 0),
194         DMA_CTRL_ACK = (1 << 1),
195         DMA_PREP_PQ_DISABLE_P = (1 << 2),
196         DMA_PREP_PQ_DISABLE_Q = (1 << 3),
197         DMA_PREP_CONTINUE = (1 << 4),
198         DMA_PREP_FENCE = (1 << 5),
199         DMA_CTRL_REUSE = (1 << 6),
200         DMA_PREP_CMD = (1 << 7),
201 };
202 
203 /**
204  * enum sum_check_bits - bit position of pq_check_flags
205  */
206 enum sum_check_bits {
207         SUM_CHECK_P = 0,
208         SUM_CHECK_Q = 1,
209 };
210 
211 /**
212  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
213  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
214  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
215  */
216 enum sum_check_flags {
217         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
218         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
219 };
220 
221 
222 /**
223  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
224  * See linux/cpumask.h
225  */
226 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
227 
228 /**
229  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
230  * @memcpy_count: transaction counter
231  * @bytes_transferred: byte counter
232  */
233 
234 struct dma_chan_percpu {
235         /* stats */
236         unsigned long memcpy_count;
237         unsigned long bytes_transferred;
238 };
239 
240 /**
241  * struct dma_router - DMA router structure
242  * @dev: pointer to the DMA router device
243  * @route_free: function to be called when the route can be disconnected
244  */
245 struct dma_router {
246         struct device *dev;
247         void (*route_free)(struct device *dev, void *route_data);
248 };
249 
250 /**
251  * struct dma_chan - devices supply DMA channels, clients use them
252  * @device: ptr to the dma device who supplies this channel, always !%NULL
253  * @cookie: last cookie value returned to client
254  * @completed_cookie: last completed cookie for this channel
255  * @chan_id: channel ID for sysfs
256  * @dev: class device for sysfs
257  * @device_node: used to add this to the device chan list
258  * @local: per-cpu pointer to a struct dma_chan_percpu
259  * @client_count: how many clients are using this channel
260  * @table_count: number of appearances in the mem-to-mem allocation table
261  * @router: pointer to the DMA router structure
262  * @route_data: channel specific data for the router
263  * @private: private data for certain client-channel associations
264  */
265 struct dma_chan {
266         struct dma_device *device;
267         dma_cookie_t cookie;
268         dma_cookie_t completed_cookie;
269 
270         /* sysfs */
271         int chan_id;
272         struct dma_chan_dev *dev;
273 
274         struct list_head device_node;
275         struct dma_chan_percpu __percpu *local;
276         int client_count;
277         int table_count;
278 
279         /* DMA router */
280         struct dma_router *router;
281         void *route_data;
282 
283         void *private;
284 };
285 
286 /**
287  * struct dma_chan_dev - relate sysfs device node to backing channel device
288  * @chan: driver channel device
289  * @device: sysfs device
290  * @dev_id: parent dma_device dev_id
291  * @idr_ref: reference count to gate release of dma_device dev_id
292  */
293 struct dma_chan_dev {
294         struct dma_chan *chan;
295         struct device device;
296         int dev_id;
297         atomic_t *idr_ref;
298 };
299 
300 /**
301  * enum dma_slave_buswidth - defines bus width of the DMA slave
302  * device, source or target buses
303  */
304 enum dma_slave_buswidth {
305         DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
306         DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
307         DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
308         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
309         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
310         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
311         DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
312         DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
313         DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
314 };
315 
316 /**
317  * struct dma_slave_config - dma slave channel runtime config
318  * @direction: whether the data shall go in or out on this slave
319  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
320  * legal values. DEPRECATED, drivers should use the direction argument
321  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
322  * the dir field in the dma_interleaved_template structure.
323  * @src_addr: this is the physical address where DMA slave data
324  * should be read (RX), if the source is memory this argument is
325  * ignored.
326  * @dst_addr: this is the physical address where DMA slave data
327  * should be written (TX), if the source is memory this argument
328  * is ignored.
329  * @src_addr_width: this is the width in bytes of the source (RX)
330  * register where DMA data shall be read. If the source
331  * is memory this may be ignored depending on architecture.
332  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
333  * @dst_addr_width: same as src_addr_width but for destination
334  * target (TX) mutatis mutandis.
335  * @src_maxburst: the maximum number of words (note: words, as in
336  * units of the src_addr_width member, not bytes) that can be sent
337  * in one burst to the device. Typically something like half the
338  * FIFO depth on I/O peripherals so you don't overflow it. This
339  * may or may not be applicable on memory sources.
340  * @dst_maxburst: same as src_maxburst but for destination target
341  * mutatis mutandis.
342  * @src_port_window_size: The length of the register area in words the data need
343  * to be accessed on the device side. It is only used for devices which is using
344  * an area instead of a single register to receive the data. Typically the DMA
345  * loops in this area in order to transfer the data.
346  * @dst_port_window_size: same as src_port_window_size but for the destination
347  * port.
348  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
349  * with 'true' if peripheral should be flow controller. Direction will be
350  * selected at Runtime.
351  * @slave_id: Slave requester id. Only valid for slave channels. The dma
352  * slave peripheral will have unique id as dma requester which need to be
353  * pass as slave config.
354  *
355  * This struct is passed in as configuration data to a DMA engine
356  * in order to set up a certain channel for DMA transport at runtime.
357  * The DMA device/engine has to provide support for an additional
358  * callback in the dma_device structure, device_config and this struct
359  * will then be passed in as an argument to the function.
360  *
361  * The rationale for adding configuration information to this struct is as
362  * follows: if it is likely that more than one DMA slave controllers in
363  * the world will support the configuration option, then make it generic.
364  * If not: if it is fixed so that it be sent in static from the platform
365  * data, then prefer to do that.
366  */
367 struct dma_slave_config {
368         enum dma_transfer_direction direction;
369         phys_addr_t src_addr;
370         phys_addr_t dst_addr;
371         enum dma_slave_buswidth src_addr_width;
372         enum dma_slave_buswidth dst_addr_width;
373         u32 src_maxburst;
374         u32 dst_maxburst;
375         u32 src_port_window_size;
376         u32 dst_port_window_size;
377         bool device_fc;
378         unsigned int slave_id;
379 };
380 
381 /**
382  * enum dma_residue_granularity - Granularity of the reported transfer residue
383  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
384  *  DMA channel is only able to tell whether a descriptor has been completed or
385  *  not, which means residue reporting is not supported by this channel. The
386  *  residue field of the dma_tx_state field will always be 0.
387  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
388  *  completed segment of the transfer (For cyclic transfers this is after each
389  *  period). This is typically implemented by having the hardware generate an
390  *  interrupt after each transferred segment and then the drivers updates the
391  *  outstanding residue by the size of the segment. Another possibility is if
392  *  the hardware supports scatter-gather and the segment descriptor has a field
393  *  which gets set after the segment has been completed. The driver then counts
394  *  the number of segments without the flag set to compute the residue.
395  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
396  *  burst. This is typically only supported if the hardware has a progress
397  *  register of some sort (E.g. a register with the current read/write address
398  *  or a register with the amount of bursts/beats/bytes that have been
399  *  transferred or still need to be transferred).
400  */
401 enum dma_residue_granularity {
402         DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
403         DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
404         DMA_RESIDUE_GRANULARITY_BURST = 2,
405 };
406 
407 /**
408  * struct dma_slave_caps - expose capabilities of a slave channel only
409  * @src_addr_widths: bit mask of src addr widths the channel supports.
410  *      Width is specified in bytes, e.g. for a channel supporting
411  *      a width of 4 the mask should have BIT(4) set.
412  * @dst_addr_widths: bit mask of dst addr widths the channel supports
413  * @directions: bit mask of slave directions the channel supports.
414  *      Since the enum dma_transfer_direction is not defined as bit flag for
415  *      each type, the dma controller should set BIT(<TYPE>) and same
416  *      should be checked by controller as well
417  * @max_burst: max burst capability per-transfer
418  * @cmd_pause: true, if pause and thereby resume is supported
419  * @cmd_terminate: true, if terminate cmd is supported
420  * @residue_granularity: granularity of the reported transfer residue
421  * @descriptor_reuse: if a descriptor can be reused by client and
422  * resubmitted multiple times
423  */
424 struct dma_slave_caps {
425         u32 src_addr_widths;
426         u32 dst_addr_widths;
427         u32 directions;
428         u32 max_burst;
429         bool cmd_pause;
430         bool cmd_terminate;
431         enum dma_residue_granularity residue_granularity;
432         bool descriptor_reuse;
433 };
434 
435 static inline const char *dma_chan_name(struct dma_chan *chan)
436 {
437         return dev_name(&chan->dev->device);
438 }
439 
440 void dma_chan_cleanup(struct kref *kref);
441 
442 /**
443  * typedef dma_filter_fn - callback filter for dma_request_channel
444  * @chan: channel to be reviewed
445  * @filter_param: opaque parameter passed through dma_request_channel
446  *
447  * When this optional parameter is specified in a call to dma_request_channel a
448  * suitable channel is passed to this routine for further dispositioning before
449  * being returned.  Where 'suitable' indicates a non-busy channel that
450  * satisfies the given capability mask.  It returns 'true' to indicate that the
451  * channel is suitable.
452  */
453 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
454 
455 typedef void (*dma_async_tx_callback)(void *dma_async_param);
456 
457 enum dmaengine_tx_result {
458         DMA_TRANS_NOERROR = 0,          /* SUCCESS */
459         DMA_TRANS_READ_FAILED,          /* Source DMA read failed */
460         DMA_TRANS_WRITE_FAILED,         /* Destination DMA write failed */
461         DMA_TRANS_ABORTED,              /* Op never submitted / aborted */
462 };
463 
464 struct dmaengine_result {
465         enum dmaengine_tx_result result;
466         u32 residue;
467 };
468 
469 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
470                                 const struct dmaengine_result *result);
471 
472 struct dmaengine_unmap_data {
473 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
474         u16 map_cnt;
475 #else
476         u8 map_cnt;
477 #endif
478         u8 to_cnt;
479         u8 from_cnt;
480         u8 bidi_cnt;
481         struct device *dev;
482         struct kref kref;
483         size_t len;
484         dma_addr_t addr[0];
485 };
486 
487 /**
488  * struct dma_async_tx_descriptor - async transaction descriptor
489  * ---dma generic offload fields---
490  * @cookie: tracking cookie for this transaction, set to -EBUSY if
491  *      this tx is sitting on a dependency list
492  * @flags: flags to augment operation preparation, control completion, and
493  *      communicate status
494  * @phys: physical address of the descriptor
495  * @chan: target channel for this operation
496  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
497  * descriptor pending. To be pushed on .issue_pending() call
498  * @callback: routine to call after this operation is complete
499  * @callback_param: general parameter to pass to the callback routine
500  * ---async_tx api specific fields---
501  * @next: at completion submit this descriptor
502  * @parent: pointer to the next level up in the dependency chain
503  * @lock: protect the parent and next pointers
504  */
505 struct dma_async_tx_descriptor {
506         dma_cookie_t cookie;
507         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
508         dma_addr_t phys;
509         struct dma_chan *chan;
510         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
511         int (*desc_free)(struct dma_async_tx_descriptor *tx);
512         dma_async_tx_callback callback;
513         dma_async_tx_callback_result callback_result;
514         void *callback_param;
515         struct dmaengine_unmap_data *unmap;
516 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
517         struct dma_async_tx_descriptor *next;
518         struct dma_async_tx_descriptor *parent;
519         spinlock_t lock;
520 #endif
521 };
522 
523 #ifdef CONFIG_DMA_ENGINE
524 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
525                                  struct dmaengine_unmap_data *unmap)
526 {
527         kref_get(&unmap->kref);
528         tx->unmap = unmap;
529 }
530 
531 struct dmaengine_unmap_data *
532 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
533 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
534 #else
535 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
536                                  struct dmaengine_unmap_data *unmap)
537 {
538 }
539 static inline struct dmaengine_unmap_data *
540 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
541 {
542         return NULL;
543 }
544 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
545 {
546 }
547 #endif
548 
549 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
550 {
551         if (tx->unmap) {
552                 dmaengine_unmap_put(tx->unmap);
553                 tx->unmap = NULL;
554         }
555 }
556 
557 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
558 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
559 {
560 }
561 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
562 {
563 }
564 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
565 {
566         BUG();
567 }
568 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
569 {
570 }
571 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
572 {
573 }
574 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
575 {
576         return NULL;
577 }
578 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
579 {
580         return NULL;
581 }
582 
583 #else
584 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
585 {
586         spin_lock_bh(&txd->lock);
587 }
588 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
589 {
590         spin_unlock_bh(&txd->lock);
591 }
592 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
593 {
594         txd->next = next;
595         next->parent = txd;
596 }
597 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
598 {
599         txd->parent = NULL;
600 }
601 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
602 {
603         txd->next = NULL;
604 }
605 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
606 {
607         return txd->parent;
608 }
609 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
610 {
611         return txd->next;
612 }
613 #endif
614 
615 /**
616  * struct dma_tx_state - filled in to report the status of
617  * a transfer.
618  * @last: last completed DMA cookie
619  * @used: last issued DMA cookie (i.e. the one in progress)
620  * @residue: the remaining number of bytes left to transmit
621  *      on the selected transfer for states DMA_IN_PROGRESS and
622  *      DMA_PAUSED if this is implemented in the driver, else 0
623  */
624 struct dma_tx_state {
625         dma_cookie_t last;
626         dma_cookie_t used;
627         u32 residue;
628 };
629 
630 /**
631  * enum dmaengine_alignment - defines alignment of the DMA async tx
632  * buffers
633  */
634 enum dmaengine_alignment {
635         DMAENGINE_ALIGN_1_BYTE = 0,
636         DMAENGINE_ALIGN_2_BYTES = 1,
637         DMAENGINE_ALIGN_4_BYTES = 2,
638         DMAENGINE_ALIGN_8_BYTES = 3,
639         DMAENGINE_ALIGN_16_BYTES = 4,
640         DMAENGINE_ALIGN_32_BYTES = 5,
641         DMAENGINE_ALIGN_64_BYTES = 6,
642 };
643 
644 /**
645  * struct dma_slave_map - associates slave device and it's slave channel with
646  * parameter to be used by a filter function
647  * @devname: name of the device
648  * @slave: slave channel name
649  * @param: opaque parameter to pass to struct dma_filter.fn
650  */
651 struct dma_slave_map {
652         const char *devname;
653         const char *slave;
654         void *param;
655 };
656 
657 /**
658  * struct dma_filter - information for slave device/channel to filter_fn/param
659  * mapping
660  * @fn: filter function callback
661  * @mapcnt: number of slave device/channel in the map
662  * @map: array of channel to filter mapping data
663  */
664 struct dma_filter {
665         dma_filter_fn fn;
666         int mapcnt;
667         const struct dma_slave_map *map;
668 };
669 
670 /**
671  * struct dma_device - info on the entity supplying DMA services
672  * @chancnt: how many DMA channels are supported
673  * @privatecnt: how many DMA channels are requested by dma_request_channel
674  * @channels: the list of struct dma_chan
675  * @global_node: list_head for global dma_device_list
676  * @filter: information for device/slave to filter function/param mapping
677  * @cap_mask: one or more dma_capability flags
678  * @max_xor: maximum number of xor sources, 0 if no capability
679  * @max_pq: maximum number of PQ sources and PQ-continue capability
680  * @copy_align: alignment shift for memcpy operations
681  * @xor_align: alignment shift for xor operations
682  * @pq_align: alignment shift for pq operations
683  * @fill_align: alignment shift for memset operations
684  * @dev_id: unique device ID
685  * @dev: struct device reference for dma mapping api
686  * @src_addr_widths: bit mask of src addr widths the device supports
687  *      Width is specified in bytes, e.g. for a device supporting
688  *      a width of 4 the mask should have BIT(4) set.
689  * @dst_addr_widths: bit mask of dst addr widths the device supports
690  * @directions: bit mask of slave directions the device supports.
691  *      Since the enum dma_transfer_direction is not defined as bit flag for
692  *      each type, the dma controller should set BIT(<TYPE>) and same
693  *      should be checked by controller as well
694  * @max_burst: max burst capability per-transfer
695  * @residue_granularity: granularity of the transfer residue reported
696  *      by tx_status
697  * @device_alloc_chan_resources: allocate resources and return the
698  *      number of allocated descriptors
699  * @device_free_chan_resources: release DMA channel's resources
700  * @device_prep_dma_memcpy: prepares a memcpy operation
701  * @device_prep_dma_xor: prepares a xor operation
702  * @device_prep_dma_xor_val: prepares a xor validation operation
703  * @device_prep_dma_pq: prepares a pq operation
704  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
705  * @device_prep_dma_memset: prepares a memset operation
706  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
707  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
708  * @device_prep_slave_sg: prepares a slave dma operation
709  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
710  *      The function takes a buffer of size buf_len. The callback function will
711  *      be called after period_len bytes have been transferred.
712  * @device_prep_interleaved_dma: Transfer expression in a generic way.
713  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
714  * @device_config: Pushes a new configuration to a channel, return 0 or an error
715  *      code
716  * @device_pause: Pauses any transfer happening on a channel. Returns
717  *      0 or an error code
718  * @device_resume: Resumes any transfer on a channel previously
719  *      paused. Returns 0 or an error code
720  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
721  *      or an error code
722  * @device_synchronize: Synchronizes the termination of a transfers to the
723  *  current context.
724  * @device_tx_status: poll for transaction completion, the optional
725  *      txstate parameter can be supplied with a pointer to get a
726  *      struct with auxiliary transfer status information, otherwise the call
727  *      will just return a simple status code
728  * @device_issue_pending: push pending transactions to hardware
729  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
730  */
731 struct dma_device {
732 
733         unsigned int chancnt;
734         unsigned int privatecnt;
735         struct list_head channels;
736         struct list_head global_node;
737         struct dma_filter filter;
738         dma_cap_mask_t  cap_mask;
739         unsigned short max_xor;
740         unsigned short max_pq;
741         enum dmaengine_alignment copy_align;
742         enum dmaengine_alignment xor_align;
743         enum dmaengine_alignment pq_align;
744         enum dmaengine_alignment fill_align;
745         #define DMA_HAS_PQ_CONTINUE (1 << 15)
746 
747         int dev_id;
748         struct device *dev;
749 
750         u32 src_addr_widths;
751         u32 dst_addr_widths;
752         u32 directions;
753         u32 max_burst;
754         bool descriptor_reuse;
755         enum dma_residue_granularity residue_granularity;
756 
757         int (*device_alloc_chan_resources)(struct dma_chan *chan);
758         void (*device_free_chan_resources)(struct dma_chan *chan);
759 
760         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
761                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
762                 size_t len, unsigned long flags);
763         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
764                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
765                 unsigned int src_cnt, size_t len, unsigned long flags);
766         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
767                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
768                 size_t len, enum sum_check_flags *result, unsigned long flags);
769         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
770                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
771                 unsigned int src_cnt, const unsigned char *scf,
772                 size_t len, unsigned long flags);
773         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
774                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
775                 unsigned int src_cnt, const unsigned char *scf, size_t len,
776                 enum sum_check_flags *pqres, unsigned long flags);
777         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
778                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
779                 unsigned long flags);
780         struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
781                 struct dma_chan *chan, struct scatterlist *sg,
782                 unsigned int nents, int value, unsigned long flags);
783         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
784                 struct dma_chan *chan, unsigned long flags);
785 
786         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
787                 struct dma_chan *chan, struct scatterlist *sgl,
788                 unsigned int sg_len, enum dma_transfer_direction direction,
789                 unsigned long flags, void *context);
790         struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
791                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
792                 size_t period_len, enum dma_transfer_direction direction,
793                 unsigned long flags);
794         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
795                 struct dma_chan *chan, struct dma_interleaved_template *xt,
796                 unsigned long flags);
797         struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
798                 struct dma_chan *chan, dma_addr_t dst, u64 data,
799                 unsigned long flags);
800 
801         int (*device_config)(struct dma_chan *chan,
802                              struct dma_slave_config *config);
803         int (*device_pause)(struct dma_chan *chan);
804         int (*device_resume)(struct dma_chan *chan);
805         int (*device_terminate_all)(struct dma_chan *chan);
806         void (*device_synchronize)(struct dma_chan *chan);
807 
808         enum dma_status (*device_tx_status)(struct dma_chan *chan,
809                                             dma_cookie_t cookie,
810                                             struct dma_tx_state *txstate);
811         void (*device_issue_pending)(struct dma_chan *chan);
812 };
813 
814 static inline int dmaengine_slave_config(struct dma_chan *chan,
815                                           struct dma_slave_config *config)
816 {
817         if (chan->device->device_config)
818                 return chan->device->device_config(chan, config);
819 
820         return -ENOSYS;
821 }
822 
823 static inline bool is_slave_direction(enum dma_transfer_direction direction)
824 {
825         return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
826 }
827 
828 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
829         struct dma_chan *chan, dma_addr_t buf, size_t len,
830         enum dma_transfer_direction dir, unsigned long flags)
831 {
832         struct scatterlist sg;
833         sg_init_table(&sg, 1);
834         sg_dma_address(&sg) = buf;
835         sg_dma_len(&sg) = len;
836 
837         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
838                 return NULL;
839 
840         return chan->device->device_prep_slave_sg(chan, &sg, 1,
841                                                   dir, flags, NULL);
842 }
843 
844 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
845         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
846         enum dma_transfer_direction dir, unsigned long flags)
847 {
848         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
849                 return NULL;
850 
851         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
852                                                   dir, flags, NULL);
853 }
854 
855 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
856 struct rio_dma_ext;
857 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
858         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
859         enum dma_transfer_direction dir, unsigned long flags,
860         struct rio_dma_ext *rio_ext)
861 {
862         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
863                 return NULL;
864 
865         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
866                                                   dir, flags, rio_ext);
867 }
868 #endif
869 
870 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
871                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
872                 size_t period_len, enum dma_transfer_direction dir,
873                 unsigned long flags)
874 {
875         if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
876                 return NULL;
877 
878         return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
879                                                 period_len, dir, flags);
880 }
881 
882 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
883                 struct dma_chan *chan, struct dma_interleaved_template *xt,
884                 unsigned long flags)
885 {
886         if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
887                 return NULL;
888 
889         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
890 }
891 
892 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
893                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
894                 unsigned long flags)
895 {
896         if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
897                 return NULL;
898 
899         return chan->device->device_prep_dma_memset(chan, dest, value,
900                                                     len, flags);
901 }
902 
903 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
904                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
905                 size_t len, unsigned long flags)
906 {
907         if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
908                 return NULL;
909 
910         return chan->device->device_prep_dma_memcpy(chan, dest, src,
911                                                     len, flags);
912 }
913 
914 /**
915  * dmaengine_terminate_all() - Terminate all active DMA transfers
916  * @chan: The channel for which to terminate the transfers
917  *
918  * This function is DEPRECATED use either dmaengine_terminate_sync() or
919  * dmaengine_terminate_async() instead.
920  */
921 static inline int dmaengine_terminate_all(struct dma_chan *chan)
922 {
923         if (chan->device->device_terminate_all)
924                 return chan->device->device_terminate_all(chan);
925 
926         return -ENOSYS;
927 }
928 
929 /**
930  * dmaengine_terminate_async() - Terminate all active DMA transfers
931  * @chan: The channel for which to terminate the transfers
932  *
933  * Calling this function will terminate all active and pending descriptors
934  * that have previously been submitted to the channel. It is not guaranteed
935  * though that the transfer for the active descriptor has stopped when the
936  * function returns. Furthermore it is possible the complete callback of a
937  * submitted transfer is still running when this function returns.
938  *
939  * dmaengine_synchronize() needs to be called before it is safe to free
940  * any memory that is accessed by previously submitted descriptors or before
941  * freeing any resources accessed from within the completion callback of any
942  * perviously submitted descriptors.
943  *
944  * This function can be called from atomic context as well as from within a
945  * complete callback of a descriptor submitted on the same channel.
946  *
947  * If none of the two conditions above apply consider using
948  * dmaengine_terminate_sync() instead.
949  */
950 static inline int dmaengine_terminate_async(struct dma_chan *chan)
951 {
952         if (chan->device->device_terminate_all)
953                 return chan->device->device_terminate_all(chan);
954 
955         return -EINVAL;
956 }
957 
958 /**
959  * dmaengine_synchronize() - Synchronize DMA channel termination
960  * @chan: The channel to synchronize
961  *
962  * Synchronizes to the DMA channel termination to the current context. When this
963  * function returns it is guaranteed that all transfers for previously issued
964  * descriptors have stopped and and it is safe to free the memory assoicated
965  * with them. Furthermore it is guaranteed that all complete callback functions
966  * for a previously submitted descriptor have finished running and it is safe to
967  * free resources accessed from within the complete callbacks.
968  *
969  * The behavior of this function is undefined if dma_async_issue_pending() has
970  * been called between dmaengine_terminate_async() and this function.
971  *
972  * This function must only be called from non-atomic context and must not be
973  * called from within a complete callback of a descriptor submitted on the same
974  * channel.
975  */
976 static inline void dmaengine_synchronize(struct dma_chan *chan)
977 {
978         might_sleep();
979 
980         if (chan->device->device_synchronize)
981                 chan->device->device_synchronize(chan);
982 }
983 
984 /**
985  * dmaengine_terminate_sync() - Terminate all active DMA transfers
986  * @chan: The channel for which to terminate the transfers
987  *
988  * Calling this function will terminate all active and pending transfers
989  * that have previously been submitted to the channel. It is similar to
990  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
991  * stopped and that all complete callbacks have finished running when the
992  * function returns.
993  *
994  * This function must only be called from non-atomic context and must not be
995  * called from within a complete callback of a descriptor submitted on the same
996  * channel.
997  */
998 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
999 {
1000         int ret;
1001 
1002         ret = dmaengine_terminate_async(chan);
1003         if (ret)
1004                 return ret;
1005 
1006         dmaengine_synchronize(chan);
1007 
1008         return 0;
1009 }
1010 
1011 static inline int dmaengine_pause(struct dma_chan *chan)
1012 {
1013         if (chan->device->device_pause)
1014                 return chan->device->device_pause(chan);
1015 
1016         return -ENOSYS;
1017 }
1018 
1019 static inline int dmaengine_resume(struct dma_chan *chan)
1020 {
1021         if (chan->device->device_resume)
1022                 return chan->device->device_resume(chan);
1023 
1024         return -ENOSYS;
1025 }
1026 
1027 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1028         dma_cookie_t cookie, struct dma_tx_state *state)
1029 {
1030         return chan->device->device_tx_status(chan, cookie, state);
1031 }
1032 
1033 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1034 {
1035         return desc->tx_submit(desc);
1036 }
1037 
1038 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1039                                          size_t off1, size_t off2, size_t len)
1040 {
1041         size_t mask;
1042 
1043         if (!align)
1044                 return true;
1045         mask = (1 << align) - 1;
1046         if (mask & (off1 | off2 | len))
1047                 return false;
1048         return true;
1049 }
1050 
1051 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1052                                        size_t off2, size_t len)
1053 {
1054         return dmaengine_check_align(dev->copy_align, off1, off2, len);
1055 }
1056 
1057 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1058                                       size_t off2, size_t len)
1059 {
1060         return dmaengine_check_align(dev->xor_align, off1, off2, len);
1061 }
1062 
1063 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1064                                      size_t off2, size_t len)
1065 {
1066         return dmaengine_check_align(dev->pq_align, off1, off2, len);
1067 }
1068 
1069 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1070                                        size_t off2, size_t len)
1071 {
1072         return dmaengine_check_align(dev->fill_align, off1, off2, len);
1073 }
1074 
1075 static inline void
1076 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1077 {
1078         dma->max_pq = maxpq;
1079         if (has_pq_continue)
1080                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1081 }
1082 
1083 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1084 {
1085         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1086 }
1087 
1088 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1089 {
1090         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1091 
1092         return (flags & mask) == mask;
1093 }
1094 
1095 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1096 {
1097         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1098 }
1099 
1100 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1101 {
1102         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1103 }
1104 
1105 /* dma_maxpq - reduce maxpq in the face of continued operations
1106  * @dma - dma device with PQ capability
1107  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1108  *
1109  * When an engine does not support native continuation we need 3 extra
1110  * source slots to reuse P and Q with the following coefficients:
1111  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1112  * 2/ {01} * Q : use Q to continue Q' calculation
1113  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1114  *
1115  * In the case where P is disabled we only need 1 extra source:
1116  * 1/ {01} * Q : use Q to continue Q' calculation
1117  */
1118 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1119 {
1120         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1121                 return dma_dev_to_maxpq(dma);
1122         else if (dmaf_p_disabled_continue(flags))
1123                 return dma_dev_to_maxpq(dma) - 1;
1124         else if (dmaf_continue(flags))
1125                 return dma_dev_to_maxpq(dma) - 3;
1126         BUG();
1127 }
1128 
1129 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1130                                       size_t dir_icg)
1131 {
1132         if (inc) {
1133                 if (dir_icg)
1134                         return dir_icg;
1135                 else if (sgl)
1136                         return icg;
1137         }
1138 
1139         return 0;
1140 }
1141 
1142 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1143                                            struct data_chunk *chunk)
1144 {
1145         return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1146                                  chunk->icg, chunk->dst_icg);
1147 }
1148 
1149 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1150                                            struct data_chunk *chunk)
1151 {
1152         return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1153                                  chunk->icg, chunk->src_icg);
1154 }
1155 
1156 /* --- public DMA engine API --- */
1157 
1158 #ifdef CONFIG_DMA_ENGINE
1159 void dmaengine_get(void);
1160 void dmaengine_put(void);
1161 #else
1162 static inline void dmaengine_get(void)
1163 {
1164 }
1165 static inline void dmaengine_put(void)
1166 {
1167 }
1168 #endif
1169 
1170 #ifdef CONFIG_ASYNC_TX_DMA
1171 #define async_dmaengine_get()   dmaengine_get()
1172 #define async_dmaengine_put()   dmaengine_put()
1173 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1174 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1175 #else
1176 #define async_dma_find_channel(type) dma_find_channel(type)
1177 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1178 #else
1179 static inline void async_dmaengine_get(void)
1180 {
1181 }
1182 static inline void async_dmaengine_put(void)
1183 {
1184 }
1185 static inline struct dma_chan *
1186 async_dma_find_channel(enum dma_transaction_type type)
1187 {
1188         return NULL;
1189 }
1190 #endif /* CONFIG_ASYNC_TX_DMA */
1191 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1192                                   struct dma_chan *chan);
1193 
1194 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1195 {
1196         tx->flags |= DMA_CTRL_ACK;
1197 }
1198 
1199 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1200 {
1201         tx->flags &= ~DMA_CTRL_ACK;
1202 }
1203 
1204 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1205 {
1206         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1207 }
1208 
1209 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1210 static inline void
1211 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1212 {
1213         set_bit(tx_type, dstp->bits);
1214 }
1215 
1216 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1217 static inline void
1218 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1219 {
1220         clear_bit(tx_type, dstp->bits);
1221 }
1222 
1223 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1224 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1225 {
1226         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1227 }
1228 
1229 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1230 static inline int
1231 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1232 {
1233         return test_bit(tx_type, srcp->bits);
1234 }
1235 
1236 #define for_each_dma_cap_mask(cap, mask) \
1237         for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1238 
1239 /**
1240  * dma_async_issue_pending - flush pending transactions to HW
1241  * @chan: target DMA channel
1242  *
1243  * This allows drivers to push copies to HW in batches,
1244  * reducing MMIO writes where possible.
1245  */
1246 static inline void dma_async_issue_pending(struct dma_chan *chan)
1247 {
1248         chan->device->device_issue_pending(chan);
1249 }
1250 
1251 /**
1252  * dma_async_is_tx_complete - poll for transaction completion
1253  * @chan: DMA channel
1254  * @cookie: transaction identifier to check status of
1255  * @last: returns last completed cookie, can be NULL
1256  * @used: returns last issued cookie, can be NULL
1257  *
1258  * If @last and @used are passed in, upon return they reflect the driver
1259  * internal state and can be used with dma_async_is_complete() to check
1260  * the status of multiple cookies without re-checking hardware state.
1261  */
1262 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1263         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1264 {
1265         struct dma_tx_state state;
1266         enum dma_status status;
1267 
1268         status = chan->device->device_tx_status(chan, cookie, &state);
1269         if (last)
1270                 *last = state.last;
1271         if (used)
1272                 *used = state.used;
1273         return status;
1274 }
1275 
1276 /**
1277  * dma_async_is_complete - test a cookie against chan state
1278  * @cookie: transaction identifier to test status of
1279  * @last_complete: last know completed transaction
1280  * @last_used: last cookie value handed out
1281  *
1282  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1283  * the test logic is separated for lightweight testing of multiple cookies
1284  */
1285 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1286                         dma_cookie_t last_complete, dma_cookie_t last_used)
1287 {
1288         if (last_complete <= last_used) {
1289                 if ((cookie <= last_complete) || (cookie > last_used))
1290                         return DMA_COMPLETE;
1291         } else {
1292                 if ((cookie <= last_complete) && (cookie > last_used))
1293                         return DMA_COMPLETE;
1294         }
1295         return DMA_IN_PROGRESS;
1296 }
1297 
1298 static inline void
1299 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1300 {
1301         if (st) {
1302                 st->last = last;
1303                 st->used = used;
1304                 st->residue = residue;
1305         }
1306 }
1307 
1308 #ifdef CONFIG_DMA_ENGINE
1309 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1310 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1311 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1312 void dma_issue_pending_all(void);
1313 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1314                                         dma_filter_fn fn, void *fn_param);
1315 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1316 
1317 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1318 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1319 
1320 void dma_release_channel(struct dma_chan *chan);
1321 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1322 #else
1323 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1324 {
1325         return NULL;
1326 }
1327 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1328 {
1329         return DMA_COMPLETE;
1330 }
1331 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1332 {
1333         return DMA_COMPLETE;
1334 }
1335 static inline void dma_issue_pending_all(void)
1336 {
1337 }
1338 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1339                                               dma_filter_fn fn, void *fn_param)
1340 {
1341         return NULL;
1342 }
1343 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1344                                                          const char *name)
1345 {
1346         return NULL;
1347 }
1348 static inline struct dma_chan *dma_request_chan(struct device *dev,
1349                                                 const char *name)
1350 {
1351         return ERR_PTR(-ENODEV);
1352 }
1353 static inline struct dma_chan *dma_request_chan_by_mask(
1354                                                 const dma_cap_mask_t *mask)
1355 {
1356         return ERR_PTR(-ENODEV);
1357 }
1358 static inline void dma_release_channel(struct dma_chan *chan)
1359 {
1360 }
1361 static inline int dma_get_slave_caps(struct dma_chan *chan,
1362                                      struct dma_slave_caps *caps)
1363 {
1364         return -ENXIO;
1365 }
1366 #endif
1367 
1368 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1369 
1370 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1371 {
1372         struct dma_slave_caps caps;
1373 
1374         dma_get_slave_caps(tx->chan, &caps);
1375 
1376         if (caps.descriptor_reuse) {
1377                 tx->flags |= DMA_CTRL_REUSE;
1378                 return 0;
1379         } else {
1380                 return -EPERM;
1381         }
1382 }
1383 
1384 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1385 {
1386         tx->flags &= ~DMA_CTRL_REUSE;
1387 }
1388 
1389 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1390 {
1391         return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1392 }
1393 
1394 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1395 {
1396         /* this is supported for reusable desc, so check that */
1397         if (dmaengine_desc_test_reuse(desc))
1398                 return desc->desc_free(desc);
1399         else
1400                 return -EPERM;
1401 }
1402 
1403 /* --- DMA device --- */
1404 
1405 int dma_async_device_register(struct dma_device *device);
1406 void dma_async_device_unregister(struct dma_device *device);
1407 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1408 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1409 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1410 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1411 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1412         __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1413 
1414 static inline struct dma_chan
1415 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1416                                   dma_filter_fn fn, void *fn_param,
1417                                   struct device *dev, const char *name)
1418 {
1419         struct dma_chan *chan;
1420 
1421         chan = dma_request_slave_channel(dev, name);
1422         if (chan)
1423                 return chan;
1424 
1425         if (!fn || !fn_param)
1426                 return NULL;
1427 
1428         return __dma_request_channel(mask, fn, fn_param);
1429 }
1430 #endif /* DMAENGINE_H */
1431 

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