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TOMOYO Linux Cross Reference
Linux/include/linux/fsl_ifc.h

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  1 /* Freescale Integrated Flash Controller
  2  *
  3  * Copyright 2011 Freescale Semiconductor, Inc
  4  *
  5  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 20  */
 21 
 22 #ifndef __ASM_FSL_IFC_H
 23 #define __ASM_FSL_IFC_H
 24 
 25 #include <linux/compiler.h>
 26 #include <linux/types.h>
 27 #include <linux/io.h>
 28 
 29 #include <linux/of_platform.h>
 30 #include <linux/interrupt.h>
 31 
 32 /*
 33  * The actual number of banks implemented depends on the IFC version
 34  *    - IFC version 1.0 implements 4 banks.
 35  *    - IFC version 1.1 onward implements 8 banks.
 36  */
 37 #define FSL_IFC_BANK_COUNT 8
 38 
 39 #define FSL_IFC_VERSION_MASK    0x0F0F0000
 40 #define FSL_IFC_VERSION_1_0_0   0x01000000
 41 #define FSL_IFC_VERSION_1_1_0   0x01010000
 42 
 43 /*
 44  * CSPR - Chip Select Property Register
 45  */
 46 #define CSPR_BA                         0xFFFF0000
 47 #define CSPR_BA_SHIFT                   16
 48 #define CSPR_PORT_SIZE                  0x00000180
 49 #define CSPR_PORT_SIZE_SHIFT            7
 50 /* Port Size 8 bit */
 51 #define CSPR_PORT_SIZE_8                0x00000080
 52 /* Port Size 16 bit */
 53 #define CSPR_PORT_SIZE_16               0x00000100
 54 /* Port Size 32 bit */
 55 #define CSPR_PORT_SIZE_32               0x00000180
 56 /* Write Protect */
 57 #define CSPR_WP                         0x00000040
 58 #define CSPR_WP_SHIFT                   6
 59 /* Machine Select */
 60 #define CSPR_MSEL                       0x00000006
 61 #define CSPR_MSEL_SHIFT                 1
 62 /* NOR */
 63 #define CSPR_MSEL_NOR                   0x00000000
 64 /* NAND */
 65 #define CSPR_MSEL_NAND                  0x00000002
 66 /* GPCM */
 67 #define CSPR_MSEL_GPCM                  0x00000004
 68 /* Bank Valid */
 69 #define CSPR_V                          0x00000001
 70 #define CSPR_V_SHIFT                    0
 71 
 72 /*
 73  * Address Mask Register
 74  */
 75 #define IFC_AMASK_MASK                  0xFFFF0000
 76 #define IFC_AMASK_SHIFT                 16
 77 #define IFC_AMASK(n)                    (IFC_AMASK_MASK << \
 78                                         (__ilog2(n) - IFC_AMASK_SHIFT))
 79 
 80 /*
 81  * Chip Select Option Register IFC_NAND Machine
 82  */
 83 /* Enable ECC Encoder */
 84 #define CSOR_NAND_ECC_ENC_EN            0x80000000
 85 #define CSOR_NAND_ECC_MODE_MASK         0x30000000
 86 /* 4 bit correction per 520 Byte sector */
 87 #define CSOR_NAND_ECC_MODE_4            0x00000000
 88 /* 8 bit correction per 528 Byte sector */
 89 #define CSOR_NAND_ECC_MODE_8            0x10000000
 90 /* Enable ECC Decoder */
 91 #define CSOR_NAND_ECC_DEC_EN            0x04000000
 92 /* Row Address Length */
 93 #define CSOR_NAND_RAL_MASK              0x01800000
 94 #define CSOR_NAND_RAL_SHIFT             20
 95 #define CSOR_NAND_RAL_1                 0x00000000
 96 #define CSOR_NAND_RAL_2                 0x00800000
 97 #define CSOR_NAND_RAL_3                 0x01000000
 98 #define CSOR_NAND_RAL_4                 0x01800000
 99 /* Page Size 512b, 2k, 4k */
100 #define CSOR_NAND_PGS_MASK              0x00180000
101 #define CSOR_NAND_PGS_SHIFT             16
102 #define CSOR_NAND_PGS_512               0x00000000
103 #define CSOR_NAND_PGS_2K                0x00080000
104 #define CSOR_NAND_PGS_4K                0x00100000
105 #define CSOR_NAND_PGS_8K                0x00180000
106 /* Spare region Size */
107 #define CSOR_NAND_SPRZ_MASK             0x0000E000
108 #define CSOR_NAND_SPRZ_SHIFT            13
109 #define CSOR_NAND_SPRZ_16               0x00000000
110 #define CSOR_NAND_SPRZ_64               0x00002000
111 #define CSOR_NAND_SPRZ_128              0x00004000
112 #define CSOR_NAND_SPRZ_210              0x00006000
113 #define CSOR_NAND_SPRZ_218              0x00008000
114 #define CSOR_NAND_SPRZ_224              0x0000A000
115 #define CSOR_NAND_SPRZ_CSOR_EXT         0x0000C000
116 /* Pages Per Block */
117 #define CSOR_NAND_PB_MASK               0x00000700
118 #define CSOR_NAND_PB_SHIFT              8
119 #define CSOR_NAND_PB(n)         ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
120 /* Time for Read Enable High to Output High Impedance */
121 #define CSOR_NAND_TRHZ_MASK             0x0000001C
122 #define CSOR_NAND_TRHZ_SHIFT            2
123 #define CSOR_NAND_TRHZ_20               0x00000000
124 #define CSOR_NAND_TRHZ_40               0x00000004
125 #define CSOR_NAND_TRHZ_60               0x00000008
126 #define CSOR_NAND_TRHZ_80               0x0000000C
127 #define CSOR_NAND_TRHZ_100              0x00000010
128 /* Buffer control disable */
129 #define CSOR_NAND_BCTLD                 0x00000001
130 
131 /*
132  * Chip Select Option Register - NOR Flash Mode
133  */
134 /* Enable Address shift Mode */
135 #define CSOR_NOR_ADM_SHFT_MODE_EN       0x80000000
136 /* Page Read Enable from NOR device */
137 #define CSOR_NOR_PGRD_EN                0x10000000
138 /* AVD Toggle Enable during Burst Program */
139 #define CSOR_NOR_AVD_TGL_PGM_EN         0x01000000
140 /* Address Data Multiplexing Shift */
141 #define CSOR_NOR_ADM_MASK               0x0003E000
142 #define CSOR_NOR_ADM_SHIFT_SHIFT        13
143 #define CSOR_NOR_ADM_SHIFT(n)   ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
144 /* Type of the NOR device hooked */
145 #define CSOR_NOR_NOR_MODE_AYSNC_NOR     0x00000000
146 #define CSOR_NOR_NOR_MODE_AVD_NOR       0x00000020
147 /* Time for Read Enable High to Output High Impedance */
148 #define CSOR_NOR_TRHZ_MASK              0x0000001C
149 #define CSOR_NOR_TRHZ_SHIFT             2
150 #define CSOR_NOR_TRHZ_20                0x00000000
151 #define CSOR_NOR_TRHZ_40                0x00000004
152 #define CSOR_NOR_TRHZ_60                0x00000008
153 #define CSOR_NOR_TRHZ_80                0x0000000C
154 #define CSOR_NOR_TRHZ_100               0x00000010
155 /* Buffer control disable */
156 #define CSOR_NOR_BCTLD                  0x00000001
157 
158 /*
159  * Chip Select Option Register - GPCM Mode
160  */
161 /* GPCM Mode - Normal */
162 #define CSOR_GPCM_GPMODE_NORMAL         0x00000000
163 /* GPCM Mode - GenericASIC */
164 #define CSOR_GPCM_GPMODE_ASIC           0x80000000
165 /* Parity Mode odd/even */
166 #define CSOR_GPCM_PARITY_EVEN           0x40000000
167 /* Parity Checking enable/disable */
168 #define CSOR_GPCM_PAR_EN                0x20000000
169 /* GPCM Timeout Count */
170 #define CSOR_GPCM_GPTO_MASK             0x0F000000
171 #define CSOR_GPCM_GPTO_SHIFT            24
172 #define CSOR_GPCM_GPTO(n)       ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
173 /* GPCM External Access Termination mode for read access */
174 #define CSOR_GPCM_RGETA_EXT             0x00080000
175 /* GPCM External Access Termination mode for write access */
176 #define CSOR_GPCM_WGETA_EXT             0x00040000
177 /* Address Data Multiplexing Shift */
178 #define CSOR_GPCM_ADM_MASK              0x0003E000
179 #define CSOR_GPCM_ADM_SHIFT_SHIFT       13
180 #define CSOR_GPCM_ADM_SHIFT(n)  ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
181 /* Generic ASIC Parity error indication delay */
182 #define CSOR_GPCM_GAPERRD_MASK          0x00000180
183 #define CSOR_GPCM_GAPERRD_SHIFT         7
184 #define CSOR_GPCM_GAPERRD(n)    (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
185 /* Time for Read Enable High to Output High Impedance */
186 #define CSOR_GPCM_TRHZ_MASK             0x0000001C
187 #define CSOR_GPCM_TRHZ_20               0x00000000
188 #define CSOR_GPCM_TRHZ_40               0x00000004
189 #define CSOR_GPCM_TRHZ_60               0x00000008
190 #define CSOR_GPCM_TRHZ_80               0x0000000C
191 #define CSOR_GPCM_TRHZ_100              0x00000010
192 /* Buffer control disable */
193 #define CSOR_GPCM_BCTLD                 0x00000001
194 
195 /*
196  * Ready Busy Status Register (RB_STAT)
197  */
198 /* CSn is READY */
199 #define IFC_RB_STAT_READY_CS0           0x80000000
200 #define IFC_RB_STAT_READY_CS1           0x40000000
201 #define IFC_RB_STAT_READY_CS2           0x20000000
202 #define IFC_RB_STAT_READY_CS3           0x10000000
203 
204 /*
205  * General Control Register (GCR)
206  */
207 #define IFC_GCR_MASK                    0x8000F800
208 /* reset all IFC hardware */
209 #define IFC_GCR_SOFT_RST_ALL            0x80000000
210 /* Turnaroud Time of external buffer */
211 #define IFC_GCR_TBCTL_TRN_TIME          0x0000F800
212 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT    11
213 
214 /*
215  * Common Event and Error Status Register (CM_EVTER_STAT)
216  */
217 /* Chip select error */
218 #define IFC_CM_EVTER_STAT_CSER          0x80000000
219 
220 /*
221  * Common Event and Error Enable Register (CM_EVTER_EN)
222  */
223 /* Chip select error checking enable */
224 #define IFC_CM_EVTER_EN_CSEREN          0x80000000
225 
226 /*
227  * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
228  */
229 /* Chip select error interrupt enable */
230 #define IFC_CM_EVTER_INTR_EN_CSERIREN   0x80000000
231 
232 /*
233  * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
234  */
235 /* transaction type of error Read/Write */
236 #define IFC_CM_ERATTR0_ERTYP_READ       0x80000000
237 #define IFC_CM_ERATTR0_ERAID            0x0FF00000
238 #define IFC_CM_ERATTR0_ERAID_SHIFT      20
239 #define IFC_CM_ERATTR0_ESRCID           0x0000FF00
240 #define IFC_CM_ERATTR0_ESRCID_SHIFT     8
241 
242 /*
243  * Clock Control Register (CCR)
244  */
245 #define IFC_CCR_MASK                    0x0F0F8800
246 /* Clock division ratio */
247 #define IFC_CCR_CLK_DIV_MASK            0x0F000000
248 #define IFC_CCR_CLK_DIV_SHIFT           24
249 #define IFC_CCR_CLK_DIV(n)              ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
250 /* IFC Clock Delay */
251 #define IFC_CCR_CLK_DLY_MASK            0x000F0000
252 #define IFC_CCR_CLK_DLY_SHIFT           16
253 #define IFC_CCR_CLK_DLY(n)              ((n) << IFC_CCR_CLK_DLY_SHIFT)
254 /* Invert IFC clock before sending out */
255 #define IFC_CCR_INV_CLK_EN              0x00008000
256 /* Fedback IFC Clock */
257 #define IFC_CCR_FB_IFC_CLK_SEL          0x00000800
258 
259 /*
260  * Clock Status Register (CSR)
261  */
262 /* Clk is stable */
263 #define IFC_CSR_CLK_STAT_STABLE         0x80000000
264 
265 /*
266  * IFC_NAND Machine Specific Registers
267  */
268 /*
269  * NAND Configuration Register (NCFGR)
270  */
271 /* Auto Boot Mode */
272 #define IFC_NAND_NCFGR_BOOT             0x80000000
273 /* Addressing Mode-ROW0+n/COL0 */
274 #define IFC_NAND_NCFGR_ADDR_MODE_RC0    0x00000000
275 /* Addressing Mode-ROW0+n/COL0+n */
276 #define IFC_NAND_NCFGR_ADDR_MODE_RC1    0x00400000
277 /* Number of loop iterations of FIR sequences for multi page operations */
278 #define IFC_NAND_NCFGR_NUM_LOOP_MASK    0x0000F000
279 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT   12
280 #define IFC_NAND_NCFGR_NUM_LOOP(n)      ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
281 /* Number of wait cycles */
282 #define IFC_NAND_NCFGR_NUM_WAIT_MASK    0x000000FF
283 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT   0
284 
285 /*
286  * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
287  */
288 /* General purpose FCM flash command bytes CMD0-CMD7 */
289 #define IFC_NAND_FCR0_CMD0              0xFF000000
290 #define IFC_NAND_FCR0_CMD0_SHIFT        24
291 #define IFC_NAND_FCR0_CMD1              0x00FF0000
292 #define IFC_NAND_FCR0_CMD1_SHIFT        16
293 #define IFC_NAND_FCR0_CMD2              0x0000FF00
294 #define IFC_NAND_FCR0_CMD2_SHIFT        8
295 #define IFC_NAND_FCR0_CMD3              0x000000FF
296 #define IFC_NAND_FCR0_CMD3_SHIFT        0
297 #define IFC_NAND_FCR1_CMD4              0xFF000000
298 #define IFC_NAND_FCR1_CMD4_SHIFT        24
299 #define IFC_NAND_FCR1_CMD5              0x00FF0000
300 #define IFC_NAND_FCR1_CMD5_SHIFT        16
301 #define IFC_NAND_FCR1_CMD6              0x0000FF00
302 #define IFC_NAND_FCR1_CMD6_SHIFT        8
303 #define IFC_NAND_FCR1_CMD7              0x000000FF
304 #define IFC_NAND_FCR1_CMD7_SHIFT        0
305 
306 /*
307  * Flash ROW and COL Address Register (ROWn, COLn)
308  */
309 /* Main/spare region locator */
310 #define IFC_NAND_COL_MS                 0x80000000
311 /* Column Address */
312 #define IFC_NAND_COL_CA_MASK            0x00000FFF
313 
314 /*
315  * NAND Flash Byte Count Register (NAND_BC)
316  */
317 /* Byte Count for read/Write */
318 #define IFC_NAND_BC                     0x000001FF
319 
320 /*
321  * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
322  */
323 /* NAND Machine specific opcodes OP0-OP14*/
324 #define IFC_NAND_FIR0_OP0               0xFC000000
325 #define IFC_NAND_FIR0_OP0_SHIFT         26
326 #define IFC_NAND_FIR0_OP1               0x03F00000
327 #define IFC_NAND_FIR0_OP1_SHIFT         20
328 #define IFC_NAND_FIR0_OP2               0x000FC000
329 #define IFC_NAND_FIR0_OP2_SHIFT         14
330 #define IFC_NAND_FIR0_OP3               0x00003F00
331 #define IFC_NAND_FIR0_OP3_SHIFT         8
332 #define IFC_NAND_FIR0_OP4               0x000000FC
333 #define IFC_NAND_FIR0_OP4_SHIFT         2
334 #define IFC_NAND_FIR1_OP5               0xFC000000
335 #define IFC_NAND_FIR1_OP5_SHIFT         26
336 #define IFC_NAND_FIR1_OP6               0x03F00000
337 #define IFC_NAND_FIR1_OP6_SHIFT         20
338 #define IFC_NAND_FIR1_OP7               0x000FC000
339 #define IFC_NAND_FIR1_OP7_SHIFT         14
340 #define IFC_NAND_FIR1_OP8               0x00003F00
341 #define IFC_NAND_FIR1_OP8_SHIFT         8
342 #define IFC_NAND_FIR1_OP9               0x000000FC
343 #define IFC_NAND_FIR1_OP9_SHIFT         2
344 #define IFC_NAND_FIR2_OP10              0xFC000000
345 #define IFC_NAND_FIR2_OP10_SHIFT        26
346 #define IFC_NAND_FIR2_OP11              0x03F00000
347 #define IFC_NAND_FIR2_OP11_SHIFT        20
348 #define IFC_NAND_FIR2_OP12              0x000FC000
349 #define IFC_NAND_FIR2_OP12_SHIFT        14
350 #define IFC_NAND_FIR2_OP13              0x00003F00
351 #define IFC_NAND_FIR2_OP13_SHIFT        8
352 #define IFC_NAND_FIR2_OP14              0x000000FC
353 #define IFC_NAND_FIR2_OP14_SHIFT        2
354 
355 /*
356  * Instruction opcodes to be programmed
357  * in FIR registers- 6bits
358  */
359 enum ifc_nand_fir_opcodes {
360         IFC_FIR_OP_NOP,
361         IFC_FIR_OP_CA0,
362         IFC_FIR_OP_CA1,
363         IFC_FIR_OP_CA2,
364         IFC_FIR_OP_CA3,
365         IFC_FIR_OP_RA0,
366         IFC_FIR_OP_RA1,
367         IFC_FIR_OP_RA2,
368         IFC_FIR_OP_RA3,
369         IFC_FIR_OP_CMD0,
370         IFC_FIR_OP_CMD1,
371         IFC_FIR_OP_CMD2,
372         IFC_FIR_OP_CMD3,
373         IFC_FIR_OP_CMD4,
374         IFC_FIR_OP_CMD5,
375         IFC_FIR_OP_CMD6,
376         IFC_FIR_OP_CMD7,
377         IFC_FIR_OP_CW0,
378         IFC_FIR_OP_CW1,
379         IFC_FIR_OP_CW2,
380         IFC_FIR_OP_CW3,
381         IFC_FIR_OP_CW4,
382         IFC_FIR_OP_CW5,
383         IFC_FIR_OP_CW6,
384         IFC_FIR_OP_CW7,
385         IFC_FIR_OP_WBCD,
386         IFC_FIR_OP_RBCD,
387         IFC_FIR_OP_BTRD,
388         IFC_FIR_OP_RDSTAT,
389         IFC_FIR_OP_NWAIT,
390         IFC_FIR_OP_WFR,
391         IFC_FIR_OP_SBRD,
392         IFC_FIR_OP_UA,
393         IFC_FIR_OP_RB,
394 };
395 
396 /*
397  * NAND Chip Select Register (NAND_CSEL)
398  */
399 #define IFC_NAND_CSEL                   0x0C000000
400 #define IFC_NAND_CSEL_SHIFT             26
401 #define IFC_NAND_CSEL_CS0               0x00000000
402 #define IFC_NAND_CSEL_CS1               0x04000000
403 #define IFC_NAND_CSEL_CS2               0x08000000
404 #define IFC_NAND_CSEL_CS3               0x0C000000
405 
406 /*
407  * NAND Operation Sequence Start (NANDSEQ_STRT)
408  */
409 /* NAND Flash Operation Start */
410 #define IFC_NAND_SEQ_STRT_FIR_STRT      0x80000000
411 /* Automatic Erase */
412 #define IFC_NAND_SEQ_STRT_AUTO_ERS      0x00800000
413 /* Automatic Program */
414 #define IFC_NAND_SEQ_STRT_AUTO_PGM      0x00100000
415 /* Automatic Copyback */
416 #define IFC_NAND_SEQ_STRT_AUTO_CPB      0x00020000
417 /* Automatic Read Operation */
418 #define IFC_NAND_SEQ_STRT_AUTO_RD       0x00004000
419 /* Automatic Status Read */
420 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD  0x00000800
421 
422 /*
423  * NAND Event and Error Status Register (NAND_EVTER_STAT)
424  */
425 /* Operation Complete */
426 #define IFC_NAND_EVTER_STAT_OPC         0x80000000
427 /* Flash Timeout Error */
428 #define IFC_NAND_EVTER_STAT_FTOER       0x08000000
429 /* Write Protect Error */
430 #define IFC_NAND_EVTER_STAT_WPER        0x04000000
431 /* ECC Error */
432 #define IFC_NAND_EVTER_STAT_ECCER       0x02000000
433 /* RCW Load Done */
434 #define IFC_NAND_EVTER_STAT_RCW_DN      0x00008000
435 /* Boot Loadr Done */
436 #define IFC_NAND_EVTER_STAT_BOOT_DN     0x00004000
437 /* Bad Block Indicator search select */
438 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
439 
440 /*
441  * NAND Flash Page Read Completion Event Status Register
442  * (PGRDCMPL_EVT_STAT)
443  */
444 #define PGRDCMPL_EVT_STAT_MASK          0xFFFF0000
445 /* Small Page 0-15 Done */
446 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
447 /* Large Page(2K) 0-3 Done */
448 #define PGRDCMPL_EVT_STAT_LP_2K(n)      (0xF << (28 - (n)*4))
449 /* Large Page(4K) 0-1 Done */
450 #define PGRDCMPL_EVT_STAT_LP_4K(n)      (0xFF << (24 - (n)*8))
451 
452 /*
453  * NAND Event and Error Enable Register (NAND_EVTER_EN)
454  */
455 /* Operation complete event enable */
456 #define IFC_NAND_EVTER_EN_OPC_EN        0x80000000
457 /* Page read complete event enable */
458 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN   0x20000000
459 /* Flash Timeout error enable */
460 #define IFC_NAND_EVTER_EN_FTOER_EN      0x08000000
461 /* Write Protect error enable */
462 #define IFC_NAND_EVTER_EN_WPER_EN       0x04000000
463 /* ECC error logging enable */
464 #define IFC_NAND_EVTER_EN_ECCER_EN      0x02000000
465 
466 /*
467  * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
468  */
469 /* Enable interrupt for operation complete */
470 #define IFC_NAND_EVTER_INTR_OPCIR_EN            0x80000000
471 /* Enable interrupt for Page read complete */
472 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN       0x20000000
473 /* Enable interrupt for Flash timeout error */
474 #define IFC_NAND_EVTER_INTR_FTOERIR_EN          0x08000000
475 /* Enable interrupt for Write protect error */
476 #define IFC_NAND_EVTER_INTR_WPERIR_EN           0x04000000
477 /* Enable interrupt for ECC error*/
478 #define IFC_NAND_EVTER_INTR_ECCERIR_EN          0x02000000
479 
480 /*
481  * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
482  */
483 #define IFC_NAND_ERATTR0_MASK           0x0C080000
484 /* Error on CS0-3 for NAND */
485 #define IFC_NAND_ERATTR0_ERCS_CS0       0x00000000
486 #define IFC_NAND_ERATTR0_ERCS_CS1       0x04000000
487 #define IFC_NAND_ERATTR0_ERCS_CS2       0x08000000
488 #define IFC_NAND_ERATTR0_ERCS_CS3       0x0C000000
489 /* Transaction type of error Read/Write */
490 #define IFC_NAND_ERATTR0_ERTTYPE_READ   0x00080000
491 
492 /*
493  * NAND Flash Status Register (NAND_FSR)
494  */
495 /* First byte of data read from read status op */
496 #define IFC_NAND_NFSR_RS0               0xFF000000
497 /* Second byte of data read from read status op */
498 #define IFC_NAND_NFSR_RS1               0x00FF0000
499 
500 /*
501  * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
502  */
503 /* Number of ECC errors on sector n (n = 0-15) */
504 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK   0x0F000000
505 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT  24
506 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK   0x000F0000
507 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT  16
508 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK   0x00000F00
509 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT  8
510 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK   0x0000000F
511 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT  0
512 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK   0x0F000000
513 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT  24
514 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK   0x000F0000
515 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT  16
516 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK   0x00000F00
517 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT  8
518 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK   0x0000000F
519 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT  0
520 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK   0x0F000000
521 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT  24
522 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK   0x000F0000
523 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT  16
524 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK  0x00000F00
525 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
526 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK  0x0000000F
527 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
528 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK  0x0F000000
529 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
530 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK  0x000F0000
531 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
532 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK  0x00000F00
533 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
534 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK  0x0000000F
535 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
536 
537 /*
538  * NAND Control Register (NANDCR)
539  */
540 #define IFC_NAND_NCR_FTOCNT_MASK        0x1E000000
541 #define IFC_NAND_NCR_FTOCNT_SHIFT       25
542 #define IFC_NAND_NCR_FTOCNT(n)  ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
543 
544 /*
545  * NAND_AUTOBOOT_TRGR
546  */
547 /* Trigger RCW load */
548 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD   0x80000000
549 /* Trigget Auto Boot */
550 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD  0x20000000
551 
552 /*
553  * NAND_MDR
554  */
555 /* 1st read data byte when opcode SBRD */
556 #define IFC_NAND_MDR_RDATA0             0xFF000000
557 /* 2nd read data byte when opcode SBRD */
558 #define IFC_NAND_MDR_RDATA1             0x00FF0000
559 
560 /*
561  * NOR Machine Specific Registers
562  */
563 /*
564  * NOR Event and Error Status Register (NOR_EVTER_STAT)
565  */
566 /* NOR Command Sequence Operation Complete */
567 #define IFC_NOR_EVTER_STAT_OPC_NOR      0x80000000
568 /* Write Protect Error */
569 #define IFC_NOR_EVTER_STAT_WPER         0x04000000
570 /* Command Sequence Timeout Error */
571 #define IFC_NOR_EVTER_STAT_STOER        0x01000000
572 
573 /*
574  * NOR Event and Error Enable Register (NOR_EVTER_EN)
575  */
576 /* NOR Command Seq complete event enable */
577 #define IFC_NOR_EVTER_EN_OPCEN_NOR      0x80000000
578 /* Write Protect Error Checking Enable */
579 #define IFC_NOR_EVTER_EN_WPEREN         0x04000000
580 /* Timeout Error Enable */
581 #define IFC_NOR_EVTER_EN_STOEREN        0x01000000
582 
583 /*
584  * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
585  */
586 /* Enable interrupt for OPC complete */
587 #define IFC_NOR_EVTER_INTR_OPCEN_NOR    0x80000000
588 /* Enable interrupt for write protect error */
589 #define IFC_NOR_EVTER_INTR_WPEREN       0x04000000
590 /* Enable interrupt for timeout error */
591 #define IFC_NOR_EVTER_INTR_STOEREN      0x01000000
592 
593 /*
594  * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
595  */
596 /* Source ID for error transaction */
597 #define IFC_NOR_ERATTR0_ERSRCID         0xFF000000
598 /* AXI ID for error transation */
599 #define IFC_NOR_ERATTR0_ERAID           0x000FF000
600 /* Chip select corresponds to NOR error */
601 #define IFC_NOR_ERATTR0_ERCS_CS0        0x00000000
602 #define IFC_NOR_ERATTR0_ERCS_CS1        0x00000010
603 #define IFC_NOR_ERATTR0_ERCS_CS2        0x00000020
604 #define IFC_NOR_ERATTR0_ERCS_CS3        0x00000030
605 /* Type of transaction read/write */
606 #define IFC_NOR_ERATTR0_ERTYPE_READ     0x00000001
607 
608 /*
609  * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
610  */
611 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP        0x000F0000
612 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER        0x00000F00
613 
614 /*
615  * NOR Control Register (NORCR)
616  */
617 #define IFC_NORCR_MASK                  0x0F0F0000
618 /* No. of Address/Data Phase */
619 #define IFC_NORCR_NUM_PHASE_MASK        0x0F000000
620 #define IFC_NORCR_NUM_PHASE_SHIFT       24
621 #define IFC_NORCR_NUM_PHASE(n)  ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
622 /* Sequence Timeout Count */
623 #define IFC_NORCR_STOCNT_MASK           0x000F0000
624 #define IFC_NORCR_STOCNT_SHIFT          16
625 #define IFC_NORCR_STOCNT(n)     ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
626 
627 /*
628  * GPCM Machine specific registers
629  */
630 /*
631  * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
632  */
633 /* Timeout error */
634 #define IFC_GPCM_EVTER_STAT_TOER        0x04000000
635 /* Parity error */
636 #define IFC_GPCM_EVTER_STAT_PER         0x01000000
637 
638 /*
639  * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
640  */
641 /* Timeout error enable */
642 #define IFC_GPCM_EVTER_EN_TOER_EN       0x04000000
643 /* Parity error enable */
644 #define IFC_GPCM_EVTER_EN_PER_EN        0x01000000
645 
646 /*
647  * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
648  */
649 /* Enable Interrupt for timeout error */
650 #define IFC_GPCM_EEIER_TOERIR_EN        0x04000000
651 /* Enable Interrupt for Parity error */
652 #define IFC_GPCM_EEIER_PERIR_EN         0x01000000
653 
654 /*
655  * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
656  */
657 /* Source ID for error transaction */
658 #define IFC_GPCM_ERATTR0_ERSRCID        0xFF000000
659 /* AXI ID for error transaction */
660 #define IFC_GPCM_ERATTR0_ERAID          0x000FF000
661 /* Chip select corresponds to GPCM error */
662 #define IFC_GPCM_ERATTR0_ERCS_CS0       0x00000000
663 #define IFC_GPCM_ERATTR0_ERCS_CS1       0x00000040
664 #define IFC_GPCM_ERATTR0_ERCS_CS2       0x00000080
665 #define IFC_GPCM_ERATTR0_ERCS_CS3       0x000000C0
666 /* Type of transaction read/Write */
667 #define IFC_GPCM_ERATTR0_ERTYPE_READ    0x00000001
668 
669 /*
670  * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
671  */
672 /* On which beat of address/data parity error is observed */
673 #define IFC_GPCM_ERATTR2_PERR_BEAT              0x00000C00
674 /* Parity Error on byte */
675 #define IFC_GPCM_ERATTR2_PERR_BYTE              0x000000F0
676 /* Parity Error reported in addr or data phase */
677 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE        0x00000001
678 
679 /*
680  * GPCM Status Register (GPCM_STAT)
681  */
682 #define IFC_GPCM_STAT_BSY               0x80000000  /* GPCM is busy */
683 
684 /*
685  * IFC Controller NAND Machine registers
686  */
687 struct fsl_ifc_nand {
688         __be32 ncfgr;
689         u32 res1[0x4];
690         __be32 nand_fcr0;
691         __be32 nand_fcr1;
692         u32 res2[0x8];
693         __be32 row0;
694         u32 res3;
695         __be32 col0;
696         u32 res4;
697         __be32 row1;
698         u32 res5;
699         __be32 col1;
700         u32 res6;
701         __be32 row2;
702         u32 res7;
703         __be32 col2;
704         u32 res8;
705         __be32 row3;
706         u32 res9;
707         __be32 col3;
708         u32 res10[0x24];
709         __be32 nand_fbcr;
710         u32 res11;
711         __be32 nand_fir0;
712         __be32 nand_fir1;
713         __be32 nand_fir2;
714         u32 res12[0x10];
715         __be32 nand_csel;
716         u32 res13;
717         __be32 nandseq_strt;
718         u32 res14;
719         __be32 nand_evter_stat;
720         u32 res15;
721         __be32 pgrdcmpl_evt_stat;
722         u32 res16[0x2];
723         __be32 nand_evter_en;
724         u32 res17[0x2];
725         __be32 nand_evter_intr_en;
726         u32 res18[0x2];
727         __be32 nand_erattr0;
728         __be32 nand_erattr1;
729         u32 res19[0x10];
730         __be32 nand_fsr;
731         u32 res20;
732         __be32 nand_eccstat[4];
733         u32 res21[0x20];
734         __be32 nanndcr;
735         u32 res22[0x2];
736         __be32 nand_autoboot_trgr;
737         u32 res23;
738         __be32 nand_mdr;
739         u32 res24[0x5C];
740 };
741 
742 /*
743  * IFC controller NOR Machine registers
744  */
745 struct fsl_ifc_nor {
746         __be32 nor_evter_stat;
747         u32 res1[0x2];
748         __be32 nor_evter_en;
749         u32 res2[0x2];
750         __be32 nor_evter_intr_en;
751         u32 res3[0x2];
752         __be32 nor_erattr0;
753         __be32 nor_erattr1;
754         __be32 nor_erattr2;
755         u32 res4[0x4];
756         __be32 norcr;
757         u32 res5[0xEF];
758 };
759 
760 /*
761  * IFC controller GPCM Machine registers
762  */
763 struct fsl_ifc_gpcm {
764         __be32 gpcm_evter_stat;
765         u32 res1[0x2];
766         __be32 gpcm_evter_en;
767         u32 res2[0x2];
768         __be32 gpcm_evter_intr_en;
769         u32 res3[0x2];
770         __be32 gpcm_erattr0;
771         __be32 gpcm_erattr1;
772         __be32 gpcm_erattr2;
773         __be32 gpcm_stat;
774         u32 res4[0x1F3];
775 };
776 
777 /*
778  * IFC Controller Registers
779  */
780 struct fsl_ifc_regs {
781         __be32 ifc_rev;
782         u32 res1[0x2];
783         struct {
784                 __be32 cspr_ext;
785                 __be32 cspr;
786                 u32 res2;
787         } cspr_cs[FSL_IFC_BANK_COUNT];
788         u32 res3[0xd];
789         struct {
790                 __be32 amask;
791                 u32 res4[0x2];
792         } amask_cs[FSL_IFC_BANK_COUNT];
793         u32 res5[0xc];
794         struct {
795                 __be32 csor;
796                 __be32 csor_ext;
797                 u32 res6;
798         } csor_cs[FSL_IFC_BANK_COUNT];
799         u32 res7[0xc];
800         struct {
801                 __be32 ftim[4];
802                 u32 res8[0x8];
803         } ftim_cs[FSL_IFC_BANK_COUNT];
804         u32 res9[0x30];
805         __be32 rb_stat;
806         u32 res10[0x2];
807         __be32 ifc_gcr;
808         u32 res11[0x2];
809         __be32 cm_evter_stat;
810         u32 res12[0x2];
811         __be32 cm_evter_en;
812         u32 res13[0x2];
813         __be32 cm_evter_intr_en;
814         u32 res14[0x2];
815         __be32 cm_erattr0;
816         __be32 cm_erattr1;
817         u32 res15[0x2];
818         __be32 ifc_ccr;
819         __be32 ifc_csr;
820         u32 res16[0x2EB];
821         struct fsl_ifc_nand ifc_nand;
822         struct fsl_ifc_nor ifc_nor;
823         struct fsl_ifc_gpcm ifc_gpcm;
824 };
825 
826 extern unsigned int convert_ifc_address(phys_addr_t addr_base);
827 extern int fsl_ifc_find(phys_addr_t addr_base);
828 
829 /* overview of the fsl ifc controller */
830 
831 struct fsl_ifc_ctrl {
832         /* device info */
833         struct device                   *dev;
834         struct fsl_ifc_regs __iomem     *regs;
835         int                             irq;
836         int                             nand_irq;
837         spinlock_t                      lock;
838         void                            *nand;
839         int                             version;
840         int                             banks;
841 
842         u32 nand_stat;
843         wait_queue_head_t nand_wait;
844 };
845 
846 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
847 
848 
849 #endif /* __ASM_FSL_IFC_H */
850 

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