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TOMOYO Linux Cross Reference
Linux/include/linux/gpio/driver.h

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  1 #ifndef __LINUX_GPIO_DRIVER_H
  2 #define __LINUX_GPIO_DRIVER_H
  3 
  4 #include <linux/device.h>
  5 #include <linux/types.h>
  6 #include <linux/irq.h>
  7 #include <linux/irqchip/chained_irq.h>
  8 #include <linux/irqdomain.h>
  9 #include <linux/lockdep.h>
 10 #include <linux/pinctrl/pinctrl.h>
 11 #include <linux/pinctrl/pinconf-generic.h>
 12 
 13 struct gpio_desc;
 14 struct of_phandle_args;
 15 struct device_node;
 16 struct seq_file;
 17 struct gpio_device;
 18 struct module;
 19 
 20 #ifdef CONFIG_GPIOLIB
 21 
 22 /**
 23  * struct gpio_chip - abstract a GPIO controller
 24  * @label: a functional name for the GPIO device, such as a part
 25  *      number or the name of the SoC IP-block implementing it.
 26  * @gpiodev: the internal state holder, opaque struct
 27  * @parent: optional parent device providing the GPIOs
 28  * @owner: helps prevent removal of modules exporting active GPIOs
 29  * @request: optional hook for chip-specific activation, such as
 30  *      enabling module power and clock; may sleep
 31  * @free: optional hook for chip-specific deactivation, such as
 32  *      disabling module power and clock; may sleep
 33  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 34  *      (same as GPIOF_DIR_XXX), or negative error
 35  * @direction_input: configures signal "offset" as input, or returns error
 36  * @direction_output: configures signal "offset" as output, or returns error
 37  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 38  * @set: assigns output value for signal "offset"
 39  * @set_multiple: assigns output values for multiple signals defined by "mask"
 40  * @set_config: optional hook for all kinds of settings. Uses the same
 41  *      packed config format as generic pinconf.
 42  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 43  *      implementation may not sleep
 44  * @dbg_show: optional routine to show contents in debugfs; default code
 45  *      will be used when this is omitted, but custom code can show extra
 46  *      state (such as pullup/pulldown configuration).
 47  * @base: identifies the first GPIO number handled by this chip;
 48  *      or, if negative during registration, requests dynamic ID allocation.
 49  *      DEPRECATION: providing anything non-negative and nailing the base
 50  *      offset of GPIO chips is deprecated. Please pass -1 as base to
 51  *      let gpiolib select the chip base in all possible cases. We want to
 52  *      get rid of the static GPIO number space in the long run.
 53  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 54  *      handled is (base + ngpio - 1).
 55  * @names: if set, must be an array of strings to use as alternative
 56  *      names for the GPIOs in this chip. Any entry in the array
 57  *      may be NULL if there is no alias for the GPIO, however the
 58  *      array must be @ngpio entries long.  A name can include a single printk
 59  *      format specifier for an unsigned int.  It is substituted by the actual
 60  *      number of the gpio.
 61  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 62  *      must while accessing GPIO expander chips over I2C or SPI. This
 63  *      implies that if the chip supports IRQs, these IRQs need to be threaded
 64  *      as the chip access may sleep when e.g. reading out the IRQ status
 65  *      registers.
 66  * @read_reg: reader function for generic GPIO
 67  * @write_reg: writer function for generic GPIO
 68  * @pin2mask: some generic GPIO controllers work with the big-endian bits
 69  *      notation, e.g. in a 8-bits register, GPIO7 is the least significant
 70  *      bit. This callback assigns the right bit mask.
 71  * @reg_dat: data (in) register for generic GPIO
 72  * @reg_set: output set register (out=high) for generic GPIO
 73  * @reg_clr: output clear register (out=low) for generic GPIO
 74  * @reg_dir: direction setting register for generic GPIO
 75  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 76  *      <register width> * 8
 77  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 78  *      shadowed and real data registers writes together.
 79  * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
 80  *      safely.
 81  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 82  *      direction safely.
 83  * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
 84  * @irqdomain: Interrupt translation domain; responsible for mapping
 85  *      between GPIO hwirq number and linux irq number
 86  * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
 87  * @irq_handler: the irq handler to use (often a predefined irq core function)
 88  *      for GPIO IRQs, provided by GPIO driver
 89  * @irq_default_type: default IRQ triggering type applied during GPIO driver
 90  *      initialization, provided by GPIO driver
 91  * @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,
 92  *      provided by GPIO driver for chained interrupt (not for nested
 93  *      interrupts).
 94  * @irq_nested: True if set the interrupt handling is nested.
 95  * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
 96  *      bits set to one
 97  * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
 98  *      be included in IRQ domain of the chip
 99  * @lock_key: per GPIO IRQ chip lockdep class
100  *
101  * A gpio_chip can help platforms abstract various sources of GPIOs so
102  * they can all be accessed through a common programing interface.
103  * Example sources would be SOC controllers, FPGAs, multifunction
104  * chips, dedicated GPIO expanders, and so on.
105  *
106  * Each chip controls a number of signals, identified in method calls
107  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
108  * are referenced through calls like gpio_get_value(gpio), the offset
109  * is calculated by subtracting @base from the gpio number.
110  */
111 struct gpio_chip {
112         const char              *label;
113         struct gpio_device      *gpiodev;
114         struct device           *parent;
115         struct module           *owner;
116 
117         int                     (*request)(struct gpio_chip *chip,
118                                                 unsigned offset);
119         void                    (*free)(struct gpio_chip *chip,
120                                                 unsigned offset);
121         int                     (*get_direction)(struct gpio_chip *chip,
122                                                 unsigned offset);
123         int                     (*direction_input)(struct gpio_chip *chip,
124                                                 unsigned offset);
125         int                     (*direction_output)(struct gpio_chip *chip,
126                                                 unsigned offset, int value);
127         int                     (*get)(struct gpio_chip *chip,
128                                                 unsigned offset);
129         void                    (*set)(struct gpio_chip *chip,
130                                                 unsigned offset, int value);
131         void                    (*set_multiple)(struct gpio_chip *chip,
132                                                 unsigned long *mask,
133                                                 unsigned long *bits);
134         int                     (*set_config)(struct gpio_chip *chip,
135                                               unsigned offset,
136                                               unsigned long config);
137         int                     (*to_irq)(struct gpio_chip *chip,
138                                                 unsigned offset);
139 
140         void                    (*dbg_show)(struct seq_file *s,
141                                                 struct gpio_chip *chip);
142         int                     base;
143         u16                     ngpio;
144         const char              *const *names;
145         bool                    can_sleep;
146 
147 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
148         unsigned long (*read_reg)(void __iomem *reg);
149         void (*write_reg)(void __iomem *reg, unsigned long data);
150         unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
151         void __iomem *reg_dat;
152         void __iomem *reg_set;
153         void __iomem *reg_clr;
154         void __iomem *reg_dir;
155         int bgpio_bits;
156         spinlock_t bgpio_lock;
157         unsigned long bgpio_data;
158         unsigned long bgpio_dir;
159 #endif
160 
161 #ifdef CONFIG_GPIOLIB_IRQCHIP
162         /*
163          * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
164          * to handle IRQs for most practical cases.
165          */
166         struct irq_chip         *irqchip;
167         struct irq_domain       *irqdomain;
168         unsigned int            irq_base;
169         irq_flow_handler_t      irq_handler;
170         unsigned int            irq_default_type;
171         unsigned int            irq_chained_parent;
172         bool                    irq_nested;
173         bool                    irq_need_valid_mask;
174         unsigned long           *irq_valid_mask;
175         struct lock_class_key   *lock_key;
176 #endif
177 
178 #if defined(CONFIG_OF_GPIO)
179         /*
180          * If CONFIG_OF is enabled, then all GPIO controllers described in the
181          * device tree automatically may have an OF translation
182          */
183         struct device_node *of_node;
184         int of_gpio_n_cells;
185         int (*of_xlate)(struct gpio_chip *gc,
186                         const struct of_phandle_args *gpiospec, u32 *flags);
187 #endif
188 };
189 
190 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
191                         unsigned offset);
192 
193 /* add/remove chips */
194 extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
195 static inline int gpiochip_add(struct gpio_chip *chip)
196 {
197         return gpiochip_add_data(chip, NULL);
198 }
199 extern void gpiochip_remove(struct gpio_chip *chip);
200 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
201                                   void *data);
202 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
203 
204 extern struct gpio_chip *gpiochip_find(void *data,
205                               int (*match)(struct gpio_chip *chip, void *data));
206 
207 /* lock/unlock as IRQ */
208 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
209 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
210 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
211 
212 /* Line status inquiry for drivers */
213 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
214 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
215 
216 /* get driver data */
217 void *gpiochip_get_data(struct gpio_chip *chip);
218 
219 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
220 
221 struct bgpio_pdata {
222         const char *label;
223         int base;
224         int ngpio;
225 };
226 
227 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
228 
229 int bgpio_init(struct gpio_chip *gc, struct device *dev,
230                unsigned long sz, void __iomem *dat, void __iomem *set,
231                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
232                unsigned long flags);
233 
234 #define BGPIOF_BIG_ENDIAN               BIT(0)
235 #define BGPIOF_UNREADABLE_REG_SET       BIT(1) /* reg_set is unreadable */
236 #define BGPIOF_UNREADABLE_REG_DIR       BIT(2) /* reg_dir is unreadable */
237 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER    BIT(3)
238 #define BGPIOF_READ_OUTPUT_REG_SET      BIT(4) /* reg_set stores output value */
239 #define BGPIOF_NO_OUTPUT                BIT(5) /* only input */
240 
241 #endif
242 
243 #ifdef CONFIG_GPIOLIB_IRQCHIP
244 
245 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
246                 struct irq_chip *irqchip,
247                 unsigned int parent_irq,
248                 irq_flow_handler_t parent_handler);
249 
250 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
251                 struct irq_chip *irqchip,
252                 unsigned int parent_irq);
253 
254 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
255                              struct irq_chip *irqchip,
256                              unsigned int first_irq,
257                              irq_flow_handler_t handler,
258                              unsigned int type,
259                              bool nested,
260                              struct lock_class_key *lock_key);
261 
262 #ifdef CONFIG_LOCKDEP
263 
264 /*
265  * Lockdep requires that each irqchip instance be created with a
266  * unique key so as to avoid unnecessary warnings. This upfront
267  * boilerplate static inlines provides such a key for each
268  * unique instance.
269  */
270 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
271                                        struct irq_chip *irqchip,
272                                        unsigned int first_irq,
273                                        irq_flow_handler_t handler,
274                                        unsigned int type)
275 {
276         static struct lock_class_key key;
277 
278         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
279                                         handler, type, false, &key);
280 }
281 
282 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
283                           struct irq_chip *irqchip,
284                           unsigned int first_irq,
285                           irq_flow_handler_t handler,
286                           unsigned int type)
287 {
288 
289         static struct lock_class_key key;
290 
291         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
292                                         handler, type, true, &key);
293 }
294 #else
295 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
296                                        struct irq_chip *irqchip,
297                                        unsigned int first_irq,
298                                        irq_flow_handler_t handler,
299                                        unsigned int type)
300 {
301         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
302                                         handler, type, false, NULL);
303 }
304 
305 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
306                           struct irq_chip *irqchip,
307                           unsigned int first_irq,
308                           irq_flow_handler_t handler,
309                           unsigned int type)
310 {
311         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
312                                         handler, type, true, NULL);
313 }
314 #endif /* CONFIG_LOCKDEP */
315 
316 #endif /* CONFIG_GPIOLIB_IRQCHIP */
317 
318 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
319 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
320 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
321                             unsigned long config);
322 
323 #ifdef CONFIG_PINCTRL
324 
325 /**
326  * struct gpio_pin_range - pin range controlled by a gpio chip
327  * @head: list for maintaining set of pin ranges, used internally
328  * @pctldev: pinctrl device which handles corresponding pins
329  * @range: actual range of pins controlled by a gpio controller
330  */
331 
332 struct gpio_pin_range {
333         struct list_head node;
334         struct pinctrl_dev *pctldev;
335         struct pinctrl_gpio_range range;
336 };
337 
338 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
339                            unsigned int gpio_offset, unsigned int pin_offset,
340                            unsigned int npins);
341 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
342                         struct pinctrl_dev *pctldev,
343                         unsigned int gpio_offset, const char *pin_group);
344 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
345 
346 #else
347 
348 static inline int
349 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
350                        unsigned int gpio_offset, unsigned int pin_offset,
351                        unsigned int npins)
352 {
353         return 0;
354 }
355 static inline int
356 gpiochip_add_pingroup_range(struct gpio_chip *chip,
357                         struct pinctrl_dev *pctldev,
358                         unsigned int gpio_offset, const char *pin_group)
359 {
360         return 0;
361 }
362 
363 static inline void
364 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
365 {
366 }
367 
368 #endif /* CONFIG_PINCTRL */
369 
370 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
371                                             const char *label);
372 void gpiochip_free_own_desc(struct gpio_desc *desc);
373 
374 #else /* CONFIG_GPIOLIB */
375 
376 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
377 {
378         /* GPIO can never have been requested */
379         WARN_ON(1);
380         return ERR_PTR(-ENODEV);
381 }
382 
383 #endif /* CONFIG_GPIOLIB */
384 
385 #endif
386 

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