~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/include/linux/hp_sdc.h

Version: ~ [ linux-5.2-rc1 ] ~ [ linux-5.1.2 ] ~ [ linux-5.0.16 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.43 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.119 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.176 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.179 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.139 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.67 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * HP i8042 System Device Controller -- header
  3  *
  4  * Copyright (c) 2001 Brian S. Julin
  5  * All rights reserved.
  6  *
  7  * Redistribution and use in source and binary forms, with or without
  8  * modification, are permitted provided that the following conditions
  9  * are met:
 10  * 1. Redistributions of source code must retain the above copyright
 11  *    notice, this list of conditions, and the following disclaimer,
 12  *    without modification.
 13  * 2. The name of the author may not be used to endorse or promote products
 14  *    derived from this software without specific prior written permission.
 15  *
 16  * Alternatively, this software may be distributed under the terms of the
 17  * GNU General Public License ("GPL").
 18  *
 19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
 23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 28  *
 29  * References:
 30  * 
 31  * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
 32  *
 33  * System Device Controller Microprocessor Firmware Theory of Operation
 34  *      for Part Number 1820-4784 Revision B.  Dwg No. A-1820-4784-2
 35  *
 36  */
 37 
 38 #ifndef _LINUX_HP_SDC_H
 39 #define _LINUX_HP_SDC_H
 40 
 41 #include <linux/interrupt.h>
 42 #include <linux/types.h>
 43 #include <linux/time.h>
 44 #include <linux/timer.h>
 45 #if defined(__hppa__)
 46 #include <asm/hardware.h>
 47 #endif
 48 
 49 
 50 /* No 4X status reads take longer than this (in usec).
 51  */
 52 #define HP_SDC_MAX_REG_DELAY 20000
 53 
 54 typedef void (hp_sdc_irqhook) (int irq, void *dev_id, 
 55                                uint8_t status, uint8_t data);
 56 
 57 int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback);
 58 int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback);
 59 int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback);
 60 int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback);
 61 int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback);
 62 int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback);
 63 
 64 typedef struct {
 65         int actidx;     /* Start of act.  Acts are atomic WRT I/O to SDC */
 66         int idx;        /* Index within the act */
 67         int endidx;     /* transaction is over and done if idx == endidx */
 68         uint8_t *seq;   /* commands/data for the transaction */
 69         union {
 70           hp_sdc_irqhook   *irqhook;    /* Callback, isr or tasklet context */
 71           struct semaphore *semaphore;  /* Semaphore to sleep on. */
 72         } act;
 73 } hp_sdc_transaction;
 74 int __hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
 75 int hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
 76 int hp_sdc_dequeue_transaction(hp_sdc_transaction *this);
 77 
 78 /* The HP_SDC_ACT* values are peculiar to this driver.
 79  * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
 80  * act to perform the dealloc.
 81  */
 82 #define HP_SDC_ACT_PRECMD       0x01            /* Send a command first */
 83 #define HP_SDC_ACT_DATAREG      0x02            /* Set data registers */
 84 #define HP_SDC_ACT_DATAOUT      0x04            /* Send data bytes */
 85 #define HP_SDC_ACT_POSTCMD      0x08            /* Send command after */
 86 #define HP_SDC_ACT_DATAIN       0x10            /* Collect data after */
 87 #define HP_SDC_ACT_DURING       0x1f
 88 #define HP_SDC_ACT_SEMAPHORE    0x20            /* Raise semaphore after */
 89 #define HP_SDC_ACT_CALLBACK     0x40            /* Pass data to IRQ handler */
 90 #define HP_SDC_ACT_DEALLOC      0x80            /* Destroy transaction after */
 91 #define HP_SDC_ACT_AFTER        0xe0
 92 #define HP_SDC_ACT_DEAD         0x60            /* Act timed out. */
 93 
 94 /* Rest of the flags are straightforward representation of the SDC interface */
 95 #define HP_SDC_STATUS_IBF       0x02    /* Input buffer full */
 96 
 97 #define HP_SDC_STATUS_IRQMASK   0xf0    /* Bits containing "level 1" irq */
 98 #define HP_SDC_STATUS_PERIODIC  0x10    /* Periodic 10ms timer */
 99 #define HP_SDC_STATUS_USERTIMER 0x20    /* "Special purpose" timer */
100 #define HP_SDC_STATUS_TIMER     0x30    /* Both PERIODIC and USERTIMER */
101 #define HP_SDC_STATUS_REG       0x40    /* Data from an i8042 register */
102 #define HP_SDC_STATUS_HILCMD    0x50    /* Command from HIL MLC */
103 #define HP_SDC_STATUS_HILDATA   0x60    /* Data from HIL MLC */
104 #define HP_SDC_STATUS_PUP       0x70    /* Successful power-up self test */
105 #define HP_SDC_STATUS_KCOOKED   0x80    /* Key from cooked kbd */
106 #define HP_SDC_STATUS_KRPG      0xc0    /* Key from Repeat Gen */
107 #define HP_SDC_STATUS_KMOD_SUP  0x10    /* Shift key is up */
108 #define HP_SDC_STATUS_KMOD_CUP  0x20    /* Control key is up */
109 
110 #define HP_SDC_NMISTATUS_FHS    0x40    /* NMI is a fast handshake irq */
111 
112 /* Internal i8042 registers (there are more, but they are not too useful). */
113 
114 #define HP_SDC_USE              0x02    /* Resource usage (including OB bit) */
115 #define HP_SDC_IM               0x04    /* Interrupt mask */
116 #define HP_SDC_CFG              0x11    /* Configuration register */
117 #define HP_SDC_KBLANGUAGE       0x12    /* Keyboard language */
118 
119 #define HP_SDC_D0               0x70    /* General purpose data buffer 0 */
120 #define HP_SDC_D1               0x71    /* General purpose data buffer 1 */
121 #define HP_SDC_D2               0x72    /* General purpose data buffer 2 */
122 #define HP_SDC_D3               0x73    /* General purpose data buffer 3 */
123 #define HP_SDC_VT1              0x74    /* Timer for voice 1 */
124 #define HP_SDC_VT2              0x75    /* Timer for voice 2 */
125 #define HP_SDC_VT3              0x76    /* Timer for voice 3 */
126 #define HP_SDC_VT4              0x77    /* Timer for voice 4 */
127 #define HP_SDC_KBN              0x78    /* Which HIL devs are Nimitz */
128 #define HP_SDC_KBC              0x79    /* Which HIL devs are cooked kbds */
129 #define HP_SDC_LPS              0x7a    /* i8042's view of HIL status */
130 #define HP_SDC_LPC              0x7b    /* i8042's view of HIL "control" */
131 #define HP_SDC_RSV              0x7c    /* Reserved "for testing" */
132 #define HP_SDC_LPR              0x7d    /* i8042 count of HIL reconfigs */
133 #define HP_SDC_XTD              0x7e    /* "Extended Configuration" register */
134 #define HP_SDC_STR              0x7f    /* i8042 self-test result */
135 
136 /* Bitfields for above registers */
137 #define HP_SDC_USE_LOOP         0x04    /* Command is currently on the loop. */
138 
139 #define HP_SDC_IM_MASK          0x1f    /* these bits not part of cmd/status */
140 #define HP_SDC_IM_FH            0x10    /* Mask the fast handshake irq */
141 #define HP_SDC_IM_PT            0x08    /* Mask the periodic timer irq */
142 #define HP_SDC_IM_TIMERS        0x04    /* Mask the MT/DT/CT irq */
143 #define HP_SDC_IM_RESET         0x02    /* Mask the reset key irq */
144 #define HP_SDC_IM_HIL           0x01    /* Mask the HIL MLC irq */
145 
146 #define HP_SDC_CFG_ROLLOVER     0x08    /* WTF is "N-key rollover"? */
147 #define HP_SDC_CFG_KBD          0x10    /* There is a keyboard */
148 #define HP_SDC_CFG_NEW          0x20    /* Supports/uses HIL MLC */
149 #define HP_SDC_CFG_KBD_OLD      0x03    /* keyboard code for non-HIL */
150 #define HP_SDC_CFG_KBD_NEW      0x07    /* keyboard code from HIL autoconfig */
151 #define HP_SDC_CFG_REV          0x40    /* Code revision bit */
152 #define HP_SDC_CFG_IDPROM       0x80    /* IDPROM present in kbd (not HIL) */
153 
154 #define HP_SDC_LPS_NDEV         0x07    /* # devices autoconfigured on HIL */
155 #define HP_SDC_LPS_ACSUCC       0x08    /* loop autoconfigured successfully */
156 #define HP_SDC_LPS_ACFAIL       0x80    /* last loop autoconfigure failed */
157 
158 #define HP_SDC_LPC_APE_IPF      0x01    /* HIL MLC APE/IPF (autopoll) set */
159 #define HP_SDC_LPC_ARCONERR     0x02    /* i8042 autoreconfigs loop on err */
160 #define HP_SDC_LPC_ARCQUIET     0x03    /* i8042 doesn't report autoreconfigs*/
161 #define HP_SDC_LPC_COOK         0x10    /* i8042 cooks devices in _KBN */
162 #define HP_SDC_LPC_RC           0x80    /* causes autoreconfig */
163 
164 #define HP_SDC_XTD_REV          0x07    /* contains revision code */
165 #define HP_SDC_XTD_REV_STRINGS(val, str) \
166 switch (val) {                                          \
167         case 0x1: str = "1820-3712"; break;             \
168         case 0x2: str = "1820-4379"; break;             \
169         case 0x3: str = "1820-4784"; break;             \
170         default: str = "unknown";                       \
171 };
172 #define HP_SDC_XTD_BEEPER       0x08    /* TI SN76494 beeper available */
173 #define HP_SDC_XTD_BBRTC        0x20    /* OKI MSM-58321 BBRTC present */
174 
175 #define HP_SDC_CMD_LOAD_RT      0x31    /* Load real time (from 8042) */
176 #define HP_SDC_CMD_LOAD_FHS     0x36    /* Load the fast handshake timer */
177 #define HP_SDC_CMD_LOAD_MT      0x38    /* Load the match timer */
178 #define HP_SDC_CMD_LOAD_DT      0x3B    /* Load the delay timer */
179 #define HP_SDC_CMD_LOAD_CT      0x3E    /* Load the cycle timer */
180 
181 #define HP_SDC_CMD_SET_IM       0x40    /* 010xxxxx == set irq mask */
182 
183 /* The documents provided do not explicitly state that all registers betweem 
184  * 0x01 and 0x1f inclusive can be read by sending their register index as a 
185  * command, but this is implied and appears to be the case.
186  */
187 #define HP_SDC_CMD_READ_RAM     0x00    /* Load from i8042 RAM (autoinc) */
188 #define HP_SDC_CMD_READ_USE     0x02    /* Undocumented! Load from usage reg */
189 #define HP_SDC_CMD_READ_IM      0x04    /* Load current interrupt mask */
190 #define HP_SDC_CMD_READ_KCC     0x11    /* Load primary kbd config code */
191 #define HP_SDC_CMD_READ_KLC     0x12    /* Load primary kbd language code */
192 #define HP_SDC_CMD_READ_T1      0x13    /* Load timer output buffer byte 1 */
193 #define HP_SDC_CMD_READ_T2      0x14    /* Load timer output buffer byte 1 */
194 #define HP_SDC_CMD_READ_T3      0x15    /* Load timer output buffer byte 1 */
195 #define HP_SDC_CMD_READ_T4      0x16    /* Load timer output buffer byte 1 */
196 #define HP_SDC_CMD_READ_T5      0x17    /* Load timer output buffer byte 1 */
197 #define HP_SDC_CMD_READ_D0      0xf0    /* Load from i8042 RAM location 0x70 */
198 #define HP_SDC_CMD_READ_D1      0xf1    /* Load from i8042 RAM location 0x71 */
199 #define HP_SDC_CMD_READ_D2      0xf2    /* Load from i8042 RAM location 0x72 */
200 #define HP_SDC_CMD_READ_D3      0xf3    /* Load from i8042 RAM location 0x73 */
201 #define HP_SDC_CMD_READ_VT1     0xf4    /* Load from i8042 RAM location 0x74 */
202 #define HP_SDC_CMD_READ_VT2     0xf5    /* Load from i8042 RAM location 0x75 */
203 #define HP_SDC_CMD_READ_VT3     0xf6    /* Load from i8042 RAM location 0x76 */
204 #define HP_SDC_CMD_READ_VT4     0xf7    /* Load from i8042 RAM location 0x77 */
205 #define HP_SDC_CMD_READ_KBN     0xf8    /* Load from i8042 RAM location 0x78 */
206 #define HP_SDC_CMD_READ_KBC     0xf9    /* Load from i8042 RAM location 0x79 */
207 #define HP_SDC_CMD_READ_LPS     0xfa    /* Load from i8042 RAM location 0x7a */
208 #define HP_SDC_CMD_READ_LPC     0xfb    /* Load from i8042 RAM location 0x7b */
209 #define HP_SDC_CMD_READ_RSV     0xfc    /* Load from i8042 RAM location 0x7c */
210 #define HP_SDC_CMD_READ_LPR     0xfd    /* Load from i8042 RAM location 0x7d */
211 #define HP_SDC_CMD_READ_XTD     0xfe    /* Load from i8042 RAM location 0x7e */
212 #define HP_SDC_CMD_READ_STR     0xff    /* Load from i8042 RAM location 0x7f */
213 
214 #define HP_SDC_CMD_SET_ARD      0xA0    /* Set emulated autorepeat delay */
215 #define HP_SDC_CMD_SET_ARR      0xA2    /* Set emulated autorepeat rate */
216 #define HP_SDC_CMD_SET_BELL     0xA3    /* Set voice 3 params for "beep" cmd */
217 #define HP_SDC_CMD_SET_RPGR     0xA6    /* Set "RPG" irq rate (doesn't work) */
218 #define HP_SDC_CMD_SET_RTMS     0xAD    /* Set the RTC time (milliseconds) */
219 #define HP_SDC_CMD_SET_RTD      0xAF    /* Set the RTC time (days) */
220 #define HP_SDC_CMD_SET_FHS      0xB2    /* Set fast handshake timer */
221 #define HP_SDC_CMD_SET_MT       0xB4    /* Set match timer */
222 #define HP_SDC_CMD_SET_DT       0xB7    /* Set delay timer */
223 #define HP_SDC_CMD_SET_CT       0xBA    /* Set cycle timer */
224 #define HP_SDC_CMD_SET_RAMP     0xC1    /* Reset READ_RAM autoinc counter */
225 #define HP_SDC_CMD_SET_D0       0xe0    /* Load to i8042 RAM location 0x70 */
226 #define HP_SDC_CMD_SET_D1       0xe1    /* Load to i8042 RAM location 0x71 */
227 #define HP_SDC_CMD_SET_D2       0xe2    /* Load to i8042 RAM location 0x72 */
228 #define HP_SDC_CMD_SET_D3       0xe3    /* Load to i8042 RAM location 0x73 */
229 #define HP_SDC_CMD_SET_VT1      0xe4    /* Load to i8042 RAM location 0x74 */
230 #define HP_SDC_CMD_SET_VT2      0xe5    /* Load to i8042 RAM location 0x75 */
231 #define HP_SDC_CMD_SET_VT3      0xe6    /* Load to i8042 RAM location 0x76 */
232 #define HP_SDC_CMD_SET_VT4      0xe7    /* Load to i8042 RAM location 0x77 */
233 #define HP_SDC_CMD_SET_KBN      0xe8    /* Load to i8042 RAM location 0x78 */
234 #define HP_SDC_CMD_SET_KBC      0xe9    /* Load to i8042 RAM location 0x79 */
235 #define HP_SDC_CMD_SET_LPS      0xea    /* Load to i8042 RAM location 0x7a */
236 #define HP_SDC_CMD_SET_LPC      0xeb    /* Load to i8042 RAM location 0x7b */
237 #define HP_SDC_CMD_SET_RSV      0xec    /* Load to i8042 RAM location 0x7c */
238 #define HP_SDC_CMD_SET_LPR      0xed    /* Load to i8042 RAM location 0x7d */
239 #define HP_SDC_CMD_SET_XTD      0xee    /* Load to i8042 RAM location 0x7e */
240 #define HP_SDC_CMD_SET_STR      0xef    /* Load to i8042 RAM location 0x7f */
241 
242 #define HP_SDC_CMD_DO_RTCW      0xc2    /* i8042 RAM 0x70 --> RTC */
243 #define HP_SDC_CMD_DO_RTCR      0xc3    /* RTC[0x70 0:3] --> irq/status/data */
244 #define HP_SDC_CMD_DO_BEEP      0xc4    /* i8042 RAM 0x70-74  --> beeper,VT3 */
245 #define HP_SDC_CMD_DO_HIL       0xc5    /* i8042 RAM 0x70-73 --> 
246                                            HIL MLC R0,R1 i8042 HIL watchdog */
247 
248 /* Values used to (de)mangle input/output to/from the HIL MLC */
249 #define HP_SDC_DATA             0x40    /* Data from an 8042 register */
250 #define HP_SDC_HIL_CMD          0x50    /* Data from HIL MLC R1/8042 */
251 #define HP_SDC_HIL_R1MASK       0x0f    /* Contents of HIL MLC R1 0:3 */
252 #define HP_SDC_HIL_AUTO         0x10    /* Set if POL results from i8042 */   
253 #define HP_SDC_HIL_ISERR        0x80    /* Has meaning as in next 4 values */
254 #define HP_SDC_HIL_RC_DONE      0x80    /* i8042 auto-configured loop */
255 #define HP_SDC_HIL_ERR          0x81    /* HIL MLC R2 had a bit set */
256 #define HP_SDC_HIL_TO           0x82    /* i8042 HIL watchdog expired */
257 #define HP_SDC_HIL_RC           0x84    /* i8042 is auto-configuring loop */
258 #define HP_SDC_HIL_DAT          0x60    /* Data from HIL MLC R0 */
259 
260 
261 typedef struct {
262         rwlock_t        ibf_lock;
263         rwlock_t        lock;           /* user/tasklet lock */
264         rwlock_t        rtq_lock;       /* isr/tasklet lock */
265         rwlock_t        hook_lock;      /* isr/user lock for handler add/del */
266 
267         unsigned int    irq, nmi;       /* Our IRQ lines */
268         unsigned long   base_io, status_io, data_io; /* Our IO ports */
269 
270         uint8_t         im;             /* Interrupt mask */
271         int             set_im;         /* Interrupt mask needs to be set. */
272 
273         int             ibf;            /* Last known status of IBF flag */
274         uint8_t         wi;             /* current i8042 write index */
275         uint8_t         r7[4];          /* current i8042[0x70 - 0x74] values */
276         uint8_t         r11, r7e;       /* Values from version/revision regs */
277 
278         hp_sdc_irqhook  *timer, *reg, *hil, *pup, *cooked;
279 
280 #define HP_SDC_QUEUE_LEN 16
281         hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */
282 
283         int             rcurr, rqty;    /* Current read transact in process */
284         ktime_t         rtime;          /* Time when current read started */
285         int             wcurr;          /* Current write transact in process */
286 
287         int             dev_err;        /* carries status from registration */
288 #if defined(__hppa__)
289         struct parisc_device    *dev;
290 #elif defined(__mc68000__)
291         void            *dev;
292 #else
293 #error No support for device registration on this arch yet.
294 #endif
295 
296         struct timer_list kicker;       /* Keeps below task alive */
297         struct tasklet_struct   task;
298 
299 } hp_i8042_sdc;
300 
301 #endif /* _LINUX_HP_SDC_H */
302 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp