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TOMOYO Linux Cross Reference
Linux/include/linux/irq.h

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  1 #ifndef _LINUX_IRQ_H
  2 #define _LINUX_IRQ_H
  3 
  4 /*
  5  * Please do not include this file in generic code.  There is currently
  6  * no requirement for any architecture to implement anything held
  7  * within this file.
  8  *
  9  * Thanks. --rmk
 10  */
 11 
 12 #include <linux/smp.h>
 13 #include <linux/linkage.h>
 14 #include <linux/cache.h>
 15 #include <linux/spinlock.h>
 16 #include <linux/cpumask.h>
 17 #include <linux/gfp.h>
 18 #include <linux/irqhandler.h>
 19 #include <linux/irqreturn.h>
 20 #include <linux/irqnr.h>
 21 #include <linux/errno.h>
 22 #include <linux/topology.h>
 23 #include <linux/wait.h>
 24 #include <linux/io.h>
 25 
 26 #include <asm/irq.h>
 27 #include <asm/ptrace.h>
 28 #include <asm/irq_regs.h>
 29 
 30 struct seq_file;
 31 struct module;
 32 struct msi_msg;
 33 
 34 /*
 35  * IRQ line status.
 36  *
 37  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
 38  *
 39  * IRQ_TYPE_NONE                - default, unspecified type
 40  * IRQ_TYPE_EDGE_RISING         - rising edge triggered
 41  * IRQ_TYPE_EDGE_FALLING        - falling edge triggered
 42  * IRQ_TYPE_EDGE_BOTH           - rising and falling edge triggered
 43  * IRQ_TYPE_LEVEL_HIGH          - high level triggered
 44  * IRQ_TYPE_LEVEL_LOW           - low level triggered
 45  * IRQ_TYPE_LEVEL_MASK          - Mask to filter out the level bits
 46  * IRQ_TYPE_SENSE_MASK          - Mask for all the above bits
 47  * IRQ_TYPE_DEFAULT             - For use by some PICs to ask irq_set_type
 48  *                                to setup the HW to a sane default (used
 49  *                                by irqdomain map() callbacks to synchronize
 50  *                                the HW state and SW flags for a newly
 51  *                                allocated descriptor).
 52  *
 53  * IRQ_TYPE_PROBE               - Special flag for probing in progress
 54  *
 55  * Bits which can be modified via irq_set/clear/modify_status_flags()
 56  * IRQ_LEVEL                    - Interrupt is level type. Will be also
 57  *                                updated in the code when the above trigger
 58  *                                bits are modified via irq_set_irq_type()
 59  * IRQ_PER_CPU                  - Mark an interrupt PER_CPU. Will protect
 60  *                                it from affinity setting
 61  * IRQ_NOPROBE                  - Interrupt cannot be probed by autoprobing
 62  * IRQ_NOREQUEST                - Interrupt cannot be requested via
 63  *                                request_irq()
 64  * IRQ_NOTHREAD                 - Interrupt cannot be threaded
 65  * IRQ_NOAUTOEN                 - Interrupt is not automatically enabled in
 66  *                                request/setup_irq()
 67  * IRQ_NO_BALANCING             - Interrupt cannot be balanced (affinity set)
 68  * IRQ_MOVE_PCNTXT              - Interrupt can be migrated from process context
 69  * IRQ_NESTED_TRHEAD            - Interrupt nests into another thread
 70  * IRQ_PER_CPU_DEVID            - Dev_id is a per-cpu variable
 71  * IRQ_IS_POLLED                - Always polled by another interrupt. Exclude
 72  *                                it from the spurious interrupt detection
 73  *                                mechanism and from core side polling.
 74  */
 75 enum {
 76         IRQ_TYPE_NONE           = 0x00000000,
 77         IRQ_TYPE_EDGE_RISING    = 0x00000001,
 78         IRQ_TYPE_EDGE_FALLING   = 0x00000002,
 79         IRQ_TYPE_EDGE_BOTH      = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
 80         IRQ_TYPE_LEVEL_HIGH     = 0x00000004,
 81         IRQ_TYPE_LEVEL_LOW      = 0x00000008,
 82         IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
 83         IRQ_TYPE_SENSE_MASK     = 0x0000000f,
 84         IRQ_TYPE_DEFAULT        = IRQ_TYPE_SENSE_MASK,
 85 
 86         IRQ_TYPE_PROBE          = 0x00000010,
 87 
 88         IRQ_LEVEL               = (1 <<  8),
 89         IRQ_PER_CPU             = (1 <<  9),
 90         IRQ_NOPROBE             = (1 << 10),
 91         IRQ_NOREQUEST           = (1 << 11),
 92         IRQ_NOAUTOEN            = (1 << 12),
 93         IRQ_NO_BALANCING        = (1 << 13),
 94         IRQ_MOVE_PCNTXT         = (1 << 14),
 95         IRQ_NESTED_THREAD       = (1 << 15),
 96         IRQ_NOTHREAD            = (1 << 16),
 97         IRQ_PER_CPU_DEVID       = (1 << 17),
 98         IRQ_IS_POLLED           = (1 << 18),
 99 };
100 
101 #define IRQF_MODIFY_MASK        \
102         (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
103          IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
104          IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
105          IRQ_IS_POLLED)
106 
107 #define IRQ_NO_BALANCING_MASK   (IRQ_PER_CPU | IRQ_NO_BALANCING)
108 
109 /*
110  * Return value for chip->irq_set_affinity()
111  *
112  * IRQ_SET_MASK_OK      - OK, core updates irq_data.affinity
113  * IRQ_SET_MASK_NOCPY   - OK, chip did update irq_data.affinity
114  * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
115  *                        support stacked irqchips, which indicates skipping
116  *                        all descendent irqchips.
117  */
118 enum {
119         IRQ_SET_MASK_OK = 0,
120         IRQ_SET_MASK_OK_NOCOPY,
121         IRQ_SET_MASK_OK_DONE,
122 };
123 
124 struct msi_desc;
125 struct irq_domain;
126 
127 /**
128  * struct irq_data - per irq and irq chip data passed down to chip functions
129  * @mask:               precomputed bitmask for accessing the chip registers
130  * @irq:                interrupt number
131  * @hwirq:              hardware interrupt number, local to the interrupt domain
132  * @node:               node index useful for balancing
133  * @state_use_accessors: status information for irq chip functions.
134  *                      Use accessor functions to deal with it
135  * @chip:               low level interrupt hardware access
136  * @domain:             Interrupt translation domain; responsible for mapping
137  *                      between hwirq number and linux irq number.
138  * @parent_data:        pointer to parent struct irq_data to support hierarchy
139  *                      irq_domain
140  * @handler_data:       per-IRQ data for the irq_chip methods
141  * @chip_data:          platform-specific per-chip private data for the chip
142  *                      methods, to allow shared chip implementations
143  * @msi_desc:           MSI descriptor
144  * @affinity:           IRQ affinity on SMP
145  *
146  * The fields here need to overlay the ones in irq_desc until we
147  * cleaned up the direct references and switched everything over to
148  * irq_data.
149  */
150 struct irq_data {
151         u32                     mask;
152         unsigned int            irq;
153         unsigned long           hwirq;
154         unsigned int            node;
155         unsigned int            state_use_accessors;
156         struct irq_chip         *chip;
157         struct irq_domain       *domain;
158 #ifdef  CONFIG_IRQ_DOMAIN_HIERARCHY
159         struct irq_data         *parent_data;
160 #endif
161         void                    *handler_data;
162         void                    *chip_data;
163         struct msi_desc         *msi_desc;
164         cpumask_var_t           affinity;
165 };
166 
167 /*
168  * Bit masks for irq_data.state
169  *
170  * IRQD_TRIGGER_MASK            - Mask for the trigger type bits
171  * IRQD_SETAFFINITY_PENDING     - Affinity setting is pending
172  * IRQD_NO_BALANCING            - Balancing disabled for this IRQ
173  * IRQD_PER_CPU                 - Interrupt is per cpu
174  * IRQD_AFFINITY_SET            - Interrupt affinity was set
175  * IRQD_LEVEL                   - Interrupt is level triggered
176  * IRQD_WAKEUP_STATE            - Interrupt is configured for wakeup
177  *                                from suspend
178  * IRDQ_MOVE_PCNTXT             - Interrupt can be moved in process
179  *                                context
180  * IRQD_IRQ_DISABLED            - Disabled state of the interrupt
181  * IRQD_IRQ_MASKED              - Masked state of the interrupt
182  * IRQD_IRQ_INPROGRESS          - In progress state of the interrupt
183  * IRQD_WAKEUP_ARMED            - Wakeup mode armed
184  */
185 enum {
186         IRQD_TRIGGER_MASK               = 0xf,
187         IRQD_SETAFFINITY_PENDING        = (1 <<  8),
188         IRQD_NO_BALANCING               = (1 << 10),
189         IRQD_PER_CPU                    = (1 << 11),
190         IRQD_AFFINITY_SET               = (1 << 12),
191         IRQD_LEVEL                      = (1 << 13),
192         IRQD_WAKEUP_STATE               = (1 << 14),
193         IRQD_MOVE_PCNTXT                = (1 << 15),
194         IRQD_IRQ_DISABLED               = (1 << 16),
195         IRQD_IRQ_MASKED                 = (1 << 17),
196         IRQD_IRQ_INPROGRESS             = (1 << 18),
197         IRQD_WAKEUP_ARMED               = (1 << 19),
198 };
199 
200 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
201 {
202         return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
203 }
204 
205 static inline bool irqd_is_per_cpu(struct irq_data *d)
206 {
207         return d->state_use_accessors & IRQD_PER_CPU;
208 }
209 
210 static inline bool irqd_can_balance(struct irq_data *d)
211 {
212         return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
213 }
214 
215 static inline bool irqd_affinity_was_set(struct irq_data *d)
216 {
217         return d->state_use_accessors & IRQD_AFFINITY_SET;
218 }
219 
220 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
221 {
222         d->state_use_accessors |= IRQD_AFFINITY_SET;
223 }
224 
225 static inline u32 irqd_get_trigger_type(struct irq_data *d)
226 {
227         return d->state_use_accessors & IRQD_TRIGGER_MASK;
228 }
229 
230 /*
231  * Must only be called inside irq_chip.irq_set_type() functions.
232  */
233 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
234 {
235         d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
236         d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
237 }
238 
239 static inline bool irqd_is_level_type(struct irq_data *d)
240 {
241         return d->state_use_accessors & IRQD_LEVEL;
242 }
243 
244 static inline bool irqd_is_wakeup_set(struct irq_data *d)
245 {
246         return d->state_use_accessors & IRQD_WAKEUP_STATE;
247 }
248 
249 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
250 {
251         return d->state_use_accessors & IRQD_MOVE_PCNTXT;
252 }
253 
254 static inline bool irqd_irq_disabled(struct irq_data *d)
255 {
256         return d->state_use_accessors & IRQD_IRQ_DISABLED;
257 }
258 
259 static inline bool irqd_irq_masked(struct irq_data *d)
260 {
261         return d->state_use_accessors & IRQD_IRQ_MASKED;
262 }
263 
264 static inline bool irqd_irq_inprogress(struct irq_data *d)
265 {
266         return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
267 }
268 
269 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
270 {
271         return d->state_use_accessors & IRQD_WAKEUP_ARMED;
272 }
273 
274 
275 /*
276  * Functions for chained handlers which can be enabled/disabled by the
277  * standard disable_irq/enable_irq calls. Must be called with
278  * irq_desc->lock held.
279  */
280 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
281 {
282         d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
283 }
284 
285 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
286 {
287         d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
288 }
289 
290 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
291 {
292         return d->hwirq;
293 }
294 
295 /**
296  * struct irq_chip - hardware interrupt chip descriptor
297  *
298  * @name:               name for /proc/interrupts
299  * @irq_startup:        start up the interrupt (defaults to ->enable if NULL)
300  * @irq_shutdown:       shut down the interrupt (defaults to ->disable if NULL)
301  * @irq_enable:         enable the interrupt (defaults to chip->unmask if NULL)
302  * @irq_disable:        disable the interrupt
303  * @irq_ack:            start of a new interrupt
304  * @irq_mask:           mask an interrupt source
305  * @irq_mask_ack:       ack and mask an interrupt source
306  * @irq_unmask:         unmask an interrupt source
307  * @irq_eoi:            end of interrupt
308  * @irq_set_affinity:   set the CPU affinity on SMP machines
309  * @irq_retrigger:      resend an IRQ to the CPU
310  * @irq_set_type:       set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
311  * @irq_set_wake:       enable/disable power-management wake-on of an IRQ
312  * @irq_bus_lock:       function to lock access to slow bus (i2c) chips
313  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
314  * @irq_cpu_online:     configure an interrupt source for a secondary CPU
315  * @irq_cpu_offline:    un-configure an interrupt source for a secondary CPU
316  * @irq_suspend:        function called from core code on suspend once per chip
317  * @irq_resume:         function called from core code on resume once per chip
318  * @irq_pm_shutdown:    function called from core code on shutdown once per chip
319  * @irq_calc_mask:      Optional function to set irq_data.mask for special cases
320  * @irq_print_chip:     optional to print special chip info in show_interrupts
321  * @irq_request_resources:      optional to request resources before calling
322  *                              any other callback related to this irq
323  * @irq_release_resources:      optional to release resources acquired with
324  *                              irq_request_resources
325  * @irq_compose_msi_msg:        optional to compose message content for MSI
326  * @irq_write_msi_msg:  optional to write message content for MSI
327  * @flags:              chip specific flags
328  */
329 struct irq_chip {
330         const char      *name;
331         unsigned int    (*irq_startup)(struct irq_data *data);
332         void            (*irq_shutdown)(struct irq_data *data);
333         void            (*irq_enable)(struct irq_data *data);
334         void            (*irq_disable)(struct irq_data *data);
335 
336         void            (*irq_ack)(struct irq_data *data);
337         void            (*irq_mask)(struct irq_data *data);
338         void            (*irq_mask_ack)(struct irq_data *data);
339         void            (*irq_unmask)(struct irq_data *data);
340         void            (*irq_eoi)(struct irq_data *data);
341 
342         int             (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
343         int             (*irq_retrigger)(struct irq_data *data);
344         int             (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
345         int             (*irq_set_wake)(struct irq_data *data, unsigned int on);
346 
347         void            (*irq_bus_lock)(struct irq_data *data);
348         void            (*irq_bus_sync_unlock)(struct irq_data *data);
349 
350         void            (*irq_cpu_online)(struct irq_data *data);
351         void            (*irq_cpu_offline)(struct irq_data *data);
352 
353         void            (*irq_suspend)(struct irq_data *data);
354         void            (*irq_resume)(struct irq_data *data);
355         void            (*irq_pm_shutdown)(struct irq_data *data);
356 
357         void            (*irq_calc_mask)(struct irq_data *data);
358 
359         void            (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
360         int             (*irq_request_resources)(struct irq_data *data);
361         void            (*irq_release_resources)(struct irq_data *data);
362 
363         void            (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
364         void            (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
365 
366         unsigned long   flags;
367 };
368 
369 /*
370  * irq_chip specific flags
371  *
372  * IRQCHIP_SET_TYPE_MASKED:     Mask before calling chip.irq_set_type()
373  * IRQCHIP_EOI_IF_HANDLED:      Only issue irq_eoi() when irq was handled
374  * IRQCHIP_MASK_ON_SUSPEND:     Mask non wake irqs in the suspend path
375  * IRQCHIP_ONOFFLINE_ENABLED:   Only call irq_on/off_line callbacks
376  *                              when irq enabled
377  * IRQCHIP_SKIP_SET_WAKE:       Skip chip.irq_set_wake(), for this irq chip
378  * IRQCHIP_ONESHOT_SAFE:        One shot does not require mask/unmask
379  * IRQCHIP_EOI_THREADED:        Chip requires eoi() on unmask in threaded mode
380  */
381 enum {
382         IRQCHIP_SET_TYPE_MASKED         = (1 <<  0),
383         IRQCHIP_EOI_IF_HANDLED          = (1 <<  1),
384         IRQCHIP_MASK_ON_SUSPEND         = (1 <<  2),
385         IRQCHIP_ONOFFLINE_ENABLED       = (1 <<  3),
386         IRQCHIP_SKIP_SET_WAKE           = (1 <<  4),
387         IRQCHIP_ONESHOT_SAFE            = (1 <<  5),
388         IRQCHIP_EOI_THREADED            = (1 <<  6),
389 };
390 
391 /* This include will go away once we isolated irq_desc usage to core code */
392 #include <linux/irqdesc.h>
393 
394 /*
395  * Pick up the arch-dependent methods:
396  */
397 #include <asm/hw_irq.h>
398 
399 #ifndef NR_IRQS_LEGACY
400 # define NR_IRQS_LEGACY 0
401 #endif
402 
403 #ifndef ARCH_IRQ_INIT_FLAGS
404 # define ARCH_IRQ_INIT_FLAGS    0
405 #endif
406 
407 #define IRQ_DEFAULT_INIT_FLAGS  ARCH_IRQ_INIT_FLAGS
408 
409 struct irqaction;
410 extern int setup_irq(unsigned int irq, struct irqaction *new);
411 extern void remove_irq(unsigned int irq, struct irqaction *act);
412 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
413 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
414 
415 extern void irq_cpu_online(void);
416 extern void irq_cpu_offline(void);
417 extern int irq_set_affinity_locked(struct irq_data *data,
418                                    const struct cpumask *cpumask, bool force);
419 
420 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
421 void irq_move_irq(struct irq_data *data);
422 void irq_move_masked_irq(struct irq_data *data);
423 #else
424 static inline void irq_move_irq(struct irq_data *data) { }
425 static inline void irq_move_masked_irq(struct irq_data *data) { }
426 #endif
427 
428 extern int no_irq_affinity;
429 
430 #ifdef CONFIG_HARDIRQS_SW_RESEND
431 int irq_set_parent(int irq, int parent_irq);
432 #else
433 static inline int irq_set_parent(int irq, int parent_irq)
434 {
435         return 0;
436 }
437 #endif
438 
439 /*
440  * Built-in IRQ handlers for various IRQ types,
441  * callable via desc->handle_irq()
442  */
443 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
444 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
445 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
446 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
447 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
448 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
449 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
450 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
451 extern void handle_nested_irq(unsigned int irq);
452 
453 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
454 #ifdef  CONFIG_IRQ_DOMAIN_HIERARCHY
455 extern void irq_chip_ack_parent(struct irq_data *data);
456 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
457 extern void irq_chip_mask_parent(struct irq_data *data);
458 extern void irq_chip_unmask_parent(struct irq_data *data);
459 extern void irq_chip_eoi_parent(struct irq_data *data);
460 extern int irq_chip_set_affinity_parent(struct irq_data *data,
461                                         const struct cpumask *dest,
462                                         bool force);
463 #endif
464 
465 /* Handling of unhandled and spurious interrupts: */
466 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
467                            irqreturn_t action_ret);
468 
469 
470 /* Enable/disable irq debugging output: */
471 extern int noirqdebug_setup(char *str);
472 
473 /* Checks whether the interrupt can be requested by request_irq(): */
474 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
475 
476 /* Dummy irq-chip implementations: */
477 extern struct irq_chip no_irq_chip;
478 extern struct irq_chip dummy_irq_chip;
479 
480 extern void
481 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
482                               irq_flow_handler_t handle, const char *name);
483 
484 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
485                                             irq_flow_handler_t handle)
486 {
487         irq_set_chip_and_handler_name(irq, chip, handle, NULL);
488 }
489 
490 extern int irq_set_percpu_devid(unsigned int irq);
491 
492 extern void
493 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
494                   const char *name);
495 
496 static inline void
497 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
498 {
499         __irq_set_handler(irq, handle, 0, NULL);
500 }
501 
502 /*
503  * Set a highlevel chained flow handler for a given IRQ.
504  * (a chained handler is automatically enabled and set to
505  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
506  */
507 static inline void
508 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
509 {
510         __irq_set_handler(irq, handle, 1, NULL);
511 }
512 
513 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
514 
515 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
516 {
517         irq_modify_status(irq, 0, set);
518 }
519 
520 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
521 {
522         irq_modify_status(irq, clr, 0);
523 }
524 
525 static inline void irq_set_noprobe(unsigned int irq)
526 {
527         irq_modify_status(irq, 0, IRQ_NOPROBE);
528 }
529 
530 static inline void irq_set_probe(unsigned int irq)
531 {
532         irq_modify_status(irq, IRQ_NOPROBE, 0);
533 }
534 
535 static inline void irq_set_nothread(unsigned int irq)
536 {
537         irq_modify_status(irq, 0, IRQ_NOTHREAD);
538 }
539 
540 static inline void irq_set_thread(unsigned int irq)
541 {
542         irq_modify_status(irq, IRQ_NOTHREAD, 0);
543 }
544 
545 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
546 {
547         if (nest)
548                 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
549         else
550                 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
551 }
552 
553 static inline void irq_set_percpu_devid_flags(unsigned int irq)
554 {
555         irq_set_status_flags(irq,
556                              IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
557                              IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
558 }
559 
560 /* Set/get chip/data for an IRQ: */
561 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
562 extern int irq_set_handler_data(unsigned int irq, void *data);
563 extern int irq_set_chip_data(unsigned int irq, void *data);
564 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
565 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
566 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
567                                 struct msi_desc *entry);
568 extern struct irq_data *irq_get_irq_data(unsigned int irq);
569 
570 static inline struct irq_chip *irq_get_chip(unsigned int irq)
571 {
572         struct irq_data *d = irq_get_irq_data(irq);
573         return d ? d->chip : NULL;
574 }
575 
576 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
577 {
578         return d->chip;
579 }
580 
581 static inline void *irq_get_chip_data(unsigned int irq)
582 {
583         struct irq_data *d = irq_get_irq_data(irq);
584         return d ? d->chip_data : NULL;
585 }
586 
587 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
588 {
589         return d->chip_data;
590 }
591 
592 static inline void *irq_get_handler_data(unsigned int irq)
593 {
594         struct irq_data *d = irq_get_irq_data(irq);
595         return d ? d->handler_data : NULL;
596 }
597 
598 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
599 {
600         return d->handler_data;
601 }
602 
603 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
604 {
605         struct irq_data *d = irq_get_irq_data(irq);
606         return d ? d->msi_desc : NULL;
607 }
608 
609 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
610 {
611         return d->msi_desc;
612 }
613 
614 static inline u32 irq_get_trigger_type(unsigned int irq)
615 {
616         struct irq_data *d = irq_get_irq_data(irq);
617         return d ? irqd_get_trigger_type(d) : 0;
618 }
619 
620 unsigned int arch_dynirq_lower_bound(unsigned int from);
621 
622 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
623                 struct module *owner);
624 
625 /* use macros to avoid needing export.h for THIS_MODULE */
626 #define irq_alloc_descs(irq, from, cnt, node)   \
627         __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
628 
629 #define irq_alloc_desc(node)                    \
630         irq_alloc_descs(-1, 0, 1, node)
631 
632 #define irq_alloc_desc_at(at, node)             \
633         irq_alloc_descs(at, at, 1, node)
634 
635 #define irq_alloc_desc_from(from, node)         \
636         irq_alloc_descs(-1, from, 1, node)
637 
638 #define irq_alloc_descs_from(from, cnt, node)   \
639         irq_alloc_descs(-1, from, cnt, node)
640 
641 void irq_free_descs(unsigned int irq, unsigned int cnt);
642 static inline void irq_free_desc(unsigned int irq)
643 {
644         irq_free_descs(irq, 1);
645 }
646 
647 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
648 unsigned int irq_alloc_hwirqs(int cnt, int node);
649 static inline unsigned int irq_alloc_hwirq(int node)
650 {
651         return irq_alloc_hwirqs(1, node);
652 }
653 void irq_free_hwirqs(unsigned int from, int cnt);
654 static inline void irq_free_hwirq(unsigned int irq)
655 {
656         return irq_free_hwirqs(irq, 1);
657 }
658 int arch_setup_hwirq(unsigned int irq, int node);
659 void arch_teardown_hwirq(unsigned int irq);
660 #endif
661 
662 #ifdef CONFIG_GENERIC_IRQ_LEGACY
663 void irq_init_desc(unsigned int irq);
664 #endif
665 
666 /**
667  * struct irq_chip_regs - register offsets for struct irq_gci
668  * @enable:     Enable register offset to reg_base
669  * @disable:    Disable register offset to reg_base
670  * @mask:       Mask register offset to reg_base
671  * @ack:        Ack register offset to reg_base
672  * @eoi:        Eoi register offset to reg_base
673  * @type:       Type configuration register offset to reg_base
674  * @polarity:   Polarity configuration register offset to reg_base
675  */
676 struct irq_chip_regs {
677         unsigned long           enable;
678         unsigned long           disable;
679         unsigned long           mask;
680         unsigned long           ack;
681         unsigned long           eoi;
682         unsigned long           type;
683         unsigned long           polarity;
684 };
685 
686 /**
687  * struct irq_chip_type - Generic interrupt chip instance for a flow type
688  * @chip:               The real interrupt chip which provides the callbacks
689  * @regs:               Register offsets for this chip
690  * @handler:            Flow handler associated with this chip
691  * @type:               Chip can handle these flow types
692  * @mask_cache_priv:    Cached mask register private to the chip type
693  * @mask_cache:         Pointer to cached mask register
694  *
695  * A irq_generic_chip can have several instances of irq_chip_type when
696  * it requires different functions and register offsets for different
697  * flow types.
698  */
699 struct irq_chip_type {
700         struct irq_chip         chip;
701         struct irq_chip_regs    regs;
702         irq_flow_handler_t      handler;
703         u32                     type;
704         u32                     mask_cache_priv;
705         u32                     *mask_cache;
706 };
707 
708 /**
709  * struct irq_chip_generic - Generic irq chip data structure
710  * @lock:               Lock to protect register and cache data access
711  * @reg_base:           Register base address (virtual)
712  * @reg_readl:          Alternate I/O accessor (defaults to readl if NULL)
713  * @reg_writel:         Alternate I/O accessor (defaults to writel if NULL)
714  * @irq_base:           Interrupt base nr for this chip
715  * @irq_cnt:            Number of interrupts handled by this chip
716  * @mask_cache:         Cached mask register shared between all chip types
717  * @type_cache:         Cached type register
718  * @polarity_cache:     Cached polarity register
719  * @wake_enabled:       Interrupt can wakeup from suspend
720  * @wake_active:        Interrupt is marked as an wakeup from suspend source
721  * @num_ct:             Number of available irq_chip_type instances (usually 1)
722  * @private:            Private data for non generic chip callbacks
723  * @installed:          bitfield to denote installed interrupts
724  * @unused:             bitfield to denote unused interrupts
725  * @domain:             irq domain pointer
726  * @list:               List head for keeping track of instances
727  * @chip_types:         Array of interrupt irq_chip_types
728  *
729  * Note, that irq_chip_generic can have multiple irq_chip_type
730  * implementations which can be associated to a particular irq line of
731  * an irq_chip_generic instance. That allows to share and protect
732  * state in an irq_chip_generic instance when we need to implement
733  * different flow mechanisms (level/edge) for it.
734  */
735 struct irq_chip_generic {
736         raw_spinlock_t          lock;
737         void __iomem            *reg_base;
738         u32                     (*reg_readl)(void __iomem *addr);
739         void                    (*reg_writel)(u32 val, void __iomem *addr);
740         unsigned int            irq_base;
741         unsigned int            irq_cnt;
742         u32                     mask_cache;
743         u32                     type_cache;
744         u32                     polarity_cache;
745         u32                     wake_enabled;
746         u32                     wake_active;
747         unsigned int            num_ct;
748         void                    *private;
749         unsigned long           installed;
750         unsigned long           unused;
751         struct irq_domain       *domain;
752         struct list_head        list;
753         struct irq_chip_type    chip_types[0];
754 };
755 
756 /**
757  * enum irq_gc_flags - Initialization flags for generic irq chips
758  * @IRQ_GC_INIT_MASK_CACHE:     Initialize the mask_cache by reading mask reg
759  * @IRQ_GC_INIT_NESTED_LOCK:    Set the lock class of the irqs to nested for
760  *                              irq chips which need to call irq_set_wake() on
761  *                              the parent irq. Usually GPIO implementations
762  * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
763  * @IRQ_GC_NO_MASK:             Do not calculate irq_data->mask
764  * @IRQ_GC_BE_IO:               Use big-endian register accesses (default: LE)
765  */
766 enum irq_gc_flags {
767         IRQ_GC_INIT_MASK_CACHE          = 1 << 0,
768         IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
769         IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
770         IRQ_GC_NO_MASK                  = 1 << 3,
771         IRQ_GC_BE_IO                    = 1 << 4,
772 };
773 
774 /*
775  * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
776  * @irqs_per_chip:      Number of interrupts per chip
777  * @num_chips:          Number of chips
778  * @irq_flags_to_set:   IRQ* flags to set on irq setup
779  * @irq_flags_to_clear: IRQ* flags to clear on irq setup
780  * @gc_flags:           Generic chip specific setup flags
781  * @gc:                 Array of pointers to generic interrupt chips
782  */
783 struct irq_domain_chip_generic {
784         unsigned int            irqs_per_chip;
785         unsigned int            num_chips;
786         unsigned int            irq_flags_to_clear;
787         unsigned int            irq_flags_to_set;
788         enum irq_gc_flags       gc_flags;
789         struct irq_chip_generic *gc[0];
790 };
791 
792 /* Generic chip callback functions */
793 void irq_gc_noop(struct irq_data *d);
794 void irq_gc_mask_disable_reg(struct irq_data *d);
795 void irq_gc_mask_set_bit(struct irq_data *d);
796 void irq_gc_mask_clr_bit(struct irq_data *d);
797 void irq_gc_unmask_enable_reg(struct irq_data *d);
798 void irq_gc_ack_set_bit(struct irq_data *d);
799 void irq_gc_ack_clr_bit(struct irq_data *d);
800 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
801 void irq_gc_eoi(struct irq_data *d);
802 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
803 
804 /* Setup functions for irq_chip_generic */
805 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
806                          irq_hw_number_t hw_irq);
807 struct irq_chip_generic *
808 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
809                        void __iomem *reg_base, irq_flow_handler_t handler);
810 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
811                             enum irq_gc_flags flags, unsigned int clr,
812                             unsigned int set);
813 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
814 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
815                              unsigned int clr, unsigned int set);
816 
817 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
818 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
819                                    int num_ct, const char *name,
820                                    irq_flow_handler_t handler,
821                                    unsigned int clr, unsigned int set,
822                                    enum irq_gc_flags flags);
823 
824 
825 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
826 {
827         return container_of(d->chip, struct irq_chip_type, chip);
828 }
829 
830 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
831 
832 #ifdef CONFIG_SMP
833 static inline void irq_gc_lock(struct irq_chip_generic *gc)
834 {
835         raw_spin_lock(&gc->lock);
836 }
837 
838 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
839 {
840         raw_spin_unlock(&gc->lock);
841 }
842 #else
843 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
844 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
845 #endif
846 
847 static inline void irq_reg_writel(struct irq_chip_generic *gc,
848                                   u32 val, int reg_offset)
849 {
850         if (gc->reg_writel)
851                 gc->reg_writel(val, gc->reg_base + reg_offset);
852         else
853                 writel(val, gc->reg_base + reg_offset);
854 }
855 
856 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
857                                 int reg_offset)
858 {
859         if (gc->reg_readl)
860                 return gc->reg_readl(gc->reg_base + reg_offset);
861         else
862                 return readl(gc->reg_base + reg_offset);
863 }
864 
865 #endif /* _LINUX_IRQ_H */
866 

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