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Linux/include/linux/mfd/mxs-lradc.h

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  1 /*
  2  * Freescale MXS Low Resolution Analog-to-Digital Converter driver
  3  *
  4  * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5  * Copyright (c) 2016 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
  6  *
  7  * Author: Marek Vasut <marex@denx.de>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 17  * GNU General Public License for more details.
 18  */
 19 
 20 #ifndef __MFD_MXS_LRADC_H
 21 #define __MFD_MXS_LRADC_H
 22 
 23 #include <linux/bitops.h>
 24 #include <linux/io.h>
 25 #include <linux/stmp_device.h>
 26 
 27 #define LRADC_MAX_DELAY_CHANS   4
 28 #define LRADC_MAX_MAPPED_CHANS  8
 29 #define LRADC_MAX_TOTAL_CHANS   16
 30 
 31 #define LRADC_DELAY_TIMER_HZ    2000
 32 
 33 #define LRADC_CTRL0                             0x00
 34 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE   BIT(23)
 35 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE     BIT(22)
 36 # define LRADC_CTRL0_MX28_YNNSW /* YM */        BIT(21)
 37 # define LRADC_CTRL0_MX28_YPNSW /* YP */        BIT(20)
 38 # define LRADC_CTRL0_MX28_YPPSW /* YP */        BIT(19)
 39 # define LRADC_CTRL0_MX28_XNNSW /* XM */        BIT(18)
 40 # define LRADC_CTRL0_MX28_XNPSW /* XM */        BIT(17)
 41 # define LRADC_CTRL0_MX28_XPPSW /* XP */        BIT(16)
 42 
 43 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE   BIT(20)
 44 # define LRADC_CTRL0_MX23_YM                    BIT(19)
 45 # define LRADC_CTRL0_MX23_XM                    BIT(18)
 46 # define LRADC_CTRL0_MX23_YP                    BIT(17)
 47 # define LRADC_CTRL0_MX23_XP                    BIT(16)
 48 
 49 # define LRADC_CTRL0_MX28_PLATE_MASK \
 50                 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
 51                 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
 52                 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
 53                 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
 54 
 55 # define LRADC_CTRL0_MX23_PLATE_MASK \
 56                 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
 57                 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
 58                 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
 59 
 60 #define LRADC_CTRL1                             0x10
 61 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN         BIT(24)
 62 #define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
 63 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK      (0x1fff << 16)
 64 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK      (0x01ff << 16)
 65 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET         16
 66 #define LRADC_CTRL1_TOUCH_DETECT_IRQ            BIT(8)
 67 #define LRADC_CTRL1_LRADC_IRQ(n)                BIT(n)
 68 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK         0x1fff
 69 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK         0x01ff
 70 #define LRADC_CTRL1_LRADC_IRQ_OFFSET            0
 71 
 72 #define LRADC_CTRL2                             0x20
 73 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET        24
 74 #define LRADC_CTRL2_TEMPSENSE_PWD               BIT(15)
 75 
 76 #define LRADC_STATUS                            0x40
 77 #define LRADC_STATUS_TOUCH_DETECT_RAW           BIT(0)
 78 
 79 #define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
 80 #define LRADC_CH_ACCUMULATE                     BIT(29)
 81 #define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
 82 #define LRADC_CH_NUM_SAMPLES_OFFSET             24
 83 #define LRADC_CH_NUM_SAMPLES(x) \
 84                                 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
 85 #define LRADC_CH_VALUE_MASK                     0x3ffff
 86 #define LRADC_CH_VALUE_OFFSET                   0
 87 
 88 #define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
 89 #define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xffUL << 24)
 90 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
 91 #define LRADC_DELAY_TRIGGER(x) \
 92                                 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
 93                                 LRADC_DELAY_TRIGGER_LRADCS_MASK)
 94 #define LRADC_DELAY_KICK                        BIT(20)
 95 #define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
 96 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
 97 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
 98                                 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
 99                                 LRADC_DELAY_TRIGGER_DELAYS_MASK)
100 #define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
101 #define LRADC_DELAY_LOOP_COUNT_OFFSET           11
102 #define LRADC_DELAY_LOOP(x) \
103                                 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
104                                 LRADC_DELAY_LOOP_COUNT_MASK)
105 #define LRADC_DELAY_DELAY_MASK                  0x7ff
106 #define LRADC_DELAY_DELAY_OFFSET                0
107 #define LRADC_DELAY_DELAY(x) \
108                                 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
109                                 LRADC_DELAY_DELAY_MASK)
110 
111 #define LRADC_CTRL4                             0x140
112 #define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
113 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
114 #define LRADC_CTRL4_LRADCSELECT(n, x) \
115                                 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
116                                 LRADC_CTRL4_LRADCSELECT_MASK(n))
117 
118 #define LRADC_RESOLUTION                        12
119 #define LRADC_SINGLE_SAMPLE_MASK                ((1 << LRADC_RESOLUTION) - 1)
120 
121 #define BUFFER_VCHANS_LIMITED           0x3f
122 #define BUFFER_VCHANS_ALL               0xff
123 
124         /*
125          * Certain LRADC channels are shared between touchscreen
126          * and/or touch-buttons and generic LRADC block. Therefore when using
127          * either of these, these channels are not available for the regular
128          * sampling. The shared channels are as follows:
129          *
130          * CH0 -- Touch button #0
131          * CH1 -- Touch button #1
132          * CH2 -- Touch screen XPUL
133          * CH3 -- Touch screen YPLL
134          * CH4 -- Touch screen XNUL
135          * CH5 -- Touch screen YNLR
136          * CH6 -- Touch screen WIPER (5-wire only)
137          *
138          * The bit fields below represents which parts of the LRADC block are
139          * switched into special mode of operation. These channels can not
140          * be sampled as regular LRADC channels. The driver will refuse any
141          * attempt to sample these channels.
142          */
143 #define CHAN_MASK_TOUCHBUTTON           (BIT(1) | BIT(0))
144 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 2)
145 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 2)
146 
147 enum mxs_lradc_id {
148         IMX23_LRADC,
149         IMX28_LRADC,
150 };
151 
152 enum mxs_lradc_ts_wires {
153         MXS_LRADC_TOUCHSCREEN_NONE = 0,
154         MXS_LRADC_TOUCHSCREEN_4WIRE,
155         MXS_LRADC_TOUCHSCREEN_5WIRE,
156 };
157 
158 /**
159  * struct mxs_lradc
160  * @soc: soc type (IMX23 or IMX28)
161  * @clk: 2 kHz clock for delay units
162  * @buffer_vchans: channels that can be used during buffered capture
163  * @touchscreen_wire: touchscreen type (4-wire or 5-wire)
164  * @use_touchbutton: button state (on or off)
165  */
166 struct mxs_lradc {
167         enum mxs_lradc_id       soc;
168         struct clk              *clk;
169         u8                      buffer_vchans;
170 
171         enum mxs_lradc_ts_wires touchscreen_wire;
172         bool                    use_touchbutton;
173 };
174 
175 static inline u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
176 {
177         switch (lradc->soc) {
178         case IMX23_LRADC:
179                 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
180         case IMX28_LRADC:
181                 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
182         default:
183                 return 0;
184         }
185 }
186 
187 #endif /* __MXS_LRADC_H */
188 

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