~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/include/linux/mfd/palmas.h

Version: ~ [ linux-5.15-rc1 ] ~ [ linux-5.14.5 ] ~ [ linux-5.13.18 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.66 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.147 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.206 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.246 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.282 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.283 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * TI Palmas
  3  *
  4  * Copyright 2011-2013 Texas Instruments Inc.
  5  *
  6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
  7  * Author: Ian Lartey <ian@slimlogic.co.uk>
  8  *
  9  *  This program is free software; you can redistribute it and/or modify it
 10  *  under  the terms of the GNU General  Public License as published by the
 11  *  Free Software Foundation;  either version 2 of the License, or (at your
 12  *  option) any later version.
 13  *
 14  */
 15 
 16 #ifndef __LINUX_MFD_PALMAS_H
 17 #define __LINUX_MFD_PALMAS_H
 18 
 19 #include <linux/usb/otg.h>
 20 #include <linux/leds.h>
 21 #include <linux/regmap.h>
 22 #include <linux/regulator/driver.h>
 23 #include <linux/extcon-provider.h>
 24 #include <linux/of_gpio.h>
 25 #include <linux/usb/phy_companion.h>
 26 
 27 #define PALMAS_NUM_CLIENTS              3
 28 
 29 /* The ID_REVISION NUMBERS */
 30 #define PALMAS_CHIP_OLD_ID              0x0000
 31 #define PALMAS_CHIP_ID                  0xC035
 32 #define PALMAS_CHIP_CHARGER_ID          0xC036
 33 
 34 #define TPS65917_RESERVED               -1
 35 
 36 #define is_palmas(a)    (((a) == PALMAS_CHIP_OLD_ID) || \
 37                         ((a) == PALMAS_CHIP_ID))
 38 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
 39 
 40 /**
 41  * Palmas PMIC feature types
 42  *
 43  * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
 44  *      regulator.
 45  *
 46  * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
 47  *      specific feature (above) or not. Return non-zero, if yes.
 48  */
 49 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST        BIT(0)
 50 #define PALMAS_PMIC_HAS(b, f)                   \
 51                         ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
 52 
 53 struct palmas_pmic;
 54 struct palmas_gpadc;
 55 struct palmas_resource;
 56 struct palmas_usb;
 57 struct palmas_pmic_driver_data;
 58 struct palmas_pmic_platform_data;
 59 
 60 enum palmas_usb_state {
 61         PALMAS_USB_STATE_DISCONNECT,
 62         PALMAS_USB_STATE_VBUS,
 63         PALMAS_USB_STATE_ID,
 64 };
 65 
 66 struct palmas {
 67         struct device *dev;
 68 
 69         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
 70         struct regmap *regmap[PALMAS_NUM_CLIENTS];
 71 
 72         /* Stored chip id */
 73         int id;
 74 
 75         unsigned int features;
 76         /* IRQ Data */
 77         int irq;
 78         u32 irq_mask;
 79         struct mutex irq_lock;
 80         struct regmap_irq_chip_data *irq_data;
 81 
 82         struct palmas_pmic_driver_data *pmic_ddata;
 83 
 84         /* Child Devices */
 85         struct palmas_pmic *pmic;
 86         struct palmas_gpadc *gpadc;
 87         struct palmas_resource *resource;
 88         struct palmas_usb *usb;
 89 
 90         /* GPIO MUXing */
 91         u8 gpio_muxed;
 92         u8 led_muxed;
 93         u8 pwm_muxed;
 94 };
 95 
 96 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 |    \
 97                         PALMAS_EXT_CONTROL_ENABLE2 |    \
 98                         PALMAS_EXT_CONTROL_NSLEEP)
 99 
100 struct palmas_sleep_requestor_info {
101         int id;
102         int reg_offset;
103         int bit_pos;
104 };
105 
106 struct palmas_regs_info {
107         char    *name;
108         char    *sname;
109         u8      vsel_addr;
110         u8      ctrl_addr;
111         u8      tstep_addr;
112         int     sleep_id;
113 };
114 
115 struct palmas_pmic_driver_data {
116         int smps_start;
117         int smps_end;
118         int ldo_begin;
119         int ldo_end;
120         int max_reg;
121         bool has_regen3;
122         struct palmas_regs_info *palmas_regs_info;
123         struct of_regulator_match *palmas_matches;
124         struct palmas_sleep_requestor_info *sleep_req_info;
125         int (*smps_register)(struct palmas_pmic *pmic,
126                              struct palmas_pmic_driver_data *ddata,
127                              struct palmas_pmic_platform_data *pdata,
128                              const char *pdev_name,
129                              struct regulator_config config);
130         int (*ldo_register)(struct palmas_pmic *pmic,
131                             struct palmas_pmic_driver_data *ddata,
132                             struct palmas_pmic_platform_data *pdata,
133                             const char *pdev_name,
134                             struct regulator_config config);
135 };
136 
137 struct palmas_adc_wakeup_property {
138         int adc_channel_number;
139         int adc_high_threshold;
140         int adc_low_threshold;
141 };
142 
143 struct palmas_gpadc_platform_data {
144         /* Channel 3 current source is only enabled during conversion */
145         int ch3_current;        /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
146 
147         /* Channel 0 current source can be used for battery detection.
148          * If used for battery detection this will cause a permanent current
149          * consumption depending on current level set here.
150          */
151         int ch0_current;        /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
152         bool extended_delay;    /* use extended delay for conversion */
153 
154         /* default BAT_REMOVAL_DAT setting on device probe */
155         int bat_removal;
156 
157         /* Sets the START_POLARITY bit in the RT_CTRL register */
158         int start_polarity;
159 
160         int auto_conversion_period_ms;
161         struct palmas_adc_wakeup_property *adc_wakeup1_data;
162         struct palmas_adc_wakeup_property *adc_wakeup2_data;
163 };
164 
165 struct palmas_reg_init {
166         /* warm_rest controls the voltage levels after a warm reset
167          *
168          * 0: reload default values from OTP on warm reset
169          * 1: maintain voltage from VSEL on warm reset
170          */
171         int warm_reset;
172 
173         /* roof_floor controls whether the regulator uses the i2c style
174          * of DVS or uses the method where a GPIO or other control method is
175          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
176          *
177          * For SMPS
178          *
179          * 0: i2c selection of voltage
180          * 1: pin selection of voltage.
181          *
182          * For LDO unused
183          */
184         int roof_floor;
185 
186         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
187          * the data sheet.
188          *
189          * For SMPS
190          *
191          * 0: Off
192          * 1: AUTO
193          * 2: ECO
194          * 3: Forced PWM
195          *
196          * For LDO
197          *
198          * 0: Off
199          * 1: On
200          */
201         int mode_sleep;
202 
203         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
204          * register. Set this is the default voltage set in OTP needs
205          * to be overridden.
206          */
207         u8 vsel;
208 
209 };
210 
211 enum palmas_regulators {
212         /* SMPS regulators */
213         PALMAS_REG_SMPS12,
214         PALMAS_REG_SMPS123,
215         PALMAS_REG_SMPS3,
216         PALMAS_REG_SMPS45,
217         PALMAS_REG_SMPS457,
218         PALMAS_REG_SMPS6,
219         PALMAS_REG_SMPS7,
220         PALMAS_REG_SMPS8,
221         PALMAS_REG_SMPS9,
222         PALMAS_REG_SMPS10_OUT2,
223         PALMAS_REG_SMPS10_OUT1,
224         /* LDO regulators */
225         PALMAS_REG_LDO1,
226         PALMAS_REG_LDO2,
227         PALMAS_REG_LDO3,
228         PALMAS_REG_LDO4,
229         PALMAS_REG_LDO5,
230         PALMAS_REG_LDO6,
231         PALMAS_REG_LDO7,
232         PALMAS_REG_LDO8,
233         PALMAS_REG_LDO9,
234         PALMAS_REG_LDOLN,
235         PALMAS_REG_LDOUSB,
236         /* External regulators */
237         PALMAS_REG_REGEN1,
238         PALMAS_REG_REGEN2,
239         PALMAS_REG_REGEN3,
240         PALMAS_REG_SYSEN1,
241         PALMAS_REG_SYSEN2,
242         /* Total number of regulators */
243         PALMAS_NUM_REGS,
244 };
245 
246 enum tps65917_regulators {
247         /* SMPS regulators */
248         TPS65917_REG_SMPS1,
249         TPS65917_REG_SMPS2,
250         TPS65917_REG_SMPS3,
251         TPS65917_REG_SMPS4,
252         TPS65917_REG_SMPS5,
253         TPS65917_REG_SMPS12,
254         /* LDO regulators */
255         TPS65917_REG_LDO1,
256         TPS65917_REG_LDO2,
257         TPS65917_REG_LDO3,
258         TPS65917_REG_LDO4,
259         TPS65917_REG_LDO5,
260         TPS65917_REG_REGEN1,
261         TPS65917_REG_REGEN2,
262         TPS65917_REG_REGEN3,
263 
264         /* Total number of regulators */
265         TPS65917_NUM_REGS,
266 };
267 
268 /* External controll signal name */
269 enum {
270         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
271         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
272         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
273 };
274 
275 /*
276  * Palmas device resources can be controlled externally for
277  * enabling/disabling it rather than register write through i2c.
278  * Add the external controlled requestor ID for different resources.
279  */
280 enum palmas_external_requestor_id {
281         PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
282         PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
283         PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
284         PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
285         PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
286         PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
287         PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
288         PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
289         PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
290         PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
291         PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
292         PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
293         PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
294         PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
295         PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
296         PALMAS_EXTERNAL_REQSTR_ID_LDO1,
297         PALMAS_EXTERNAL_REQSTR_ID_LDO2,
298         PALMAS_EXTERNAL_REQSTR_ID_LDO3,
299         PALMAS_EXTERNAL_REQSTR_ID_LDO4,
300         PALMAS_EXTERNAL_REQSTR_ID_LDO5,
301         PALMAS_EXTERNAL_REQSTR_ID_LDO6,
302         PALMAS_EXTERNAL_REQSTR_ID_LDO7,
303         PALMAS_EXTERNAL_REQSTR_ID_LDO8,
304         PALMAS_EXTERNAL_REQSTR_ID_LDO9,
305         PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
306         PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
307 
308         /* Last entry */
309         PALMAS_EXTERNAL_REQSTR_ID_MAX,
310 };
311 
312 enum tps65917_external_requestor_id {
313         TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
314         TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
315         TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
316         TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
317         TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
318         TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
319         TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
320         TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
321         TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
322         TPS65917_EXTERNAL_REQSTR_ID_LDO1,
323         TPS65917_EXTERNAL_REQSTR_ID_LDO2,
324         TPS65917_EXTERNAL_REQSTR_ID_LDO3,
325         TPS65917_EXTERNAL_REQSTR_ID_LDO4,
326         TPS65917_EXTERNAL_REQSTR_ID_LDO5,
327         /* Last entry */
328         TPS65917_EXTERNAL_REQSTR_ID_MAX,
329 };
330 
331 struct palmas_pmic_platform_data {
332         /* An array of pointers to regulator init data indexed by regulator
333          * ID
334          */
335         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
336 
337         /* An array of pointers to structures containing sleep mode and DVS
338          * configuration for regulators indexed by ID
339          */
340         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
341 
342         /* use LDO6 for vibrator control */
343         int ldo6_vibrator;
344 
345         /* Enable tracking mode of LDO8 */
346         bool enable_ldo8_tracking;
347 };
348 
349 struct palmas_usb_platform_data {
350         /* Do we enable the wakeup comparator on probe */
351         int wakeup;
352 };
353 
354 struct palmas_resource_platform_data {
355         int regen1_mode_sleep;
356         int regen2_mode_sleep;
357         int sysen1_mode_sleep;
358         int sysen2_mode_sleep;
359 
360         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
361         u8 nsleep_res;
362         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
363         u8 nsleep_smps;
364         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
365         u8 nsleep_ldo1;
366         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
367         u8 nsleep_ldo2;
368 
369         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
370         u8 enable1_res;
371         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
372         u8 enable1_smps;
373         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
374         u8 enable1_ldo1;
375         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
376         u8 enable1_ldo2;
377 
378         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
379         u8 enable2_res;
380         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
381         u8 enable2_smps;
382         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
383         u8 enable2_ldo1;
384         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
385         u8 enable2_ldo2;
386 };
387 
388 struct palmas_clk_platform_data {
389         int clk32kg_mode_sleep;
390         int clk32kgaudio_mode_sleep;
391 };
392 
393 struct palmas_platform_data {
394         int irq_flags;
395         int gpio_base;
396 
397         /* bit value to be loaded to the POWER_CTRL register */
398         u8 power_ctrl;
399 
400         /*
401          * boolean to select if we want to configure muxing here
402          * then the two value to load into the registers if true
403          */
404         int mux_from_pdata;
405         u8 pad1, pad2;
406         bool pm_off;
407 
408         struct palmas_pmic_platform_data *pmic_pdata;
409         struct palmas_gpadc_platform_data *gpadc_pdata;
410         struct palmas_usb_platform_data *usb_pdata;
411         struct palmas_resource_platform_data *resource_pdata;
412         struct palmas_clk_platform_data *clk_pdata;
413 };
414 
415 struct palmas_gpadc_calibration {
416         s32 gain;
417         s32 gain_error;
418         s32 offset_error;
419 };
420 
421 #define PALMAS_DATASHEET_NAME(_name)    "palmas-gpadc-chan-"#_name
422 
423 struct palmas_gpadc_result {
424         s32 raw_code;
425         s32 corrected_code;
426         s32 result;
427 };
428 
429 #define PALMAS_MAX_CHANNELS 16
430 
431 /* Define the tps65917 IRQ numbers */
432 enum tps65917_irqs {
433         /* INT1 registers */
434         TPS65917_RESERVED1,
435         TPS65917_PWRON_IRQ,
436         TPS65917_LONG_PRESS_KEY_IRQ,
437         TPS65917_RESERVED2,
438         TPS65917_PWRDOWN_IRQ,
439         TPS65917_HOTDIE_IRQ,
440         TPS65917_VSYS_MON_IRQ,
441         TPS65917_RESERVED3,
442         /* INT2 registers */
443         TPS65917_RESERVED4,
444         TPS65917_OTP_ERROR_IRQ,
445         TPS65917_WDT_IRQ,
446         TPS65917_RESERVED5,
447         TPS65917_RESET_IN_IRQ,
448         TPS65917_FSD_IRQ,
449         TPS65917_SHORT_IRQ,
450         TPS65917_RESERVED6,
451         /* INT3 registers */
452         TPS65917_GPADC_AUTO_0_IRQ,
453         TPS65917_GPADC_AUTO_1_IRQ,
454         TPS65917_GPADC_EOC_SW_IRQ,
455         TPS65917_RESREVED6,
456         TPS65917_RESERVED7,
457         TPS65917_RESERVED8,
458         TPS65917_RESERVED9,
459         TPS65917_VBUS_IRQ,
460         /* INT4 registers */
461         TPS65917_GPIO_0_IRQ,
462         TPS65917_GPIO_1_IRQ,
463         TPS65917_GPIO_2_IRQ,
464         TPS65917_GPIO_3_IRQ,
465         TPS65917_GPIO_4_IRQ,
466         TPS65917_GPIO_5_IRQ,
467         TPS65917_GPIO_6_IRQ,
468         TPS65917_RESERVED10,
469         /* Total Number IRQs */
470         TPS65917_NUM_IRQ,
471 };
472 
473 /* Define the palmas IRQ numbers */
474 enum palmas_irqs {
475         /* INT1 registers */
476         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
477         PALMAS_PWRON_IRQ,
478         PALMAS_LONG_PRESS_KEY_IRQ,
479         PALMAS_RPWRON_IRQ,
480         PALMAS_PWRDOWN_IRQ,
481         PALMAS_HOTDIE_IRQ,
482         PALMAS_VSYS_MON_IRQ,
483         PALMAS_VBAT_MON_IRQ,
484         /* INT2 registers */
485         PALMAS_RTC_ALARM_IRQ,
486         PALMAS_RTC_TIMER_IRQ,
487         PALMAS_WDT_IRQ,
488         PALMAS_BATREMOVAL_IRQ,
489         PALMAS_RESET_IN_IRQ,
490         PALMAS_FBI_BB_IRQ,
491         PALMAS_SHORT_IRQ,
492         PALMAS_VAC_ACOK_IRQ,
493         /* INT3 registers */
494         PALMAS_GPADC_AUTO_0_IRQ,
495         PALMAS_GPADC_AUTO_1_IRQ,
496         PALMAS_GPADC_EOC_SW_IRQ,
497         PALMAS_GPADC_EOC_RT_IRQ,
498         PALMAS_ID_OTG_IRQ,
499         PALMAS_ID_IRQ,
500         PALMAS_VBUS_OTG_IRQ,
501         PALMAS_VBUS_IRQ,
502         /* INT4 registers */
503         PALMAS_GPIO_0_IRQ,
504         PALMAS_GPIO_1_IRQ,
505         PALMAS_GPIO_2_IRQ,
506         PALMAS_GPIO_3_IRQ,
507         PALMAS_GPIO_4_IRQ,
508         PALMAS_GPIO_5_IRQ,
509         PALMAS_GPIO_6_IRQ,
510         PALMAS_GPIO_7_IRQ,
511         /* Total Number IRQs */
512         PALMAS_NUM_IRQ,
513 };
514 
515 /* Palmas GPADC Channels */
516 enum {
517         PALMAS_ADC_CH_IN0,
518         PALMAS_ADC_CH_IN1,
519         PALMAS_ADC_CH_IN2,
520         PALMAS_ADC_CH_IN3,
521         PALMAS_ADC_CH_IN4,
522         PALMAS_ADC_CH_IN5,
523         PALMAS_ADC_CH_IN6,
524         PALMAS_ADC_CH_IN7,
525         PALMAS_ADC_CH_IN8,
526         PALMAS_ADC_CH_IN9,
527         PALMAS_ADC_CH_IN10,
528         PALMAS_ADC_CH_IN11,
529         PALMAS_ADC_CH_IN12,
530         PALMAS_ADC_CH_IN13,
531         PALMAS_ADC_CH_IN14,
532         PALMAS_ADC_CH_IN15,
533         PALMAS_ADC_CH_MAX,
534 };
535 
536 /* Palmas GPADC Channel0 Current Source */
537 enum {
538         PALMAS_ADC_CH0_CURRENT_SRC_0,
539         PALMAS_ADC_CH0_CURRENT_SRC_5,
540         PALMAS_ADC_CH0_CURRENT_SRC_15,
541         PALMAS_ADC_CH0_CURRENT_SRC_20,
542 };
543 
544 /* Palmas GPADC Channel3 Current Source */
545 enum {
546         PALMAS_ADC_CH3_CURRENT_SRC_0,
547         PALMAS_ADC_CH3_CURRENT_SRC_10,
548         PALMAS_ADC_CH3_CURRENT_SRC_400,
549         PALMAS_ADC_CH3_CURRENT_SRC_800,
550 };
551 
552 struct palmas_pmic {
553         struct palmas *palmas;
554         struct device *dev;
555         struct regulator_desc desc[PALMAS_NUM_REGS];
556         struct regulator_dev *rdev[PALMAS_NUM_REGS];
557         struct mutex mutex;
558 
559         int smps123;
560         int smps457;
561         int smps12;
562 
563         int range[PALMAS_REG_SMPS10_OUT1];
564         unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
565         unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
566 };
567 
568 struct palmas_resource {
569         struct palmas *palmas;
570         struct device *dev;
571 };
572 
573 struct palmas_usb {
574         struct palmas *palmas;
575         struct device *dev;
576 
577         struct extcon_dev *edev;
578 
579         int id_otg_irq;
580         int id_irq;
581         int vbus_otg_irq;
582         int vbus_irq;
583 
584         int gpio_id_irq;
585         int gpio_vbus_irq;
586         struct gpio_desc *id_gpiod;
587         struct gpio_desc *vbus_gpiod;
588         unsigned long sw_debounce_jiffies;
589         struct delayed_work wq_detectid;
590 
591         enum palmas_usb_state linkstat;
592         int wakeup;
593         bool enable_vbus_detection;
594         bool enable_id_detection;
595         bool enable_gpio_id_detection;
596         bool enable_gpio_vbus_detection;
597 };
598 
599 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
600 
601 enum usb_irq_events {
602         /* Wakeup events from INT3 */
603         PALMAS_USB_ID_WAKEPUP,
604         PALMAS_USB_VBUS_WAKEUP,
605 
606         /* ID_OTG_EVENTS */
607         PALMAS_USB_ID_GND,
608         N_PALMAS_USB_ID_GND,
609         PALMAS_USB_ID_C,
610         N_PALMAS_USB_ID_C,
611         PALMAS_USB_ID_B,
612         N_PALMAS_USB_ID_B,
613         PALMAS_USB_ID_A,
614         N_PALMAS_USB_ID_A,
615         PALMAS_USB_ID_FLOAT,
616         N_PALMAS_USB_ID_FLOAT,
617 
618         /* VBUS_OTG_EVENTS */
619         PALMAS_USB_VB_SESS_END,
620         N_PALMAS_USB_VB_SESS_END,
621         PALMAS_USB_VB_SESS_VLD,
622         N_PALMAS_USB_VB_SESS_VLD,
623         PALMAS_USB_VA_SESS_VLD,
624         N_PALMAS_USB_VA_SESS_VLD,
625         PALMAS_USB_VA_VBUS_VLD,
626         N_PALMAS_USB_VA_VBUS_VLD,
627         PALMAS_USB_VADP_SNS,
628         N_PALMAS_USB_VADP_SNS,
629         PALMAS_USB_VADP_PRB,
630         N_PALMAS_USB_VADP_PRB,
631         PALMAS_USB_VOTG_SESS_VLD,
632         N_PALMAS_USB_VOTG_SESS_VLD,
633 };
634 
635 /* defines so we can store the mux settings */
636 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
637 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
638 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
639 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
640 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
641 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
642 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
643 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
644 
645 #define PALMAS_LED1_MUXED                                       (1 << 0)
646 #define PALMAS_LED2_MUXED                                       (1 << 1)
647 
648 #define PALMAS_PWM1_MUXED                                       (1 << 0)
649 #define PALMAS_PWM2_MUXED                                       (1 << 1)
650 
651 /* helper macro to get correct slave number */
652 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
653 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xFF) + y)
654 
655 /* Base addresses of IP blocks in Palmas */
656 #define PALMAS_SMPS_DVS_BASE                                    0x020
657 #define PALMAS_RTC_BASE                                         0x100
658 #define PALMAS_VALIDITY_BASE                                    0x118
659 #define PALMAS_SMPS_BASE                                        0x120
660 #define PALMAS_LDO_BASE                                         0x150
661 #define PALMAS_DVFS_BASE                                        0x180
662 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
663 #define PALMAS_RESOURCE_BASE                                    0x1D4
664 #define PALMAS_PU_PD_OD_BASE                                    0x1F0
665 #define PALMAS_LED_BASE                                         0x200
666 #define PALMAS_INTERRUPT_BASE                                   0x210
667 #define PALMAS_USB_OTG_BASE                                     0x250
668 #define PALMAS_VIBRATOR_BASE                                    0x270
669 #define PALMAS_GPIO_BASE                                        0x280
670 #define PALMAS_USB_BASE                                         0x290
671 #define PALMAS_GPADC_BASE                                       0x2C0
672 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
673 
674 /* Registers for function RTC */
675 #define PALMAS_SECONDS_REG                                      0x00
676 #define PALMAS_MINUTES_REG                                      0x01
677 #define PALMAS_HOURS_REG                                        0x02
678 #define PALMAS_DAYS_REG                                         0x03
679 #define PALMAS_MONTHS_REG                                       0x04
680 #define PALMAS_YEARS_REG                                        0x05
681 #define PALMAS_WEEKS_REG                                        0x06
682 #define PALMAS_ALARM_SECONDS_REG                                0x08
683 #define PALMAS_ALARM_MINUTES_REG                                0x09
684 #define PALMAS_ALARM_HOURS_REG                                  0x0A
685 #define PALMAS_ALARM_DAYS_REG                                   0x0B
686 #define PALMAS_ALARM_MONTHS_REG                                 0x0C
687 #define PALMAS_ALARM_YEARS_REG                                  0x0D
688 #define PALMAS_RTC_CTRL_REG                                     0x10
689 #define PALMAS_RTC_STATUS_REG                                   0x11
690 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
691 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
692 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
693 #define PALMAS_RTC_RES_PROG_REG                                 0x15
694 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
695 
696 /* Bit definitions for SECONDS_REG */
697 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
698 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           0x04
699 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0F
700 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0x00
701 
702 /* Bit definitions for MINUTES_REG */
703 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
704 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           0x04
705 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0F
706 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0x00
707 
708 /* Bit definitions for HOURS_REG */
709 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
710 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           0x07
711 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
712 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            0x04
713 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0F
714 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0x00
715 
716 /* Bit definitions for DAYS_REG */
717 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
718 #define PALMAS_DAYS_REG_DAY1_SHIFT                              0x04
719 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0F
720 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0x00
721 
722 /* Bit definitions for MONTHS_REG */
723 #define PALMAS_MONTHS_REG_MONTH1                                0x10
724 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          0x04
725 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0F
726 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0x00
727 
728 /* Bit definitions for YEARS_REG */
729 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
730 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            0x04
731 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0F
732 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0x00
733 
734 /* Bit definitions for WEEKS_REG */
735 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
736 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0x00
737 
738 /* Bit definitions for ALARM_SECONDS_REG */
739 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
740 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               0x04
741 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0F
742 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0x00
743 
744 /* Bit definitions for ALARM_MINUTES_REG */
745 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
746 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               0x04
747 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0F
748 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0x00
749 
750 /* Bit definitions for ALARM_HOURS_REG */
751 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
752 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               0x07
753 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
754 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                0x04
755 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0F
756 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0x00
757 
758 /* Bit definitions for ALARM_DAYS_REG */
759 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
760 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  0x04
761 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0F
762 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0x00
763 
764 /* Bit definitions for ALARM_MONTHS_REG */
765 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
766 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              0x04
767 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0F
768 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0x00
769 
770 /* Bit definitions for ALARM_YEARS_REG */
771 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
772 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                0x04
773 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0F
774 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0x00
775 
776 /* Bit definitions for RTC_CTRL_REG */
777 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
778 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     0x07
779 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
780 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      0x06
781 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
782 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                0x05
783 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
784 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     0x04
785 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
786 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    0x03
787 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
788 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     0x02
789 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
790 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     0x01
791 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
792 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0x00
793 
794 /* Bit definitions for RTC_STATUS_REG */
795 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
796 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    0x07
797 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
798 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       0x06
799 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
800 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    0x05
801 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
802 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    0x04
803 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
804 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    0x03
805 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
806 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    0x02
807 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
808 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         0x01
809 
810 /* Bit definitions for RTC_INTERRUPTS_REG */
811 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
812 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        0x04
813 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
814 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                0x03
815 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
816 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                0x02
817 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
818 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0x00
819 
820 /* Bit definitions for RTC_COMP_LSB_REG */
821 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xFF
822 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0x00
823 
824 /* Bit definitions for RTC_COMP_MSB_REG */
825 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xFF
826 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0x00
827 
828 /* Bit definitions for RTC_RES_PROG_REG */
829 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3F
830 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0x00
831 
832 /* Bit definitions for RTC_RESET_STATUS_REG */
833 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
834 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0x00
835 
836 /* Registers for function BACKUP */
837 #define PALMAS_BACKUP0                                          0x00
838 #define PALMAS_BACKUP1                                          0x01
839 #define PALMAS_BACKUP2                                          0x02
840 #define PALMAS_BACKUP3                                          0x03
841 #define PALMAS_BACKUP4                                          0x04
842 #define PALMAS_BACKUP5                                          0x05
843 #define PALMAS_BACKUP6                                          0x06
844 #define PALMAS_BACKUP7                                          0x07
845 
846 /* Bit definitions for BACKUP0 */
847 #define PALMAS_BACKUP0_BACKUP_MASK                              0xFF
848 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0x00
849 
850 /* Bit definitions for BACKUP1 */
851 #define PALMAS_BACKUP1_BACKUP_MASK                              0xFF
852 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0x00
853 
854 /* Bit definitions for BACKUP2 */
855 #define PALMAS_BACKUP2_BACKUP_MASK                              0xFF
856 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0x00
857 
858 /* Bit definitions for BACKUP3 */
859 #define PALMAS_BACKUP3_BACKUP_MASK                              0xFF
860 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0x00
861 
862 /* Bit definitions for BACKUP4 */
863 #define PALMAS_BACKUP4_BACKUP_MASK                              0xFF
864 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0x00
865 
866 /* Bit definitions for BACKUP5 */
867 #define PALMAS_BACKUP5_BACKUP_MASK                              0xFF
868 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0x00
869 
870 /* Bit definitions for BACKUP6 */
871 #define PALMAS_BACKUP6_BACKUP_MASK                              0xFF
872 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0x00
873 
874 /* Bit definitions for BACKUP7 */
875 #define PALMAS_BACKUP7_BACKUP_MASK                              0xFF
876 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0x00
877 
878 /* Registers for function SMPS */
879 #define PALMAS_SMPS12_CTRL                                      0x00
880 #define PALMAS_SMPS12_TSTEP                                     0x01
881 #define PALMAS_SMPS12_FORCE                                     0x02
882 #define PALMAS_SMPS12_VOLTAGE                                   0x03
883 #define PALMAS_SMPS3_CTRL                                       0x04
884 #define PALMAS_SMPS3_VOLTAGE                                    0x07
885 #define PALMAS_SMPS45_CTRL                                      0x08
886 #define PALMAS_SMPS45_TSTEP                                     0x09
887 #define PALMAS_SMPS45_FORCE                                     0x0A
888 #define PALMAS_SMPS45_VOLTAGE                                   0x0B
889 #define PALMAS_SMPS6_CTRL                                       0x0C
890 #define PALMAS_SMPS6_TSTEP                                      0x0D
891 #define PALMAS_SMPS6_FORCE                                      0x0E
892 #define PALMAS_SMPS6_VOLTAGE                                    0x0F
893 #define PALMAS_SMPS7_CTRL                                       0x10
894 #define PALMAS_SMPS7_VOLTAGE                                    0x13
895 #define PALMAS_SMPS8_CTRL                                       0x14
896 #define PALMAS_SMPS8_TSTEP                                      0x15
897 #define PALMAS_SMPS8_FORCE                                      0x16
898 #define PALMAS_SMPS8_VOLTAGE                                    0x17
899 #define PALMAS_SMPS9_CTRL                                       0x18
900 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
901 #define PALMAS_SMPS10_CTRL                                      0x1C
902 #define PALMAS_SMPS10_STATUS                                    0x1F
903 #define PALMAS_SMPS_CTRL                                        0x24
904 #define PALMAS_SMPS_PD_CTRL                                     0x25
905 #define PALMAS_SMPS_DITHER_EN                                   0x26
906 #define PALMAS_SMPS_THERMAL_EN                                  0x27
907 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
908 #define PALMAS_SMPS_SHORT_STATUS                                0x29
909 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
910 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
911 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
912 
913 /* Bit definitions for SMPS12_CTRL */
914 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
915 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           0x07
916 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
917 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  0x06
918 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
919 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         0x04
920 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
921 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     0x02
922 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
923 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0x00
924 
925 /* Bit definitions for SMPS12_TSTEP */
926 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
927 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0x00
928 
929 /* Bit definitions for SMPS12_FORCE */
930 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
931 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           0x07
932 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7F
933 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0x00
934 
935 /* Bit definitions for SMPS12_VOLTAGE */
936 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
937 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       0x07
938 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7F
939 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0x00
940 
941 /* Bit definitions for SMPS3_CTRL */
942 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
943 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            0x07
944 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
945 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          0x04
946 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
947 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      0x02
948 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
949 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0x00
950 
951 /* Bit definitions for SMPS3_VOLTAGE */
952 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
953 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        0x07
954 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7F
955 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0x00
956 
957 /* Bit definitions for SMPS45_CTRL */
958 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
959 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           0x07
960 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
961 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  0x06
962 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
963 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         0x04
964 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
965 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     0x02
966 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
967 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0x00
968 
969 /* Bit definitions for SMPS45_TSTEP */
970 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
971 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0x00
972 
973 /* Bit definitions for SMPS45_FORCE */
974 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
975 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           0x07
976 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7F
977 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0x00
978 
979 /* Bit definitions for SMPS45_VOLTAGE */
980 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
981 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       0x07
982 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7F
983 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0x00
984 
985 /* Bit definitions for SMPS6_CTRL */
986 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
987 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            0x07
988 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
989 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   0x06
990 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
991 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          0x04
992 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
993 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      0x02
994 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
995 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0x00
996 
997 /* Bit definitions for SMPS6_TSTEP */
998 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
999 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0x00
1000 
1001 /* Bit definitions for SMPS6_FORCE */
1002 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
1003 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            0x07
1004 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7F
1005 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0x00
1006 
1007 /* Bit definitions for SMPS6_VOLTAGE */
1008 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
1009 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        0x07
1010 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7F
1011 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0x00
1012 
1013 /* Bit definitions for SMPS7_CTRL */
1014 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
1015 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            0x07
1016 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
1017 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          0x04
1018 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
1019 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      0x02
1020 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
1021 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0x00
1022 
1023 /* Bit definitions for SMPS7_VOLTAGE */
1024 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
1025 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        0x07
1026 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7F
1027 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0x00
1028 
1029 /* Bit definitions for SMPS8_CTRL */
1030 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
1031 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            0x07
1032 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
1033 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   0x06
1034 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
1035 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          0x04
1036 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
1037 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      0x02
1038 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
1039 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0x00
1040 
1041 /* Bit definitions for SMPS8_TSTEP */
1042 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
1043 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0x00
1044 
1045 /* Bit definitions for SMPS8_FORCE */
1046 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
1047 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            0x07
1048 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7F
1049 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0x00
1050 
1051 /* Bit definitions for SMPS8_VOLTAGE */
1052 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
1053 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        0x07
1054 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7F
1055 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0x00
1056 
1057 /* Bit definitions for SMPS9_CTRL */
1058 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
1059 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            0x07
1060 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
1061 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          0x04
1062 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
1063 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      0x02
1064 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
1065 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0x00
1066 
1067 /* Bit definitions for SMPS9_VOLTAGE */
1068 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
1069 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        0x07
1070 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7F
1071 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0x00
1072 
1073 /* Bit definitions for SMPS10_CTRL */
1074 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
1075 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     0x04
1076 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0F
1077 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0x00
1078 
1079 /* Bit definitions for SMPS10_STATUS */
1080 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0F
1081 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0x00
1082 
1083 /* Bit definitions for SMPS_CTRL */
1084 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
1085 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                0x05
1086 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
1087 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                0x04
1088 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
1089 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                0x02
1090 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
1091 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0x00
1092 
1093 /* Bit definitions for SMPS_PD_CTRL */
1094 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
1095 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         0x06
1096 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
1097 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         0x05
1098 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
1099 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         0x04
1100 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
1101 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         0x03
1102 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
1103 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        0x02
1104 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
1105 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         0x01
1106 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
1107 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0x00
1108 
1109 /* Bit definitions for SMPS_THERMAL_EN */
1110 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
1111 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      0x06
1112 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
1113 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      0x05
1114 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
1115 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      0x03
1116 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
1117 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    0x02
1118 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
1119 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0x00
1120 
1121 /* Bit definitions for SMPS_THERMAL_STATUS */
1122 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
1123 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  0x06
1124 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
1125 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  0x05
1126 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
1127 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  0x03
1128 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
1129 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                0x02
1130 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
1131 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0x00
1132 
1133 /* Bit definitions for SMPS_SHORT_STATUS */
1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
1135 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   0x07
1136 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
1137 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    0x06
1138 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
1139 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    0x05
1140 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
1141 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    0x04
1142 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
1143 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    0x03
1144 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
1145 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   0x02
1146 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
1147 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    0x01
1148 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
1149 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0x00
1150 
1151 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1152 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
1153 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       0x06
1154 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
1155 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       0x05
1156 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
1157 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       0x04
1158 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
1159 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       0x03
1160 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
1161 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      0x02
1162 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
1163 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       0x01
1164 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
1165 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0x00
1166 
1167 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
1169 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                0x07
1170 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
1171 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 0x06
1172 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
1173 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 0x05
1174 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
1175 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 0x04
1176 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
1177 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 0x03
1178 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
1179 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                0x02
1180 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
1181 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 0x01
1182 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
1183 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0x00
1184 
1185 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1186 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
1187 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1188 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
1189 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                0x02
1190 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
1191 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  0x01
1192 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
1193 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0x00
1194 
1195 /* Registers for function LDO */
1196 #define PALMAS_LDO1_CTRL                                        0x00
1197 #define PALMAS_LDO1_VOLTAGE                                     0x01
1198 #define PALMAS_LDO2_CTRL                                        0x02
1199 #define PALMAS_LDO2_VOLTAGE                                     0x03
1200 #define PALMAS_LDO3_CTRL                                        0x04
1201 #define PALMAS_LDO3_VOLTAGE                                     0x05
1202 #define PALMAS_LDO4_CTRL                                        0x06
1203 #define PALMAS_LDO4_VOLTAGE                                     0x07
1204 #define PALMAS_LDO5_CTRL                                        0x08
1205 #define PALMAS_LDO5_VOLTAGE                                     0x09
1206 #define PALMAS_LDO6_CTRL                                        0x0A
1207 #define PALMAS_LDO6_VOLTAGE                                     0x0B
1208 #define PALMAS_LDO7_CTRL                                        0x0C
1209 #define PALMAS_LDO7_VOLTAGE                                     0x0D
1210 #define PALMAS_LDO8_CTRL                                        0x0E
1211 #define PALMAS_LDO8_VOLTAGE                                     0x0F
1212 #define PALMAS_LDO9_CTRL                                        0x10
1213 #define PALMAS_LDO9_VOLTAGE                                     0x11
1214 #define PALMAS_LDOLN_CTRL                                       0x12
1215 #define PALMAS_LDOLN_VOLTAGE                                    0x13
1216 #define PALMAS_LDOUSB_CTRL                                      0x14
1217 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
1218 #define PALMAS_LDO_CTRL                                         0x1A
1219 #define PALMAS_LDO_PD_CTRL1                                     0x1B
1220 #define PALMAS_LDO_PD_CTRL2                                     0x1C
1221 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
1222 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
1223 
1224 /* Bit definitions for LDO1_CTRL */
1225 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
1226 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             0x07
1227 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
1228 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           0x04
1229 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
1230 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       0x02
1231 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
1232 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0x00
1233 
1234 /* Bit definitions for LDO1_VOLTAGE */
1235 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3F
1236 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0x00
1237 
1238 /* Bit definitions for LDO2_CTRL */
1239 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1240 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             0x07
1241 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1242 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           0x04
1243 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1244 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       0x02
1245 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1246 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0x00
1247 
1248 /* Bit definitions for LDO2_VOLTAGE */
1249 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3F
1250 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0x00
1251 
1252 /* Bit definitions for LDO3_CTRL */
1253 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1254 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             0x07
1255 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1256 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           0x04
1257 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1258 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       0x02
1259 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1260 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0x00
1261 
1262 /* Bit definitions for LDO3_VOLTAGE */
1263 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3F
1264 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0x00
1265 
1266 /* Bit definitions for LDO4_CTRL */
1267 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1268 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             0x07
1269 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1270 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           0x04
1271 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1272 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       0x02
1273 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1274 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0x00
1275 
1276 /* Bit definitions for LDO4_VOLTAGE */
1277 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3F
1278 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0x00
1279 
1280 /* Bit definitions for LDO5_CTRL */
1281 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1282 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             0x07
1283 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1284 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           0x04
1285 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1286 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       0x02
1287 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1288 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0x00
1289 
1290 /* Bit definitions for LDO5_VOLTAGE */
1291 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3F
1292 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0x00
1293 
1294 /* Bit definitions for LDO6_CTRL */
1295 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1296 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             0x07
1297 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1298 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       0x06
1299 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1300 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           0x04
1301 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1302 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       0x02
1303 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1304 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0x00
1305 
1306 /* Bit definitions for LDO6_VOLTAGE */
1307 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3F
1308 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0x00
1309 
1310 /* Bit definitions for LDO7_CTRL */
1311 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1312 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             0x07
1313 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1314 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           0x04
1315 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1316 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       0x02
1317 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1318 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0x00
1319 
1320 /* Bit definitions for LDO7_VOLTAGE */
1321 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3F
1322 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0x00
1323 
1324 /* Bit definitions for LDO8_CTRL */
1325 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1326 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             0x07
1327 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1328 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  0x06
1329 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1330 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           0x04
1331 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1332 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       0x02
1333 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1334 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0x00
1335 
1336 /* Bit definitions for LDO8_VOLTAGE */
1337 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3F
1338 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0x00
1339 
1340 /* Bit definitions for LDO9_CTRL */
1341 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1342 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             0x07
1343 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1344 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    0x06
1345 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1346 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           0x04
1347 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1348 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       0x02
1349 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1350 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0x00
1351 
1352 /* Bit definitions for LDO9_VOLTAGE */
1353 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3F
1354 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0x00
1355 
1356 /* Bit definitions for LDOLN_CTRL */
1357 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1358 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            0x07
1359 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1360 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          0x04
1361 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1362 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      0x02
1363 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1364 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0x00
1365 
1366 /* Bit definitions for LDOLN_VOLTAGE */
1367 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3F
1368 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0x00
1369 
1370 /* Bit definitions for LDOUSB_CTRL */
1371 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1372 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           0x07
1373 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1374 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         0x04
1375 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1376 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     0x02
1377 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1378 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0x00
1379 
1380 /* Bit definitions for LDOUSB_VOLTAGE */
1381 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3F
1382 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0x00
1383 
1384 /* Bit definitions for LDO_CTRL */
1385 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1386 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0x00
1387 
1388 /* Bit definitions for LDO_PD_CTRL1 */
1389 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1390 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          0x07
1391 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1392 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          0x06
1393 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1394 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          0x05
1395 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1396 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          0x04
1397 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1398 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          0x03
1399 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1400 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          0x02
1401 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1402 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          0x01
1403 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1404 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0x00
1405 
1406 /* Bit definitions for LDO_PD_CTRL2 */
1407 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1408 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        0x02
1409 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1410 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         0x01
1411 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1412 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0x00
1413 
1414 /* Bit definitions for LDO_SHORT_STATUS1 */
1415 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1416 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     0x07
1417 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1418 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     0x06
1419 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1420 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     0x05
1421 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1422 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     0x04
1423 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1424 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     0x03
1425 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1426 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     0x02
1427 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1428 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     0x01
1429 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1430 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0x00
1431 
1432 /* Bit definitions for LDO_SHORT_STATUS2 */
1433 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1434 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  0x03
1435 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1436 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   0x02
1437 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1438 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    0x01
1439 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1440 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0x00
1441 
1442 /* Registers for function PMU_CONTROL */
1443 #define PALMAS_DEV_CTRL                                         0x00
1444 #define PALMAS_POWER_CTRL                                       0x01
1445 #define PALMAS_VSYS_LO                                          0x02
1446 #define PALMAS_VSYS_MON                                         0x03
1447 #define PALMAS_VBAT_MON                                         0x04
1448 #define PALMAS_WATCHDOG                                         0x05
1449 #define PALMAS_BOOT_STATUS                                      0x06
1450 #define PALMAS_BATTERY_BOUNCE                                   0x07
1451 #define PALMAS_BACKUP_BATTERY_CTRL                              0x08
1452 #define PALMAS_LONG_PRESS_KEY                                   0x09
1453 #define PALMAS_OSC_THERM_CTRL                                   0x0A
1454 #define PALMAS_BATDEBOUNCING                                    0x0B
1455 #define PALMAS_SWOFF_HWRST                                      0x0F
1456 #define PALMAS_SWOFF_COLDRST                                    0x10
1457 #define PALMAS_SWOFF_STATUS                                     0x11
1458 #define PALMAS_PMU_CONFIG                                       0x12
1459 #define PALMAS_SPARE                                            0x14
1460 #define PALMAS_PMU_SECONDARY_INT                                0x15
1461 #define PALMAS_SW_REVISION                                      0x17
1462 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1463 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1464 
1465 /* Bit definitions for DEV_CTRL */
1466 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1467 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        0x02
1468 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1469 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            0x01
1470 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1471 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0x00
1472 
1473 /* Bit definitions for POWER_CTRL */
1474 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1475 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    0x02
1476 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1477 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    0x01
1478 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1479 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0x00
1480 
1481 /* Bit definitions for VSYS_LO */
1482 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1F
1483 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0x00
1484 
1485 /* Bit definitions for VSYS_MON */
1486 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1487 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            0x07
1488 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3F
1489 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0x00
1490 
1491 /* Bit definitions for VBAT_MON */
1492 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1493 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            0x07
1494 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3F
1495 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0x00
1496 
1497 /* Bit definitions for WATCHDOG */
1498 #define PALMAS_WATCHDOG_LOCK                                    0x20
1499 #define PALMAS_WATCHDOG_LOCK_SHIFT                              0x05
1500 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1501 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            0x04
1502 #define PALMAS_WATCHDOG_MODE                                    0x08
1503 #define PALMAS_WATCHDOG_MODE_SHIFT                              0x03
1504 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1505 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0x00
1506 
1507 /* Bit definitions for BOOT_STATUS */
1508 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1509 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          0x01
1510 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1511 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0x00
1512 
1513 /* Bit definitions for BATTERY_BOUNCE */
1514 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3F
1515 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0x00
1516 
1517 /* Bit definitions for BACKUP_BATTERY_CTRL */
1518 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1519 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             0x07
1520 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1521 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            0x06
1522 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1523 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            0x05
1524 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1525 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              0x04
1526 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1527 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      0x03
1528 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1529 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 0x01
1530 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1531 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0x00
1532 
1533 /* Bit definitions for LONG_PRESS_KEY */
1534 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1535 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    0x07
1536 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1537 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 0x04
1538 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1539 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    0x02
1540 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1541 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0x00
1542 
1543 /* Bit definitions for OSC_THERM_CTRL */
1544 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1545 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            0x07
1546 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1547 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           0x06
1548 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1549 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         0x05
1550 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1551 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          0x04
1552 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1553 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                0x02
1554 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1555 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  0x01
1556 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1557 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0x00
1558 
1559 /* Bit definitions for BATDEBOUNCING */
1560 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1561 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               0x07
1562 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1563 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     0x03
1564 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1565 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0x00
1566 
1567 /* Bit definitions for SWOFF_HWRST */
1568 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1569 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      0x07
1570 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1571 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        0x06
1572 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1573 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            0x05
1574 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1575 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          0x04
1576 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1577 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       0x03
1578 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1579 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         0x02
1580 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1581 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        0x01
1582 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1583 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0x00
1584 
1585 /* Bit definitions for SWOFF_COLDRST */
1586 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1587 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    0x07
1588 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1589 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      0x06
1590 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1591 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          0x05
1592 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1593 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        0x04
1594 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1595 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     0x03
1596 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1597 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       0x02
1598 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1599 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      0x01
1600 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1601 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0x00
1602 
1603 /* Bit definitions for SWOFF_STATUS */
1604 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1605 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     0x07
1606 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1607 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       0x06
1608 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1609 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           0x05
1610 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1611 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         0x04
1612 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1613 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      0x03
1614 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1615 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        0x02
1616 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1617 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       0x01
1618 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1619 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0x00
1620 
1621 /* Bit definitions for PMU_CONFIG */
1622 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1623 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   0x06
1624 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1625 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           0x04
1626 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1627 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       0x02
1628 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1629 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  0x01
1630 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1631 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0x00
1632 
1633 /* Bit definitions for SPARE */
1634 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1635 #define PALMAS_SPARE_SPARE_SHIFT                                0x03
1636 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1637 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            0x02
1638 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1639 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            0x01
1640 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1641 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0x00
1642 
1643 /* Bit definitions for PMU_SECONDARY_INT */
1644 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1645 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         0x07
1646 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1647 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      0x06
1648 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1649 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               0x05
1650 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1651 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              0x04
1652 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1653 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            0x03
1654 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1655 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         0x02
1656 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1657 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  0x01
1658 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1659 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0x00
1660 
1661 /* Bit definitions for SW_REVISION */
1662 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xFF
1663 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0x00
1664 
1665 /* Bit definitions for EXT_CHRG_CTRL */
1666 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1667 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              0x07
1668 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1669 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           0x06
1670 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1671 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          0x03
1672 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1673 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   0x02
1674 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1675 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  0x01
1676 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1677 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0x00
1678 
1679 /* Bit definitions for PMU_SECONDARY_INT2 */
1680 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1681 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           0x05
1682 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1683 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           0x04
1684 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1685 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              0x01
1686 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1687 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0x00
1688 
1689 /* Registers for function RESOURCE */
1690 #define PALMAS_CLK32KG_CTRL                                     0x00
1691 #define PALMAS_CLK32KGAUDIO_CTRL                                0x01
1692 #define PALMAS_REGEN1_CTRL                                      0x02
1693 #define PALMAS_REGEN2_CTRL                                      0x03
1694 #define PALMAS_SYSEN1_CTRL                                      0x04
1695 #define PALMAS_SYSEN2_CTRL                                      0x05
1696 #define PALMAS_NSLEEP_RES_ASSIGN                                0x06
1697 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x07
1698 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x08
1699 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x09
1700 #define PALMAS_ENABLE1_RES_ASSIGN                               0x0A
1701 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0x0B
1702 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0x0C
1703 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0x0D
1704 #define PALMAS_ENABLE2_RES_ASSIGN                               0x0E
1705 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0x0F
1706 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1707 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1708 #define PALMAS_REGEN3_CTRL                                      0x12
1709 
1710 /* Bit definitions for CLK32KG_CTRL */
1711 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1712 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        0x04
1713 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1714 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    0x02
1715 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1716 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0x00
1717 
1718 /* Bit definitions for CLK32KGAUDIO_CTRL */
1719 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1720 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   0x04
1721 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1722 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                0x03
1723 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1724 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               0x02
1725 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1726 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0x00
1727 
1728 /* Bit definitions for REGEN1_CTRL */
1729 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1730 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         0x04
1731 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1732 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     0x02
1733 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1734 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0x00
1735 
1736 /* Bit definitions for REGEN2_CTRL */
1737 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1738 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         0x04
1739 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1740 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     0x02
1741 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1742 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0x00
1743 
1744 /* Bit definitions for SYSEN1_CTRL */
1745 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1746 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         0x04
1747 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1748 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     0x02
1749 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1750 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0x00
1751 
1752 /* Bit definitions for SYSEN2_CTRL */
1753 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1754 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         0x04
1755 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1756 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     0x02
1757 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1758 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0x00
1759 
1760 /* Bit definitions for NSLEEP_RES_ASSIGN */
1761 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1762 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   0x06
1763 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1764 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             0x05
1765 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1766 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  0x04
1767 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1768 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   0x03
1769 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1770 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   0x02
1771 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1772 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   0x01
1773 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1774 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0x00
1775 
1776 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1778 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  0x07
1779 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1780 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   0x06
1781 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1782 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   0x05
1783 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1784 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   0x04
1785 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1786 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   0x03
1787 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1788 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  0x02
1789 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1790 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   0x01
1791 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1792 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0x00
1793 
1794 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1796 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    0x07
1797 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1798 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    0x06
1799 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1800 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    0x05
1801 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1802 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    0x04
1803 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1804 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    0x03
1805 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1806 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    0x02
1807 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1808 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    0x01
1809 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1810 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0x00
1811 
1812 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1813 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1814 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  0x02
1815 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1816 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   0x01
1817 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1818 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0x00
1819 
1820 /* Bit definitions for ENABLE1_RES_ASSIGN */
1821 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1822 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  0x06
1823 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1824 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            0x05
1825 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1826 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 0x04
1827 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1828 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  0x03
1829 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1830 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  0x02
1831 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1832 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  0x01
1833 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1834 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0x00
1835 
1836 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1838 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 0x07
1839 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1840 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  0x06
1841 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1842 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  0x05
1843 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1844 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  0x04
1845 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1846 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  0x03
1847 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1848 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 0x02
1849 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1850 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  0x01
1851 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1852 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0x00
1853 
1854 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1856 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   0x07
1857 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1858 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   0x06
1859 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1860 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   0x05
1861 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1862 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   0x04
1863 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1864 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   0x03
1865 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1866 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   0x02
1867 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1868 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   0x01
1869 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1870 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0x00
1871 
1872 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1873 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1874 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 0x02
1875 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1876 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  0x01
1877 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1878 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0x00
1879 
1880 /* Bit definitions for ENABLE2_RES_ASSIGN */
1881 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1882 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  0x06
1883 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1884 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            0x05
1885 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1886 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 0x04
1887 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1888 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  0x03
1889 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1890 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  0x02
1891 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1892 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  0x01
1893 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1894 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0x00
1895 
1896 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1898 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 0x07
1899 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1900 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  0x06
1901 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1902 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  0x05
1903 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1904 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  0x04
1905 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1906 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  0x03
1907 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1908 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 0x02
1909 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1910 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  0x01
1911 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1912 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0x00
1913 
1914 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1916 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   0x07
1917 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1918 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   0x06
1919 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1920 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   0x05
1921 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1922 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   0x04
1923 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1924 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   0x03
1925 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1926 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   0x02
1927 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1928 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   0x01
1929 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1930 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0x00
1931 
1932 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1933 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1934 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 0x02
1935 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1936 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  0x01
1937 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1938 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0x00
1939 
1940 /* Bit definitions for REGEN3_CTRL */
1941 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1942 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         0x04
1943 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1944 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     0x02
1945 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1946 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0x00
1947 
1948 /* Registers for function PAD_CONTROL */
1949 #define PALMAS_OD_OUTPUT_CTRL2                                  0x02
1950 #define PALMAS_POLARITY_CTRL2                                   0x03
1951 #define PALMAS_PU_PD_INPUT_CTRL1                                0x04
1952 #define PALMAS_PU_PD_INPUT_CTRL2                                0x05
1953 #define PALMAS_PU_PD_INPUT_CTRL3                                0x06
1954 #define PALMAS_PU_PD_INPUT_CTRL5                                0x07
1955 #define PALMAS_OD_OUTPUT_CTRL                                   0x08
1956 #define PALMAS_POLARITY_CTRL                                    0x09
1957 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x0A
1958 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x0B
1959 #define PALMAS_I2C_SPI                                          0x0C
1960 #define PALMAS_PU_PD_INPUT_CTRL4                                0x0D
1961 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0x0E
1962 #define PALMAS_PRIMARY_SECONDARY_PAD4                           0x0F
1963 
1964 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1965 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1966 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              0x06
1967 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1968 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           0x05
1969 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1970 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           0x04
1971 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1972 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               0x02
1973 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1974 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              0x01
1975 
1976 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1977 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1978 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               0x05
1979 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1980 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               0x04
1981 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1982 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               0x03
1983 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1984 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               0x02
1985 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1986 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                0x01
1987 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1988 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0x00
1989 
1990 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1991 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1992 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  0x06
1993 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1994 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            0x04
1995 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1996 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             0x02
1997 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1998 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0x00
1999 
2000 /* Bit definitions for OD_OUTPUT_CTRL */
2001 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
2002 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    0x07
2003 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
2004 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  0x06
2005 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
2006 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    0x05
2007 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
2008 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      0x03
2009 
2010 /* Bit definitions for POLARITY_CTRL */
2011 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
2012 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 0x07
2013 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
2014 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             0x06
2015 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
2016 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             0x05
2017 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
2018 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              0x04
2019 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
2020 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            0x03
2021 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
2022 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   0x02
2023 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
2024 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  0x01
2025 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
2026 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0x00
2027 
2028 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2029 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
2030 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              0x07
2031 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
2032 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              0x05
2033 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
2034 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              0x03
2035 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
2036 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              0x02
2037 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
2038 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 0x01
2039 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
2040 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0x00
2041 
2042 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2043 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
2044 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              0x04
2045 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
2046 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              0x03
2047 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
2048 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              0x01
2049 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
2050 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0x00
2051 
2052 /* Bit definitions for I2C_SPI */
2053 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
2054 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         0x07
2055 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
2056 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    0x06
2057 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
2058 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            0x05
2059 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
2060 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            0x04
2061 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0F
2062 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0x00
2063 
2064 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2065 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
2066 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             0x06
2067 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
2068 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             0x04
2069 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
2070 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             0x02
2071 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
2072 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0x00
2073 
2074 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2075 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
2076 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               0x01
2077 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
2078 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0x00
2079 
2080 /* Registers for function LED_PWM */
2081 #define PALMAS_LED_PERIOD_CTRL                                  0x00
2082 #define PALMAS_LED_CTRL                                         0x01
2083 #define PALMAS_PWM_CTRL1                                        0x02
2084 #define PALMAS_PWM_CTRL2                                        0x03
2085 
2086 /* Bit definitions for LED_PERIOD_CTRL */
2087 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
2088 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               0x03
2089 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
2090 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0x00
2091 
2092 /* Bit definitions for LED_CTRL */
2093 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
2094 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         0x05
2095 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
2096 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         0x04
2097 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
2098 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     0x02
2099 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
2100 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0x00
2101 
2102 /* Bit definitions for PWM_CTRL1 */
2103 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
2104 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      0x01
2105 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
2106 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0x00
2107 
2108 /* Bit definitions for PWM_CTRL2 */
2109 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xFF
2110 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0x00
2111 
2112 /* Registers for function INTERRUPT */
2113 #define PALMAS_INT1_STATUS                                      0x00
2114 #define PALMAS_INT1_MASK                                        0x01
2115 #define PALMAS_INT1_LINE_STATE                                  0x02
2116 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x03
2117 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x04
2118 #define PALMAS_INT2_STATUS                                      0x05
2119 #define PALMAS_INT2_MASK                                        0x06
2120 #define PALMAS_INT2_LINE_STATE                                  0x07
2121 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x08
2122 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x09
2123 #define PALMAS_INT3_STATUS                                      0x0A
2124 #define PALMAS_INT3_MASK                                        0x0B
2125 #define PALMAS_INT3_LINE_STATE                                  0x0C
2126 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0x0D
2127 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0x0E
2128 #define PALMAS_INT4_STATUS                                      0x0F
2129 #define PALMAS_INT4_MASK                                        0x10
2130 #define PALMAS_INT4_LINE_STATE                                  0x11
2131 #define PALMAS_INT4_EDGE_DETECT1                                0x12
2132 #define PALMAS_INT4_EDGE_DETECT2                                0x13
2133 #define PALMAS_INT_CTRL                                         0x14
2134 
2135 /* Bit definitions for INT1_STATUS */
2136 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
2137 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       0x07
2138 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
2139 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       0x06
2140 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
2141 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         0x05
2142 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
2143 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        0x04
2144 #define PALMAS_INT1_STATUS_RPWRON                               0x08
2145 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         0x03
2146 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
2147 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 0x02
2148 #define PALMAS_INT1_STATUS_PWRON                                0x02
2149 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          0x01
2150 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
2151 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0x00
2152 
2153 /* Bit definitions for INT1_MASK */
2154 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
2155 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         0x07
2156 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
2157 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         0x06
2158 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
2159 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           0x05
2160 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
2161 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          0x04
2162 #define PALMAS_INT1_MASK_RPWRON                                 0x08
2163 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           0x03
2164 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
2165 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   0x02
2166 #define PALMAS_INT1_MASK_PWRON                                  0x02
2167 #define PALMAS_INT1_MASK_PWRON_SHIFT                            0x01
2168 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
2169 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0x00
2170 
2171 /* Bit definitions for INT1_LINE_STATE */
2172 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
2173 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   0x07
2174 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
2175 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   0x06
2176 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
2177 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     0x05
2178 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
2179 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    0x04
2180 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
2181 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     0x03
2182 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
2183 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             0x02
2184 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
2185 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      0x01
2186 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
2187 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0x00
2188 
2189 /* Bit definitions for INT2_STATUS */
2190 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
2191 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       0x07
2192 #define PALMAS_INT2_STATUS_SHORT                                0x40
2193 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          0x06
2194 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
2195 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         0x05
2196 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
2197 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       0x04
2198 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
2199 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     0x03
2200 #define PALMAS_INT2_STATUS_WDT                                  0x04
2201 #define PALMAS_INT2_STATUS_WDT_SHIFT                            0x02
2202 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
2203 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      0x01
2204 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
2205 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0x00
2206 
2207 /* Bit definitions for INT2_MASK */
2208 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
2209 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         0x07
2210 #define PALMAS_INT2_MASK_SHORT                                  0x40
2211 #define PALMAS_INT2_MASK_SHORT_SHIFT                            0x06
2212 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
2213 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           0x05
2214 #define PALMAS_INT2_MASK_RESET_IN                               0x10
2215 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         0x04
2216 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
2217 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       0x03
2218 #define PALMAS_INT2_MASK_WDT                                    0x04
2219 #define PALMAS_INT2_MASK_WDT_SHIFT                              0x02
2220 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
2221 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        0x01
2222 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
2223 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0x00
2224 
2225 /* Bit definitions for INT2_LINE_STATE */
2226 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
2227 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   0x07
2228 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
2229 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      0x06
2230 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
2231 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     0x05
2232 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
2233 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   0x04
2234 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
2235 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 0x03
2236 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
2237 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        0x02
2238 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
2239 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  0x01
2240 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
2241 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0x00
2242 
2243 /* Bit definitions for INT3_STATUS */
2244 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2245 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           0x07
2246 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2247 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       0x06
2248 #define PALMAS_INT3_STATUS_ID                                   0x20
2249 #define PALMAS_INT3_STATUS_ID_SHIFT                             0x05
2250 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2251 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         0x04
2252 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2253 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   0x03
2254 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2255 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   0x02
2256 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2257 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   0x01
2258 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2259 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0x00
2260 
2261 /* Bit definitions for INT3_MASK */
2262 #define PALMAS_INT3_MASK_VBUS                                   0x80
2263 #define PALMAS_INT3_MASK_VBUS_SHIFT                             0x07
2264 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2265 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         0x06
2266 #define PALMAS_INT3_MASK_ID                                     0x20
2267 #define PALMAS_INT3_MASK_ID_SHIFT                               0x05
2268 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2269 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           0x04
2270 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2271 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     0x03
2272 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2273 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     0x02
2274 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2275 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     0x01
2276 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2277 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0x00
2278 
2279 /* Bit definitions for INT3_LINE_STATE */
2280 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2281 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       0x07
2282 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2283 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   0x06
2284 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2285 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         0x05
2286 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2287 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     0x04
2288 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2289 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               0x03
2290 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2291 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               0x02
2292 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2293 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               0x01
2294 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2295 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0x00
2296 
2297 /* Bit definitions for INT4_STATUS */
2298 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2299 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         0x07
2300 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2301 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         0x06
2302 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2303 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         0x05
2304 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2305 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         0x04
2306 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2307 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         0x03
2308 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2309 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         0x02
2310 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2311 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         0x01
2312 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2313 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0x00
2314 
2315 /* Bit definitions for INT4_MASK */
2316 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2317 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           0x07
2318 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2319 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           0x06
2320 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2321 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           0x05
2322 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2323 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           0x04
2324 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2325 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           0x03
2326 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2327 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           0x02
2328 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2329 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           0x01
2330 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2331 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0x00
2332 
2333 /* Bit definitions for INT4_LINE_STATE */
2334 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2335 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     0x07
2336 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2337 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     0x06
2338 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2339 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     0x05
2340 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2341 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     0x04
2342 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2343 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     0x03
2344 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2345 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     0x02
2346 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2347 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     0x01
2348 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2349 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0x00
2350 
2351 /* Bit definitions for INT4_EDGE_DETECT1 */
2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2353 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            0x07
2354 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2355 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           0x06
2356 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2357 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            0x05
2358 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2359 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           0x04
2360 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2361 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            0x03
2362 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2363 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           0x02
2364 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2365 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            0x01
2366 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2367 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0x00
2368 
2369 /* Bit definitions for INT4_EDGE_DETECT2 */
2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2371 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            0x07
2372 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2373 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           0x06
2374 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2375 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            0x05
2376 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2377 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           0x04
2378 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2379 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            0x03
2380 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2381 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           0x02
2382 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2383 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            0x01
2384 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2385 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0x00
2386 
2387 /* Bit definitions for INT_CTRL */
2388 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2389 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       0x02
2390 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2391 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0x00
2392 
2393 /* Registers for function USB_OTG */
2394 #define PALMAS_USB_WAKEUP                                       0x03
2395 #define PALMAS_USB_VBUS_CTRL_SET                                0x04
2396 #define PALMAS_USB_VBUS_CTRL_CLR                                0x05
2397 #define PALMAS_USB_ID_CTRL_SET                                  0x06
2398 #define PALMAS_USB_ID_CTRL_CLEAR                                0x07
2399 #define PALMAS_USB_VBUS_INT_SRC                                 0x08
2400 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x09
2401 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0x0A
2402 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0x0B
2403 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0x0C
2404 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0x0D
2405 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0x0E
2406 #define PALMAS_USB_ID_INT_SRC                                   0x0F
2407 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2408 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2409 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2410 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2411 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2412 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2413 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2414 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2415 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2416 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2417 #define PALMAS_USB_OTG_REVISION                                 0x1A
2418 
2419 /* Bit definitions for USB_WAKEUP */
2420 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2421 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0x00
2422 
2423 /* Bit definitions for USB_VBUS_CTRL_SET */
2424 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2425 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           0x07
2426 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2427 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             0x05
2428 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2429 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            0x04
2430 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2431 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           0x03
2432 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2433 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            0x02
2434 
2435 /* Bit definitions for USB_VBUS_CTRL_CLR */
2436 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2437 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           0x07
2438 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2439 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             0x05
2440 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2441 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            0x04
2442 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2443 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           0x03
2444 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2445 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            0x02
2446 
2447 /* Bit definitions for USB_ID_CTRL_SET */
2448 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2449 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 0x07
2450 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2451 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 0x06
2452 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2453 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 0x05
2454 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2455 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 0x04
2456 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2457 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  0x03
2458 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2459 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                0x02
2460 
2461 /* Bit definitions for USB_ID_CTRL_CLEAR */
2462 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2463 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               0x07
2464 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2465 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               0x06
2466 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2467 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               0x05
2468 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2469 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               0x04
2470 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2471 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                0x03
2472 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2473 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              0x02
2474 
2475 /* Bit definitions for USB_VBUS_INT_SRC */
2476 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2477 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             0x07
2478 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2479 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  0x06
2480 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2481 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  0x05
2482 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2483 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               0x03
2484 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2485 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               0x02
2486 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2487 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               0x01
2488 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2489 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0x00
2490 
2491 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2493 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       0x07
2494 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2495 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            0x06
2496 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2497 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            0x05
2498 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2499 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 0x04
2500 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2501 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         0x03
2502 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2503 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         0x02
2504 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2505 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         0x01
2506 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2507 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0x00
2508 
2509 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2511 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       0x07
2512 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2513 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            0x06
2514 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2515 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            0x05
2516 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2517 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 0x04
2518 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2519 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         0x03
2520 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2521 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         0x02
2522 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2523 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         0x01
2524 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2525 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0x00
2526 
2527 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2528 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2529 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       0x07
2530 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2531 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            0x06
2532 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2533 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            0x05
2534 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2535 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         0x03
2536 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2537 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         0x02
2538 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2539 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         0x01
2540 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2541 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0x00
2542 
2543 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2544 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2545 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       0x07
2546 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2547 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            0x06
2548 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2549 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            0x05
2550 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2551 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         0x03
2552 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2553 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         0x02
2554 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2555 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         0x01
2556 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2557 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0x00
2558 
2559 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2561 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       0x07
2562 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2563 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            0x06
2564 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2565 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            0x05
2566 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2567 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 0x04
2568 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2569 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         0x03
2570 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2571 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         0x02
2572 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2573 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         0x01
2574 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2575 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0x00
2576 
2577 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2579 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       0x07
2580 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2581 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            0x06
2582 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2583 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            0x05
2584 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2585 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 0x04
2586 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2587 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         0x03
2588 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2589 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         0x02
2590 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2591 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         0x01
2592 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2593 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0x00
2594 
2595 /* Bit definitions for USB_ID_INT_SRC */
2596 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2597 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    0x04
2598 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2599 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        0x03
2600 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2601 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        0x02
2602 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2603 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        0x01
2604 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2605 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0x00
2606 
2607 /* Bit definitions for USB_ID_INT_LATCH_SET */
2608 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2609 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              0x04
2610 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2611 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  0x03
2612 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2613 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  0x02
2614 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2615 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  0x01
2616 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2617 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0x00
2618 
2619 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2620 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2621 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              0x04
2622 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2623 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  0x03
2624 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2625 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  0x02
2626 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2627 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  0x01
2628 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2629 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0x00
2630 
2631 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2632 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2633 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              0x04
2634 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2635 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  0x03
2636 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2637 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  0x02
2638 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2639 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  0x01
2640 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2641 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0x00
2642 
2643 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2644 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2645 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              0x04
2646 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2647 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  0x03
2648 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2649 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  0x02
2650 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2651 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  0x01
2652 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2653 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0x00
2654 
2655 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2656 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2657 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              0x04
2658 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2659 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  0x03
2660 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2661 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  0x02
2662 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2663 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  0x01
2664 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2665 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0x00
2666 
2667 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2668 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2669 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              0x04
2670 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2671 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  0x03
2672 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2673 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  0x02
2674 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2675 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  0x01
2676 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2677 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0x00
2678 
2679 /* Bit definitions for USB_OTG_ADP_CTRL */
2680 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2681 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    0x02
2682 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2683 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0x00
2684 
2685 /* Bit definitions for USB_OTG_ADP_HIGH */
2686 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xFF
2687 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0x00
2688 
2689 /* Bit definitions for USB_OTG_ADP_LOW */
2690 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xFF
2691 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0x00
2692 
2693 /* Bit definitions for USB_OTG_ADP_RISE */
2694 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xFF
2695 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0x00
2696 
2697 /* Bit definitions for USB_OTG_REVISION */
2698 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2699 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0x00
2700 
2701 /* Registers for function VIBRATOR */
2702 #define PALMAS_VIBRA_CTRL                                       0x00
2703 
2704 /* Bit definitions for VIBRA_CTRL */
2705 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2706 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    0x01
2707 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2708 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0x00
2709 
2710 /* Registers for function GPIO */
2711 #define PALMAS_GPIO_DATA_IN                                     0x00
2712 #define PALMAS_GPIO_DATA_DIR                                    0x01
2713 #define PALMAS_GPIO_DATA_OUT                                    0x02
2714 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x03
2715 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x04
2716 #define PALMAS_GPIO_SET_DATA_OUT                                0x05
2717 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x06
2718 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x07
2719 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x08
2720 #define PALMAS_GPIO_DATA_IN2                                    0x09
2721 #define PALMAS_GPIO_DATA_DIR2                                   0x0A
2722 #define PALMAS_GPIO_DATA_OUT2                                   0x0B
2723 #define PALMAS_GPIO_DEBOUNCE_EN2                                0x0C
2724 #define PALMAS_GPIO_CLEAR_DATA_OUT2                             0x0D
2725 #define PALMAS_GPIO_SET_DATA_OUT2                               0x0E
2726 #define PALMAS_PU_PD_GPIO_CTRL3                                 0x0F
2727 #define PALMAS_PU_PD_GPIO_CTRL4                                 0x10
2728 #define PALMAS_OD_OUTPUT_GPIO_CTRL2                             0x11
2729 
2730 /* Bit definitions for GPIO_DATA_IN */
2731 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2732 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     0x07
2733 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2734 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     0x06
2735 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2736 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     0x05
2737 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2738 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     0x04
2739 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2740 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     0x03
2741 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2742 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     0x02
2743 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2744 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     0x01
2745 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2746 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0x00
2747 
2748 /* Bit definitions for GPIO_DATA_DIR */
2749 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2750 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   0x07
2751 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2752 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   0x06
2753 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2754 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   0x05
2755 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2756 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   0x04
2757 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2758 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   0x03
2759 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2760 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   0x02
2761 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2762 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   0x01
2763 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2764 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0x00
2765 
2766 /* Bit definitions for GPIO_DATA_OUT */
2767 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2768 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   0x07
2769 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2770 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   0x06
2771 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2772 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   0x05
2773 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2774 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   0x04
2775 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2776 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   0x03
2777 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2778 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   0x02
2779 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2780 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   0x01
2781 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2782 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0x00
2783 
2784 /* Bit definitions for GPIO_DEBOUNCE_EN */
2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2786 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        0x07
2787 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2788 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        0x06
2789 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2790 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        0x05
2791 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2792 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        0x04
2793 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2794 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        0x03
2795 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2796 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        0x02
2797 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2798 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        0x01
2799 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2800 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0x00
2801 
2802 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2804 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  0x07
2805 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2806 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  0x06
2807 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2808 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  0x05
2809 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2810 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  0x04
2811 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2812 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  0x03
2813 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2814 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  0x02
2815 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2816 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  0x01
2817 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2818 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0x00
2819 
2820 /* Bit definitions for GPIO_SET_DATA_OUT */
2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2822 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      0x07
2823 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2824 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      0x06
2825 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2826 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      0x05
2827 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2828 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      0x04
2829 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2830 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      0x03
2831 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2832 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      0x02
2833 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2834 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      0x01
2835 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2836 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0x00
2837 
2838 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2839 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2840 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 0x06
2841 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2842 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 0x05
2843 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2844 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 0x04
2845 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2846 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 0x03
2847 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2848 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 0x02
2849 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2850 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0x00
2851 
2852 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2853 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2854 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 0x06
2855 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2856 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 0x05
2857 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2858 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 0x04
2859 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2860 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 0x03
2861 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2862 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 0x02
2863 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2864 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 0x01
2865 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2866 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0x00
2867 
2868 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2869 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2870 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              0x05
2871 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2872 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              0x02
2873 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2874 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              0x01
2875 
2876 /* Registers for function GPADC */
2877 #define PALMAS_GPADC_CTRL1                                      0x00
2878 #define PALMAS_GPADC_CTRL2                                      0x01
2879 #define PALMAS_GPADC_RT_CTRL                                    0x02
2880 #define PALMAS_GPADC_AUTO_CTRL                                  0x03
2881 #define PALMAS_GPADC_STATUS                                     0x04
2882 #define PALMAS_GPADC_RT_SELECT                                  0x05
2883 #define PALMAS_GPADC_RT_CONV0_LSB                               0x06
2884 #define PALMAS_GPADC_RT_CONV0_MSB                               0x07
2885 #define PALMAS_GPADC_AUTO_SELECT                                0x08
2886 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x09
2887 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0x0A
2888 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0x0B
2889 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0x0C
2890 #define PALMAS_GPADC_SW_SELECT                                  0x0D
2891 #define PALMAS_GPADC_SW_CONV0_LSB                               0x0E
2892 #define PALMAS_GPADC_SW_CONV0_MSB                               0x0F
2893 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2894 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2895 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2896 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2897 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2898 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2899 
2900 /* Bit definitions for GPADC_CTRL1 */
2901 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2902 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       0x06
2903 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2904 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                0x04
2905 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2906 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                0x02
2907 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2908 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                0x01
2909 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2910 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0x00
2911 
2912 /* Bit definitions for GPADC_CTRL2 */
2913 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2914 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       0x01
2915 
2916 /* Bit definitions for GPADC_RT_CTRL */
2917 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2918 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 0x01
2919 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2920 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0x00
2921 
2922 /* Bit definitions for GPADC_AUTO_CTRL */
2923 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2924 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             0x07
2925 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2926 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             0x06
2927 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2928 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              0x05
2929 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2930 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              0x04
2931 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0F
2932 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0x00
2933 
2934 /* Bit definitions for GPADC_STATUS */
2935 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2936 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               0x04
2937 
2938 /* Bit definitions for GPADC_RT_SELECT */
2939 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2940 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 0x07
2941 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0F
2942 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0x00
2943 
2944 /* Bit definitions for GPADC_RT_CONV0_LSB */
2945 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xFF
2946 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0x00
2947 
2948 /* Bit definitions for GPADC_RT_CONV0_MSB */
2949 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0F
2950 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0x00
2951 
2952 /* Bit definitions for GPADC_AUTO_SELECT */
2953 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xF0
2954 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           0x04
2955 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0F
2956 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0x00
2957 
2958 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2959 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xFF
2960 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0x00
2961 
2962 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2963 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0F
2964 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0x00
2965 
2966 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2967 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xFF
2968 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0x00
2969 
2970 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2971 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0F
2972 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0x00
2973 
2974 /* Bit definitions for GPADC_SW_SELECT */
2975 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2976 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 0x07
2977 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2978 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             0x04
2979 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0F
2980 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0x00
2981 
2982 /* Bit definitions for GPADC_SW_CONV0_LSB */
2983 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xFF
2984 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0x00
2985 
2986 /* Bit definitions for GPADC_SW_CONV0_MSB */
2987 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0F
2988 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0x00
2989 
2990 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2991 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xFF
2992 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0x00
2993 
2994 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2995 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2996 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      0x07
2997 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0F
2998 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0x00
2999 
3000 /* Bit definitions for GPADC_THRES_CONV1_LSB */
3001 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xFF
3002 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0x00
3003 
3004 /* Bit definitions for GPADC_THRES_CONV1_MSB */
3005 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
3006 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      0x07
3007 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0F
3008 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0x00
3009 
3010 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
3011 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
3012 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      0x05
3013 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
3014 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    0x04
3015 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0F
3016 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0x00
3017 
3018 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3019 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
3020 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    0x07
3021 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7F
3022 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0x00
3023 
3024 /* Registers for function GPADC */
3025 #define PALMAS_GPADC_TRIM1                                      0x00
3026 #define PALMAS_GPADC_TRIM2                                      0x01
3027 #define PALMAS_GPADC_TRIM3                                      0x02
3028 #define PALMAS_GPADC_TRIM4                                      0x03
3029 #define PALMAS_GPADC_TRIM5                                      0x04
3030 #define PALMAS_GPADC_TRIM6                                      0x05
3031 #define PALMAS_GPADC_TRIM7                                      0x06
3032 #define PALMAS_GPADC_TRIM8                                      0x07
3033 #define PALMAS_GPADC_TRIM9                                      0x08
3034 #define PALMAS_GPADC_TRIM10                                     0x09
3035 #define PALMAS_GPADC_TRIM11                                     0x0A
3036 #define PALMAS_GPADC_TRIM12                                     0x0B
3037 #define PALMAS_GPADC_TRIM13                                     0x0C
3038 #define PALMAS_GPADC_TRIM14                                     0x0D
3039 #define PALMAS_GPADC_TRIM15                                     0x0E
3040 #define PALMAS_GPADC_TRIM16                                     0x0F
3041 
3042 /* TPS659038 regen2_ctrl offset iss different from palmas */
3043 #define TPS659038_REGEN2_CTRL                                   0x12
3044 
3045 /* TPS65917 Interrupt registers */
3046 
3047 /* Registers for function INTERRUPT */
3048 #define TPS65917_INT1_STATUS                                    0x00
3049 #define TPS65917_INT1_MASK                                      0x01
3050 #define TPS65917_INT1_LINE_STATE                                0x02
3051 #define TPS65917_INT2_STATUS                                    0x05
3052 #define TPS65917_INT2_MASK                                      0x06
3053 #define TPS65917_INT2_LINE_STATE                                0x07
3054 #define TPS65917_INT3_STATUS                                    0x0A
3055 #define TPS65917_INT3_MASK                                      0x0B
3056 #define TPS65917_INT3_LINE_STATE                                0x0C
3057 #define TPS65917_INT4_STATUS                                    0x0F
3058 #define TPS65917_INT4_MASK                                      0x10
3059 #define TPS65917_INT4_LINE_STATE                                0x11
3060 #define TPS65917_INT4_EDGE_DETECT1                              0x12
3061 #define TPS65917_INT4_EDGE_DETECT2                              0x13
3062 #define TPS65917_INT_CTRL                                       0x14
3063 
3064 /* Bit definitions for INT1_STATUS */
3065 #define TPS65917_INT1_STATUS_VSYS_MON                           0x40
3066 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT                     0x06
3067 #define TPS65917_INT1_STATUS_HOTDIE                             0x20
3068 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT                       0x05
3069 #define TPS65917_INT1_STATUS_PWRDOWN                            0x10
3070 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT                      0x04
3071 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY                     0x04
3072 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT               0x02
3073 #define TPS65917_INT1_STATUS_PWRON                              0x02
3074 #define TPS65917_INT1_STATUS_PWRON_SHIFT                        0x01
3075 
3076 /* Bit definitions for INT1_MASK */
3077 #define TPS65917_INT1_MASK_VSYS_MON                             0x40
3078 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT                       0x06
3079 #define TPS65917_INT1_MASK_HOTDIE                               0x20
3080 #define TPS65917_INT1_MASK_HOTDIE_SHIFT                 0x05
3081 #define TPS65917_INT1_MASK_PWRDOWN                              0x10
3082 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT                        0x04
3083 #define TPS65917_INT1_MASK_LONG_PRESS_KEY                       0x04
3084 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT         0x02
3085 #define TPS65917_INT1_MASK_PWRON                                0x02
3086 #define TPS65917_INT1_MASK_PWRON_SHIFT                          0x01
3087 
3088 /* Bit definitions for INT1_LINE_STATE */
3089 #define TPS65917_INT1_LINE_STATE_VSYS_MON                       0x40
3090 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT         0x06
3091 #define TPS65917_INT1_LINE_STATE_HOTDIE                 0x20
3092 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT                   0x05
3093 #define TPS65917_INT1_LINE_STATE_PWRDOWN                        0x10
3094 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT                  0x04
3095 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY         0x04
3096 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT           0x02
3097 #define TPS65917_INT1_LINE_STATE_PWRON                          0x02
3098 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT                    0x01
3099 
3100 /* Bit definitions for INT2_STATUS */
3101 #define TPS65917_INT2_STATUS_SHORT                              0x40
3102 #define TPS65917_INT2_STATUS_SHORT_SHIFT                        0x06
3103 #define TPS65917_INT2_STATUS_FSD                                0x20
3104 #define TPS65917_INT2_STATUS_FSD_SHIFT                          0x05
3105 #define TPS65917_INT2_STATUS_RESET_IN                           0x10
3106 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT                     0x04
3107 #define TPS65917_INT2_STATUS_WDT                                0x04
3108 #define TPS65917_INT2_STATUS_WDT_SHIFT                          0x02
3109 #define TPS65917_INT2_STATUS_OTP_ERROR                          0x02
3110 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT                    0x01
3111 
3112 /* Bit definitions for INT2_MASK */
3113 #define TPS65917_INT2_MASK_SHORT                                0x40
3114 #define TPS65917_INT2_MASK_SHORT_SHIFT                          0x06
3115 #define TPS65917_INT2_MASK_FSD                                  0x20
3116 #define TPS65917_INT2_MASK_FSD_SHIFT                            0x05
3117 #define TPS65917_INT2_MASK_RESET_IN                             0x10
3118 #define TPS65917_INT2_MASK_RESET_IN_SHIFT                       0x04
3119 #define TPS65917_INT2_MASK_WDT                                  0x04
3120 #define TPS65917_INT2_MASK_WDT_SHIFT                            0x02
3121 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER                      0x02
3122 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT                      0x01
3123 
3124 /* Bit definitions for INT2_LINE_STATE */
3125 #define TPS65917_INT2_LINE_STATE_SHORT                          0x40
3126 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT                    0x06
3127 #define TPS65917_INT2_LINE_STATE_FSD                            0x20
3128 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT                      0x05
3129 #define TPS65917_INT2_LINE_STATE_RESET_IN                       0x10
3130 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT         0x04
3131 #define TPS65917_INT2_LINE_STATE_WDT                            0x04
3132 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT                      0x02
3133 #define TPS65917_INT2_LINE_STATE_OTP_ERROR                      0x02
3134 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT                0x01
3135 
3136 /* Bit definitions for INT3_STATUS */
3137 #define TPS65917_INT3_STATUS_VBUS                               0x80
3138 #define TPS65917_INT3_STATUS_VBUS_SHIFT                 0x07
3139 #define TPS65917_INT3_STATUS_GPADC_EOC_SW                       0x04
3140 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT         0x02
3141 #define TPS65917_INT3_STATUS_GPADC_AUTO_1                       0x02
3142 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT         0x01
3143 #define TPS65917_INT3_STATUS_GPADC_AUTO_0                       0x01
3144 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT         0x00
3145 
3146 /* Bit definitions for INT3_MASK */
3147 #define TPS65917_INT3_MASK_VBUS                         0x80
3148 #define TPS65917_INT3_MASK_VBUS_SHIFT                           0x07
3149 #define TPS65917_INT3_MASK_GPADC_EOC_SW                 0x04
3150 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT                   0x02
3151 #define TPS65917_INT3_MASK_GPADC_AUTO_1                 0x02
3152 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT                   0x01
3153 #define TPS65917_INT3_MASK_GPADC_AUTO_0                 0x01
3154 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT                   0x00
3155 
3156 /* Bit definitions for INT3_LINE_STATE */
3157 #define TPS65917_INT3_LINE_STATE_VBUS                           0x80
3158 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT                     0x07
3159 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW                   0x04
3160 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT             0x02
3161 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1                   0x02
3162 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT             0x01
3163 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0                   0x01
3164 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT             0x00
3165 
3166 /* Bit definitions for INT4_STATUS */
3167 #define TPS65917_INT4_STATUS_GPIO_6                             0x40
3168 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT                       0x06
3169 #define TPS65917_INT4_STATUS_GPIO_5                             0x20
3170 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT                       0x05
3171 #define TPS65917_INT4_STATUS_GPIO_4                             0x10
3172 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT                       0x04
3173 #define TPS65917_INT4_STATUS_GPIO_3                             0x08
3174 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT                       0x03
3175 #define TPS65917_INT4_STATUS_GPIO_2                             0x04
3176 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT                       0x02
3177 #define TPS65917_INT4_STATUS_GPIO_1                             0x02
3178 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT                       0x01
3179 #define TPS65917_INT4_STATUS_GPIO_0                             0x01
3180 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT                       0x00
3181 
3182 /* Bit definitions for INT4_MASK */
3183 #define TPS65917_INT4_MASK_GPIO_6                               0x40
3184 #define TPS65917_INT4_MASK_GPIO_6_SHIFT                 0x06
3185 #define TPS65917_INT4_MASK_GPIO_5                               0x20
3186 #define TPS65917_INT4_MASK_GPIO_5_SHIFT                 0x05
3187 #define TPS65917_INT4_MASK_GPIO_4                               0x10
3188 #define TPS65917_INT4_MASK_GPIO_4_SHIFT                 0x04
3189 #define TPS65917_INT4_MASK_GPIO_3                               0x08
3190 #define TPS65917_INT4_MASK_GPIO_3_SHIFT                 0x03
3191 #define TPS65917_INT4_MASK_GPIO_2                               0x04
3192 #define TPS65917_INT4_MASK_GPIO_2_SHIFT                 0x02
3193 #define TPS65917_INT4_MASK_GPIO_1                               0x02
3194 #define TPS65917_INT4_MASK_GPIO_1_SHIFT                 0x01
3195 #define TPS65917_INT4_MASK_GPIO_0                               0x01
3196 #define TPS65917_INT4_MASK_GPIO_0_SHIFT                 0x00
3197 
3198 /* Bit definitions for INT4_LINE_STATE */
3199 #define TPS65917_INT4_LINE_STATE_GPIO_6                 0x40
3200 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT                   0x06
3201 #define TPS65917_INT4_LINE_STATE_GPIO_5                 0x20
3202 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT                   0x05
3203 #define TPS65917_INT4_LINE_STATE_GPIO_4                 0x10
3204 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT                   0x04
3205 #define TPS65917_INT4_LINE_STATE_GPIO_3                 0x08
3206 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT                   0x03
3207 #define TPS65917_INT4_LINE_STATE_GPIO_2                 0x04
3208 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT                   0x02
3209 #define TPS65917_INT4_LINE_STATE_GPIO_1                 0x02
3210 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT                   0x01
3211 #define TPS65917_INT4_LINE_STATE_GPIO_0                 0x01
3212 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT                   0x00
3213 
3214 /* Bit definitions for INT4_EDGE_DETECT1 */
3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING                0x80
3216 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT          0x07
3217 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING               0x40
3218 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3219 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING                0x20
3220 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT          0x05
3221 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING               0x10
3222 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3223 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING                0x08
3224 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT          0x03
3225 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING               0x04
3226 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3227 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING                0x02
3228 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT          0x01
3229 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING               0x01
3230 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3231 
3232 /* Bit definitions for INT4_EDGE_DETECT2 */
3233 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING                0x20
3234 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT          0x05
3235 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING               0x10
3236 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3237 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING                0x08
3238 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT          0x03
3239 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING               0x04
3240 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3241 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING                0x02
3242 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT          0x01
3243 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING               0x01
3244 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3245 
3246 /* Bit definitions for INT_CTRL */
3247 #define TPS65917_INT_CTRL_INT_PENDING                           0x04
3248 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT                     0x02
3249 #define TPS65917_INT_CTRL_INT_CLEAR                             0x01
3250 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT                       0x00
3251 
3252 /* TPS65917 SMPS Registers */
3253 
3254 /* Registers for function SMPS */
3255 #define TPS65917_SMPS1_CTRL                                     0x00
3256 #define TPS65917_SMPS1_FORCE                                    0x02
3257 #define TPS65917_SMPS1_VOLTAGE                                  0x03
3258 #define TPS65917_SMPS2_CTRL                                     0x04
3259 #define TPS65917_SMPS2_FORCE                                    0x06
3260 #define TPS65917_SMPS2_VOLTAGE                                  0x07
3261 #define TPS65917_SMPS3_CTRL                                     0x0C
3262 #define TPS65917_SMPS3_FORCE                                    0x0E
3263 #define TPS65917_SMPS3_VOLTAGE                                  0x0F
3264 #define TPS65917_SMPS4_CTRL                                     0x10
3265 #define TPS65917_SMPS4_VOLTAGE                                  0x13
3266 #define TPS65917_SMPS5_CTRL                                     0x18
3267 #define TPS65917_SMPS5_VOLTAGE                                  0x1B
3268 #define TPS65917_SMPS_CTRL                                      0x24
3269 #define TPS65917_SMPS_PD_CTRL                                   0x25
3270 #define TPS65917_SMPS_THERMAL_EN                                0x27
3271 #define TPS65917_SMPS_THERMAL_STATUS                            0x28
3272 #define TPS65917_SMPS_SHORT_STATUS                              0x29
3273 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN         0x2A
3274 #define TPS65917_SMPS_POWERGOOD_MASK1                           0x2B
3275 #define TPS65917_SMPS_POWERGOOD_MASK2                           0x2C
3276 
3277 /* Bit definitions for SMPS1_CTRL */
3278 #define TPS65917_SMPS1_CTRL_WR_S                                0x80
3279 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT                          0x07
3280 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN                       0x40
3281 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT         0x06
3282 #define TPS65917_SMPS1_CTRL_STATUS_MASK                 0x30
3283 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT                        0x04
3284 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK                     0x0C
3285 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT                    0x02
3286 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK                    0x03
3287 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT                   0x00
3288 
3289 /* Bit definitions for SMPS1_FORCE */
3290 #define TPS65917_SMPS1_FORCE_CMD                                0x80
3291 #define TPS65917_SMPS1_FORCE_CMD_SHIFT                          0x07
3292 #define TPS65917_SMPS1_FORCE_VSEL_MASK                          0x7F
3293 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT                 0x00
3294 
3295 /* Bit definitions for SMPS1_VOLTAGE */
3296 #define TPS65917_SMPS1_VOLTAGE_RANGE                            0x80
3297 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT                      0x07
3298 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK                        0x7F
3299 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT                       0x00
3300 
3301 /* Bit definitions for SMPS2_CTRL */
3302 #define TPS65917_SMPS2_CTRL_WR_S                                0x80
3303 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT                          0x07
3304 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN                       0x40
3305 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT         0x06
3306 #define TPS65917_SMPS2_CTRL_STATUS_MASK                 0x30
3307 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT                        0x04
3308 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK                     0x0C
3309 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT                    0x02
3310 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK                    0x03
3311 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT                   0x00
3312 
3313 /* Bit definitions for SMPS2_FORCE */
3314 #define TPS65917_SMPS2_FORCE_CMD                                0x80
3315 #define TPS65917_SMPS2_FORCE_CMD_SHIFT                          0x07
3316 #define TPS65917_SMPS2_FORCE_VSEL_MASK                          0x7F
3317 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT                 0x00
3318 
3319 /* Bit definitions for SMPS2_VOLTAGE */
3320 #define TPS65917_SMPS2_VOLTAGE_RANGE                            0x80
3321 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT                      0x07
3322 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK                        0x7F
3323 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT                       0x00
3324 
3325 /* Bit definitions for SMPS3_CTRL */
3326 #define TPS65917_SMPS3_CTRL_WR_S                                0x80
3327 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT                          0x07
3328 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN                       0x40
3329 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT         0x06
3330 #define TPS65917_SMPS3_CTRL_STATUS_MASK                 0x30
3331 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT                        0x04
3332 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK                     0x0C
3333 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT                    0x02
3334 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK                    0x03
3335 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT                   0x00
3336 
3337 /* Bit definitions for SMPS3_FORCE */
3338 #define TPS65917_SMPS3_FORCE_CMD                                0x80
3339 #define TPS65917_SMPS3_FORCE_CMD_SHIFT                          0x07
3340 #define TPS65917_SMPS3_FORCE_VSEL_MASK                          0x7F
3341 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT                 0x00
3342 
3343 /* Bit definitions for SMPS3_VOLTAGE */
3344 #define TPS65917_SMPS3_VOLTAGE_RANGE                            0x80
3345 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT                      0x07
3346 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK                        0x7F
3347 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT                       0x00
3348 
3349 /* Bit definitions for SMPS4_CTRL */
3350 #define TPS65917_SMPS4_CTRL_WR_S                                0x80
3351 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT                          0x07
3352 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN                       0x40
3353 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT         0x06
3354 #define TPS65917_SMPS4_CTRL_STATUS_MASK                 0x30
3355 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT                        0x04
3356 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK                     0x0C
3357 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT                    0x02
3358 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK                    0x03
3359 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT                   0x00
3360 
3361 /* Bit definitions for SMPS4_VOLTAGE */
3362 #define TPS65917_SMPS4_VOLTAGE_RANGE                            0x80
3363 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT                      0x07
3364 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK                        0x7F
3365 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT                       0x00
3366 
3367 /* Bit definitions for SMPS5_CTRL */
3368 #define TPS65917_SMPS5_CTRL_WR_S                                0x80
3369 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT                          0x07
3370 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN                       0x40
3371 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT         0x06
3372 #define TPS65917_SMPS5_CTRL_STATUS_MASK                 0x30
3373 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT                        0x04
3374 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK                     0x0C
3375 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT                    0x02
3376 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK                    0x03
3377 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT                   0x00
3378 
3379 /* Bit definitions for SMPS5_VOLTAGE */
3380 #define TPS65917_SMPS5_VOLTAGE_RANGE                            0x80
3381 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT                      0x07
3382 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK                        0x7F
3383 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT                       0x00
3384 
3385 /* Bit definitions for SMPS_CTRL */
3386 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN                      0x10
3387 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT                0x04
3388 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL                    0x03
3389 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT              0x00
3390 
3391 /* Bit definitions for SMPS_PD_CTRL */
3392 #define TPS65917_SMPS_PD_CTRL_SMPS5                             0x40
3393 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT                       0x06
3394 #define TPS65917_SMPS_PD_CTRL_SMPS4                             0x10
3395 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT                       0x04
3396 #define TPS65917_SMPS_PD_CTRL_SMPS3                             0x08
3397 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT                       0x03
3398 #define TPS65917_SMPS_PD_CTRL_SMPS2                             0x02
3399 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT                       0x01
3400 #define TPS65917_SMPS_PD_CTRL_SMPS1                             0x01
3401 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT                       0x00
3402 
3403 /* Bit definitions for SMPS_THERMAL_EN */
3404 #define TPS65917_SMPS_THERMAL_EN_SMPS5                          0x40
3405 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT                    0x06
3406 #define TPS65917_SMPS_THERMAL_EN_SMPS3                          0x08
3407 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT                    0x03
3408 #define TPS65917_SMPS_THERMAL_EN_SMPS12                 0x01
3409 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT                   0x00
3410 
3411 /* Bit definitions for SMPS_THERMAL_STATUS */
3412 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5                      0x40
3413 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT                0x06
3414 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3                      0x08
3415 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT                0x03
3416 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12                     0x01
3417 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT               0x00
3418 
3419 /* Bit definitions for SMPS_SHORT_STATUS */
3420 #define TPS65917_SMPS_SHORT_STATUS_SMPS5                        0x40
3421 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT                  0x06
3422 #define TPS65917_SMPS_SHORT_STATUS_SMPS4                        0x10
3423 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT                  0x04
3424 #define TPS65917_SMPS_SHORT_STATUS_SMPS3                        0x08
3425 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT                  0x03
3426 #define TPS65917_SMPS_SHORT_STATUS_SMPS2                        0x02
3427 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT                  0x01
3428 #define TPS65917_SMPS_SHORT_STATUS_SMPS1                        0x01
3429 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT                  0x00
3430 
3431 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3432 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5           0x40
3433 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT     0x06
3434 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4           0x10
3435 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT     0x04
3436 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3           0x08
3437 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT     0x03
3438 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2           0x02
3439 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT     0x01
3440 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1           0x01
3441 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT     0x00
3442 
3443 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
3444 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5                     0x40
3445 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT               0x06
3446 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4                     0x10
3447 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT               0x04
3448 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3                     0x08
3449 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT               0x03
3450 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2                     0x02
3451 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT               0x01
3452 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1                     0x01
3453 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT               0x00
3454 
3455 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
3456 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT             0x80
3457 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT       0x07
3458 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT                   0x10
3459 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM                 0x04
3460 
3461 /* Bit definitions for SMPS_PLL_CTRL */
3462 
3463 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT          0x08
3464 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS                0x03
3465 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3466 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK               0x02
3467 
3468 /* Registers for function LDO */
3469 #define TPS65917_LDO1_CTRL                                      0x00
3470 #define TPS65917_LDO1_VOLTAGE                                   0x01
3471 #define TPS65917_LDO2_CTRL                                      0x02
3472 #define TPS65917_LDO2_VOLTAGE                                   0x03
3473 #define TPS65917_LDO3_CTRL                                      0x04
3474 #define TPS65917_LDO3_VOLTAGE                                   0x05
3475 #define TPS65917_LDO4_CTRL                                      0x0E
3476 #define TPS65917_LDO4_VOLTAGE                                   0x0F
3477 #define TPS65917_LDO5_CTRL                                      0x12
3478 #define TPS65917_LDO5_VOLTAGE                                   0x13
3479 #define TPS65917_LDO_PD_CTRL1                                   0x1B
3480 #define TPS65917_LDO_PD_CTRL2                                   0x1C
3481 #define TPS65917_LDO_SHORT_STATUS1                              0x1D
3482 #define TPS65917_LDO_SHORT_STATUS2                              0x1E
3483 #define TPS65917_LDO_PD_CTRL3                                   0x2D
3484 #define TPS65917_LDO_SHORT_STATUS3                              0x2E
3485 
3486 /* Bit definitions for LDO1_CTRL */
3487 #define TPS65917_LDO1_CTRL_WR_S                         0x80
3488 #define TPS65917_LDO1_CTRL_WR_S_SHIFT                           0x07
3489 #define TPS65917_LDO1_CTRL_BYPASS_EN                            0x40
3490 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT                      0x06
3491 #define TPS65917_LDO1_CTRL_STATUS                               0x10
3492 #define TPS65917_LDO1_CTRL_STATUS_SHIFT                 0x04
3493 #define TPS65917_LDO1_CTRL_MODE_SLEEP                           0x04
3494 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT                     0x02
3495 #define TPS65917_LDO1_CTRL_MODE_ACTIVE                          0x01
3496 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT                    0x00
3497 
3498 /* Bit definitions for LDO1_VOLTAGE */
3499 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK                 0x2F
3500 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT                        0x00
3501 
3502 /* Bit definitions for LDO2_CTRL */
3503 #define TPS65917_LDO2_CTRL_WR_S                         0x80
3504 #define TPS65917_LDO2_CTRL_WR_S_SHIFT                           0x07
3505 #define TPS65917_LDO2_CTRL_BYPASS_EN                            0x40
3506 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT                      0x06
3507 #define TPS65917_LDO2_CTRL_STATUS                               0x10
3508 #define TPS65917_LDO2_CTRL_STATUS_SHIFT                 0x04
3509 #define TPS65917_LDO2_CTRL_MODE_SLEEP                           0x04
3510 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT                     0x02
3511 #define TPS65917_LDO2_CTRL_MODE_ACTIVE                          0x01
3512 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT                    0x00
3513 
3514 /* Bit definitions for LDO2_VOLTAGE */
3515 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK                 0x2F
3516 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT                        0x00
3517 
3518 /* Bit definitions for LDO3_CTRL */
3519 #define TPS65917_LDO3_CTRL_WR_S                         0x80
3520 #define TPS65917_LDO3_CTRL_WR_S_SHIFT                           0x07
3521 #define TPS65917_LDO3_CTRL_STATUS                               0x10
3522 #define TPS65917_LDO3_CTRL_STATUS_SHIFT                 0x04
3523 #define TPS65917_LDO3_CTRL_MODE_SLEEP                           0x04
3524 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT                     0x02
3525 #define TPS65917_LDO3_CTRL_MODE_ACTIVE                          0x01
3526 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT                    0x00
3527 
3528 /* Bit definitions for LDO3_VOLTAGE */
3529 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK                 0x2F
3530 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT                        0x00
3531 
3532 /* Bit definitions for LDO4_CTRL */
3533 #define TPS65917_LDO4_CTRL_WR_S                         0x80
3534 #define TPS65917_LDO4_CTRL_WR_S_SHIFT                           0x07
3535 #define TPS65917_LDO4_CTRL_STATUS                               0x10
3536 #define TPS65917_LDO4_CTRL_STATUS_SHIFT                 0x04
3537 #define TPS65917_LDO4_CTRL_MODE_SLEEP                           0x04
3538 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT                     0x02
3539 #define TPS65917_LDO4_CTRL_MODE_ACTIVE                          0x01
3540 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT                    0x00
3541 
3542 /* Bit definitions for LDO4_VOLTAGE */
3543 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK                 0x2F
3544 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT                        0x00
3545 
3546 /* Bit definitions for LDO5_CTRL */
3547 #define TPS65917_LDO5_CTRL_WR_S                         0x80
3548 #define TPS65917_LDO5_CTRL_WR_S_SHIFT                           0x07
3549 #define TPS65917_LDO5_CTRL_STATUS                               0x10
3550 #define TPS65917_LDO5_CTRL_STATUS_SHIFT                 0x04
3551 #define TPS65917_LDO5_CTRL_MODE_SLEEP                           0x04
3552 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT                     0x02
3553 #define TPS65917_LDO5_CTRL_MODE_ACTIVE                          0x01
3554 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT                    0x00
3555 
3556 /* Bit definitions for LDO5_VOLTAGE */
3557 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK                 0x2F
3558 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT                        0x00
3559 
3560 /* Bit definitions for LDO_PD_CTRL1 */
3561 #define TPS65917_LDO_PD_CTRL1_LDO4                              0x80
3562 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT                        0x07
3563 #define TPS65917_LDO_PD_CTRL1_LDO2                              0x02
3564 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT                        0x01
3565 #define TPS65917_LDO_PD_CTRL1_LDO1                              0x01
3566 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT                        0x00
3567 
3568 /* Bit definitions for LDO_PD_CTRL2 */
3569 #define TPS65917_LDO_PD_CTRL2_LDO3                              0x04
3570 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT                        0x02
3571 #define TPS65917_LDO_PD_CTRL2_LDO5                              0x02
3572 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT                        0x01
3573 
3574 /* Bit definitions for LDO_PD_CTRL3 */
3575 #define TPS65917_LDO_PD_CTRL2_LDOVANA                           0x80
3576 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT                     0x07
3577 
3578 /* Bit definitions for LDO_SHORT_STATUS1 */
3579 #define TPS65917_LDO_SHORT_STATUS1_LDO4                 0x80
3580 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT                   0x07
3581 #define TPS65917_LDO_SHORT_STATUS1_LDO2                 0x02
3582 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT                   0x01
3583 #define TPS65917_LDO_SHORT_STATUS1_LDO1                 0x01
3584 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT                   0x00
3585 
3586 /* Bit definitions for LDO_SHORT_STATUS2 */
3587 #define TPS65917_LDO_SHORT_STATUS2_LDO3                 0x04
3588 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT                   0x02
3589 #define TPS65917_LDO_SHORT_STATUS2_LDO5                 0x02
3590 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT                   0x01
3591 
3592 /* Bit definitions for LDO_SHORT_STATUS2 */
3593 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA                      0x80
3594 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT                0x07
3595 
3596 /* Bit definitions for REGEN1_CTRL */
3597 #define TPS65917_REGEN1_CTRL_STATUS                             0x10
3598 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT                       0x04
3599 #define TPS65917_REGEN1_CTRL_MODE_SLEEP                 0x04
3600 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT                   0x02
3601 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE                        0x01
3602 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT                  0x00
3603 
3604 /* Bit definitions for PLLEN_CTRL */
3605 #define TPS65917_PLLEN_CTRL_STATUS                              0x10
3606 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT                        0x04
3607 #define TPS65917_PLLEN_CTRL_MODE_SLEEP                          0x04
3608 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT                    0x02
3609 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE                 0x01
3610 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT                   0x00
3611 
3612 /* Bit definitions for REGEN2_CTRL */
3613 #define TPS65917_REGEN2_CTRL_STATUS                             0x10
3614 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT                       0x04
3615 #define TPS65917_REGEN2_CTRL_MODE_SLEEP                 0x04
3616 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT                   0x02
3617 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE                        0x01
3618 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT                  0x00
3619 
3620 /* Bit definitions for NSLEEP_RES_ASSIGN */
3621 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN                       0x08
3622 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT         0x03
3623 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3                       0x04
3624 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT         0x02
3625 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2                       0x02
3626 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT         0x01
3627 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1                       0x01
3628 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT         0x00
3629 
3630 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
3631 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5                       0x40
3632 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT         0x06
3633 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4                       0x10
3634 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT         0x04
3635 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3                       0x08
3636 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT         0x03
3637 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2                       0x02
3638 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT         0x01
3639 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1                       0x01
3640 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT         0x00
3641 
3642 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3643 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4                        0x80
3644 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                  0x07
3645 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2                        0x02
3646 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                  0x01
3647 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1                        0x01
3648 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                  0x00
3649 
3650 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3651 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3                        0x04
3652 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT                  0x02
3653 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5                        0x02
3654 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT                  0x01
3655 
3656 /* Bit definitions for ENABLE1_RES_ASSIGN */
3657 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN                       0x08
3658 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT         0x03
3659 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3                      0x04
3660 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                0x02
3661 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2                      0x02
3662 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                0x01
3663 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1                      0x01
3664 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                0x00
3665 
3666 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
3667 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5                      0x40
3668 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT                0x06
3669 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4                      0x10
3670 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT                0x04
3671 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3                      0x08
3672 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                0x03
3673 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2                      0x02
3674 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT                0x01
3675 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1                      0x01
3676 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT                0x00
3677 
3678 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3679 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4                       0x80
3680 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT         0x07
3681 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2                       0x02
3682 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT         0x01
3683 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1                       0x01
3684 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT         0x00
3685 
3686 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3687 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3                       0x04
3688 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT         0x02
3689 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5                       0x02
3690 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT         0x01
3691 
3692 /* Bit definitions for ENABLE2_RES_ASSIGN */
3693 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN                       0x08
3694 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT         0x03
3695 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3                      0x04
3696 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                0x02
3697 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2                      0x02
3698 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                0x01
3699 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1                      0x01
3700 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                0x00
3701 
3702 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
3703 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5                      0x40
3704 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT                0x06
3705 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4                      0x10
3706 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT                0x04
3707 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3                      0x08
3708 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                0x03
3709 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2                      0x02
3710 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT                0x01
3711 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1                      0x01
3712 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT                0x00
3713 
3714 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3715 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4                       0x80
3716 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT         0x07
3717 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2                       0x02
3718 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT         0x01
3719 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1                       0x01
3720 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT         0x00
3721 
3722 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3723 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3                       0x04
3724 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT         0x02
3725 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5                       0x02
3726 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT         0x01
3727 
3728 /* Bit definitions for REGEN3_CTRL */
3729 #define TPS65917_REGEN3_CTRL_STATUS                             0x10
3730 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT                       0x04
3731 #define TPS65917_REGEN3_CTRL_MODE_SLEEP                 0x04
3732 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT                   0x02
3733 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE                        0x01
3734 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT                  0x00
3735 
3736 /* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
3737 #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK             0xC
3738 
3739 /* Registers for function RESOURCE */
3740 #define TPS65917_REGEN1_CTRL                                    0x2
3741 #define TPS65917_PLLEN_CTRL                                     0x3
3742 #define TPS65917_NSLEEP_RES_ASSIGN                              0x6
3743 #define TPS65917_NSLEEP_SMPS_ASSIGN                             0x7
3744 #define TPS65917_NSLEEP_LDO_ASSIGN1                             0x8
3745 #define TPS65917_NSLEEP_LDO_ASSIGN2                             0x9
3746 #define TPS65917_ENABLE1_RES_ASSIGN                             0xA
3747 #define TPS65917_ENABLE1_SMPS_ASSIGN                            0xB
3748 #define TPS65917_ENABLE1_LDO_ASSIGN1                            0xC
3749 #define TPS65917_ENABLE1_LDO_ASSIGN2                            0xD
3750 #define TPS65917_ENABLE2_RES_ASSIGN                             0xE
3751 #define TPS65917_ENABLE2_SMPS_ASSIGN                            0xF
3752 #define TPS65917_ENABLE2_LDO_ASSIGN1                            0x10
3753 #define TPS65917_ENABLE2_LDO_ASSIGN2                            0x11
3754 #define TPS65917_REGEN2_CTRL                                    0x12
3755 #define TPS65917_REGEN3_CTRL                                    0x13
3756 
3757 static inline int palmas_read(struct palmas *palmas, unsigned int base,
3758                 unsigned int reg, unsigned int *val)
3759 {
3760         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3761         int slave_id = PALMAS_BASE_TO_SLAVE(base);
3762 
3763         return regmap_read(palmas->regmap[slave_id], addr, val);
3764 }
3765 
3766 static inline int palmas_write(struct palmas *palmas, unsigned int base,
3767                 unsigned int reg, unsigned int value)
3768 {
3769         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3770         int slave_id = PALMAS_BASE_TO_SLAVE(base);
3771 
3772         return regmap_write(palmas->regmap[slave_id], addr, value);
3773 }
3774 
3775 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3776         unsigned int reg, const void *val, size_t val_count)
3777 {
3778         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3779         int slave_id = PALMAS_BASE_TO_SLAVE(base);
3780 
3781         return regmap_bulk_write(palmas->regmap[slave_id], addr,
3782                         val, val_count);
3783 }
3784 
3785 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3786                 unsigned int reg, void *val, size_t val_count)
3787 {
3788         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3789         int slave_id = PALMAS_BASE_TO_SLAVE(base);
3790 
3791         return regmap_bulk_read(palmas->regmap[slave_id], addr,
3792                 val, val_count);
3793 }
3794 
3795 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3796         unsigned int reg, unsigned int mask, unsigned int val)
3797 {
3798         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3799         int slave_id = PALMAS_BASE_TO_SLAVE(base);
3800 
3801         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3802 }
3803 
3804 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3805 {
3806         return regmap_irq_get_virq(palmas->irq_data, irq);
3807 }
3808 
3809 
3810 int palmas_ext_control_req_config(struct palmas *palmas,
3811         enum palmas_external_requestor_id ext_control_req_id,
3812         int ext_ctrl, bool enable);
3813 
3814 #endif /*  __LINUX_MFD_PALMAS_H */
3815 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp