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Linux/include/linux/mfd/si476x-platform.h

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  1 /*
  2  * include/media/si476x-platform.h -- Platform data specific definitions
  3  *
  4  * Copyright (C) 2013 Andrey Smirnov
  5  *
  6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; version 2 of the License.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  */
 18 
 19 #ifndef __SI476X_PLATFORM_H__
 20 #define __SI476X_PLATFORM_H__
 21 
 22 /* It is possible to select one of the four adresses using pins A0
 23  * and A1 on SI476x */
 24 #define SI476X_I2C_ADDR_1       0x60
 25 #define SI476X_I2C_ADDR_2       0x61
 26 #define SI476X_I2C_ADDR_3       0x62
 27 #define SI476X_I2C_ADDR_4       0x63
 28 
 29 enum si476x_iqclk_config {
 30         SI476X_IQCLK_NOOP = 0,
 31         SI476X_IQCLK_TRISTATE = 1,
 32         SI476X_IQCLK_IQ = 21,
 33 };
 34 enum si476x_iqfs_config {
 35         SI476X_IQFS_NOOP = 0,
 36         SI476X_IQFS_TRISTATE = 1,
 37         SI476X_IQFS_IQ = 21,
 38 };
 39 enum si476x_iout_config {
 40         SI476X_IOUT_NOOP = 0,
 41         SI476X_IOUT_TRISTATE = 1,
 42         SI476X_IOUT_OUTPUT = 22,
 43 };
 44 enum si476x_qout_config {
 45         SI476X_QOUT_NOOP = 0,
 46         SI476X_QOUT_TRISTATE = 1,
 47         SI476X_QOUT_OUTPUT = 22,
 48 };
 49 
 50 enum si476x_dclk_config {
 51         SI476X_DCLK_NOOP      = 0,
 52         SI476X_DCLK_TRISTATE  = 1,
 53         SI476X_DCLK_DAUDIO    = 10,
 54 };
 55 
 56 enum si476x_dfs_config {
 57         SI476X_DFS_NOOP      = 0,
 58         SI476X_DFS_TRISTATE  = 1,
 59         SI476X_DFS_DAUDIO    = 10,
 60 };
 61 
 62 enum si476x_dout_config {
 63         SI476X_DOUT_NOOP       = 0,
 64         SI476X_DOUT_TRISTATE   = 1,
 65         SI476X_DOUT_I2S_OUTPUT = 12,
 66         SI476X_DOUT_I2S_INPUT  = 13,
 67 };
 68 
 69 enum si476x_xout_config {
 70         SI476X_XOUT_NOOP        = 0,
 71         SI476X_XOUT_TRISTATE    = 1,
 72         SI476X_XOUT_I2S_INPUT   = 13,
 73         SI476X_XOUT_MODE_SELECT = 23,
 74 };
 75 
 76 enum si476x_icin_config {
 77         SI476X_ICIN_NOOP        = 0,
 78         SI476X_ICIN_TRISTATE    = 1,
 79         SI476X_ICIN_GPO1_HIGH   = 2,
 80         SI476X_ICIN_GPO1_LOW    = 3,
 81         SI476X_ICIN_IC_LINK     = 30,
 82 };
 83 
 84 enum si476x_icip_config {
 85         SI476X_ICIP_NOOP        = 0,
 86         SI476X_ICIP_TRISTATE    = 1,
 87         SI476X_ICIP_GPO2_HIGH   = 2,
 88         SI476X_ICIP_GPO2_LOW    = 3,
 89         SI476X_ICIP_IC_LINK     = 30,
 90 };
 91 
 92 enum si476x_icon_config {
 93         SI476X_ICON_NOOP        = 0,
 94         SI476X_ICON_TRISTATE    = 1,
 95         SI476X_ICON_I2S         = 10,
 96         SI476X_ICON_IC_LINK     = 30,
 97 };
 98 
 99 enum si476x_icop_config {
100         SI476X_ICOP_NOOP        = 0,
101         SI476X_ICOP_TRISTATE    = 1,
102         SI476X_ICOP_I2S         = 10,
103         SI476X_ICOP_IC_LINK     = 30,
104 };
105 
106 
107 enum si476x_lrout_config {
108         SI476X_LROUT_NOOP       = 0,
109         SI476X_LROUT_TRISTATE   = 1,
110         SI476X_LROUT_AUDIO      = 2,
111         SI476X_LROUT_MPX        = 3,
112 };
113 
114 
115 enum si476x_intb_config {
116         SI476X_INTB_NOOP     = 0,
117         SI476X_INTB_TRISTATE = 1,
118         SI476X_INTB_DAUDIO   = 10,
119         SI476X_INTB_IRQ      = 40,
120 };
121 
122 enum si476x_a1_config {
123         SI476X_A1_NOOP     = 0,
124         SI476X_A1_TRISTATE = 1,
125         SI476X_A1_IRQ      = 40,
126 };
127 
128 
129 struct si476x_pinmux {
130         enum si476x_dclk_config  dclk;
131         enum si476x_dfs_config   dfs;
132         enum si476x_dout_config  dout;
133         enum si476x_xout_config  xout;
134 
135         enum si476x_iqclk_config iqclk;
136         enum si476x_iqfs_config  iqfs;
137         enum si476x_iout_config  iout;
138         enum si476x_qout_config  qout;
139 
140         enum si476x_icin_config  icin;
141         enum si476x_icip_config  icip;
142         enum si476x_icon_config  icon;
143         enum si476x_icop_config  icop;
144 
145         enum si476x_lrout_config lrout;
146 
147         enum si476x_intb_config  intb;
148         enum si476x_a1_config    a1;
149 };
150 
151 enum si476x_ibias6x {
152         SI476X_IBIAS6X_OTHER                    = 0,
153         SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK       = 1,
154 };
155 
156 enum si476x_xstart {
157         SI476X_XSTART_MULTIPLE_TUNER    = 0x11,
158         SI476X_XSTART_NORMAL            = 0x77,
159 };
160 
161 enum si476x_freq {
162         SI476X_FREQ_4_MHZ               = 0,
163         SI476X_FREQ_37P209375_MHZ       = 1,
164         SI476X_FREQ_36P4_MHZ            = 2,
165         SI476X_FREQ_37P8_MHZ            =  3,
166 };
167 
168 enum si476x_xmode {
169         SI476X_XMODE_CRYSTAL_RCVR1      = 1,
170         SI476X_XMODE_EXT_CLOCK          = 2,
171         SI476X_XMODE_CRYSTAL_RCVR2_3    = 3,
172 };
173 
174 enum si476x_xbiashc {
175         SI476X_XBIASHC_SINGLE_RECEIVER = 0,
176         SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
177 };
178 
179 enum si476x_xbias {
180         SI476X_XBIAS_RCVR2_3    = 0,
181         SI476X_XBIAS_4MHZ_RCVR1 = 3,
182         SI476X_XBIAS_RCVR1      = 7,
183 };
184 
185 enum si476x_func {
186         SI476X_FUNC_BOOTLOADER  = 0,
187         SI476X_FUNC_FM_RECEIVER = 1,
188         SI476X_FUNC_AM_RECEIVER = 2,
189         SI476X_FUNC_WB_RECEIVER = 3,
190 };
191 
192 
193 /**
194  * @xcload: Selects the amount of additional on-chip capacitance to
195  *          be connected between XTAL1 and gnd and between XTAL2 and
196  *          GND. One half of the capacitance value shown here is the
197  *          additional load capacitance presented to the xtal. The
198  *          minimum step size is 0.277 pF. Recommended value is 0x28
199  *          but it will be layout dependent. Range is 0–0x3F i.e.
200  *          (0–16.33 pF)
201  * @ctsien: enable CTSINT(interrupt request when CTS condition
202  *          arises) when set
203  * @intsel: when set A1 pin becomes the interrupt pin; otherwise,
204  *          INTB is the interrupt pin
205  * @func:   selects the boot function of the device. I.e.
206  *          SI476X_BOOTLOADER  - Boot loader
207  *          SI476X_FM_RECEIVER - FM receiver
208  *          SI476X_AM_RECEIVER - AM receiver
209  *          SI476X_WB_RECEIVER - Weatherband receiver
210  * @freq:   oscillator's crystal frequency:
211  *          SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
212  *          SI476X_XTAL_36P4_MHZ      - 36.4 Mhz
213  *          SI476X_XTAL_37P8_MHZ      - 37.8 Mhz
214  */
215 struct si476x_power_up_args {
216         enum si476x_ibias6x ibias6x;
217         enum si476x_xstart  xstart;
218         u8   xcload;
219         bool fastboot;
220         enum si476x_xbiashc xbiashc;
221         enum si476x_xbias   xbias;
222         enum si476x_func    func;
223         enum si476x_freq    freq;
224         enum si476x_xmode   xmode;
225 };
226 
227 
228 /**
229  * enum si476x_phase_diversity_mode - possbile phase diversity modes
230  * for SI4764/5/6/7 chips.
231  *
232  * @SI476X_PHDIV_DISABLED:              Phase diversity feature is
233  *                                      disabled.
234  * @SI476X_PHDIV_PRIMARY_COMBINING:     Tuner works as a primary tuner
235  *                                      in combination with a
236  *                                      secondary one.
237  * @SI476X_PHDIV_PRIMARY_ANTENNA:       Tuner works as a primary tuner
238  *                                      using only its own antenna.
239  * @SI476X_PHDIV_SECONDARY_ANTENNA:     Tuner works as a primary tuner
240  *                                      usning seconary tuner's antenna.
241  * @SI476X_PHDIV_SECONDARY_COMBINING:   Tuner works as a secondary
242  *                                      tuner in combination with the
243  *                                      primary one.
244  */
245 enum si476x_phase_diversity_mode {
246         SI476X_PHDIV_DISABLED                   = 0,
247         SI476X_PHDIV_PRIMARY_COMBINING          = 1,
248         SI476X_PHDIV_PRIMARY_ANTENNA            = 2,
249         SI476X_PHDIV_SECONDARY_ANTENNA          = 3,
250         SI476X_PHDIV_SECONDARY_COMBINING        = 5,
251 };
252 
253 
254 /*
255  * Platform dependent definition
256  */
257 struct si476x_platform_data {
258         int gpio_reset; /* < 0 if not used */
259 
260         struct si476x_power_up_args power_up_parameters;
261         enum si476x_phase_diversity_mode diversity_mode;
262 
263         struct si476x_pinmux pinmux;
264 };
265 
266 
267 #endif /* __SI476X_PLATFORM_H__ */
268 

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