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TOMOYO Linux Cross Reference
Linux/include/linux/mfd/wm8400-private.h

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  1 /* SPDX-License-Identifier: GPL-2.0-or-later */
  2 /*
  3  * wm8400 private definitions.
  4  *
  5  * Copyright 2008 Wolfson Microelectronics plc
  6  */
  7 
  8 #ifndef __LINUX_MFD_WM8400_PRIV_H
  9 #define __LINUX_MFD_WM8400_PRIV_H
 10 
 11 #include <linux/mfd/wm8400.h>
 12 #include <linux/mutex.h>
 13 #include <linux/platform_device.h>
 14 #include <linux/regmap.h>
 15 
 16 #define WM8400_REGISTER_COUNT 0x55
 17 
 18 struct wm8400 {
 19         struct device *dev;
 20         struct regmap *regmap;
 21 
 22         struct platform_device regulators[6];
 23 };
 24 
 25 /*
 26  * Register values.
 27  */
 28 #define WM8400_RESET_ID                         0x00
 29 #define WM8400_ID                               0x01
 30 #define WM8400_POWER_MANAGEMENT_1               0x02
 31 #define WM8400_POWER_MANAGEMENT_2               0x03
 32 #define WM8400_POWER_MANAGEMENT_3               0x04
 33 #define WM8400_AUDIO_INTERFACE_1                0x05
 34 #define WM8400_AUDIO_INTERFACE_2                0x06
 35 #define WM8400_CLOCKING_1                       0x07
 36 #define WM8400_CLOCKING_2                       0x08
 37 #define WM8400_AUDIO_INTERFACE_3                0x09
 38 #define WM8400_AUDIO_INTERFACE_4                0x0A
 39 #define WM8400_DAC_CTRL                         0x0B
 40 #define WM8400_LEFT_DAC_DIGITAL_VOLUME          0x0C
 41 #define WM8400_RIGHT_DAC_DIGITAL_VOLUME         0x0D
 42 #define WM8400_DIGITAL_SIDE_TONE                0x0E
 43 #define WM8400_ADC_CTRL                         0x0F
 44 #define WM8400_LEFT_ADC_DIGITAL_VOLUME          0x10
 45 #define WM8400_RIGHT_ADC_DIGITAL_VOLUME         0x11
 46 #define WM8400_GPIO_CTRL_1                      0x12
 47 #define WM8400_GPIO1_GPIO2                      0x13
 48 #define WM8400_GPIO3_GPIO4                      0x14
 49 #define WM8400_GPIO5_GPIO6                      0x15
 50 #define WM8400_GPIOCTRL_2                       0x16
 51 #define WM8400_GPIO_POL                         0x17
 52 #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME       0x18
 53 #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME       0x19
 54 #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
 55 #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
 56 #define WM8400_LEFT_OUTPUT_VOLUME               0x1C
 57 #define WM8400_RIGHT_OUTPUT_VOLUME              0x1D
 58 #define WM8400_LINE_OUTPUTS_VOLUME              0x1E
 59 #define WM8400_OUT3_4_VOLUME                    0x1F
 60 #define WM8400_LEFT_OPGA_VOLUME                 0x20
 61 #define WM8400_RIGHT_OPGA_VOLUME                0x21
 62 #define WM8400_SPEAKER_VOLUME                   0x22
 63 #define WM8400_CLASSD1                          0x23
 64 #define WM8400_CLASSD3                          0x25
 65 #define WM8400_INPUT_MIXER1                     0x27
 66 #define WM8400_INPUT_MIXER2                     0x28
 67 #define WM8400_INPUT_MIXER3                     0x29
 68 #define WM8400_INPUT_MIXER4                     0x2A
 69 #define WM8400_INPUT_MIXER5                     0x2B
 70 #define WM8400_INPUT_MIXER6                     0x2C
 71 #define WM8400_OUTPUT_MIXER1                    0x2D
 72 #define WM8400_OUTPUT_MIXER2                    0x2E
 73 #define WM8400_OUTPUT_MIXER3                    0x2F
 74 #define WM8400_OUTPUT_MIXER4                    0x30
 75 #define WM8400_OUTPUT_MIXER5                    0x31
 76 #define WM8400_OUTPUT_MIXER6                    0x32
 77 #define WM8400_OUT3_4_MIXER                     0x33
 78 #define WM8400_LINE_MIXER1                      0x34
 79 #define WM8400_LINE_MIXER2                      0x35
 80 #define WM8400_SPEAKER_MIXER                    0x36
 81 #define WM8400_ADDITIONAL_CONTROL               0x37
 82 #define WM8400_ANTIPOP1                         0x38
 83 #define WM8400_ANTIPOP2                         0x39
 84 #define WM8400_MICBIAS                          0x3A
 85 #define WM8400_FLL_CONTROL_1                    0x3C
 86 #define WM8400_FLL_CONTROL_2                    0x3D
 87 #define WM8400_FLL_CONTROL_3                    0x3E
 88 #define WM8400_FLL_CONTROL_4                    0x3F
 89 #define WM8400_LDO1_CONTROL                     0x41
 90 #define WM8400_LDO2_CONTROL                     0x42
 91 #define WM8400_LDO3_CONTROL                     0x43
 92 #define WM8400_LDO4_CONTROL                     0x44
 93 #define WM8400_DCDC1_CONTROL_1                  0x46
 94 #define WM8400_DCDC1_CONTROL_2                  0x47
 95 #define WM8400_DCDC2_CONTROL_1                  0x48
 96 #define WM8400_DCDC2_CONTROL_2                  0x49
 97 #define WM8400_INTERFACE                        0x4B
 98 #define WM8400_PM_GENERAL                       0x4C
 99 #define WM8400_PM_SHUTDOWN_CONTROL              0x4E
100 #define WM8400_INTERRUPT_STATUS_1               0x4F
101 #define WM8400_INTERRUPT_STATUS_1_MASK          0x50
102 #define WM8400_INTERRUPT_LEVELS                 0x51
103 #define WM8400_SHUTDOWN_REASON                  0x52
104 #define WM8400_LINE_CIRCUITS                    0x54
105 
106 /*
107  * Field Definitions.
108  */
109 
110 /*
111  * R0 (0x00) - Reset/ID
112  */
113 #define WM8400_SW_RESET_CHIP_ID_MASK            0xFFFF  /* SW_RESET/CHIP_ID - [15:0] */
114 #define WM8400_SW_RESET_CHIP_ID_SHIFT                0  /* SW_RESET/CHIP_ID - [15:0] */
115 #define WM8400_SW_RESET_CHIP_ID_WIDTH               16  /* SW_RESET/CHIP_ID - [15:0] */
116 
117 /*
118  * R1 (0x01) - ID
119  */
120 #define WM8400_CHIP_REV_MASK                    0x7000  /* CHIP_REV - [14:12] */
121 #define WM8400_CHIP_REV_SHIFT                       12  /* CHIP_REV - [14:12] */
122 #define WM8400_CHIP_REV_WIDTH                        3  /* CHIP_REV - [14:12] */
123 
124 /*
125  * R18 (0x12) - GPIO CTRL 1
126  */
127 #define WM8400_IRQ                              0x1000  /* IRQ */
128 #define WM8400_IRQ_MASK                         0x1000  /* IRQ */
129 #define WM8400_IRQ_SHIFT                            12  /* IRQ */
130 #define WM8400_IRQ_WIDTH                             1  /* IRQ */
131 #define WM8400_TEMPOK                           0x0800  /* TEMPOK */
132 #define WM8400_TEMPOK_MASK                      0x0800  /* TEMPOK */
133 #define WM8400_TEMPOK_SHIFT                         11  /* TEMPOK */
134 #define WM8400_TEMPOK_WIDTH                          1  /* TEMPOK */
135 #define WM8400_MIC1SHRT                         0x0400  /* MIC1SHRT */
136 #define WM8400_MIC1SHRT_MASK                    0x0400  /* MIC1SHRT */
137 #define WM8400_MIC1SHRT_SHIFT                       10  /* MIC1SHRT */
138 #define WM8400_MIC1SHRT_WIDTH                        1  /* MIC1SHRT */
139 #define WM8400_MIC1DET                          0x0200  /* MIC1DET */
140 #define WM8400_MIC1DET_MASK                     0x0200  /* MIC1DET */
141 #define WM8400_MIC1DET_SHIFT                         9  /* MIC1DET */
142 #define WM8400_MIC1DET_WIDTH                         1  /* MIC1DET */
143 #define WM8400_FLL_LCK                          0x0100  /* FLL_LCK */
144 #define WM8400_FLL_LCK_MASK                     0x0100  /* FLL_LCK */
145 #define WM8400_FLL_LCK_SHIFT                         8  /* FLL_LCK */
146 #define WM8400_FLL_LCK_WIDTH                         1  /* FLL_LCK */
147 #define WM8400_GPIO_STATUS_MASK                 0x00FF  /* GPIO_STATUS - [7:0] */
148 #define WM8400_GPIO_STATUS_SHIFT                     0  /* GPIO_STATUS - [7:0] */
149 #define WM8400_GPIO_STATUS_WIDTH                     8  /* GPIO_STATUS - [7:0] */
150 
151 /*
152  * R19 (0x13) - GPIO1 & GPIO2
153  */
154 #define WM8400_GPIO2_DEB_ENA                    0x8000  /* GPIO2_DEB_ENA */
155 #define WM8400_GPIO2_DEB_ENA_MASK               0x8000  /* GPIO2_DEB_ENA */
156 #define WM8400_GPIO2_DEB_ENA_SHIFT                  15  /* GPIO2_DEB_ENA */
157 #define WM8400_GPIO2_DEB_ENA_WIDTH                   1  /* GPIO2_DEB_ENA */
158 #define WM8400_GPIO2_IRQ_ENA                    0x4000  /* GPIO2_IRQ_ENA */
159 #define WM8400_GPIO2_IRQ_ENA_MASK               0x4000  /* GPIO2_IRQ_ENA */
160 #define WM8400_GPIO2_IRQ_ENA_SHIFT                  14  /* GPIO2_IRQ_ENA */
161 #define WM8400_GPIO2_IRQ_ENA_WIDTH                   1  /* GPIO2_IRQ_ENA */
162 #define WM8400_GPIO2_PU                         0x2000  /* GPIO2_PU */
163 #define WM8400_GPIO2_PU_MASK                    0x2000  /* GPIO2_PU */
164 #define WM8400_GPIO2_PU_SHIFT                       13  /* GPIO2_PU */
165 #define WM8400_GPIO2_PU_WIDTH                        1  /* GPIO2_PU */
166 #define WM8400_GPIO2_PD                         0x1000  /* GPIO2_PD */
167 #define WM8400_GPIO2_PD_MASK                    0x1000  /* GPIO2_PD */
168 #define WM8400_GPIO2_PD_SHIFT                       12  /* GPIO2_PD */
169 #define WM8400_GPIO2_PD_WIDTH                        1  /* GPIO2_PD */
170 #define WM8400_GPIO2_SEL_MASK                   0x0F00  /* GPIO2_SEL - [11:8] */
171 #define WM8400_GPIO2_SEL_SHIFT                       8  /* GPIO2_SEL - [11:8] */
172 #define WM8400_GPIO2_SEL_WIDTH                       4  /* GPIO2_SEL - [11:8] */
173 #define WM8400_GPIO1_DEB_ENA                    0x0080  /* GPIO1_DEB_ENA */
174 #define WM8400_GPIO1_DEB_ENA_MASK               0x0080  /* GPIO1_DEB_ENA */
175 #define WM8400_GPIO1_DEB_ENA_SHIFT                   7  /* GPIO1_DEB_ENA */
176 #define WM8400_GPIO1_DEB_ENA_WIDTH                   1  /* GPIO1_DEB_ENA */
177 #define WM8400_GPIO1_IRQ_ENA                    0x0040  /* GPIO1_IRQ_ENA */
178 #define WM8400_GPIO1_IRQ_ENA_MASK               0x0040  /* GPIO1_IRQ_ENA */
179 #define WM8400_GPIO1_IRQ_ENA_SHIFT                   6  /* GPIO1_IRQ_ENA */
180 #define WM8400_GPIO1_IRQ_ENA_WIDTH                   1  /* GPIO1_IRQ_ENA */
181 #define WM8400_GPIO1_PU                         0x0020  /* GPIO1_PU */
182 #define WM8400_GPIO1_PU_MASK                    0x0020  /* GPIO1_PU */
183 #define WM8400_GPIO1_PU_SHIFT                        5  /* GPIO1_PU */
184 #define WM8400_GPIO1_PU_WIDTH                        1  /* GPIO1_PU */
185 #define WM8400_GPIO1_PD                         0x0010  /* GPIO1_PD */
186 #define WM8400_GPIO1_PD_MASK                    0x0010  /* GPIO1_PD */
187 #define WM8400_GPIO1_PD_SHIFT                        4  /* GPIO1_PD */
188 #define WM8400_GPIO1_PD_WIDTH                        1  /* GPIO1_PD */
189 #define WM8400_GPIO1_SEL_MASK                   0x000F  /* GPIO1_SEL - [3:0] */
190 #define WM8400_GPIO1_SEL_SHIFT                       0  /* GPIO1_SEL - [3:0] */
191 #define WM8400_GPIO1_SEL_WIDTH                       4  /* GPIO1_SEL - [3:0] */
192 
193 /*
194  * R20 (0x14) - GPIO3 & GPIO4
195  */
196 #define WM8400_GPIO4_DEB_ENA                    0x8000  /* GPIO4_DEB_ENA */
197 #define WM8400_GPIO4_DEB_ENA_MASK               0x8000  /* GPIO4_DEB_ENA */
198 #define WM8400_GPIO4_DEB_ENA_SHIFT                  15  /* GPIO4_DEB_ENA */
199 #define WM8400_GPIO4_DEB_ENA_WIDTH                   1  /* GPIO4_DEB_ENA */
200 #define WM8400_GPIO4_IRQ_ENA                    0x4000  /* GPIO4_IRQ_ENA */
201 #define WM8400_GPIO4_IRQ_ENA_MASK               0x4000  /* GPIO4_IRQ_ENA */
202 #define WM8400_GPIO4_IRQ_ENA_SHIFT                  14  /* GPIO4_IRQ_ENA */
203 #define WM8400_GPIO4_IRQ_ENA_WIDTH                   1  /* GPIO4_IRQ_ENA */
204 #define WM8400_GPIO4_PU                         0x2000  /* GPIO4_PU */
205 #define WM8400_GPIO4_PU_MASK                    0x2000  /* GPIO4_PU */
206 #define WM8400_GPIO4_PU_SHIFT                       13  /* GPIO4_PU */
207 #define WM8400_GPIO4_PU_WIDTH                        1  /* GPIO4_PU */
208 #define WM8400_GPIO4_PD                         0x1000  /* GPIO4_PD */
209 #define WM8400_GPIO4_PD_MASK                    0x1000  /* GPIO4_PD */
210 #define WM8400_GPIO4_PD_SHIFT                       12  /* GPIO4_PD */
211 #define WM8400_GPIO4_PD_WIDTH                        1  /* GPIO4_PD */
212 #define WM8400_GPIO4_SEL_MASK                   0x0F00  /* GPIO4_SEL - [11:8] */
213 #define WM8400_GPIO4_SEL_SHIFT                       8  /* GPIO4_SEL - [11:8] */
214 #define WM8400_GPIO4_SEL_WIDTH                       4  /* GPIO4_SEL - [11:8] */
215 #define WM8400_GPIO3_DEB_ENA                    0x0080  /* GPIO3_DEB_ENA */
216 #define WM8400_GPIO3_DEB_ENA_MASK               0x0080  /* GPIO3_DEB_ENA */
217 #define WM8400_GPIO3_DEB_ENA_SHIFT                   7  /* GPIO3_DEB_ENA */
218 #define WM8400_GPIO3_DEB_ENA_WIDTH                   1  /* GPIO3_DEB_ENA */
219 #define WM8400_GPIO3_IRQ_ENA                    0x0040  /* GPIO3_IRQ_ENA */
220 #define WM8400_GPIO3_IRQ_ENA_MASK               0x0040  /* GPIO3_IRQ_ENA */
221 #define WM8400_GPIO3_IRQ_ENA_SHIFT                   6  /* GPIO3_IRQ_ENA */
222 #define WM8400_GPIO3_IRQ_ENA_WIDTH                   1  /* GPIO3_IRQ_ENA */
223 #define WM8400_GPIO3_PU                         0x0020  /* GPIO3_PU */
224 #define WM8400_GPIO3_PU_MASK                    0x0020  /* GPIO3_PU */
225 #define WM8400_GPIO3_PU_SHIFT                        5  /* GPIO3_PU */
226 #define WM8400_GPIO3_PU_WIDTH                        1  /* GPIO3_PU */
227 #define WM8400_GPIO3_PD                         0x0010  /* GPIO3_PD */
228 #define WM8400_GPIO3_PD_MASK                    0x0010  /* GPIO3_PD */
229 #define WM8400_GPIO3_PD_SHIFT                        4  /* GPIO3_PD */
230 #define WM8400_GPIO3_PD_WIDTH                        1  /* GPIO3_PD */
231 #define WM8400_GPIO3_SEL_MASK                   0x000F  /* GPIO3_SEL - [3:0] */
232 #define WM8400_GPIO3_SEL_SHIFT                       0  /* GPIO3_SEL - [3:0] */
233 #define WM8400_GPIO3_SEL_WIDTH                       4  /* GPIO3_SEL - [3:0] */
234 
235 /*
236  * R21 (0x15) - GPIO5 & GPIO6
237  */
238 #define WM8400_GPIO6_DEB_ENA                    0x8000  /* GPIO6_DEB_ENA */
239 #define WM8400_GPIO6_DEB_ENA_MASK               0x8000  /* GPIO6_DEB_ENA */
240 #define WM8400_GPIO6_DEB_ENA_SHIFT                  15  /* GPIO6_DEB_ENA */
241 #define WM8400_GPIO6_DEB_ENA_WIDTH                   1  /* GPIO6_DEB_ENA */
242 #define WM8400_GPIO6_IRQ_ENA                    0x4000  /* GPIO6_IRQ_ENA */
243 #define WM8400_GPIO6_IRQ_ENA_MASK               0x4000  /* GPIO6_IRQ_ENA */
244 #define WM8400_GPIO6_IRQ_ENA_SHIFT                  14  /* GPIO6_IRQ_ENA */
245 #define WM8400_GPIO6_IRQ_ENA_WIDTH                   1  /* GPIO6_IRQ_ENA */
246 #define WM8400_GPIO6_PU                         0x2000  /* GPIO6_PU */
247 #define WM8400_GPIO6_PU_MASK                    0x2000  /* GPIO6_PU */
248 #define WM8400_GPIO6_PU_SHIFT                       13  /* GPIO6_PU */
249 #define WM8400_GPIO6_PU_WIDTH                        1  /* GPIO6_PU */
250 #define WM8400_GPIO6_PD                         0x1000  /* GPIO6_PD */
251 #define WM8400_GPIO6_PD_MASK                    0x1000  /* GPIO6_PD */
252 #define WM8400_GPIO6_PD_SHIFT                       12  /* GPIO6_PD */
253 #define WM8400_GPIO6_PD_WIDTH                        1  /* GPIO6_PD */
254 #define WM8400_GPIO6_SEL_MASK                   0x0F00  /* GPIO6_SEL - [11:8] */
255 #define WM8400_GPIO6_SEL_SHIFT                       8  /* GPIO6_SEL - [11:8] */
256 #define WM8400_GPIO6_SEL_WIDTH                       4  /* GPIO6_SEL - [11:8] */
257 #define WM8400_GPIO5_DEB_ENA                    0x0080  /* GPIO5_DEB_ENA */
258 #define WM8400_GPIO5_DEB_ENA_MASK               0x0080  /* GPIO5_DEB_ENA */
259 #define WM8400_GPIO5_DEB_ENA_SHIFT                   7  /* GPIO5_DEB_ENA */
260 #define WM8400_GPIO5_DEB_ENA_WIDTH                   1  /* GPIO5_DEB_ENA */
261 #define WM8400_GPIO5_IRQ_ENA                    0x0040  /* GPIO5_IRQ_ENA */
262 #define WM8400_GPIO5_IRQ_ENA_MASK               0x0040  /* GPIO5_IRQ_ENA */
263 #define WM8400_GPIO5_IRQ_ENA_SHIFT                   6  /* GPIO5_IRQ_ENA */
264 #define WM8400_GPIO5_IRQ_ENA_WIDTH                   1  /* GPIO5_IRQ_ENA */
265 #define WM8400_GPIO5_PU                         0x0020  /* GPIO5_PU */
266 #define WM8400_GPIO5_PU_MASK                    0x0020  /* GPIO5_PU */
267 #define WM8400_GPIO5_PU_SHIFT                        5  /* GPIO5_PU */
268 #define WM8400_GPIO5_PU_WIDTH                        1  /* GPIO5_PU */
269 #define WM8400_GPIO5_PD                         0x0010  /* GPIO5_PD */
270 #define WM8400_GPIO5_PD_MASK                    0x0010  /* GPIO5_PD */
271 #define WM8400_GPIO5_PD_SHIFT                        4  /* GPIO5_PD */
272 #define WM8400_GPIO5_PD_WIDTH                        1  /* GPIO5_PD */
273 #define WM8400_GPIO5_SEL_MASK                   0x000F  /* GPIO5_SEL - [3:0] */
274 #define WM8400_GPIO5_SEL_SHIFT                       0  /* GPIO5_SEL - [3:0] */
275 #define WM8400_GPIO5_SEL_WIDTH                       4  /* GPIO5_SEL - [3:0] */
276 
277 /*
278  * R22 (0x16) - GPIOCTRL 2
279  */
280 #define WM8400_TEMPOK_IRQ_ENA                   0x0800  /* TEMPOK_IRQ_ENA */
281 #define WM8400_TEMPOK_IRQ_ENA_MASK              0x0800  /* TEMPOK_IRQ_ENA */
282 #define WM8400_TEMPOK_IRQ_ENA_SHIFT                 11  /* TEMPOK_IRQ_ENA */
283 #define WM8400_TEMPOK_IRQ_ENA_WIDTH                  1  /* TEMPOK_IRQ_ENA */
284 #define WM8400_MIC1SHRT_IRQ_ENA                 0x0400  /* MIC1SHRT_IRQ_ENA */
285 #define WM8400_MIC1SHRT_IRQ_ENA_MASK            0x0400  /* MIC1SHRT_IRQ_ENA */
286 #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT               10  /* MIC1SHRT_IRQ_ENA */
287 #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH                1  /* MIC1SHRT_IRQ_ENA */
288 #define WM8400_MIC1DET_IRQ_ENA                  0x0200  /* MIC1DET_IRQ_ENA */
289 #define WM8400_MIC1DET_IRQ_ENA_MASK             0x0200  /* MIC1DET_IRQ_ENA */
290 #define WM8400_MIC1DET_IRQ_ENA_SHIFT                 9  /* MIC1DET_IRQ_ENA */
291 #define WM8400_MIC1DET_IRQ_ENA_WIDTH                 1  /* MIC1DET_IRQ_ENA */
292 #define WM8400_FLL_LCK_IRQ_ENA                  0x0100  /* FLL_LCK_IRQ_ENA */
293 #define WM8400_FLL_LCK_IRQ_ENA_MASK             0x0100  /* FLL_LCK_IRQ_ENA */
294 #define WM8400_FLL_LCK_IRQ_ENA_SHIFT                 8  /* FLL_LCK_IRQ_ENA */
295 #define WM8400_FLL_LCK_IRQ_ENA_WIDTH                 1  /* FLL_LCK_IRQ_ENA */
296 #define WM8400_GPI8_DEB_ENA                     0x0080  /* GPI8_DEB_ENA */
297 #define WM8400_GPI8_DEB_ENA_MASK                0x0080  /* GPI8_DEB_ENA */
298 #define WM8400_GPI8_DEB_ENA_SHIFT                    7  /* GPI8_DEB_ENA */
299 #define WM8400_GPI8_DEB_ENA_WIDTH                    1  /* GPI8_DEB_ENA */
300 #define WM8400_GPI8_IRQ_ENA                     0x0040  /* GPI8_IRQ_ENA */
301 #define WM8400_GPI8_IRQ_ENA_MASK                0x0040  /* GPI8_IRQ_ENA */
302 #define WM8400_GPI8_IRQ_ENA_SHIFT                    6  /* GPI8_IRQ_ENA */
303 #define WM8400_GPI8_IRQ_ENA_WIDTH                    1  /* GPI8_IRQ_ENA */
304 #define WM8400_GPI8_ENA                         0x0010  /* GPI8_ENA */
305 #define WM8400_GPI8_ENA_MASK                    0x0010  /* GPI8_ENA */
306 #define WM8400_GPI8_ENA_SHIFT                        4  /* GPI8_ENA */
307 #define WM8400_GPI8_ENA_WIDTH                        1  /* GPI8_ENA */
308 #define WM8400_GPI7_DEB_ENA                     0x0008  /* GPI7_DEB_ENA */
309 #define WM8400_GPI7_DEB_ENA_MASK                0x0008  /* GPI7_DEB_ENA */
310 #define WM8400_GPI7_DEB_ENA_SHIFT                    3  /* GPI7_DEB_ENA */
311 #define WM8400_GPI7_DEB_ENA_WIDTH                    1  /* GPI7_DEB_ENA */
312 #define WM8400_GPI7_IRQ_ENA                     0x0004  /* GPI7_IRQ_ENA */
313 #define WM8400_GPI7_IRQ_ENA_MASK                0x0004  /* GPI7_IRQ_ENA */
314 #define WM8400_GPI7_IRQ_ENA_SHIFT                    2  /* GPI7_IRQ_ENA */
315 #define WM8400_GPI7_IRQ_ENA_WIDTH                    1  /* GPI7_IRQ_ENA */
316 #define WM8400_GPI7_ENA                         0x0001  /* GPI7_ENA */
317 #define WM8400_GPI7_ENA_MASK                    0x0001  /* GPI7_ENA */
318 #define WM8400_GPI7_ENA_SHIFT                        0  /* GPI7_ENA */
319 #define WM8400_GPI7_ENA_WIDTH                        1  /* GPI7_ENA */
320 
321 /*
322  * R23 (0x17) - GPIO_POL
323  */
324 #define WM8400_IRQ_INV                          0x1000  /* IRQ_INV */
325 #define WM8400_IRQ_INV_MASK                     0x1000  /* IRQ_INV */
326 #define WM8400_IRQ_INV_SHIFT                        12  /* IRQ_INV */
327 #define WM8400_IRQ_INV_WIDTH                         1  /* IRQ_INV */
328 #define WM8400_TEMPOK_POL                       0x0800  /* TEMPOK_POL */
329 #define WM8400_TEMPOK_POL_MASK                  0x0800  /* TEMPOK_POL */
330 #define WM8400_TEMPOK_POL_SHIFT                     11  /* TEMPOK_POL */
331 #define WM8400_TEMPOK_POL_WIDTH                      1  /* TEMPOK_POL */
332 #define WM8400_MIC1SHRT_POL                     0x0400  /* MIC1SHRT_POL */
333 #define WM8400_MIC1SHRT_POL_MASK                0x0400  /* MIC1SHRT_POL */
334 #define WM8400_MIC1SHRT_POL_SHIFT                   10  /* MIC1SHRT_POL */
335 #define WM8400_MIC1SHRT_POL_WIDTH                    1  /* MIC1SHRT_POL */
336 #define WM8400_MIC1DET_POL                      0x0200  /* MIC1DET_POL */
337 #define WM8400_MIC1DET_POL_MASK                 0x0200  /* MIC1DET_POL */
338 #define WM8400_MIC1DET_POL_SHIFT                     9  /* MIC1DET_POL */
339 #define WM8400_MIC1DET_POL_WIDTH                     1  /* MIC1DET_POL */
340 #define WM8400_FLL_LCK_POL                      0x0100  /* FLL_LCK_POL */
341 #define WM8400_FLL_LCK_POL_MASK                 0x0100  /* FLL_LCK_POL */
342 #define WM8400_FLL_LCK_POL_SHIFT                     8  /* FLL_LCK_POL */
343 #define WM8400_FLL_LCK_POL_WIDTH                     1  /* FLL_LCK_POL */
344 #define WM8400_GPIO_POL_MASK                    0x00FF  /* GPIO_POL - [7:0] */
345 #define WM8400_GPIO_POL_SHIFT                        0  /* GPIO_POL - [7:0] */
346 #define WM8400_GPIO_POL_WIDTH                        8  /* GPIO_POL - [7:0] */
347 
348 /*
349  * R65 (0x41) - LDO 1 Control
350  */
351 #define WM8400_LDO1_ENA                         0x8000  /* LDO1_ENA */
352 #define WM8400_LDO1_ENA_MASK                    0x8000  /* LDO1_ENA */
353 #define WM8400_LDO1_ENA_SHIFT                       15  /* LDO1_ENA */
354 #define WM8400_LDO1_ENA_WIDTH                        1  /* LDO1_ENA */
355 #define WM8400_LDO1_SWI                         0x4000  /* LDO1_SWI */
356 #define WM8400_LDO1_SWI_MASK                    0x4000  /* LDO1_SWI */
357 #define WM8400_LDO1_SWI_SHIFT                       14  /* LDO1_SWI */
358 #define WM8400_LDO1_SWI_WIDTH                        1  /* LDO1_SWI */
359 #define WM8400_LDO1_OPFLT                       0x1000  /* LDO1_OPFLT */
360 #define WM8400_LDO1_OPFLT_MASK                  0x1000  /* LDO1_OPFLT */
361 #define WM8400_LDO1_OPFLT_SHIFT                     12  /* LDO1_OPFLT */
362 #define WM8400_LDO1_OPFLT_WIDTH                      1  /* LDO1_OPFLT */
363 #define WM8400_LDO1_ERRACT                      0x0800  /* LDO1_ERRACT */
364 #define WM8400_LDO1_ERRACT_MASK                 0x0800  /* LDO1_ERRACT */
365 #define WM8400_LDO1_ERRACT_SHIFT                    11  /* LDO1_ERRACT */
366 #define WM8400_LDO1_ERRACT_WIDTH                     1  /* LDO1_ERRACT */
367 #define WM8400_LDO1_HIB_MODE                    0x0400  /* LDO1_HIB_MODE */
368 #define WM8400_LDO1_HIB_MODE_MASK               0x0400  /* LDO1_HIB_MODE */
369 #define WM8400_LDO1_HIB_MODE_SHIFT                  10  /* LDO1_HIB_MODE */
370 #define WM8400_LDO1_HIB_MODE_WIDTH                   1  /* LDO1_HIB_MODE */
371 #define WM8400_LDO1_VIMG_MASK                   0x03E0  /* LDO1_VIMG - [9:5] */
372 #define WM8400_LDO1_VIMG_SHIFT                       5  /* LDO1_VIMG - [9:5] */
373 #define WM8400_LDO1_VIMG_WIDTH                       5  /* LDO1_VIMG - [9:5] */
374 #define WM8400_LDO1_VSEL_MASK                   0x001F  /* LDO1_VSEL - [4:0] */
375 #define WM8400_LDO1_VSEL_SHIFT                       0  /* LDO1_VSEL - [4:0] */
376 #define WM8400_LDO1_VSEL_WIDTH                       5  /* LDO1_VSEL - [4:0] */
377 
378 /*
379  * R66 (0x42) - LDO 2 Control
380  */
381 #define WM8400_LDO2_ENA                         0x8000  /* LDO2_ENA */
382 #define WM8400_LDO2_ENA_MASK                    0x8000  /* LDO2_ENA */
383 #define WM8400_LDO2_ENA_SHIFT                       15  /* LDO2_ENA */
384 #define WM8400_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
385 #define WM8400_LDO2_SWI                         0x4000  /* LDO2_SWI */
386 #define WM8400_LDO2_SWI_MASK                    0x4000  /* LDO2_SWI */
387 #define WM8400_LDO2_SWI_SHIFT                       14  /* LDO2_SWI */
388 #define WM8400_LDO2_SWI_WIDTH                        1  /* LDO2_SWI */
389 #define WM8400_LDO2_OPFLT                       0x1000  /* LDO2_OPFLT */
390 #define WM8400_LDO2_OPFLT_MASK                  0x1000  /* LDO2_OPFLT */
391 #define WM8400_LDO2_OPFLT_SHIFT                     12  /* LDO2_OPFLT */
392 #define WM8400_LDO2_OPFLT_WIDTH                      1  /* LDO2_OPFLT */
393 #define WM8400_LDO2_ERRACT                      0x0800  /* LDO2_ERRACT */
394 #define WM8400_LDO2_ERRACT_MASK                 0x0800  /* LDO2_ERRACT */
395 #define WM8400_LDO2_ERRACT_SHIFT                    11  /* LDO2_ERRACT */
396 #define WM8400_LDO2_ERRACT_WIDTH                     1  /* LDO2_ERRACT */
397 #define WM8400_LDO2_HIB_MODE                    0x0400  /* LDO2_HIB_MODE */
398 #define WM8400_LDO2_HIB_MODE_MASK               0x0400  /* LDO2_HIB_MODE */
399 #define WM8400_LDO2_HIB_MODE_SHIFT                  10  /* LDO2_HIB_MODE */
400 #define WM8400_LDO2_HIB_MODE_WIDTH                   1  /* LDO2_HIB_MODE */
401 #define WM8400_LDO2_VIMG_MASK                   0x03E0  /* LDO2_VIMG - [9:5] */
402 #define WM8400_LDO2_VIMG_SHIFT                       5  /* LDO2_VIMG - [9:5] */
403 #define WM8400_LDO2_VIMG_WIDTH                       5  /* LDO2_VIMG - [9:5] */
404 #define WM8400_LDO2_VSEL_MASK                   0x001F  /* LDO2_VSEL - [4:0] */
405 #define WM8400_LDO2_VSEL_SHIFT                       0  /* LDO2_VSEL - [4:0] */
406 #define WM8400_LDO2_VSEL_WIDTH                       5  /* LDO2_VSEL - [4:0] */
407 
408 /*
409  * R67 (0x43) - LDO 3 Control
410  */
411 #define WM8400_LDO3_ENA                         0x8000  /* LDO3_ENA */
412 #define WM8400_LDO3_ENA_MASK                    0x8000  /* LDO3_ENA */
413 #define WM8400_LDO3_ENA_SHIFT                       15  /* LDO3_ENA */
414 #define WM8400_LDO3_ENA_WIDTH                        1  /* LDO3_ENA */
415 #define WM8400_LDO3_SWI                         0x4000  /* LDO3_SWI */
416 #define WM8400_LDO3_SWI_MASK                    0x4000  /* LDO3_SWI */
417 #define WM8400_LDO3_SWI_SHIFT                       14  /* LDO3_SWI */
418 #define WM8400_LDO3_SWI_WIDTH                        1  /* LDO3_SWI */
419 #define WM8400_LDO3_OPFLT                       0x1000  /* LDO3_OPFLT */
420 #define WM8400_LDO3_OPFLT_MASK                  0x1000  /* LDO3_OPFLT */
421 #define WM8400_LDO3_OPFLT_SHIFT                     12  /* LDO3_OPFLT */
422 #define WM8400_LDO3_OPFLT_WIDTH                      1  /* LDO3_OPFLT */
423 #define WM8400_LDO3_ERRACT                      0x0800  /* LDO3_ERRACT */
424 #define WM8400_LDO3_ERRACT_MASK                 0x0800  /* LDO3_ERRACT */
425 #define WM8400_LDO3_ERRACT_SHIFT                    11  /* LDO3_ERRACT */
426 #define WM8400_LDO3_ERRACT_WIDTH                     1  /* LDO3_ERRACT */
427 #define WM8400_LDO3_HIB_MODE                    0x0400  /* LDO3_HIB_MODE */
428 #define WM8400_LDO3_HIB_MODE_MASK               0x0400  /* LDO3_HIB_MODE */
429 #define WM8400_LDO3_HIB_MODE_SHIFT                  10  /* LDO3_HIB_MODE */
430 #define WM8400_LDO3_HIB_MODE_WIDTH                   1  /* LDO3_HIB_MODE */
431 #define WM8400_LDO3_VIMG_MASK                   0x03E0  /* LDO3_VIMG - [9:5] */
432 #define WM8400_LDO3_VIMG_SHIFT                       5  /* LDO3_VIMG - [9:5] */
433 #define WM8400_LDO3_VIMG_WIDTH                       5  /* LDO3_VIMG - [9:5] */
434 #define WM8400_LDO3_VSEL_MASK                   0x001F  /* LDO3_VSEL - [4:0] */
435 #define WM8400_LDO3_VSEL_SHIFT                       0  /* LDO3_VSEL - [4:0] */
436 #define WM8400_LDO3_VSEL_WIDTH                       5  /* LDO3_VSEL - [4:0] */
437 
438 /*
439  * R68 (0x44) - LDO 4 Control
440  */
441 #define WM8400_LDO4_ENA                         0x8000  /* LDO4_ENA */
442 #define WM8400_LDO4_ENA_MASK                    0x8000  /* LDO4_ENA */
443 #define WM8400_LDO4_ENA_SHIFT                       15  /* LDO4_ENA */
444 #define WM8400_LDO4_ENA_WIDTH                        1  /* LDO4_ENA */
445 #define WM8400_LDO4_SWI                         0x4000  /* LDO4_SWI */
446 #define WM8400_LDO4_SWI_MASK                    0x4000  /* LDO4_SWI */
447 #define WM8400_LDO4_SWI_SHIFT                       14  /* LDO4_SWI */
448 #define WM8400_LDO4_SWI_WIDTH                        1  /* LDO4_SWI */
449 #define WM8400_LDO4_OPFLT                       0x1000  /* LDO4_OPFLT */
450 #define WM8400_LDO4_OPFLT_MASK                  0x1000  /* LDO4_OPFLT */
451 #define WM8400_LDO4_OPFLT_SHIFT                     12  /* LDO4_OPFLT */
452 #define WM8400_LDO4_OPFLT_WIDTH                      1  /* LDO4_OPFLT */
453 #define WM8400_LDO4_ERRACT                      0x0800  /* LDO4_ERRACT */
454 #define WM8400_LDO4_ERRACT_MASK                 0x0800  /* LDO4_ERRACT */
455 #define WM8400_LDO4_ERRACT_SHIFT                    11  /* LDO4_ERRACT */
456 #define WM8400_LDO4_ERRACT_WIDTH                     1  /* LDO4_ERRACT */
457 #define WM8400_LDO4_HIB_MODE                    0x0400  /* LDO4_HIB_MODE */
458 #define WM8400_LDO4_HIB_MODE_MASK               0x0400  /* LDO4_HIB_MODE */
459 #define WM8400_LDO4_HIB_MODE_SHIFT                  10  /* LDO4_HIB_MODE */
460 #define WM8400_LDO4_HIB_MODE_WIDTH                   1  /* LDO4_HIB_MODE */
461 #define WM8400_LDO4_VIMG_MASK                   0x03E0  /* LDO4_VIMG - [9:5] */
462 #define WM8400_LDO4_VIMG_SHIFT                       5  /* LDO4_VIMG - [9:5] */
463 #define WM8400_LDO4_VIMG_WIDTH                       5  /* LDO4_VIMG - [9:5] */
464 #define WM8400_LDO4_VSEL_MASK                   0x001F  /* LDO4_VSEL - [4:0] */
465 #define WM8400_LDO4_VSEL_SHIFT                       0  /* LDO4_VSEL - [4:0] */
466 #define WM8400_LDO4_VSEL_WIDTH                       5  /* LDO4_VSEL - [4:0] */
467 
468 /*
469  * R70 (0x46) - DCDC1 Control 1
470  */
471 #define WM8400_DC1_ENA                          0x8000  /* DC1_ENA */
472 #define WM8400_DC1_ENA_MASK                     0x8000  /* DC1_ENA */
473 #define WM8400_DC1_ENA_SHIFT                        15  /* DC1_ENA */
474 #define WM8400_DC1_ENA_WIDTH                         1  /* DC1_ENA */
475 #define WM8400_DC1_ACTIVE                       0x4000  /* DC1_ACTIVE */
476 #define WM8400_DC1_ACTIVE_MASK                  0x4000  /* DC1_ACTIVE */
477 #define WM8400_DC1_ACTIVE_SHIFT                     14  /* DC1_ACTIVE */
478 #define WM8400_DC1_ACTIVE_WIDTH                      1  /* DC1_ACTIVE */
479 #define WM8400_DC1_SLEEP                        0x2000  /* DC1_SLEEP */
480 #define WM8400_DC1_SLEEP_MASK                   0x2000  /* DC1_SLEEP */
481 #define WM8400_DC1_SLEEP_SHIFT                      13  /* DC1_SLEEP */
482 #define WM8400_DC1_SLEEP_WIDTH                       1  /* DC1_SLEEP */
483 #define WM8400_DC1_OPFLT                        0x1000  /* DC1_OPFLT */
484 #define WM8400_DC1_OPFLT_MASK                   0x1000  /* DC1_OPFLT */
485 #define WM8400_DC1_OPFLT_SHIFT                      12  /* DC1_OPFLT */
486 #define WM8400_DC1_OPFLT_WIDTH                       1  /* DC1_OPFLT */
487 #define WM8400_DC1_ERRACT                       0x0800  /* DC1_ERRACT */
488 #define WM8400_DC1_ERRACT_MASK                  0x0800  /* DC1_ERRACT */
489 #define WM8400_DC1_ERRACT_SHIFT                     11  /* DC1_ERRACT */
490 #define WM8400_DC1_ERRACT_WIDTH                      1  /* DC1_ERRACT */
491 #define WM8400_DC1_HIB_MODE                     0x0400  /* DC1_HIB_MODE */
492 #define WM8400_DC1_HIB_MODE_MASK                0x0400  /* DC1_HIB_MODE */
493 #define WM8400_DC1_HIB_MODE_SHIFT                   10  /* DC1_HIB_MODE */
494 #define WM8400_DC1_HIB_MODE_WIDTH                    1  /* DC1_HIB_MODE */
495 #define WM8400_DC1_SOFTST_MASK                  0x0300  /* DC1_SOFTST - [9:8] */
496 #define WM8400_DC1_SOFTST_SHIFT                      8  /* DC1_SOFTST - [9:8] */
497 #define WM8400_DC1_SOFTST_WIDTH                      2  /* DC1_SOFTST - [9:8] */
498 #define WM8400_DC1_OV_PROT                      0x0080  /* DC1_OV_PROT */
499 #define WM8400_DC1_OV_PROT_MASK                 0x0080  /* DC1_OV_PROT */
500 #define WM8400_DC1_OV_PROT_SHIFT                     7  /* DC1_OV_PROT */
501 #define WM8400_DC1_OV_PROT_WIDTH                     1  /* DC1_OV_PROT */
502 #define WM8400_DC1_VSEL_MASK                    0x007F  /* DC1_VSEL - [6:0] */
503 #define WM8400_DC1_VSEL_SHIFT                        0  /* DC1_VSEL - [6:0] */
504 #define WM8400_DC1_VSEL_WIDTH                        7  /* DC1_VSEL - [6:0] */
505 
506 /*
507  * R71 (0x47) - DCDC1 Control 2
508  */
509 #define WM8400_DC1_FRC_PWM                      0x2000  /* DC1_FRC_PWM */
510 #define WM8400_DC1_FRC_PWM_MASK                 0x2000  /* DC1_FRC_PWM */
511 #define WM8400_DC1_FRC_PWM_SHIFT                    13  /* DC1_FRC_PWM */
512 #define WM8400_DC1_FRC_PWM_WIDTH                     1  /* DC1_FRC_PWM */
513 #define WM8400_DC1_STBY_LIM_MASK                0x0300  /* DC1_STBY_LIM - [9:8] */
514 #define WM8400_DC1_STBY_LIM_SHIFT                    8  /* DC1_STBY_LIM - [9:8] */
515 #define WM8400_DC1_STBY_LIM_WIDTH                    2  /* DC1_STBY_LIM - [9:8] */
516 #define WM8400_DC1_ACT_LIM                      0x0080  /* DC1_ACT_LIM */
517 #define WM8400_DC1_ACT_LIM_MASK                 0x0080  /* DC1_ACT_LIM */
518 #define WM8400_DC1_ACT_LIM_SHIFT                     7  /* DC1_ACT_LIM */
519 #define WM8400_DC1_ACT_LIM_WIDTH                     1  /* DC1_ACT_LIM */
520 #define WM8400_DC1_VIMG_MASK                    0x007F  /* DC1_VIMG - [6:0] */
521 #define WM8400_DC1_VIMG_SHIFT                        0  /* DC1_VIMG - [6:0] */
522 #define WM8400_DC1_VIMG_WIDTH                        7  /* DC1_VIMG - [6:0] */
523 
524 /*
525  * R72 (0x48) - DCDC2 Control 1
526  */
527 #define WM8400_DC2_ENA                          0x8000  /* DC2_ENA */
528 #define WM8400_DC2_ENA_MASK                     0x8000  /* DC2_ENA */
529 #define WM8400_DC2_ENA_SHIFT                        15  /* DC2_ENA */
530 #define WM8400_DC2_ENA_WIDTH                         1  /* DC2_ENA */
531 #define WM8400_DC2_ACTIVE                       0x4000  /* DC2_ACTIVE */
532 #define WM8400_DC2_ACTIVE_MASK                  0x4000  /* DC2_ACTIVE */
533 #define WM8400_DC2_ACTIVE_SHIFT                     14  /* DC2_ACTIVE */
534 #define WM8400_DC2_ACTIVE_WIDTH                      1  /* DC2_ACTIVE */
535 #define WM8400_DC2_SLEEP                        0x2000  /* DC2_SLEEP */
536 #define WM8400_DC2_SLEEP_MASK                   0x2000  /* DC2_SLEEP */
537 #define WM8400_DC2_SLEEP_SHIFT                      13  /* DC2_SLEEP */
538 #define WM8400_DC2_SLEEP_WIDTH                       1  /* DC2_SLEEP */
539 #define WM8400_DC2_OPFLT                        0x1000  /* DC2_OPFLT */
540 #define WM8400_DC2_OPFLT_MASK                   0x1000  /* DC2_OPFLT */
541 #define WM8400_DC2_OPFLT_SHIFT                      12  /* DC2_OPFLT */
542 #define WM8400_DC2_OPFLT_WIDTH                       1  /* DC2_OPFLT */
543 #define WM8400_DC2_ERRACT                       0x0800  /* DC2_ERRACT */
544 #define WM8400_DC2_ERRACT_MASK                  0x0800  /* DC2_ERRACT */
545 #define WM8400_DC2_ERRACT_SHIFT                     11  /* DC2_ERRACT */
546 #define WM8400_DC2_ERRACT_WIDTH                      1  /* DC2_ERRACT */
547 #define WM8400_DC2_HIB_MODE                     0x0400  /* DC2_HIB_MODE */
548 #define WM8400_DC2_HIB_MODE_MASK                0x0400  /* DC2_HIB_MODE */
549 #define WM8400_DC2_HIB_MODE_SHIFT                   10  /* DC2_HIB_MODE */
550 #define WM8400_DC2_HIB_MODE_WIDTH                    1  /* DC2_HIB_MODE */
551 #define WM8400_DC2_SOFTST_MASK                  0x0300  /* DC2_SOFTST - [9:8] */
552 #define WM8400_DC2_SOFTST_SHIFT                      8  /* DC2_SOFTST - [9:8] */
553 #define WM8400_DC2_SOFTST_WIDTH                      2  /* DC2_SOFTST - [9:8] */
554 #define WM8400_DC2_OV_PROT                      0x0080  /* DC2_OV_PROT */
555 #define WM8400_DC2_OV_PROT_MASK                 0x0080  /* DC2_OV_PROT */
556 #define WM8400_DC2_OV_PROT_SHIFT                     7  /* DC2_OV_PROT */
557 #define WM8400_DC2_OV_PROT_WIDTH                     1  /* DC2_OV_PROT */
558 #define WM8400_DC2_VSEL_MASK                    0x007F  /* DC2_VSEL - [6:0] */
559 #define WM8400_DC2_VSEL_SHIFT                        0  /* DC2_VSEL - [6:0] */
560 #define WM8400_DC2_VSEL_WIDTH                        7  /* DC2_VSEL - [6:0] */
561 
562 /*
563  * R73 (0x49) - DCDC2 Control 2
564  */
565 #define WM8400_DC2_FRC_PWM                      0x2000  /* DC2_FRC_PWM */
566 #define WM8400_DC2_FRC_PWM_MASK                 0x2000  /* DC2_FRC_PWM */
567 #define WM8400_DC2_FRC_PWM_SHIFT                    13  /* DC2_FRC_PWM */
568 #define WM8400_DC2_FRC_PWM_WIDTH                     1  /* DC2_FRC_PWM */
569 #define WM8400_DC2_STBY_LIM_MASK                0x0300  /* DC2_STBY_LIM - [9:8] */
570 #define WM8400_DC2_STBY_LIM_SHIFT                    8  /* DC2_STBY_LIM - [9:8] */
571 #define WM8400_DC2_STBY_LIM_WIDTH                    2  /* DC2_STBY_LIM - [9:8] */
572 #define WM8400_DC2_ACT_LIM                      0x0080  /* DC2_ACT_LIM */
573 #define WM8400_DC2_ACT_LIM_MASK                 0x0080  /* DC2_ACT_LIM */
574 #define WM8400_DC2_ACT_LIM_SHIFT                     7  /* DC2_ACT_LIM */
575 #define WM8400_DC2_ACT_LIM_WIDTH                     1  /* DC2_ACT_LIM */
576 #define WM8400_DC2_VIMG_MASK                    0x007F  /* DC2_VIMG - [6:0] */
577 #define WM8400_DC2_VIMG_SHIFT                        0  /* DC2_VIMG - [6:0] */
578 #define WM8400_DC2_VIMG_WIDTH                        7  /* DC2_VIMG - [6:0] */
579 
580 /*
581  * R75 (0x4B) - Interface
582  */
583 #define WM8400_AUTOINC                          0x0008  /* AUTOINC */
584 #define WM8400_AUTOINC_MASK                     0x0008  /* AUTOINC */
585 #define WM8400_AUTOINC_SHIFT                         3  /* AUTOINC */
586 #define WM8400_AUTOINC_WIDTH                         1  /* AUTOINC */
587 #define WM8400_ARA_ENA                          0x0004  /* ARA_ENA */
588 #define WM8400_ARA_ENA_MASK                     0x0004  /* ARA_ENA */
589 #define WM8400_ARA_ENA_SHIFT                         2  /* ARA_ENA */
590 #define WM8400_ARA_ENA_WIDTH                         1  /* ARA_ENA */
591 #define WM8400_SPI_CFG                          0x0002  /* SPI_CFG */
592 #define WM8400_SPI_CFG_MASK                     0x0002  /* SPI_CFG */
593 #define WM8400_SPI_CFG_SHIFT                         1  /* SPI_CFG */
594 #define WM8400_SPI_CFG_WIDTH                         1  /* SPI_CFG */
595 
596 /*
597  * R76 (0x4C) - PM GENERAL
598  */
599 #define WM8400_CODEC_SOFTST                     0x8000  /* CODEC_SOFTST */
600 #define WM8400_CODEC_SOFTST_MASK                0x8000  /* CODEC_SOFTST */
601 #define WM8400_CODEC_SOFTST_SHIFT                   15  /* CODEC_SOFTST */
602 #define WM8400_CODEC_SOFTST_WIDTH                    1  /* CODEC_SOFTST */
603 #define WM8400_CODEC_SOFTSD                     0x4000  /* CODEC_SOFTSD */
604 #define WM8400_CODEC_SOFTSD_MASK                0x4000  /* CODEC_SOFTSD */
605 #define WM8400_CODEC_SOFTSD_SHIFT                   14  /* CODEC_SOFTSD */
606 #define WM8400_CODEC_SOFTSD_WIDTH                    1  /* CODEC_SOFTSD */
607 #define WM8400_CHIP_SOFTSD                      0x2000  /* CHIP_SOFTSD */
608 #define WM8400_CHIP_SOFTSD_MASK                 0x2000  /* CHIP_SOFTSD */
609 #define WM8400_CHIP_SOFTSD_SHIFT                    13  /* CHIP_SOFTSD */
610 #define WM8400_CHIP_SOFTSD_WIDTH                     1  /* CHIP_SOFTSD */
611 #define WM8400_DSLEEP1_POL                      0x0008  /* DSLEEP1_POL */
612 #define WM8400_DSLEEP1_POL_MASK                 0x0008  /* DSLEEP1_POL */
613 #define WM8400_DSLEEP1_POL_SHIFT                     3  /* DSLEEP1_POL */
614 #define WM8400_DSLEEP1_POL_WIDTH                     1  /* DSLEEP1_POL */
615 #define WM8400_DSLEEP2_POL                      0x0004  /* DSLEEP2_POL */
616 #define WM8400_DSLEEP2_POL_MASK                 0x0004  /* DSLEEP2_POL */
617 #define WM8400_DSLEEP2_POL_SHIFT                     2  /* DSLEEP2_POL */
618 #define WM8400_DSLEEP2_POL_WIDTH                     1  /* DSLEEP2_POL */
619 #define WM8400_PWR_STATE_MASK                   0x0003  /* PWR_STATE - [1:0] */
620 #define WM8400_PWR_STATE_SHIFT                       0  /* PWR_STATE - [1:0] */
621 #define WM8400_PWR_STATE_WIDTH                       2  /* PWR_STATE - [1:0] */
622 
623 /*
624  * R78 (0x4E) - PM Shutdown Control
625  */
626 #define WM8400_CHIP_GT150_ERRACT                0x0200  /* CHIP_GT150_ERRACT */
627 #define WM8400_CHIP_GT150_ERRACT_MASK           0x0200  /* CHIP_GT150_ERRACT */
628 #define WM8400_CHIP_GT150_ERRACT_SHIFT               9  /* CHIP_GT150_ERRACT */
629 #define WM8400_CHIP_GT150_ERRACT_WIDTH               1  /* CHIP_GT150_ERRACT */
630 #define WM8400_CHIP_GT115_ERRACT                0x0100  /* CHIP_GT115_ERRACT */
631 #define WM8400_CHIP_GT115_ERRACT_MASK           0x0100  /* CHIP_GT115_ERRACT */
632 #define WM8400_CHIP_GT115_ERRACT_SHIFT               8  /* CHIP_GT115_ERRACT */
633 #define WM8400_CHIP_GT115_ERRACT_WIDTH               1  /* CHIP_GT115_ERRACT */
634 #define WM8400_LINE_CMP_ERRACT                  0x0080  /* LINE_CMP_ERRACT */
635 #define WM8400_LINE_CMP_ERRACT_MASK             0x0080  /* LINE_CMP_ERRACT */
636 #define WM8400_LINE_CMP_ERRACT_SHIFT                 7  /* LINE_CMP_ERRACT */
637 #define WM8400_LINE_CMP_ERRACT_WIDTH                 1  /* LINE_CMP_ERRACT */
638 #define WM8400_UVLO_ERRACT                      0x0040  /* UVLO_ERRACT */
639 #define WM8400_UVLO_ERRACT_MASK                 0x0040  /* UVLO_ERRACT */
640 #define WM8400_UVLO_ERRACT_SHIFT                     6  /* UVLO_ERRACT */
641 #define WM8400_UVLO_ERRACT_WIDTH                     1  /* UVLO_ERRACT */
642 
643 /*
644  * R79 (0x4F) - Interrupt Status 1
645  */
646 #define WM8400_MICD_CINT                        0x8000  /* MICD_CINT */
647 #define WM8400_MICD_CINT_MASK                   0x8000  /* MICD_CINT */
648 #define WM8400_MICD_CINT_SHIFT                      15  /* MICD_CINT */
649 #define WM8400_MICD_CINT_WIDTH                       1  /* MICD_CINT */
650 #define WM8400_MICSCD_CINT                      0x4000  /* MICSCD_CINT */
651 #define WM8400_MICSCD_CINT_MASK                 0x4000  /* MICSCD_CINT */
652 #define WM8400_MICSCD_CINT_SHIFT                    14  /* MICSCD_CINT */
653 #define WM8400_MICSCD_CINT_WIDTH                     1  /* MICSCD_CINT */
654 #define WM8400_JDL_CINT                         0x2000  /* JDL_CINT */
655 #define WM8400_JDL_CINT_MASK                    0x2000  /* JDL_CINT */
656 #define WM8400_JDL_CINT_SHIFT                       13  /* JDL_CINT */
657 #define WM8400_JDL_CINT_WIDTH                        1  /* JDL_CINT */
658 #define WM8400_JDR_CINT                         0x1000  /* JDR_CINT */
659 #define WM8400_JDR_CINT_MASK                    0x1000  /* JDR_CINT */
660 #define WM8400_JDR_CINT_SHIFT                       12  /* JDR_CINT */
661 #define WM8400_JDR_CINT_WIDTH                        1  /* JDR_CINT */
662 #define WM8400_CODEC_SEQ_END_EINT               0x0800  /* CODEC_SEQ_END_EINT */
663 #define WM8400_CODEC_SEQ_END_EINT_MASK          0x0800  /* CODEC_SEQ_END_EINT */
664 #define WM8400_CODEC_SEQ_END_EINT_SHIFT             11  /* CODEC_SEQ_END_EINT */
665 #define WM8400_CODEC_SEQ_END_EINT_WIDTH              1  /* CODEC_SEQ_END_EINT */
666 #define WM8400_CDEL_TO_EINT                     0x0400  /* CDEL_TO_EINT */
667 #define WM8400_CDEL_TO_EINT_MASK                0x0400  /* CDEL_TO_EINT */
668 #define WM8400_CDEL_TO_EINT_SHIFT                   10  /* CDEL_TO_EINT */
669 #define WM8400_CDEL_TO_EINT_WIDTH                    1  /* CDEL_TO_EINT */
670 #define WM8400_CHIP_GT150_EINT                  0x0200  /* CHIP_GT150_EINT */
671 #define WM8400_CHIP_GT150_EINT_MASK             0x0200  /* CHIP_GT150_EINT */
672 #define WM8400_CHIP_GT150_EINT_SHIFT                 9  /* CHIP_GT150_EINT */
673 #define WM8400_CHIP_GT150_EINT_WIDTH                 1  /* CHIP_GT150_EINT */
674 #define WM8400_CHIP_GT115_EINT                  0x0100  /* CHIP_GT115_EINT */
675 #define WM8400_CHIP_GT115_EINT_MASK             0x0100  /* CHIP_GT115_EINT */
676 #define WM8400_CHIP_GT115_EINT_SHIFT                 8  /* CHIP_GT115_EINT */
677 #define WM8400_CHIP_GT115_EINT_WIDTH                 1  /* CHIP_GT115_EINT */
678 #define WM8400_LINE_CMP_EINT                    0x0080  /* LINE_CMP_EINT */
679 #define WM8400_LINE_CMP_EINT_MASK               0x0080  /* LINE_CMP_EINT */
680 #define WM8400_LINE_CMP_EINT_SHIFT                   7  /* LINE_CMP_EINT */
681 #define WM8400_LINE_CMP_EINT_WIDTH                   1  /* LINE_CMP_EINT */
682 #define WM8400_UVLO_EINT                        0x0040  /* UVLO_EINT */
683 #define WM8400_UVLO_EINT_MASK                   0x0040  /* UVLO_EINT */
684 #define WM8400_UVLO_EINT_SHIFT                       6  /* UVLO_EINT */
685 #define WM8400_UVLO_EINT_WIDTH                       1  /* UVLO_EINT */
686 #define WM8400_DC2_UV_EINT                      0x0020  /* DC2_UV_EINT */
687 #define WM8400_DC2_UV_EINT_MASK                 0x0020  /* DC2_UV_EINT */
688 #define WM8400_DC2_UV_EINT_SHIFT                     5  /* DC2_UV_EINT */
689 #define WM8400_DC2_UV_EINT_WIDTH                     1  /* DC2_UV_EINT */
690 #define WM8400_DC1_UV_EINT                      0x0010  /* DC1_UV_EINT */
691 #define WM8400_DC1_UV_EINT_MASK                 0x0010  /* DC1_UV_EINT */
692 #define WM8400_DC1_UV_EINT_SHIFT                     4  /* DC1_UV_EINT */
693 #define WM8400_DC1_UV_EINT_WIDTH                     1  /* DC1_UV_EINT */
694 #define WM8400_LDO4_UV_EINT                     0x0008  /* LDO4_UV_EINT */
695 #define WM8400_LDO4_UV_EINT_MASK                0x0008  /* LDO4_UV_EINT */
696 #define WM8400_LDO4_UV_EINT_SHIFT                    3  /* LDO4_UV_EINT */
697 #define WM8400_LDO4_UV_EINT_WIDTH                    1  /* LDO4_UV_EINT */
698 #define WM8400_LDO3_UV_EINT                     0x0004  /* LDO3_UV_EINT */
699 #define WM8400_LDO3_UV_EINT_MASK                0x0004  /* LDO3_UV_EINT */
700 #define WM8400_LDO3_UV_EINT_SHIFT                    2  /* LDO3_UV_EINT */
701 #define WM8400_LDO3_UV_EINT_WIDTH                    1  /* LDO3_UV_EINT */
702 #define WM8400_LDO2_UV_EINT                     0x0002  /* LDO2_UV_EINT */
703 #define WM8400_LDO2_UV_EINT_MASK                0x0002  /* LDO2_UV_EINT */
704 #define WM8400_LDO2_UV_EINT_SHIFT                    1  /* LDO2_UV_EINT */
705 #define WM8400_LDO2_UV_EINT_WIDTH                    1  /* LDO2_UV_EINT */
706 #define WM8400_LDO1_UV_EINT                     0x0001  /* LDO1_UV_EINT */
707 #define WM8400_LDO1_UV_EINT_MASK                0x0001  /* LDO1_UV_EINT */
708 #define WM8400_LDO1_UV_EINT_SHIFT                    0  /* LDO1_UV_EINT */
709 #define WM8400_LDO1_UV_EINT_WIDTH                    1  /* LDO1_UV_EINT */
710 
711 /*
712  * R80 (0x50) - Interrupt Status 1 Mask
713  */
714 #define WM8400_IM_MICD_CINT                     0x8000  /* IM_MICD_CINT */
715 #define WM8400_IM_MICD_CINT_MASK                0x8000  /* IM_MICD_CINT */
716 #define WM8400_IM_MICD_CINT_SHIFT                   15  /* IM_MICD_CINT */
717 #define WM8400_IM_MICD_CINT_WIDTH                    1  /* IM_MICD_CINT */
718 #define WM8400_IM_MICSCD_CINT                   0x4000  /* IM_MICSCD_CINT */
719 #define WM8400_IM_MICSCD_CINT_MASK              0x4000  /* IM_MICSCD_CINT */
720 #define WM8400_IM_MICSCD_CINT_SHIFT                 14  /* IM_MICSCD_CINT */
721 #define WM8400_IM_MICSCD_CINT_WIDTH                  1  /* IM_MICSCD_CINT */
722 #define WM8400_IM_JDL_CINT                      0x2000  /* IM_JDL_CINT */
723 #define WM8400_IM_JDL_CINT_MASK                 0x2000  /* IM_JDL_CINT */
724 #define WM8400_IM_JDL_CINT_SHIFT                    13  /* IM_JDL_CINT */
725 #define WM8400_IM_JDL_CINT_WIDTH                     1  /* IM_JDL_CINT */
726 #define WM8400_IM_JDR_CINT                      0x1000  /* IM_JDR_CINT */
727 #define WM8400_IM_JDR_CINT_MASK                 0x1000  /* IM_JDR_CINT */
728 #define WM8400_IM_JDR_CINT_SHIFT                    12  /* IM_JDR_CINT */
729 #define WM8400_IM_JDR_CINT_WIDTH                     1  /* IM_JDR_CINT */
730 #define WM8400_IM_CODEC_SEQ_END_EINT            0x0800  /* IM_CODEC_SEQ_END_EINT */
731 #define WM8400_IM_CODEC_SEQ_END_EINT_MASK       0x0800  /* IM_CODEC_SEQ_END_EINT */
732 #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT          11  /* IM_CODEC_SEQ_END_EINT */
733 #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH           1  /* IM_CODEC_SEQ_END_EINT */
734 #define WM8400_IM_CDEL_TO_EINT                  0x0400  /* IM_CDEL_TO_EINT */
735 #define WM8400_IM_CDEL_TO_EINT_MASK             0x0400  /* IM_CDEL_TO_EINT */
736 #define WM8400_IM_CDEL_TO_EINT_SHIFT                10  /* IM_CDEL_TO_EINT */
737 #define WM8400_IM_CDEL_TO_EINT_WIDTH                 1  /* IM_CDEL_TO_EINT */
738 #define WM8400_IM_CHIP_GT150_EINT               0x0200  /* IM_CHIP_GT150_EINT */
739 #define WM8400_IM_CHIP_GT150_EINT_MASK          0x0200  /* IM_CHIP_GT150_EINT */
740 #define WM8400_IM_CHIP_GT150_EINT_SHIFT              9  /* IM_CHIP_GT150_EINT */
741 #define WM8400_IM_CHIP_GT150_EINT_WIDTH              1  /* IM_CHIP_GT150_EINT */
742 #define WM8400_IM_CHIP_GT115_EINT               0x0100  /* IM_CHIP_GT115_EINT */
743 #define WM8400_IM_CHIP_GT115_EINT_MASK          0x0100  /* IM_CHIP_GT115_EINT */
744 #define WM8400_IM_CHIP_GT115_EINT_SHIFT              8  /* IM_CHIP_GT115_EINT */
745 #define WM8400_IM_CHIP_GT115_EINT_WIDTH              1  /* IM_CHIP_GT115_EINT */
746 #define WM8400_IM_LINE_CMP_EINT                 0x0080  /* IM_LINE_CMP_EINT */
747 #define WM8400_IM_LINE_CMP_EINT_MASK            0x0080  /* IM_LINE_CMP_EINT */
748 #define WM8400_IM_LINE_CMP_EINT_SHIFT                7  /* IM_LINE_CMP_EINT */
749 #define WM8400_IM_LINE_CMP_EINT_WIDTH                1  /* IM_LINE_CMP_EINT */
750 #define WM8400_IM_UVLO_EINT                     0x0040  /* IM_UVLO_EINT */
751 #define WM8400_IM_UVLO_EINT_MASK                0x0040  /* IM_UVLO_EINT */
752 #define WM8400_IM_UVLO_EINT_SHIFT                    6  /* IM_UVLO_EINT */
753 #define WM8400_IM_UVLO_EINT_WIDTH                    1  /* IM_UVLO_EINT */
754 #define WM8400_IM_DC2_UV_EINT                   0x0020  /* IM_DC2_UV_EINT */
755 #define WM8400_IM_DC2_UV_EINT_MASK              0x0020  /* IM_DC2_UV_EINT */
756 #define WM8400_IM_DC2_UV_EINT_SHIFT                  5  /* IM_DC2_UV_EINT */
757 #define WM8400_IM_DC2_UV_EINT_WIDTH                  1  /* IM_DC2_UV_EINT */
758 #define WM8400_IM_DC1_UV_EINT                   0x0010  /* IM_DC1_UV_EINT */
759 #define WM8400_IM_DC1_UV_EINT_MASK              0x0010  /* IM_DC1_UV_EINT */
760 #define WM8400_IM_DC1_UV_EINT_SHIFT                  4  /* IM_DC1_UV_EINT */
761 #define WM8400_IM_DC1_UV_EINT_WIDTH                  1  /* IM_DC1_UV_EINT */
762 #define WM8400_IM_LDO4_UV_EINT                  0x0008  /* IM_LDO4_UV_EINT */
763 #define WM8400_IM_LDO4_UV_EINT_MASK             0x0008  /* IM_LDO4_UV_EINT */
764 #define WM8400_IM_LDO4_UV_EINT_SHIFT                 3  /* IM_LDO4_UV_EINT */
765 #define WM8400_IM_LDO4_UV_EINT_WIDTH                 1  /* IM_LDO4_UV_EINT */
766 #define WM8400_IM_LDO3_UV_EINT                  0x0004  /* IM_LDO3_UV_EINT */
767 #define WM8400_IM_LDO3_UV_EINT_MASK             0x0004  /* IM_LDO3_UV_EINT */
768 #define WM8400_IM_LDO3_UV_EINT_SHIFT                 2  /* IM_LDO3_UV_EINT */
769 #define WM8400_IM_LDO3_UV_EINT_WIDTH                 1  /* IM_LDO3_UV_EINT */
770 #define WM8400_IM_LDO2_UV_EINT                  0x0002  /* IM_LDO2_UV_EINT */
771 #define WM8400_IM_LDO2_UV_EINT_MASK             0x0002  /* IM_LDO2_UV_EINT */
772 #define WM8400_IM_LDO2_UV_EINT_SHIFT                 1  /* IM_LDO2_UV_EINT */
773 #define WM8400_IM_LDO2_UV_EINT_WIDTH                 1  /* IM_LDO2_UV_EINT */
774 #define WM8400_IM_LDO1_UV_EINT                  0x0001  /* IM_LDO1_UV_EINT */
775 #define WM8400_IM_LDO1_UV_EINT_MASK             0x0001  /* IM_LDO1_UV_EINT */
776 #define WM8400_IM_LDO1_UV_EINT_SHIFT                 0  /* IM_LDO1_UV_EINT */
777 #define WM8400_IM_LDO1_UV_EINT_WIDTH                 1  /* IM_LDO1_UV_EINT */
778 
779 /*
780  * R81 (0x51) - Interrupt Levels
781  */
782 #define WM8400_MICD_LVL                         0x8000  /* MICD_LVL */
783 #define WM8400_MICD_LVL_MASK                    0x8000  /* MICD_LVL */
784 #define WM8400_MICD_LVL_SHIFT                       15  /* MICD_LVL */
785 #define WM8400_MICD_LVL_WIDTH                        1  /* MICD_LVL */
786 #define WM8400_MICSCD_LVL                       0x4000  /* MICSCD_LVL */
787 #define WM8400_MICSCD_LVL_MASK                  0x4000  /* MICSCD_LVL */
788 #define WM8400_MICSCD_LVL_SHIFT                     14  /* MICSCD_LVL */
789 #define WM8400_MICSCD_LVL_WIDTH                      1  /* MICSCD_LVL */
790 #define WM8400_JDL_LVL                          0x2000  /* JDL_LVL */
791 #define WM8400_JDL_LVL_MASK                     0x2000  /* JDL_LVL */
792 #define WM8400_JDL_LVL_SHIFT                        13  /* JDL_LVL */
793 #define WM8400_JDL_LVL_WIDTH                         1  /* JDL_LVL */
794 #define WM8400_JDR_LVL                          0x1000  /* JDR_LVL */
795 #define WM8400_JDR_LVL_MASK                     0x1000  /* JDR_LVL */
796 #define WM8400_JDR_LVL_SHIFT                        12  /* JDR_LVL */
797 #define WM8400_JDR_LVL_WIDTH                         1  /* JDR_LVL */
798 #define WM8400_CODEC_SEQ_END_LVL                0x0800  /* CODEC_SEQ_END_LVL */
799 #define WM8400_CODEC_SEQ_END_LVL_MASK           0x0800  /* CODEC_SEQ_END_LVL */
800 #define WM8400_CODEC_SEQ_END_LVL_SHIFT              11  /* CODEC_SEQ_END_LVL */
801 #define WM8400_CODEC_SEQ_END_LVL_WIDTH               1  /* CODEC_SEQ_END_LVL */
802 #define WM8400_CDEL_TO_LVL                      0x0400  /* CDEL_TO_LVL */
803 #define WM8400_CDEL_TO_LVL_MASK                 0x0400  /* CDEL_TO_LVL */
804 #define WM8400_CDEL_TO_LVL_SHIFT                    10  /* CDEL_TO_LVL */
805 #define WM8400_CDEL_TO_LVL_WIDTH                     1  /* CDEL_TO_LVL */
806 #define WM8400_CHIP_GT150_LVL                   0x0200  /* CHIP_GT150_LVL */
807 #define WM8400_CHIP_GT150_LVL_MASK              0x0200  /* CHIP_GT150_LVL */
808 #define WM8400_CHIP_GT150_LVL_SHIFT                  9  /* CHIP_GT150_LVL */
809 #define WM8400_CHIP_GT150_LVL_WIDTH                  1  /* CHIP_GT150_LVL */
810 #define WM8400_CHIP_GT115_LVL                   0x0100  /* CHIP_GT115_LVL */
811 #define WM8400_CHIP_GT115_LVL_MASK              0x0100  /* CHIP_GT115_LVL */
812 #define WM8400_CHIP_GT115_LVL_SHIFT                  8  /* CHIP_GT115_LVL */
813 #define WM8400_CHIP_GT115_LVL_WIDTH                  1  /* CHIP_GT115_LVL */
814 #define WM8400_LINE_CMP_LVL                     0x0080  /* LINE_CMP_LVL */
815 #define WM8400_LINE_CMP_LVL_MASK                0x0080  /* LINE_CMP_LVL */
816 #define WM8400_LINE_CMP_LVL_SHIFT                    7  /* LINE_CMP_LVL */
817 #define WM8400_LINE_CMP_LVL_WIDTH                    1  /* LINE_CMP_LVL */
818 #define WM8400_UVLO_LVL                         0x0040  /* UVLO_LVL */
819 #define WM8400_UVLO_LVL_MASK                    0x0040  /* UVLO_LVL */
820 #define WM8400_UVLO_LVL_SHIFT                        6  /* UVLO_LVL */
821 #define WM8400_UVLO_LVL_WIDTH                        1  /* UVLO_LVL */
822 #define WM8400_DC2_UV_LVL                       0x0020  /* DC2_UV_LVL */
823 #define WM8400_DC2_UV_LVL_MASK                  0x0020  /* DC2_UV_LVL */
824 #define WM8400_DC2_UV_LVL_SHIFT                      5  /* DC2_UV_LVL */
825 #define WM8400_DC2_UV_LVL_WIDTH                      1  /* DC2_UV_LVL */
826 #define WM8400_DC1_UV_LVL                       0x0010  /* DC1_UV_LVL */
827 #define WM8400_DC1_UV_LVL_MASK                  0x0010  /* DC1_UV_LVL */
828 #define WM8400_DC1_UV_LVL_SHIFT                      4  /* DC1_UV_LVL */
829 #define WM8400_DC1_UV_LVL_WIDTH                      1  /* DC1_UV_LVL */
830 #define WM8400_LDO4_UV_LVL                      0x0008  /* LDO4_UV_LVL */
831 #define WM8400_LDO4_UV_LVL_MASK                 0x0008  /* LDO4_UV_LVL */
832 #define WM8400_LDO4_UV_LVL_SHIFT                     3  /* LDO4_UV_LVL */
833 #define WM8400_LDO4_UV_LVL_WIDTH                     1  /* LDO4_UV_LVL */
834 #define WM8400_LDO3_UV_LVL                      0x0004  /* LDO3_UV_LVL */
835 #define WM8400_LDO3_UV_LVL_MASK                 0x0004  /* LDO3_UV_LVL */
836 #define WM8400_LDO3_UV_LVL_SHIFT                     2  /* LDO3_UV_LVL */
837 #define WM8400_LDO3_UV_LVL_WIDTH                     1  /* LDO3_UV_LVL */
838 #define WM8400_LDO2_UV_LVL                      0x0002  /* LDO2_UV_LVL */
839 #define WM8400_LDO2_UV_LVL_MASK                 0x0002  /* LDO2_UV_LVL */
840 #define WM8400_LDO2_UV_LVL_SHIFT                     1  /* LDO2_UV_LVL */
841 #define WM8400_LDO2_UV_LVL_WIDTH                     1  /* LDO2_UV_LVL */
842 #define WM8400_LDO1_UV_LVL                      0x0001  /* LDO1_UV_LVL */
843 #define WM8400_LDO1_UV_LVL_MASK                 0x0001  /* LDO1_UV_LVL */
844 #define WM8400_LDO1_UV_LVL_SHIFT                     0  /* LDO1_UV_LVL */
845 #define WM8400_LDO1_UV_LVL_WIDTH                     1  /* LDO1_UV_LVL */
846 
847 /*
848  * R82 (0x52) - Shutdown Reason
849  */
850 #define WM8400_SDR_CHIP_SOFTSD                  0x2000  /* SDR_CHIP_SOFTSD */
851 #define WM8400_SDR_CHIP_SOFTSD_MASK             0x2000  /* SDR_CHIP_SOFTSD */
852 #define WM8400_SDR_CHIP_SOFTSD_SHIFT                13  /* SDR_CHIP_SOFTSD */
853 #define WM8400_SDR_CHIP_SOFTSD_WIDTH                 1  /* SDR_CHIP_SOFTSD */
854 #define WM8400_SDR_NPDN                         0x0800  /* SDR_NPDN */
855 #define WM8400_SDR_NPDN_MASK                    0x0800  /* SDR_NPDN */
856 #define WM8400_SDR_NPDN_SHIFT                       11  /* SDR_NPDN */
857 #define WM8400_SDR_NPDN_WIDTH                        1  /* SDR_NPDN */
858 #define WM8400_SDR_CHIP_GT150                   0x0200  /* SDR_CHIP_GT150 */
859 #define WM8400_SDR_CHIP_GT150_MASK              0x0200  /* SDR_CHIP_GT150 */
860 #define WM8400_SDR_CHIP_GT150_SHIFT                  9  /* SDR_CHIP_GT150 */
861 #define WM8400_SDR_CHIP_GT150_WIDTH                  1  /* SDR_CHIP_GT150 */
862 #define WM8400_SDR_CHIP_GT115                   0x0100  /* SDR_CHIP_GT115 */
863 #define WM8400_SDR_CHIP_GT115_MASK              0x0100  /* SDR_CHIP_GT115 */
864 #define WM8400_SDR_CHIP_GT115_SHIFT                  8  /* SDR_CHIP_GT115 */
865 #define WM8400_SDR_CHIP_GT115_WIDTH                  1  /* SDR_CHIP_GT115 */
866 #define WM8400_SDR_LINE_CMP                     0x0080  /* SDR_LINE_CMP */
867 #define WM8400_SDR_LINE_CMP_MASK                0x0080  /* SDR_LINE_CMP */
868 #define WM8400_SDR_LINE_CMP_SHIFT                    7  /* SDR_LINE_CMP */
869 #define WM8400_SDR_LINE_CMP_WIDTH                    1  /* SDR_LINE_CMP */
870 #define WM8400_SDR_UVLO                         0x0040  /* SDR_UVLO */
871 #define WM8400_SDR_UVLO_MASK                    0x0040  /* SDR_UVLO */
872 #define WM8400_SDR_UVLO_SHIFT                        6  /* SDR_UVLO */
873 #define WM8400_SDR_UVLO_WIDTH                        1  /* SDR_UVLO */
874 #define WM8400_SDR_DC2_UV                       0x0020  /* SDR_DC2_UV */
875 #define WM8400_SDR_DC2_UV_MASK                  0x0020  /* SDR_DC2_UV */
876 #define WM8400_SDR_DC2_UV_SHIFT                      5  /* SDR_DC2_UV */
877 #define WM8400_SDR_DC2_UV_WIDTH                      1  /* SDR_DC2_UV */
878 #define WM8400_SDR_DC1_UV                       0x0010  /* SDR_DC1_UV */
879 #define WM8400_SDR_DC1_UV_MASK                  0x0010  /* SDR_DC1_UV */
880 #define WM8400_SDR_DC1_UV_SHIFT                      4  /* SDR_DC1_UV */
881 #define WM8400_SDR_DC1_UV_WIDTH                      1  /* SDR_DC1_UV */
882 #define WM8400_SDR_LDO4_UV                      0x0008  /* SDR_LDO4_UV */
883 #define WM8400_SDR_LDO4_UV_MASK                 0x0008  /* SDR_LDO4_UV */
884 #define WM8400_SDR_LDO4_UV_SHIFT                     3  /* SDR_LDO4_UV */
885 #define WM8400_SDR_LDO4_UV_WIDTH                     1  /* SDR_LDO4_UV */
886 #define WM8400_SDR_LDO3_UV                      0x0004  /* SDR_LDO3_UV */
887 #define WM8400_SDR_LDO3_UV_MASK                 0x0004  /* SDR_LDO3_UV */
888 #define WM8400_SDR_LDO3_UV_SHIFT                     2  /* SDR_LDO3_UV */
889 #define WM8400_SDR_LDO3_UV_WIDTH                     1  /* SDR_LDO3_UV */
890 #define WM8400_SDR_LDO2_UV                      0x0002  /* SDR_LDO2_UV */
891 #define WM8400_SDR_LDO2_UV_MASK                 0x0002  /* SDR_LDO2_UV */
892 #define WM8400_SDR_LDO2_UV_SHIFT                     1  /* SDR_LDO2_UV */
893 #define WM8400_SDR_LDO2_UV_WIDTH                     1  /* SDR_LDO2_UV */
894 #define WM8400_SDR_LDO1_UV                      0x0001  /* SDR_LDO1_UV */
895 #define WM8400_SDR_LDO1_UV_MASK                 0x0001  /* SDR_LDO1_UV */
896 #define WM8400_SDR_LDO1_UV_SHIFT                     0  /* SDR_LDO1_UV */
897 #define WM8400_SDR_LDO1_UV_WIDTH                     1  /* SDR_LDO1_UV */
898 
899 /*
900  * R84 (0x54) - Line Circuits
901  */
902 #define WM8400_BG_LINE_COMP                     0x8000  /* BG_LINE_COMP */
903 #define WM8400_BG_LINE_COMP_MASK                0x8000  /* BG_LINE_COMP */
904 #define WM8400_BG_LINE_COMP_SHIFT                   15  /* BG_LINE_COMP */
905 #define WM8400_BG_LINE_COMP_WIDTH                    1  /* BG_LINE_COMP */
906 #define WM8400_LINE_CMP_VTHI_MASK               0x00F0  /* LINE_CMP_VTHI - [7:4] */
907 #define WM8400_LINE_CMP_VTHI_SHIFT                   4  /* LINE_CMP_VTHI - [7:4] */
908 #define WM8400_LINE_CMP_VTHI_WIDTH                   4  /* LINE_CMP_VTHI - [7:4] */
909 #define WM8400_LINE_CMP_VTHD_MASK               0x000F  /* LINE_CMP_VTHD - [3:0] */
910 #define WM8400_LINE_CMP_VTHD_SHIFT                   0  /* LINE_CMP_VTHD - [3:0] */
911 #define WM8400_LINE_CMP_VTHD_WIDTH                   4  /* LINE_CMP_VTHD - [3:0] */
912 
913 #endif
914 

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