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TOMOYO Linux Cross Reference
Linux/include/linux/mlx4/device.h

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  1 /*
  2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
  3  *
  4  * This software is available to you under a choice of one of two
  5  * licenses.  You may choose to be licensed under the terms of the GNU
  6  * General Public License (GPL) Version 2, available from the file
  7  * COPYING in the main directory of this source tree, or the
  8  * OpenIB.org BSD license below:
  9  *
 10  *     Redistribution and use in source and binary forms, with or
 11  *     without modification, are permitted provided that the following
 12  *     conditions are met:
 13  *
 14  *      - Redistributions of source code must retain the above
 15  *        copyright notice, this list of conditions and the following
 16  *        disclaimer.
 17  *
 18  *      - Redistributions in binary form must reproduce the above
 19  *        copyright notice, this list of conditions and the following
 20  *        disclaimer in the documentation and/or other materials
 21  *        provided with the distribution.
 22  *
 23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30  * SOFTWARE.
 31  */
 32 
 33 #ifndef MLX4_DEVICE_H
 34 #define MLX4_DEVICE_H
 35 
 36 #include <linux/pci.h>
 37 #include <linux/completion.h>
 38 #include <linux/radix-tree.h>
 39 
 40 #include <asm/atomic.h>
 41 
 42 enum {
 43         MLX4_FLAG_MSI_X         = 1 << 0,
 44         MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
 45 };
 46 
 47 enum {
 48         MLX4_MAX_PORTS          = 2
 49 };
 50 
 51 enum {
 52         MLX4_BOARD_ID_LEN = 64
 53 };
 54 
 55 enum {
 56         MLX4_DEV_CAP_FLAG_RC            = 1 <<  0,
 57         MLX4_DEV_CAP_FLAG_UC            = 1 <<  1,
 58         MLX4_DEV_CAP_FLAG_UD            = 1 <<  2,
 59         MLX4_DEV_CAP_FLAG_SRQ           = 1 <<  6,
 60         MLX4_DEV_CAP_FLAG_IPOIB_CSUM    = 1 <<  7,
 61         MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 <<  8,
 62         MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 <<  9,
 63         MLX4_DEV_CAP_FLAG_DPDP          = 1 << 12,
 64         MLX4_DEV_CAP_FLAG_MEM_WINDOW    = 1 << 16,
 65         MLX4_DEV_CAP_FLAG_APM           = 1 << 17,
 66         MLX4_DEV_CAP_FLAG_ATOMIC        = 1 << 18,
 67         MLX4_DEV_CAP_FLAG_RAW_MCAST     = 1 << 19,
 68         MLX4_DEV_CAP_FLAG_UD_AV_PORT    = 1 << 20,
 69         MLX4_DEV_CAP_FLAG_UD_MCAST      = 1 << 21
 70 };
 71 
 72 enum {
 73         MLX4_BMME_FLAG_LOCAL_INV        = 1 <<  6,
 74         MLX4_BMME_FLAG_REMOTE_INV       = 1 <<  7,
 75         MLX4_BMME_FLAG_TYPE_2_WIN       = 1 <<  9,
 76         MLX4_BMME_FLAG_RESERVED_LKEY    = 1 << 10,
 77         MLX4_BMME_FLAG_FAST_REG_WR      = 1 << 11,
 78 };
 79 
 80 enum mlx4_event {
 81         MLX4_EVENT_TYPE_COMP               = 0x00,
 82         MLX4_EVENT_TYPE_PATH_MIG           = 0x01,
 83         MLX4_EVENT_TYPE_COMM_EST           = 0x02,
 84         MLX4_EVENT_TYPE_SQ_DRAINED         = 0x03,
 85         MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE    = 0x13,
 86         MLX4_EVENT_TYPE_SRQ_LIMIT          = 0x14,
 87         MLX4_EVENT_TYPE_CQ_ERROR           = 0x04,
 88         MLX4_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 89         MLX4_EVENT_TYPE_EEC_CATAS_ERROR    = 0x06,
 90         MLX4_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 91         MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 92         MLX4_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 93         MLX4_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 94         MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
 95         MLX4_EVENT_TYPE_PORT_CHANGE        = 0x09,
 96         MLX4_EVENT_TYPE_EQ_OVERFLOW        = 0x0f,
 97         MLX4_EVENT_TYPE_ECC_DETECT         = 0x0e,
 98         MLX4_EVENT_TYPE_CMD                = 0x0a
 99 };
100 
101 enum {
102         MLX4_PORT_CHANGE_SUBTYPE_DOWN   = 1,
103         MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
104 };
105 
106 enum {
107         MLX4_PERM_LOCAL_READ    = 1 << 10,
108         MLX4_PERM_LOCAL_WRITE   = 1 << 11,
109         MLX4_PERM_REMOTE_READ   = 1 << 12,
110         MLX4_PERM_REMOTE_WRITE  = 1 << 13,
111         MLX4_PERM_ATOMIC        = 1 << 14
112 };
113 
114 enum {
115         MLX4_OPCODE_NOP                 = 0x00,
116         MLX4_OPCODE_SEND_INVAL          = 0x01,
117         MLX4_OPCODE_RDMA_WRITE          = 0x08,
118         MLX4_OPCODE_RDMA_WRITE_IMM      = 0x09,
119         MLX4_OPCODE_SEND                = 0x0a,
120         MLX4_OPCODE_SEND_IMM            = 0x0b,
121         MLX4_OPCODE_LSO                 = 0x0e,
122         MLX4_OPCODE_RDMA_READ           = 0x10,
123         MLX4_OPCODE_ATOMIC_CS           = 0x11,
124         MLX4_OPCODE_ATOMIC_FA           = 0x12,
125         MLX4_OPCODE_ATOMIC_MASK_CS      = 0x14,
126         MLX4_OPCODE_ATOMIC_MASK_FA      = 0x15,
127         MLX4_OPCODE_BIND_MW             = 0x18,
128         MLX4_OPCODE_FMR                 = 0x19,
129         MLX4_OPCODE_LOCAL_INVAL         = 0x1b,
130         MLX4_OPCODE_CONFIG_CMD          = 0x1f,
131 
132         MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
133         MLX4_RECV_OPCODE_SEND           = 0x01,
134         MLX4_RECV_OPCODE_SEND_IMM       = 0x02,
135         MLX4_RECV_OPCODE_SEND_INVAL     = 0x03,
136 
137         MLX4_CQE_OPCODE_ERROR           = 0x1e,
138         MLX4_CQE_OPCODE_RESIZE          = 0x16,
139 };
140 
141 enum {
142         MLX4_STAT_RATE_OFFSET   = 5
143 };
144 
145 enum {
146         MLX4_MTT_FLAG_PRESENT           = 1
147 };
148 
149 enum mlx4_qp_region {
150         MLX4_QP_REGION_FW = 0,
151         MLX4_QP_REGION_ETH_ADDR,
152         MLX4_QP_REGION_FC_ADDR,
153         MLX4_QP_REGION_FC_EXCH,
154         MLX4_NUM_QP_REGION
155 };
156 
157 enum mlx4_port_type {
158         MLX4_PORT_TYPE_IB       = 1,
159         MLX4_PORT_TYPE_ETH      = 2,
160         MLX4_PORT_TYPE_AUTO     = 3
161 };
162 
163 enum mlx4_special_vlan_idx {
164         MLX4_NO_VLAN_IDX        = 0,
165         MLX4_VLAN_MISS_IDX,
166         MLX4_VLAN_REGULAR
167 };
168 
169 enum {
170         MLX4_NUM_FEXCH          = 64 * 1024,
171 };
172 
173 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
174 {
175         return (major << 32) | (minor << 16) | subminor;
176 }
177 
178 struct mlx4_caps {
179         u64                     fw_ver;
180         int                     num_ports;
181         int                     vl_cap[MLX4_MAX_PORTS + 1];
182         int                     ib_mtu_cap[MLX4_MAX_PORTS + 1];
183         __be32                  ib_port_def_cap[MLX4_MAX_PORTS + 1];
184         u64                     def_mac[MLX4_MAX_PORTS + 1];
185         int                     eth_mtu_cap[MLX4_MAX_PORTS + 1];
186         int                     gid_table_len[MLX4_MAX_PORTS + 1];
187         int                     pkey_table_len[MLX4_MAX_PORTS + 1];
188         int                     local_ca_ack_delay;
189         int                     num_uars;
190         int                     bf_reg_size;
191         int                     bf_regs_per_page;
192         int                     max_sq_sg;
193         int                     max_rq_sg;
194         int                     num_qps;
195         int                     max_wqes;
196         int                     max_sq_desc_sz;
197         int                     max_rq_desc_sz;
198         int                     max_qp_init_rdma;
199         int                     max_qp_dest_rdma;
200         int                     sqp_start;
201         int                     num_srqs;
202         int                     max_srq_wqes;
203         int                     max_srq_sge;
204         int                     reserved_srqs;
205         int                     num_cqs;
206         int                     max_cqes;
207         int                     reserved_cqs;
208         int                     num_eqs;
209         int                     reserved_eqs;
210         int                     num_comp_vectors;
211         int                     num_mpts;
212         int                     num_mtt_segs;
213         int                     mtts_per_seg;
214         int                     fmr_reserved_mtts;
215         int                     reserved_mtts;
216         int                     reserved_mrws;
217         int                     reserved_uars;
218         int                     num_mgms;
219         int                     num_amgms;
220         int                     reserved_mcgs;
221         int                     num_qp_per_mgm;
222         int                     num_pds;
223         int                     reserved_pds;
224         int                     mtt_entry_sz;
225         u32                     max_msg_sz;
226         u32                     page_size_cap;
227         u32                     flags;
228         u32                     bmme_flags;
229         u32                     reserved_lkey;
230         u16                     stat_rate_support;
231         u8                      port_width_cap[MLX4_MAX_PORTS + 1];
232         int                     max_gso_sz;
233         int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
234         int                     reserved_qps;
235         int                     reserved_qps_base[MLX4_NUM_QP_REGION];
236         int                     log_num_macs;
237         int                     log_num_vlans;
238         int                     log_num_prios;
239         enum mlx4_port_type     port_type[MLX4_MAX_PORTS + 1];
240         u8                      supported_type[MLX4_MAX_PORTS + 1];
241         u32                     port_mask;
242         enum mlx4_port_type     possible_type[MLX4_MAX_PORTS + 1];
243 };
244 
245 struct mlx4_buf_list {
246         void                   *buf;
247         dma_addr_t              map;
248 };
249 
250 struct mlx4_buf {
251         struct mlx4_buf_list    direct;
252         struct mlx4_buf_list   *page_list;
253         int                     nbufs;
254         int                     npages;
255         int                     page_shift;
256 };
257 
258 struct mlx4_mtt {
259         u32                     first_seg;
260         int                     order;
261         int                     page_shift;
262 };
263 
264 enum {
265         MLX4_DB_PER_PAGE = PAGE_SIZE / 4
266 };
267 
268 struct mlx4_db_pgdir {
269         struct list_head        list;
270         DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
271         DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
272         unsigned long          *bits[2];
273         __be32                 *db_page;
274         dma_addr_t              db_dma;
275 };
276 
277 struct mlx4_ib_user_db_page;
278 
279 struct mlx4_db {
280         __be32                  *db;
281         union {
282                 struct mlx4_db_pgdir            *pgdir;
283                 struct mlx4_ib_user_db_page     *user_page;
284         }                       u;
285         dma_addr_t              dma;
286         int                     index;
287         int                     order;
288 };
289 
290 struct mlx4_hwq_resources {
291         struct mlx4_db          db;
292         struct mlx4_mtt         mtt;
293         struct mlx4_buf         buf;
294 };
295 
296 struct mlx4_mr {
297         struct mlx4_mtt         mtt;
298         u64                     iova;
299         u64                     size;
300         u32                     key;
301         u32                     pd;
302         u32                     access;
303         int                     enabled;
304 };
305 
306 struct mlx4_fmr {
307         struct mlx4_mr          mr;
308         struct mlx4_mpt_entry  *mpt;
309         __be64                 *mtts;
310         dma_addr_t              dma_handle;
311         int                     max_pages;
312         int                     max_maps;
313         int                     maps;
314         u8                      page_shift;
315 };
316 
317 struct mlx4_uar {
318         unsigned long           pfn;
319         int                     index;
320 };
321 
322 struct mlx4_cq {
323         void (*comp)            (struct mlx4_cq *);
324         void (*event)           (struct mlx4_cq *, enum mlx4_event);
325 
326         struct mlx4_uar        *uar;
327 
328         u32                     cons_index;
329 
330         __be32                 *set_ci_db;
331         __be32                 *arm_db;
332         int                     arm_sn;
333 
334         int                     cqn;
335         unsigned                vector;
336 
337         atomic_t                refcount;
338         struct completion       free;
339 };
340 
341 struct mlx4_qp {
342         void (*event)           (struct mlx4_qp *, enum mlx4_event);
343 
344         int                     qpn;
345 
346         atomic_t                refcount;
347         struct completion       free;
348 };
349 
350 struct mlx4_srq {
351         void (*event)           (struct mlx4_srq *, enum mlx4_event);
352 
353         int                     srqn;
354         int                     max;
355         int                     max_gs;
356         int                     wqe_shift;
357 
358         atomic_t                refcount;
359         struct completion       free;
360 };
361 
362 struct mlx4_av {
363         __be32                  port_pd;
364         u8                      reserved1;
365         u8                      g_slid;
366         __be16                  dlid;
367         u8                      reserved2;
368         u8                      gid_index;
369         u8                      stat_rate;
370         u8                      hop_limit;
371         __be32                  sl_tclass_flowlabel;
372         u8                      dgid[16];
373 };
374 
375 struct mlx4_dev {
376         struct pci_dev         *pdev;
377         unsigned long           flags;
378         struct mlx4_caps        caps;
379         struct radix_tree_root  qp_table_tree;
380         u32                     rev_id;
381         char                    board_id[MLX4_BOARD_ID_LEN];
382 };
383 
384 struct mlx4_init_port_param {
385         int                     set_guid0;
386         int                     set_node_guid;
387         int                     set_si_guid;
388         u16                     mtu;
389         int                     port_width_cap;
390         u16                     vl_cap;
391         u16                     max_gid;
392         u16                     max_pkey;
393         u64                     guid0;
394         u64                     node_guid;
395         u64                     si_guid;
396 };
397 
398 #define mlx4_foreach_port(port, dev, type)                              \
399         for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)     \
400                 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
401                      ~(dev)->caps.port_mask) & 1 << ((port) - 1))
402 
403 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
404                    struct mlx4_buf *buf);
405 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
406 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
407 {
408         if (BITS_PER_LONG == 64 || buf->nbufs == 1)
409                 return buf->direct.buf + offset;
410         else
411                 return buf->page_list[offset >> PAGE_SHIFT].buf +
412                         (offset & (PAGE_SIZE - 1));
413 }
414 
415 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
416 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
417 
418 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
419 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
420 
421 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
422                   struct mlx4_mtt *mtt);
423 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
424 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
425 
426 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
427                   int npages, int page_shift, struct mlx4_mr *mr);
428 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
429 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
430 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
431                    int start_index, int npages, u64 *page_list);
432 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
433                        struct mlx4_buf *buf);
434 
435 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
436 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
437 
438 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
439                        int size, int max_direct);
440 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
441                        int size);
442 
443 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
444                   struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
445                   unsigned vector, int collapsed);
446 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
447 
448 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
449 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
450 
451 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
452 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
453 
454 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
455                    u64 db_rec, struct mlx4_srq *srq);
456 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
457 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
458 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
459 
460 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
461 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
462 
463 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
464                           int block_mcast_loopback);
465 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
466 
467 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
468 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
469 
470 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
471 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
472 
473 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
474                       int npages, u64 iova, u32 *lkey, u32 *rkey);
475 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
476                    int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
477 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
478 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
479                     u32 *lkey, u32 *rkey);
480 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
481 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
482 
483 #endif /* MLX4_DEVICE_H */
484 

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