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TOMOYO Linux Cross Reference
Linux/include/linux/mlx4/device.h

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  1 /*
  2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
  3  *
  4  * This software is available to you under a choice of one of two
  5  * licenses.  You may choose to be licensed under the terms of the GNU
  6  * General Public License (GPL) Version 2, available from the file
  7  * COPYING in the main directory of this source tree, or the
  8  * OpenIB.org BSD license below:
  9  *
 10  *     Redistribution and use in source and binary forms, with or
 11  *     without modification, are permitted provided that the following
 12  *     conditions are met:
 13  *
 14  *      - Redistributions of source code must retain the above
 15  *        copyright notice, this list of conditions and the following
 16  *        disclaimer.
 17  *
 18  *      - Redistributions in binary form must reproduce the above
 19  *        copyright notice, this list of conditions and the following
 20  *        disclaimer in the documentation and/or other materials
 21  *        provided with the distribution.
 22  *
 23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30  * SOFTWARE.
 31  */
 32 
 33 #ifndef MLX4_DEVICE_H
 34 #define MLX4_DEVICE_H
 35 
 36 #include <linux/if_ether.h>
 37 #include <linux/pci.h>
 38 #include <linux/completion.h>
 39 #include <linux/radix-tree.h>
 40 #include <linux/cpu_rmap.h>
 41 #include <linux/crash_dump.h>
 42 
 43 #include <linux/atomic.h>
 44 
 45 #include <linux/timecounter.h>
 46 
 47 #define DEFAULT_UAR_PAGE_SHIFT  12
 48 
 49 #define MAX_MSIX_P_PORT         17
 50 #define MAX_MSIX                64
 51 #define MIN_MSIX_P_PORT         5
 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
 53                                          (dev_cap).num_ports * MIN_MSIX_P_PORT)
 54 
 55 #define MLX4_MAX_100M_UNITS_VAL         255     /*
 56                                                  * work around: can't set values
 57                                                  * greater then this value when
 58                                                  * using 100 Mbps units.
 59                                                  */
 60 #define MLX4_RATELIMIT_100M_UNITS       3       /* 100 Mbps */
 61 #define MLX4_RATELIMIT_1G_UNITS         4       /* 1 Gbps */
 62 #define MLX4_RATELIMIT_DEFAULT          0x00ff
 63 
 64 #define MLX4_ROCE_MAX_GIDS      128
 65 #define MLX4_ROCE_PF_GIDS       16
 66 
 67 enum {
 68         MLX4_FLAG_MSI_X         = 1 << 0,
 69         MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
 70         MLX4_FLAG_MASTER        = 1 << 2,
 71         MLX4_FLAG_SLAVE         = 1 << 3,
 72         MLX4_FLAG_SRIOV         = 1 << 4,
 73         MLX4_FLAG_OLD_REG_MAC   = 1 << 6,
 74         MLX4_FLAG_BONDED        = 1 << 7,
 75         MLX4_FLAG_SECURE_HOST   = 1 << 8,
 76 };
 77 
 78 enum {
 79         MLX4_PORT_CAP_IS_SM     = 1 << 1,
 80         MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
 81 };
 82 
 83 enum {
 84         MLX4_MAX_PORTS          = 2,
 85         MLX4_MAX_PORT_PKEYS     = 128,
 86         MLX4_MAX_PORT_GIDS      = 128
 87 };
 88 
 89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
 90  * These qkeys must not be allowed for general use. This is a 64k range,
 91  * and to test for violation, we use the mask (protect against future chg).
 92  */
 93 #define MLX4_RESERVED_QKEY_BASE  (0xFFFF0000)
 94 #define MLX4_RESERVED_QKEY_MASK  (0xFFFF0000)
 95 
 96 enum {
 97         MLX4_BOARD_ID_LEN = 64
 98 };
 99 
100 enum {
101         MLX4_MAX_NUM_PF         = 16,
102         MLX4_MAX_NUM_VF         = 126,
103         MLX4_MAX_NUM_VF_P_PORT  = 64,
104         MLX4_MFUNC_MAX          = 128,
105         MLX4_MAX_EQ_NUM         = 1024,
106         MLX4_MFUNC_EQ_NUM       = 4,
107         MLX4_MFUNC_MAX_EQES     = 8,
108         MLX4_MFUNC_EQE_MASK     = (MLX4_MFUNC_MAX_EQES - 1)
109 };
110 
111 /* Driver supports 3 diffrent device methods to manage traffic steering:
112  *      -device managed - High level API for ib and eth flow steering. FW is
113  *                        managing flow steering tables.
114  *      - B0 steering mode - Common low level API for ib and (if supported) eth.
115  *      - A0 steering mode - Limited low level API for eth. In case of IB,
116  *                           B0 mode is in use.
117  */
118 enum {
119         MLX4_STEERING_MODE_A0,
120         MLX4_STEERING_MODE_B0,
121         MLX4_STEERING_MODE_DEVICE_MANAGED
122 };
123 
124 enum {
125         MLX4_STEERING_DMFS_A0_DEFAULT,
126         MLX4_STEERING_DMFS_A0_DYNAMIC,
127         MLX4_STEERING_DMFS_A0_STATIC,
128         MLX4_STEERING_DMFS_A0_DISABLE,
129         MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
130 };
131 
132 static inline const char *mlx4_steering_mode_str(int steering_mode)
133 {
134         switch (steering_mode) {
135         case MLX4_STEERING_MODE_A0:
136                 return "A0 steering";
137 
138         case MLX4_STEERING_MODE_B0:
139                 return "B0 steering";
140 
141         case MLX4_STEERING_MODE_DEVICE_MANAGED:
142                 return "Device managed flow steering";
143 
144         default:
145                 return "Unrecognize steering mode";
146         }
147 }
148 
149 enum {
150         MLX4_TUNNEL_OFFLOAD_MODE_NONE,
151         MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152 };
153 
154 enum {
155         MLX4_DEV_CAP_FLAG_RC            = 1LL <<  0,
156         MLX4_DEV_CAP_FLAG_UC            = 1LL <<  1,
157         MLX4_DEV_CAP_FLAG_UD            = 1LL <<  2,
158         MLX4_DEV_CAP_FLAG_XRC           = 1LL <<  3,
159         MLX4_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
160         MLX4_DEV_CAP_FLAG_IPOIB_CSUM    = 1LL <<  7,
161         MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
162         MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
163         MLX4_DEV_CAP_FLAG_DPDP          = 1LL << 12,
164         MLX4_DEV_CAP_FLAG_BLH           = 1LL << 15,
165         MLX4_DEV_CAP_FLAG_MEM_WINDOW    = 1LL << 16,
166         MLX4_DEV_CAP_FLAG_APM           = 1LL << 17,
167         MLX4_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
168         MLX4_DEV_CAP_FLAG_RAW_MCAST     = 1LL << 19,
169         MLX4_DEV_CAP_FLAG_UD_AV_PORT    = 1LL << 20,
170         MLX4_DEV_CAP_FLAG_UD_MCAST      = 1LL << 21,
171         MLX4_DEV_CAP_FLAG_IBOE          = 1LL << 30,
172         MLX4_DEV_CAP_FLAG_UC_LOOPBACK   = 1LL << 32,
173         MLX4_DEV_CAP_FLAG_FCS_KEEP      = 1LL << 34,
174         MLX4_DEV_CAP_FLAG_WOL_PORT1     = 1LL << 37,
175         MLX4_DEV_CAP_FLAG_WOL_PORT2     = 1LL << 38,
176         MLX4_DEV_CAP_FLAG_UDP_RSS       = 1LL << 40,
177         MLX4_DEV_CAP_FLAG_VEP_UC_STEER  = 1LL << 41,
178         MLX4_DEV_CAP_FLAG_VEP_MC_STEER  = 1LL << 42,
179         MLX4_DEV_CAP_FLAG_COUNTERS      = 1LL << 48,
180         MLX4_DEV_CAP_FLAG_RSS_IP_FRAG   = 1LL << 52,
181         MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
182         MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
183         MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
184         MLX4_DEV_CAP_FLAG_64B_EQE       = 1LL << 61,
185         MLX4_DEV_CAP_FLAG_64B_CQE       = 1LL << 62
186 };
187 
188 enum {
189         MLX4_DEV_CAP_FLAG2_RSS                  = 1LL <<  0,
190         MLX4_DEV_CAP_FLAG2_RSS_TOP              = 1LL <<  1,
191         MLX4_DEV_CAP_FLAG2_RSS_XOR              = 1LL <<  2,
192         MLX4_DEV_CAP_FLAG2_FS_EN                = 1LL <<  3,
193         MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN      = 1LL <<  4,
194         MLX4_DEV_CAP_FLAG2_TS                   = 1LL <<  5,
195         MLX4_DEV_CAP_FLAG2_VLAN_CONTROL         = 1LL <<  6,
196         MLX4_DEV_CAP_FLAG2_FSM                  = 1LL <<  7,
197         MLX4_DEV_CAP_FLAG2_UPDATE_QP            = 1LL <<  8,
198         MLX4_DEV_CAP_FLAG2_DMFS_IPOIB           = 1LL <<  9,
199         MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS       = 1LL <<  10,
200         MLX4_DEV_CAP_FLAG2_MAD_DEMUX            = 1LL <<  11,
201         MLX4_DEV_CAP_FLAG2_CQE_STRIDE           = 1LL <<  12,
202         MLX4_DEV_CAP_FLAG2_EQE_STRIDE           = 1LL <<  13,
203         MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL        = 1LL <<  14,
204         MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP    = 1LL <<  15,
205         MLX4_DEV_CAP_FLAG2_CONFIG_DEV           = 1LL <<  16,
206         MLX4_DEV_CAP_FLAG2_SYS_EQS              = 1LL <<  17,
207         MLX4_DEV_CAP_FLAG2_80_VFS               = 1LL <<  18,
208         MLX4_DEV_CAP_FLAG2_FS_A0                = 1LL <<  19,
209         MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
210         MLX4_DEV_CAP_FLAG2_PORT_REMAP           = 1LL <<  21,
211         MLX4_DEV_CAP_FLAG2_QCN                  = 1LL <<  22,
212         MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT        = 1LL <<  23,
213         MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN         = 1LL <<  24,
214         MLX4_DEV_CAP_FLAG2_QOS_VPP              = 1LL <<  25,
215         MLX4_DEV_CAP_FLAG2_ETS_CFG              = 1LL <<  26,
216         MLX4_DEV_CAP_FLAG2_PORT_BEACON          = 1LL <<  27,
217         MLX4_DEV_CAP_FLAG2_IGNORE_FCS           = 1LL <<  28,
218         MLX4_DEV_CAP_FLAG2_PHV_EN               = 1LL <<  29,
219         MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN      = 1LL <<  30,
220         MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
221         MLX4_DEV_CAP_FLAG2_LB_SRC_CHK           = 1ULL << 32,
222         MLX4_DEV_CAP_FLAG2_ROCE_V1_V2           = 1ULL <<  33,
223         MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER   = 1ULL <<  34,
224         MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT        = 1ULL <<  35,
225         MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP          = 1ULL <<  36,
226         MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
227 };
228 
229 enum {
230         MLX4_QUERY_FUNC_FLAGS_BF_RES_QP         = 1LL << 0,
231         MLX4_QUERY_FUNC_FLAGS_A0_RES_QP         = 1LL << 1
232 };
233 
234 enum {
235         MLX4_VF_CAP_FLAG_RESET                  = 1 << 0
236 };
237 
238 /* bit enums for an 8-bit flags field indicating special use
239  * QPs which require special handling in qp_reserve_range.
240  * Currently, this only includes QPs used by the ETH interface,
241  * where we expect to use blueflame.  These QPs must not have
242  * bits 6 and 7 set in their qp number.
243  *
244  * This enum may use only bits 0..7.
245  */
246 enum {
247         MLX4_RESERVE_A0_QP      = 1 << 6,
248         MLX4_RESERVE_ETH_BF_QP  = 1 << 7,
249 };
250 
251 enum {
252         MLX4_DEV_CAP_64B_EQE_ENABLED    = 1LL << 0,
253         MLX4_DEV_CAP_64B_CQE_ENABLED    = 1LL << 1,
254         MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
255         MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
256 };
257 
258 enum {
259         MLX4_USER_DEV_CAP_LARGE_CQE     = 1L << 0
260 };
261 
262 enum {
263         MLX4_FUNC_CAP_64B_EQE_CQE       = 1L << 0,
264         MLX4_FUNC_CAP_EQE_CQE_STRIDE    = 1L << 1,
265         MLX4_FUNC_CAP_DMFS_A0_STATIC    = 1L << 2
266 };
267 
268 
269 #define MLX4_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
270 
271 enum {
272         MLX4_BMME_FLAG_WIN_TYPE_2B      = 1 <<  1,
273         MLX4_BMME_FLAG_LOCAL_INV        = 1 <<  6,
274         MLX4_BMME_FLAG_REMOTE_INV       = 1 <<  7,
275         MLX4_BMME_FLAG_TYPE_2_WIN       = 1 <<  9,
276         MLX4_BMME_FLAG_RESERVED_LKEY    = 1 << 10,
277         MLX4_BMME_FLAG_FAST_REG_WR      = 1 << 11,
278         MLX4_BMME_FLAG_ROCE_V1_V2       = 1 << 19,
279         MLX4_BMME_FLAG_PORT_REMAP       = 1 << 24,
280         MLX4_BMME_FLAG_VSD_INIT2RTR     = 1 << 28,
281 };
282 
283 enum {
284         MLX4_FLAG_PORT_REMAP            = MLX4_BMME_FLAG_PORT_REMAP,
285         MLX4_FLAG_ROCE_V1_V2            = MLX4_BMME_FLAG_ROCE_V1_V2
286 };
287 
288 enum mlx4_event {
289         MLX4_EVENT_TYPE_COMP               = 0x00,
290         MLX4_EVENT_TYPE_PATH_MIG           = 0x01,
291         MLX4_EVENT_TYPE_COMM_EST           = 0x02,
292         MLX4_EVENT_TYPE_SQ_DRAINED         = 0x03,
293         MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE    = 0x13,
294         MLX4_EVENT_TYPE_SRQ_LIMIT          = 0x14,
295         MLX4_EVENT_TYPE_CQ_ERROR           = 0x04,
296         MLX4_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
297         MLX4_EVENT_TYPE_EEC_CATAS_ERROR    = 0x06,
298         MLX4_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
299         MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
300         MLX4_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
301         MLX4_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
302         MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
303         MLX4_EVENT_TYPE_PORT_CHANGE        = 0x09,
304         MLX4_EVENT_TYPE_EQ_OVERFLOW        = 0x0f,
305         MLX4_EVENT_TYPE_ECC_DETECT         = 0x0e,
306         MLX4_EVENT_TYPE_CMD                = 0x0a,
307         MLX4_EVENT_TYPE_VEP_UPDATE         = 0x19,
308         MLX4_EVENT_TYPE_COMM_CHANNEL       = 0x18,
309         MLX4_EVENT_TYPE_OP_REQUIRED        = 0x1a,
310         MLX4_EVENT_TYPE_FATAL_WARNING      = 0x1b,
311         MLX4_EVENT_TYPE_FLR_EVENT          = 0x1c,
312         MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
313         MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT  = 0x3e,
314         MLX4_EVENT_TYPE_NONE               = 0xff,
315 };
316 
317 enum {
318         MLX4_PORT_CHANGE_SUBTYPE_DOWN   = 1,
319         MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
320 };
321 
322 enum {
323         MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE          = 1,
324         MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE  = 2,
325 };
326 
327 enum {
328         MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
329 };
330 
331 enum slave_port_state {
332         SLAVE_PORT_DOWN = 0,
333         SLAVE_PENDING_UP,
334         SLAVE_PORT_UP,
335 };
336 
337 enum slave_port_gen_event {
338         SLAVE_PORT_GEN_EVENT_DOWN = 0,
339         SLAVE_PORT_GEN_EVENT_UP,
340         SLAVE_PORT_GEN_EVENT_NONE,
341 };
342 
343 enum slave_port_state_event {
344         MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
345         MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
346         MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
347         MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
348 };
349 
350 enum {
351         MLX4_PERM_LOCAL_READ    = 1 << 10,
352         MLX4_PERM_LOCAL_WRITE   = 1 << 11,
353         MLX4_PERM_REMOTE_READ   = 1 << 12,
354         MLX4_PERM_REMOTE_WRITE  = 1 << 13,
355         MLX4_PERM_ATOMIC        = 1 << 14,
356         MLX4_PERM_BIND_MW       = 1 << 15,
357         MLX4_PERM_MASK          = 0xFC00
358 };
359 
360 enum {
361         MLX4_OPCODE_NOP                 = 0x00,
362         MLX4_OPCODE_SEND_INVAL          = 0x01,
363         MLX4_OPCODE_RDMA_WRITE          = 0x08,
364         MLX4_OPCODE_RDMA_WRITE_IMM      = 0x09,
365         MLX4_OPCODE_SEND                = 0x0a,
366         MLX4_OPCODE_SEND_IMM            = 0x0b,
367         MLX4_OPCODE_LSO                 = 0x0e,
368         MLX4_OPCODE_RDMA_READ           = 0x10,
369         MLX4_OPCODE_ATOMIC_CS           = 0x11,
370         MLX4_OPCODE_ATOMIC_FA           = 0x12,
371         MLX4_OPCODE_MASKED_ATOMIC_CS    = 0x14,
372         MLX4_OPCODE_MASKED_ATOMIC_FA    = 0x15,
373         MLX4_OPCODE_BIND_MW             = 0x18,
374         MLX4_OPCODE_FMR                 = 0x19,
375         MLX4_OPCODE_LOCAL_INVAL         = 0x1b,
376         MLX4_OPCODE_CONFIG_CMD          = 0x1f,
377 
378         MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
379         MLX4_RECV_OPCODE_SEND           = 0x01,
380         MLX4_RECV_OPCODE_SEND_IMM       = 0x02,
381         MLX4_RECV_OPCODE_SEND_INVAL     = 0x03,
382 
383         MLX4_CQE_OPCODE_ERROR           = 0x1e,
384         MLX4_CQE_OPCODE_RESIZE          = 0x16,
385 };
386 
387 enum {
388         MLX4_STAT_RATE_OFFSET   = 5
389 };
390 
391 enum mlx4_protocol {
392         MLX4_PROT_IB_IPV6 = 0,
393         MLX4_PROT_ETH,
394         MLX4_PROT_IB_IPV4,
395         MLX4_PROT_FCOE
396 };
397 
398 enum {
399         MLX4_MTT_FLAG_PRESENT           = 1
400 };
401 
402 enum mlx4_qp_region {
403         MLX4_QP_REGION_FW = 0,
404         MLX4_QP_REGION_RSS_RAW_ETH,
405         MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
406         MLX4_QP_REGION_ETH_ADDR,
407         MLX4_QP_REGION_FC_ADDR,
408         MLX4_QP_REGION_FC_EXCH,
409         MLX4_NUM_QP_REGION
410 };
411 
412 enum mlx4_port_type {
413         MLX4_PORT_TYPE_NONE     = 0,
414         MLX4_PORT_TYPE_IB       = 1,
415         MLX4_PORT_TYPE_ETH      = 2,
416         MLX4_PORT_TYPE_AUTO     = 3
417 };
418 
419 enum mlx4_special_vlan_idx {
420         MLX4_NO_VLAN_IDX        = 0,
421         MLX4_VLAN_MISS_IDX,
422         MLX4_VLAN_REGULAR
423 };
424 
425 enum mlx4_steer_type {
426         MLX4_MC_STEER = 0,
427         MLX4_UC_STEER,
428         MLX4_NUM_STEERS
429 };
430 
431 enum {
432         MLX4_NUM_FEXCH          = 64 * 1024,
433 };
434 
435 enum {
436         MLX4_MAX_FAST_REG_PAGES = 511,
437 };
438 
439 enum {
440         /*
441          * Max wqe size for rdma read is 512 bytes, so this
442          * limits our max_sge_rd as the wqe needs to fit:
443          * - ctrl segment (16 bytes)
444          * - rdma segment (16 bytes)
445          * - scatter elements (16 bytes each)
446          */
447         MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
448 };
449 
450 enum {
451         MLX4_DEV_PMC_SUBTYPE_GUID_INFO   = 0x14,
452         MLX4_DEV_PMC_SUBTYPE_PORT_INFO   = 0x15,
453         MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE  = 0x16,
454         MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
455 };
456 
457 /* Port mgmt change event handling */
458 enum {
459         MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK       = 1 << 0,
460         MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK           = 1 << 1,
461         MLX4_EQ_PORT_INFO_LID_CHANGE_MASK               = 1 << 2,
462         MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK             = 1 << 3,
463         MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK        = 1 << 4,
464 };
465 
466 union sl2vl_tbl_to_u64 {
467         u8      sl8[8];
468         u64     sl64;
469 };
470 
471 enum {
472         MLX4_DEVICE_STATE_UP                    = 1 << 0,
473         MLX4_DEVICE_STATE_INTERNAL_ERROR        = 1 << 1,
474 };
475 
476 enum {
477         MLX4_INTERFACE_STATE_UP         = 1 << 0,
478         MLX4_INTERFACE_STATE_DELETION   = 1 << 1,
479 };
480 
481 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
482                              MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
483 
484 enum mlx4_module_id {
485         MLX4_MODULE_ID_SFP              = 0x3,
486         MLX4_MODULE_ID_QSFP             = 0xC,
487         MLX4_MODULE_ID_QSFP_PLUS        = 0xD,
488         MLX4_MODULE_ID_QSFP28           = 0x11,
489 };
490 
491 enum { /* rl */
492         MLX4_QP_RATE_LIMIT_NONE         = 0,
493         MLX4_QP_RATE_LIMIT_KBS          = 1,
494         MLX4_QP_RATE_LIMIT_MBS          = 2,
495         MLX4_QP_RATE_LIMIT_GBS          = 3
496 };
497 
498 struct mlx4_rate_limit_caps {
499         u16     num_rates; /* Number of different rates */
500         u8      min_unit;
501         u16     min_val;
502         u8      max_unit;
503         u16     max_val;
504 };
505 
506 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
507 {
508         return (major << 32) | (minor << 16) | subminor;
509 }
510 
511 struct mlx4_phys_caps {
512         u32                     gid_phys_table_len[MLX4_MAX_PORTS + 1];
513         u32                     pkey_phys_table_len[MLX4_MAX_PORTS + 1];
514         u32                     num_phys_eqs;
515         u32                     base_sqpn;
516         u32                     base_proxy_sqpn;
517         u32                     base_tunnel_sqpn;
518 };
519 
520 struct mlx4_caps {
521         u64                     fw_ver;
522         u32                     function;
523         int                     num_ports;
524         int                     vl_cap[MLX4_MAX_PORTS + 1];
525         int                     ib_mtu_cap[MLX4_MAX_PORTS + 1];
526         __be32                  ib_port_def_cap[MLX4_MAX_PORTS + 1];
527         u64                     def_mac[MLX4_MAX_PORTS + 1];
528         int                     eth_mtu_cap[MLX4_MAX_PORTS + 1];
529         int                     gid_table_len[MLX4_MAX_PORTS + 1];
530         int                     pkey_table_len[MLX4_MAX_PORTS + 1];
531         int                     trans_type[MLX4_MAX_PORTS + 1];
532         int                     vendor_oui[MLX4_MAX_PORTS + 1];
533         int                     wavelength[MLX4_MAX_PORTS + 1];
534         u64                     trans_code[MLX4_MAX_PORTS + 1];
535         int                     local_ca_ack_delay;
536         int                     num_uars;
537         u32                     uar_page_size;
538         int                     bf_reg_size;
539         int                     bf_regs_per_page;
540         int                     max_sq_sg;
541         int                     max_rq_sg;
542         int                     num_qps;
543         int                     max_wqes;
544         int                     max_sq_desc_sz;
545         int                     max_rq_desc_sz;
546         int                     max_qp_init_rdma;
547         int                     max_qp_dest_rdma;
548         int                     max_tc_eth;
549         u32                     *qp0_qkey;
550         u32                     *qp0_proxy;
551         u32                     *qp1_proxy;
552         u32                     *qp0_tunnel;
553         u32                     *qp1_tunnel;
554         int                     num_srqs;
555         int                     max_srq_wqes;
556         int                     max_srq_sge;
557         int                     reserved_srqs;
558         int                     num_cqs;
559         int                     max_cqes;
560         int                     reserved_cqs;
561         int                     num_sys_eqs;
562         int                     num_eqs;
563         int                     reserved_eqs;
564         int                     num_comp_vectors;
565         int                     num_mpts;
566         int                     max_fmr_maps;
567         int                     num_mtts;
568         int                     fmr_reserved_mtts;
569         int                     reserved_mtts;
570         int                     reserved_mrws;
571         int                     reserved_uars;
572         int                     num_mgms;
573         int                     num_amgms;
574         int                     reserved_mcgs;
575         int                     num_qp_per_mgm;
576         int                     steering_mode;
577         int                     dmfs_high_steer_mode;
578         int                     fs_log_max_ucast_qp_range_size;
579         int                     num_pds;
580         int                     reserved_pds;
581         int                     max_xrcds;
582         int                     reserved_xrcds;
583         int                     mtt_entry_sz;
584         u32                     max_msg_sz;
585         u32                     page_size_cap;
586         u64                     flags;
587         u64                     flags2;
588         u32                     bmme_flags;
589         u32                     reserved_lkey;
590         u16                     stat_rate_support;
591         u8                      port_width_cap[MLX4_MAX_PORTS + 1];
592         int                     max_gso_sz;
593         int                     max_rss_tbl_sz;
594         int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
595         int                     reserved_qps;
596         int                     reserved_qps_base[MLX4_NUM_QP_REGION];
597         int                     log_num_macs;
598         int                     log_num_vlans;
599         enum mlx4_port_type     port_type[MLX4_MAX_PORTS + 1];
600         u8                      supported_type[MLX4_MAX_PORTS + 1];
601         u8                      suggested_type[MLX4_MAX_PORTS + 1];
602         u8                      default_sense[MLX4_MAX_PORTS + 1];
603         u32                     port_mask[MLX4_MAX_PORTS + 1];
604         enum mlx4_port_type     possible_type[MLX4_MAX_PORTS + 1];
605         u32                     max_counters;
606         u8                      port_ib_mtu[MLX4_MAX_PORTS + 1];
607         u16                     sqp_demux;
608         u32                     eqe_size;
609         u32                     cqe_size;
610         u8                      eqe_factor;
611         u32                     userspace_caps; /* userspace must be aware of these */
612         u32                     function_caps;  /* VFs must be aware of these */
613         u16                     hca_core_clock;
614         u64                     phys_port_id[MLX4_MAX_PORTS + 1];
615         int                     tunnel_offload_mode;
616         u8                      rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
617         u8                      phv_bit[MLX4_MAX_PORTS + 1];
618         u8                      alloc_res_qp_mask;
619         u32                     dmfs_high_rate_qpn_base;
620         u32                     dmfs_high_rate_qpn_range;
621         u32                     vf_caps;
622         struct mlx4_rate_limit_caps rl_caps;
623 };
624 
625 struct mlx4_buf_list {
626         void                   *buf;
627         dma_addr_t              map;
628 };
629 
630 struct mlx4_buf {
631         struct mlx4_buf_list    direct;
632         struct mlx4_buf_list   *page_list;
633         int                     nbufs;
634         int                     npages;
635         int                     page_shift;
636 };
637 
638 struct mlx4_mtt {
639         u32                     offset;
640         int                     order;
641         int                     page_shift;
642 };
643 
644 enum {
645         MLX4_DB_PER_PAGE = PAGE_SIZE / 4
646 };
647 
648 struct mlx4_db_pgdir {
649         struct list_head        list;
650         DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
651         DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
652         unsigned long          *bits[2];
653         __be32                 *db_page;
654         dma_addr_t              db_dma;
655 };
656 
657 struct mlx4_ib_user_db_page;
658 
659 struct mlx4_db {
660         __be32                  *db;
661         union {
662                 struct mlx4_db_pgdir            *pgdir;
663                 struct mlx4_ib_user_db_page     *user_page;
664         }                       u;
665         dma_addr_t              dma;
666         int                     index;
667         int                     order;
668 };
669 
670 struct mlx4_hwq_resources {
671         struct mlx4_db          db;
672         struct mlx4_mtt         mtt;
673         struct mlx4_buf         buf;
674 };
675 
676 struct mlx4_mr {
677         struct mlx4_mtt         mtt;
678         u64                     iova;
679         u64                     size;
680         u32                     key;
681         u32                     pd;
682         u32                     access;
683         int                     enabled;
684 };
685 
686 enum mlx4_mw_type {
687         MLX4_MW_TYPE_1 = 1,
688         MLX4_MW_TYPE_2 = 2,
689 };
690 
691 struct mlx4_mw {
692         u32                     key;
693         u32                     pd;
694         enum mlx4_mw_type       type;
695         int                     enabled;
696 };
697 
698 struct mlx4_fmr {
699         struct mlx4_mr          mr;
700         struct mlx4_mpt_entry  *mpt;
701         __be64                 *mtts;
702         dma_addr_t              dma_handle;
703         int                     max_pages;
704         int                     max_maps;
705         int                     maps;
706         u8                      page_shift;
707 };
708 
709 struct mlx4_uar {
710         unsigned long           pfn;
711         int                     index;
712         struct list_head        bf_list;
713         unsigned                free_bf_bmap;
714         void __iomem           *map;
715         void __iomem           *bf_map;
716 };
717 
718 struct mlx4_bf {
719         unsigned int            offset;
720         int                     buf_size;
721         struct mlx4_uar        *uar;
722         void __iomem           *reg;
723 };
724 
725 struct mlx4_cq {
726         void (*comp)            (struct mlx4_cq *);
727         void (*event)           (struct mlx4_cq *, enum mlx4_event);
728 
729         struct mlx4_uar        *uar;
730 
731         u32                     cons_index;
732 
733         u16                     irq;
734         __be32                 *set_ci_db;
735         __be32                 *arm_db;
736         int                     arm_sn;
737 
738         int                     cqn;
739         unsigned                vector;
740 
741         atomic_t                refcount;
742         struct completion       free;
743         struct {
744                 struct list_head list;
745                 void (*comp)(struct mlx4_cq *);
746                 void            *priv;
747         } tasklet_ctx;
748         int             reset_notify_added;
749         struct list_head        reset_notify;
750 };
751 
752 struct mlx4_qp {
753         void (*event)           (struct mlx4_qp *, enum mlx4_event);
754 
755         int                     qpn;
756 
757         atomic_t                refcount;
758         struct completion       free;
759 };
760 
761 struct mlx4_srq {
762         void (*event)           (struct mlx4_srq *, enum mlx4_event);
763 
764         int                     srqn;
765         int                     max;
766         int                     max_gs;
767         int                     wqe_shift;
768 
769         atomic_t                refcount;
770         struct completion       free;
771 };
772 
773 struct mlx4_av {
774         __be32                  port_pd;
775         u8                      reserved1;
776         u8                      g_slid;
777         __be16                  dlid;
778         u8                      reserved2;
779         u8                      gid_index;
780         u8                      stat_rate;
781         u8                      hop_limit;
782         __be32                  sl_tclass_flowlabel;
783         u8                      dgid[16];
784 };
785 
786 struct mlx4_eth_av {
787         __be32          port_pd;
788         u8              reserved1;
789         u8              smac_idx;
790         u16             reserved2;
791         u8              reserved3;
792         u8              gid_index;
793         u8              stat_rate;
794         u8              hop_limit;
795         __be32          sl_tclass_flowlabel;
796         u8              dgid[16];
797         u8              s_mac[6];
798         u8              reserved4[2];
799         __be16          vlan;
800         u8              mac[ETH_ALEN];
801 };
802 
803 union mlx4_ext_av {
804         struct mlx4_av          ib;
805         struct mlx4_eth_av      eth;
806 };
807 
808 /* Counters should be saturate once they reach their maximum value */
809 #define ASSIGN_32BIT_COUNTER(counter, value) do {       \
810         if ((value) > U32_MAX)                          \
811                 counter = cpu_to_be32(U32_MAX);         \
812         else                                            \
813                 counter = cpu_to_be32(value);           \
814 } while (0)
815 
816 struct mlx4_counter {
817         u8      reserved1[3];
818         u8      counter_mode;
819         __be32  num_ifc;
820         u32     reserved2[2];
821         __be64  rx_frames;
822         __be64  rx_bytes;
823         __be64  tx_frames;
824         __be64  tx_bytes;
825 };
826 
827 struct mlx4_quotas {
828         int qp;
829         int cq;
830         int srq;
831         int mpt;
832         int mtt;
833         int counter;
834         int xrcd;
835 };
836 
837 struct mlx4_vf_dev {
838         u8                      min_port;
839         u8                      n_ports;
840 };
841 
842 enum mlx4_pci_status {
843         MLX4_PCI_STATUS_DISABLED,
844         MLX4_PCI_STATUS_ENABLED,
845 };
846 
847 struct mlx4_dev_persistent {
848         struct pci_dev         *pdev;
849         struct mlx4_dev        *dev;
850         int                     nvfs[MLX4_MAX_PORTS + 1];
851         int                     num_vfs;
852         enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
853         enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
854         struct work_struct      catas_work;
855         struct workqueue_struct *catas_wq;
856         struct mutex    device_state_mutex; /* protect HW state */
857         u8              state;
858         struct mutex    interface_state_mutex; /* protect SW state */
859         u8      interface_state;
860         struct mutex            pci_status_mutex; /* sync pci state */
861         enum mlx4_pci_status    pci_status;
862 };
863 
864 struct mlx4_dev {
865         struct mlx4_dev_persistent *persist;
866         unsigned long           flags;
867         unsigned long           num_slaves;
868         struct mlx4_caps        caps;
869         struct mlx4_phys_caps   phys_caps;
870         struct mlx4_quotas      quotas;
871         struct radix_tree_root  qp_table_tree;
872         u8                      rev_id;
873         u8                      port_random_macs;
874         char                    board_id[MLX4_BOARD_ID_LEN];
875         int                     numa_node;
876         int                     oper_log_mgm_entry_size;
877         u64                     regid_promisc_array[MLX4_MAX_PORTS + 1];
878         u64                     regid_allmulti_array[MLX4_MAX_PORTS + 1];
879         struct mlx4_vf_dev     *dev_vfs;
880         u8  uar_page_shift;
881 };
882 
883 struct mlx4_clock_params {
884         u64 offset;
885         u8 bar;
886         u8 size;
887 };
888 
889 struct mlx4_eqe {
890         u8                      reserved1;
891         u8                      type;
892         u8                      reserved2;
893         u8                      subtype;
894         union {
895                 u32             raw[6];
896                 struct {
897                         __be32  cqn;
898                 } __packed comp;
899                 struct {
900                         u16     reserved1;
901                         __be16  token;
902                         u32     reserved2;
903                         u8      reserved3[3];
904                         u8      status;
905                         __be64  out_param;
906                 } __packed cmd;
907                 struct {
908                         __be32  qpn;
909                 } __packed qp;
910                 struct {
911                         __be32  srqn;
912                 } __packed srq;
913                 struct {
914                         __be32  cqn;
915                         u32     reserved1;
916                         u8      reserved2[3];
917                         u8      syndrome;
918                 } __packed cq_err;
919                 struct {
920                         u32     reserved1[2];
921                         __be32  port;
922                 } __packed port_change;
923                 struct {
924                         #define COMM_CHANNEL_BIT_ARRAY_SIZE     4
925                         u32 reserved;
926                         u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
927                 } __packed comm_channel_arm;
928                 struct {
929                         u8      port;
930                         u8      reserved[3];
931                         __be64  mac;
932                 } __packed mac_update;
933                 struct {
934                         __be32  slave_id;
935                 } __packed flr_event;
936                 struct {
937                         __be16  current_temperature;
938                         __be16  warning_threshold;
939                 } __packed warming;
940                 struct {
941                         u8 reserved[3];
942                         u8 port;
943                         union {
944                                 struct {
945                                         __be16 mstr_sm_lid;
946                                         __be16 port_lid;
947                                         __be32 changed_attr;
948                                         u8 reserved[3];
949                                         u8 mstr_sm_sl;
950                                         __be64 gid_prefix;
951                                 } __packed port_info;
952                                 struct {
953                                         __be32 block_ptr;
954                                         __be32 tbl_entries_mask;
955                                 } __packed tbl_change_info;
956                                 struct {
957                                         u8 sl2vl_table[8];
958                                 } __packed sl2vl_tbl_change_info;
959                         } params;
960                 } __packed port_mgmt_change;
961                 struct {
962                         u8 reserved[3];
963                         u8 port;
964                         u32 reserved1[5];
965                 } __packed bad_cable;
966         }                       event;
967         u8                      slave_id;
968         u8                      reserved3[2];
969         u8                      owner;
970 } __packed;
971 
972 struct mlx4_init_port_param {
973         int                     set_guid0;
974         int                     set_node_guid;
975         int                     set_si_guid;
976         u16                     mtu;
977         int                     port_width_cap;
978         u16                     vl_cap;
979         u16                     max_gid;
980         u16                     max_pkey;
981         u64                     guid0;
982         u64                     node_guid;
983         u64                     si_guid;
984 };
985 
986 #define MAD_IFC_DATA_SZ 192
987 /* MAD IFC Mailbox */
988 struct mlx4_mad_ifc {
989         u8      base_version;
990         u8      mgmt_class;
991         u8      class_version;
992         u8      method;
993         __be16  status;
994         __be16  class_specific;
995         __be64  tid;
996         __be16  attr_id;
997         __be16  resv;
998         __be32  attr_mod;
999         __be64  mkey;
1000         __be16  dr_slid;
1001         __be16  dr_dlid;
1002         u8      reserved[28];
1003         u8      data[MAD_IFC_DATA_SZ];
1004 } __packed;
1005 
1006 #define mlx4_foreach_port(port, dev, type)                              \
1007         for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)     \
1008                 if ((type) == (dev)->caps.port_mask[(port)])
1009 
1010 #define mlx4_foreach_ib_transport_port(port, dev)                         \
1011         for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)       \
1012                 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1013                         ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
1014                         ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
1015 
1016 #define MLX4_INVALID_SLAVE_ID   0xFF
1017 #define MLX4_SINK_COUNTER_INDEX(dev)    (dev->caps.max_counters - 1)
1018 
1019 void handle_port_mgmt_change_event(struct work_struct *work);
1020 
1021 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1022 {
1023         return dev->caps.function;
1024 }
1025 
1026 static inline int mlx4_is_master(struct mlx4_dev *dev)
1027 {
1028         return dev->flags & MLX4_FLAG_MASTER;
1029 }
1030 
1031 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1032 {
1033         return dev->phys_caps.base_sqpn + 8 +
1034                 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1035 }
1036 
1037 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1038 {
1039         return (qpn < dev->phys_caps.base_sqpn + 8 +
1040                 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1041                 qpn >= dev->phys_caps.base_sqpn) ||
1042                (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1043 }
1044 
1045 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1046 {
1047         int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1048 
1049         if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1050                 return 1;
1051 
1052         return 0;
1053 }
1054 
1055 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1056 {
1057         return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1058 }
1059 
1060 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1061 {
1062         return dev->flags & MLX4_FLAG_SLAVE;
1063 }
1064 
1065 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1066 {
1067         return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1068 }
1069 
1070 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1071                    struct mlx4_buf *buf, gfp_t gfp);
1072 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1073 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1074 {
1075         if (buf->nbufs == 1)
1076                 return buf->direct.buf + offset;
1077         else
1078                 return buf->page_list[offset >> PAGE_SHIFT].buf +
1079                         (offset & (PAGE_SIZE - 1));
1080 }
1081 
1082 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1083 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1084 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1085 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1086 
1087 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1088 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1089 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1090 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1091 
1092 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1093                   struct mlx4_mtt *mtt);
1094 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1095 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1096 
1097 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1098                   int npages, int page_shift, struct mlx4_mr *mr);
1099 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1100 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1101 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1102                   struct mlx4_mw *mw);
1103 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1104 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1105 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1106                    int start_index, int npages, u64 *page_list);
1107 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1108                        struct mlx4_buf *buf, gfp_t gfp);
1109 
1110 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1111                   gfp_t gfp);
1112 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1113 
1114 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1115                        int size);
1116 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1117                        int size);
1118 
1119 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1120                   struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1121                   unsigned vector, int collapsed, int timestamp_en);
1122 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1123 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1124                           int *base, u8 flags);
1125 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1126 
1127 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1128                   gfp_t gfp);
1129 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1130 
1131 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1132                    struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1133 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1134 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1135 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1136 
1137 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1138 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1139 
1140 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1141                         int block_mcast_loopback, enum mlx4_protocol prot);
1142 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1143                         enum mlx4_protocol prot);
1144 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1145                           u8 port, int block_mcast_loopback,
1146                           enum mlx4_protocol protocol, u64 *reg_id);
1147 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1148                           enum mlx4_protocol protocol, u64 reg_id);
1149 
1150 enum {
1151         MLX4_DOMAIN_UVERBS      = 0x1000,
1152         MLX4_DOMAIN_ETHTOOL     = 0x2000,
1153         MLX4_DOMAIN_RFS         = 0x3000,
1154         MLX4_DOMAIN_NIC    = 0x5000,
1155 };
1156 
1157 enum mlx4_net_trans_rule_id {
1158         MLX4_NET_TRANS_RULE_ID_ETH = 0,
1159         MLX4_NET_TRANS_RULE_ID_IB,
1160         MLX4_NET_TRANS_RULE_ID_IPV6,
1161         MLX4_NET_TRANS_RULE_ID_IPV4,
1162         MLX4_NET_TRANS_RULE_ID_TCP,
1163         MLX4_NET_TRANS_RULE_ID_UDP,
1164         MLX4_NET_TRANS_RULE_ID_VXLAN,
1165         MLX4_NET_TRANS_RULE_NUM, /* should be last */
1166 };
1167 
1168 extern const u16 __sw_id_hw[];
1169 
1170 static inline int map_hw_to_sw_id(u16 header_id)
1171 {
1172 
1173         int i;
1174         for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1175                 if (header_id == __sw_id_hw[i])
1176                         return i;
1177         }
1178         return -EINVAL;
1179 }
1180 
1181 enum mlx4_net_trans_promisc_mode {
1182         MLX4_FS_REGULAR = 1,
1183         MLX4_FS_ALL_DEFAULT,
1184         MLX4_FS_MC_DEFAULT,
1185         MLX4_FS_MIRROR_RX_PORT,
1186         MLX4_FS_MIRROR_SX_PORT,
1187         MLX4_FS_UC_SNIFFER,
1188         MLX4_FS_MC_SNIFFER,
1189         MLX4_FS_MODE_NUM, /* should be last */
1190 };
1191 
1192 struct mlx4_spec_eth {
1193         u8      dst_mac[ETH_ALEN];
1194         u8      dst_mac_msk[ETH_ALEN];
1195         u8      src_mac[ETH_ALEN];
1196         u8      src_mac_msk[ETH_ALEN];
1197         u8      ether_type_enable;
1198         __be16  ether_type;
1199         __be16  vlan_id_msk;
1200         __be16  vlan_id;
1201 };
1202 
1203 struct mlx4_spec_tcp_udp {
1204         __be16 dst_port;
1205         __be16 dst_port_msk;
1206         __be16 src_port;
1207         __be16 src_port_msk;
1208 };
1209 
1210 struct mlx4_spec_ipv4 {
1211         __be32 dst_ip;
1212         __be32 dst_ip_msk;
1213         __be32 src_ip;
1214         __be32 src_ip_msk;
1215 };
1216 
1217 struct mlx4_spec_ib {
1218         __be32  l3_qpn;
1219         __be32  qpn_msk;
1220         u8      dst_gid[16];
1221         u8      dst_gid_msk[16];
1222 };
1223 
1224 struct mlx4_spec_vxlan {
1225         __be32 vni;
1226         __be32 vni_mask;
1227 
1228 };
1229 
1230 struct mlx4_spec_list {
1231         struct  list_head list;
1232         enum    mlx4_net_trans_rule_id id;
1233         union {
1234                 struct mlx4_spec_eth eth;
1235                 struct mlx4_spec_ib ib;
1236                 struct mlx4_spec_ipv4 ipv4;
1237                 struct mlx4_spec_tcp_udp tcp_udp;
1238                 struct mlx4_spec_vxlan vxlan;
1239         };
1240 };
1241 
1242 enum mlx4_net_trans_hw_rule_queue {
1243         MLX4_NET_TRANS_Q_FIFO,
1244         MLX4_NET_TRANS_Q_LIFO,
1245 };
1246 
1247 struct mlx4_net_trans_rule {
1248         struct  list_head list;
1249         enum    mlx4_net_trans_hw_rule_queue queue_mode;
1250         bool    exclusive;
1251         bool    allow_loopback;
1252         enum    mlx4_net_trans_promisc_mode promisc_mode;
1253         u8      port;
1254         u16     priority;
1255         u32     qpn;
1256 };
1257 
1258 struct mlx4_net_trans_rule_hw_ctrl {
1259         __be16 prio;
1260         u8 type;
1261         u8 flags;
1262         u8 rsvd1;
1263         u8 funcid;
1264         u8 vep;
1265         u8 port;
1266         __be32 qpn;
1267         __be32 rsvd2;
1268 };
1269 
1270 struct mlx4_net_trans_rule_hw_ib {
1271         u8 size;
1272         u8 rsvd1;
1273         __be16 id;
1274         u32 rsvd2;
1275         __be32 l3_qpn;
1276         __be32 qpn_mask;
1277         u8 dst_gid[16];
1278         u8 dst_gid_msk[16];
1279 } __packed;
1280 
1281 struct mlx4_net_trans_rule_hw_eth {
1282         u8      size;
1283         u8      rsvd;
1284         __be16  id;
1285         u8      rsvd1[6];
1286         u8      dst_mac[6];
1287         u16     rsvd2;
1288         u8      dst_mac_msk[6];
1289         u16     rsvd3;
1290         u8      src_mac[6];
1291         u16     rsvd4;
1292         u8      src_mac_msk[6];
1293         u8      rsvd5;
1294         u8      ether_type_enable;
1295         __be16  ether_type;
1296         __be16  vlan_tag_msk;
1297         __be16  vlan_tag;
1298 } __packed;
1299 
1300 struct mlx4_net_trans_rule_hw_tcp_udp {
1301         u8      size;
1302         u8      rsvd;
1303         __be16  id;
1304         __be16  rsvd1[3];
1305         __be16  dst_port;
1306         __be16  rsvd2;
1307         __be16  dst_port_msk;
1308         __be16  rsvd3;
1309         __be16  src_port;
1310         __be16  rsvd4;
1311         __be16  src_port_msk;
1312 } __packed;
1313 
1314 struct mlx4_net_trans_rule_hw_ipv4 {
1315         u8      size;
1316         u8      rsvd;
1317         __be16  id;
1318         __be32  rsvd1;
1319         __be32  dst_ip;
1320         __be32  dst_ip_msk;
1321         __be32  src_ip;
1322         __be32  src_ip_msk;
1323 } __packed;
1324 
1325 struct mlx4_net_trans_rule_hw_vxlan {
1326         u8      size;
1327         u8      rsvd;
1328         __be16  id;
1329         __be32  rsvd1;
1330         __be32  vni;
1331         __be32  vni_mask;
1332 } __packed;
1333 
1334 struct _rule_hw {
1335         union {
1336                 struct {
1337                         u8 size;
1338                         u8 rsvd;
1339                         __be16 id;
1340                 };
1341                 struct mlx4_net_trans_rule_hw_eth eth;
1342                 struct mlx4_net_trans_rule_hw_ib ib;
1343                 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1344                 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1345                 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1346         };
1347 };
1348 
1349 enum {
1350         VXLAN_STEER_BY_OUTER_MAC        = 1 << 0,
1351         VXLAN_STEER_BY_OUTER_VLAN       = 1 << 1,
1352         VXLAN_STEER_BY_VSID_VNI         = 1 << 2,
1353         VXLAN_STEER_BY_INNER_MAC        = 1 << 3,
1354         VXLAN_STEER_BY_INNER_VLAN       = 1 << 4,
1355 };
1356 
1357 enum {
1358         MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1359 };
1360 
1361 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1362                                 enum mlx4_net_trans_promisc_mode mode);
1363 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1364                                    enum mlx4_net_trans_promisc_mode mode);
1365 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1366 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1367 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1368 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1369 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1370 
1371 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1372 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1373 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1374 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1375 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1376                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1377 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1378                            u8 promisc);
1379 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1380 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1381                             u8 ignore_fcs_value);
1382 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1383 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1384 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1385 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1386                                       bool *vlan_offload_disabled);
1387 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1388                                        struct _rule_hw *eth_header);
1389 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1390 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1391 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1392 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1393 
1394 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1395                       int npages, u64 iova, u32 *lkey, u32 *rkey);
1396 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1397                    int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1398 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1399 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1400                     u32 *lkey, u32 *rkey);
1401 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1402 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1403 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1404 int mlx4_test_async(struct mlx4_dev *dev);
1405 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1406                              const u32 offset[], u32 value[],
1407                              size_t array_len, u8 port);
1408 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1409 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1410 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1411 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1412 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1413 
1414 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1415 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1416 
1417 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1418 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1419 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1420 
1421 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1422 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1423 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1424 
1425 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1426                          int port);
1427 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1428 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1429 int mlx4_flow_attach(struct mlx4_dev *dev,
1430                      struct mlx4_net_trans_rule *rule, u64 *reg_id);
1431 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1432 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1433                                     enum mlx4_net_trans_promisc_mode flow_type);
1434 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1435                                   enum mlx4_net_trans_rule_id id);
1436 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1437 
1438 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1439                           int port, int qpn, u16 prio, u64 *reg_id);
1440 
1441 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1442                           int i, int val);
1443 
1444 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1445 
1446 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1447 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1448 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1449 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1450 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1451 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1452 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1453 
1454 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1455 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1456 
1457 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1458                                  int *slave_id);
1459 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1460                                  u8 *gid);
1461 
1462 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1463                                       u32 max_range_qpn);
1464 
1465 u64 mlx4_read_clock(struct mlx4_dev *dev);
1466 
1467 struct mlx4_active_ports {
1468         DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1469 };
1470 /* Returns a bitmap of the physical ports which are assigned to slave */
1471 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1472 
1473 /* Returns the physical port that represents the virtual port of the slave, */
1474 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1475 /* mapping is returned.                                                     */
1476 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1477 
1478 struct mlx4_slaves_pport {
1479         DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1480 };
1481 /* Returns a bitmap of all slaves that are assigned to port. */
1482 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1483                                                    int port);
1484 
1485 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1486 /* the ports that are set in crit_ports.                               */
1487 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1488                 struct mlx4_dev *dev,
1489                 const struct mlx4_active_ports *crit_ports);
1490 
1491 /* Returns the slave's virtual port that represents the physical port. */
1492 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1493 
1494 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1495 
1496 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1497 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1498 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1499 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1500 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1501 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1502 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1503                                  int enable);
1504 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1505                        struct mlx4_mpt_entry ***mpt_entry);
1506 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1507                          struct mlx4_mpt_entry **mpt_entry);
1508 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1509                          u32 pdn);
1510 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1511                              struct mlx4_mpt_entry *mpt_entry,
1512                              u32 access);
1513 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1514                         struct mlx4_mpt_entry **mpt_entry);
1515 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1516 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1517                             u64 iova, u64 size, int npages,
1518                             int page_shift, struct mlx4_mpt_entry *mpt_entry);
1519 
1520 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1521                          u16 offset, u16 size, u8 *data);
1522 int mlx4_max_tc(struct mlx4_dev *dev);
1523 
1524 /* Returns true if running in low memory profile (kdump kernel) */
1525 static inline bool mlx4_low_memory_profile(void)
1526 {
1527         return is_kdump_kernel();
1528 }
1529 
1530 /* ACCESS REG commands */
1531 enum mlx4_access_reg_method {
1532         MLX4_ACCESS_REG_QUERY = 0x1,
1533         MLX4_ACCESS_REG_WRITE = 0x2,
1534 };
1535 
1536 /* ACCESS PTYS Reg command */
1537 enum mlx4_ptys_proto {
1538         MLX4_PTYS_IB = 1<<0,
1539         MLX4_PTYS_EN = 1<<2,
1540 };
1541 
1542 struct mlx4_ptys_reg {
1543         u8 resrvd1;
1544         u8 local_port;
1545         u8 resrvd2;
1546         u8 proto_mask;
1547         __be32 resrvd3[2];
1548         __be32 eth_proto_cap;
1549         __be16 ib_width_cap;
1550         __be16 ib_speed_cap;
1551         __be32 resrvd4;
1552         __be32 eth_proto_admin;
1553         __be16 ib_width_admin;
1554         __be16 ib_speed_admin;
1555         __be32 resrvd5;
1556         __be32 eth_proto_oper;
1557         __be16 ib_width_oper;
1558         __be16 ib_speed_oper;
1559         __be32 resrvd6;
1560         __be32 eth_proto_lp_adv;
1561 } __packed;
1562 
1563 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1564                          enum mlx4_access_reg_method method,
1565                          struct mlx4_ptys_reg *ptys_reg);
1566 
1567 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1568                                    struct mlx4_clock_params *params);
1569 
1570 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1571 {
1572         return (index << (PAGE_SHIFT - dev->uar_page_shift));
1573 }
1574 
1575 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1576 {
1577         /* The first 128 UARs are used for EQ doorbells */
1578         return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1579 }
1580 #endif /* MLX4_DEVICE_H */
1581 

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