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TOMOYO Linux Cross Reference
Linux/include/linux/mtd/nand.h

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  1 /*
  2  *  linux/include/linux/mtd/nand.h
  3  *
  4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  5  *                        Steven J. Hill <sjhill@realitydiluted.com>
  6  *                        Thomas Gleixner <tglx@linutronix.de>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  *
 12  * Info:
 13  *      Contains standard defines and IDs for NAND flash devices
 14  *
 15  * Changelog:
 16  *      See git changelog.
 17  */
 18 #ifndef __LINUX_MTD_NAND_H
 19 #define __LINUX_MTD_NAND_H
 20 
 21 #include <linux/wait.h>
 22 #include <linux/spinlock.h>
 23 #include <linux/mtd/mtd.h>
 24 #include <linux/mtd/flashchip.h>
 25 #include <linux/mtd/bbm.h>
 26 
 27 struct mtd_info;
 28 struct nand_flash_dev;
 29 struct device_node;
 30 
 31 /* Scan and identify a NAND device */
 32 int nand_scan(struct mtd_info *mtd, int max_chips);
 33 /*
 34  * Separate phases of nand_scan(), allowing board driver to intervene
 35  * and override command or ECC setup according to flash type.
 36  */
 37 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
 38                            struct nand_flash_dev *table);
 39 int nand_scan_tail(struct mtd_info *mtd);
 40 
 41 /* Unregister the MTD device and free resources held by the NAND device */
 42 void nand_release(struct mtd_info *mtd);
 43 
 44 /* Internal helper for board drivers which need to override command function */
 45 void nand_wait_ready(struct mtd_info *mtd);
 46 
 47 /* locks all blocks present in the device */
 48 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 49 
 50 /* unlocks specified locked blocks */
 51 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 52 
 53 /* The maximum number of NAND chips in an array */
 54 #define NAND_MAX_CHIPS          8
 55 
 56 /*
 57  * Constants for hardware specific CLE/ALE/NCE function
 58  *
 59  * These are bits which can be or'ed to set/clear multiple
 60  * bits in one go.
 61  */
 62 /* Select the chip by setting nCE to low */
 63 #define NAND_NCE                0x01
 64 /* Select the command latch by setting CLE to high */
 65 #define NAND_CLE                0x02
 66 /* Select the address latch by setting ALE to high */
 67 #define NAND_ALE                0x04
 68 
 69 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
 70 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
 71 #define NAND_CTRL_CHANGE        0x80
 72 
 73 /*
 74  * Standard NAND flash commands
 75  */
 76 #define NAND_CMD_READ0          0
 77 #define NAND_CMD_READ1          1
 78 #define NAND_CMD_RNDOUT         5
 79 #define NAND_CMD_PAGEPROG       0x10
 80 #define NAND_CMD_READOOB        0x50
 81 #define NAND_CMD_ERASE1         0x60
 82 #define NAND_CMD_STATUS         0x70
 83 #define NAND_CMD_SEQIN          0x80
 84 #define NAND_CMD_RNDIN          0x85
 85 #define NAND_CMD_READID         0x90
 86 #define NAND_CMD_ERASE2         0xd0
 87 #define NAND_CMD_PARAM          0xec
 88 #define NAND_CMD_GET_FEATURES   0xee
 89 #define NAND_CMD_SET_FEATURES   0xef
 90 #define NAND_CMD_RESET          0xff
 91 
 92 #define NAND_CMD_LOCK           0x2a
 93 #define NAND_CMD_UNLOCK1        0x23
 94 #define NAND_CMD_UNLOCK2        0x24
 95 
 96 /* Extended commands for large page devices */
 97 #define NAND_CMD_READSTART      0x30
 98 #define NAND_CMD_RNDOUTSTART    0xE0
 99 #define NAND_CMD_CACHEDPROG     0x15
100 
101 #define NAND_CMD_NONE           -1
102 
103 /* Status bits */
104 #define NAND_STATUS_FAIL        0x01
105 #define NAND_STATUS_FAIL_N1     0x02
106 #define NAND_STATUS_TRUE_READY  0x20
107 #define NAND_STATUS_READY       0x40
108 #define NAND_STATUS_WP          0x80
109 
110 /*
111  * Constants for ECC_MODES
112  */
113 typedef enum {
114         NAND_ECC_NONE,
115         NAND_ECC_SOFT,
116         NAND_ECC_HW,
117         NAND_ECC_HW_SYNDROME,
118         NAND_ECC_HW_OOB_FIRST,
119 } nand_ecc_modes_t;
120 
121 enum nand_ecc_algo {
122         NAND_ECC_UNKNOWN,
123         NAND_ECC_HAMMING,
124         NAND_ECC_BCH,
125 };
126 
127 /*
128  * Constants for Hardware ECC
129  */
130 /* Reset Hardware ECC for read */
131 #define NAND_ECC_READ           0
132 /* Reset Hardware ECC for write */
133 #define NAND_ECC_WRITE          1
134 /* Enable Hardware ECC before syndrome is read back from flash */
135 #define NAND_ECC_READSYN        2
136 
137 /*
138  * Enable generic NAND 'page erased' check. This check is only done when
139  * ecc.correct() returns -EBADMSG.
140  * Set this flag if your implementation does not fix bitflips in erased
141  * pages and you want to rely on the default implementation.
142  */
143 #define NAND_ECC_GENERIC_ERASED_CHECK   BIT(0)
144 #define NAND_ECC_MAXIMIZE               BIT(1)
145 /*
146  * If your controller already sends the required NAND commands when
147  * reading or writing a page, then the framework is not supposed to
148  * send READ0 and SEQIN/PAGEPROG respectively.
149  */
150 #define NAND_ECC_CUSTOM_PAGE_ACCESS     BIT(2)
151 
152 /* Bit mask for flags passed to do_nand_read_ecc */
153 #define NAND_GET_DEVICE         0x80
154 
155 
156 /*
157  * Option constants for bizarre disfunctionality and real
158  * features.
159  */
160 /* Buswidth is 16 bit */
161 #define NAND_BUSWIDTH_16        0x00000002
162 /* Chip has cache program function */
163 #define NAND_CACHEPRG           0x00000008
164 /*
165  * Chip requires ready check on read (for auto-incremented sequential read).
166  * True only for small page devices; large page devices do not support
167  * autoincrement.
168  */
169 #define NAND_NEED_READRDY       0x00000100
170 
171 /* Chip does not allow subpage writes */
172 #define NAND_NO_SUBPAGE_WRITE   0x00000200
173 
174 /* Device is one of 'new' xD cards that expose fake nand command set */
175 #define NAND_BROKEN_XD          0x00000400
176 
177 /* Device behaves just like nand, but is readonly */
178 #define NAND_ROM                0x00000800
179 
180 /* Device supports subpage reads */
181 #define NAND_SUBPAGE_READ       0x00001000
182 
183 /*
184  * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
185  * patterns.
186  */
187 #define NAND_NEED_SCRAMBLING    0x00002000
188 
189 /* Options valid for Samsung large page devices */
190 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
191 
192 /* Macros to identify the above */
193 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
194 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
195 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
196 
197 /* Non chip related options */
198 /* This option skips the bbt scan during initialization. */
199 #define NAND_SKIP_BBTSCAN       0x00010000
200 /*
201  * This option is defined if the board driver allocates its own buffers
202  * (e.g. because it needs them DMA-coherent).
203  */
204 #define NAND_OWN_BUFFERS        0x00020000
205 /* Chip may not exist, so silence any errors in scan */
206 #define NAND_SCAN_SILENT_NODEV  0x00040000
207 /*
208  * Autodetect nand buswidth with readid/onfi.
209  * This suppose the driver will configure the hardware in 8 bits mode
210  * when calling nand_scan_ident, and update its configuration
211  * before calling nand_scan_tail.
212  */
213 #define NAND_BUSWIDTH_AUTO      0x00080000
214 /*
215  * This option could be defined by controller drivers to protect against
216  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
217  */
218 #define NAND_USE_BOUNCE_BUFFER  0x00100000
219 
220 /*
221  * In case your controller is implementing ->cmd_ctrl() and is relying on the
222  * default ->cmdfunc() implementation, you may want to let the core handle the
223  * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
224  * requested.
225  * If your controller already takes care of this delay, you don't need to set
226  * this flag.
227  */
228 #define NAND_WAIT_TCCS          0x00200000
229 
230 /* Options set by nand scan */
231 /* Nand scan has allocated controller struct */
232 #define NAND_CONTROLLER_ALLOC   0x80000000
233 
234 /* Cell info constants */
235 #define NAND_CI_CHIPNR_MSK      0x03
236 #define NAND_CI_CELLTYPE_MSK    0x0C
237 #define NAND_CI_CELLTYPE_SHIFT  2
238 
239 /* Keep gcc happy */
240 struct nand_chip;
241 
242 /* ONFI features */
243 #define ONFI_FEATURE_16_BIT_BUS         (1 << 0)
244 #define ONFI_FEATURE_EXT_PARAM_PAGE     (1 << 7)
245 
246 /* ONFI timing mode, used in both asynchronous and synchronous mode */
247 #define ONFI_TIMING_MODE_0              (1 << 0)
248 #define ONFI_TIMING_MODE_1              (1 << 1)
249 #define ONFI_TIMING_MODE_2              (1 << 2)
250 #define ONFI_TIMING_MODE_3              (1 << 3)
251 #define ONFI_TIMING_MODE_4              (1 << 4)
252 #define ONFI_TIMING_MODE_5              (1 << 5)
253 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
254 
255 /* ONFI feature address */
256 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
257 
258 /* Vendor-specific feature address (Micron) */
259 #define ONFI_FEATURE_ADDR_READ_RETRY    0x89
260 
261 /* ONFI subfeature parameters length */
262 #define ONFI_SUBFEATURE_PARAM_LEN       4
263 
264 /* ONFI optional commands SET/GET FEATURES supported? */
265 #define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
266 
267 struct nand_onfi_params {
268         /* rev info and features block */
269         /* 'O' 'N' 'F' 'I'  */
270         u8 sig[4];
271         __le16 revision;
272         __le16 features;
273         __le16 opt_cmd;
274         u8 reserved0[2];
275         __le16 ext_param_page_length; /* since ONFI 2.1 */
276         u8 num_of_param_pages;        /* since ONFI 2.1 */
277         u8 reserved1[17];
278 
279         /* manufacturer information block */
280         char manufacturer[12];
281         char model[20];
282         u8 jedec_id;
283         __le16 date_code;
284         u8 reserved2[13];
285 
286         /* memory organization block */
287         __le32 byte_per_page;
288         __le16 spare_bytes_per_page;
289         __le32 data_bytes_per_ppage;
290         __le16 spare_bytes_per_ppage;
291         __le32 pages_per_block;
292         __le32 blocks_per_lun;
293         u8 lun_count;
294         u8 addr_cycles;
295         u8 bits_per_cell;
296         __le16 bb_per_lun;
297         __le16 block_endurance;
298         u8 guaranteed_good_blocks;
299         __le16 guaranteed_block_endurance;
300         u8 programs_per_page;
301         u8 ppage_attr;
302         u8 ecc_bits;
303         u8 interleaved_bits;
304         u8 interleaved_ops;
305         u8 reserved3[13];
306 
307         /* electrical parameter block */
308         u8 io_pin_capacitance_max;
309         __le16 async_timing_mode;
310         __le16 program_cache_timing_mode;
311         __le16 t_prog;
312         __le16 t_bers;
313         __le16 t_r;
314         __le16 t_ccs;
315         __le16 src_sync_timing_mode;
316         u8 src_ssync_features;
317         __le16 clk_pin_capacitance_typ;
318         __le16 io_pin_capacitance_typ;
319         __le16 input_pin_capacitance_typ;
320         u8 input_pin_capacitance_max;
321         u8 driver_strength_support;
322         __le16 t_int_r;
323         __le16 t_adl;
324         u8 reserved4[8];
325 
326         /* vendor */
327         __le16 vendor_revision;
328         u8 vendor[88];
329 
330         __le16 crc;
331 } __packed;
332 
333 #define ONFI_CRC_BASE   0x4F4E
334 
335 /* Extended ECC information Block Definition (since ONFI 2.1) */
336 struct onfi_ext_ecc_info {
337         u8 ecc_bits;
338         u8 codeword_size;
339         __le16 bb_per_lun;
340         __le16 block_endurance;
341         u8 reserved[2];
342 } __packed;
343 
344 #define ONFI_SECTION_TYPE_0     0       /* Unused section. */
345 #define ONFI_SECTION_TYPE_1     1       /* for additional sections. */
346 #define ONFI_SECTION_TYPE_2     2       /* for ECC information. */
347 struct onfi_ext_section {
348         u8 type;
349         u8 length;
350 } __packed;
351 
352 #define ONFI_EXT_SECTION_MAX 8
353 
354 /* Extended Parameter Page Definition (since ONFI 2.1) */
355 struct onfi_ext_param_page {
356         __le16 crc;
357         u8 sig[4];             /* 'E' 'P' 'P' 'S' */
358         u8 reserved0[10];
359         struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
360 
361         /*
362          * The actual size of the Extended Parameter Page is in
363          * @ext_param_page_length of nand_onfi_params{}.
364          * The following are the variable length sections.
365          * So we do not add any fields below. Please see the ONFI spec.
366          */
367 } __packed;
368 
369 struct nand_onfi_vendor_micron {
370         u8 two_plane_read;
371         u8 read_cache;
372         u8 read_unique_id;
373         u8 dq_imped;
374         u8 dq_imped_num_settings;
375         u8 dq_imped_feat_addr;
376         u8 rb_pulldown_strength;
377         u8 rb_pulldown_strength_feat_addr;
378         u8 rb_pulldown_strength_num_settings;
379         u8 otp_mode;
380         u8 otp_page_start;
381         u8 otp_data_prot_addr;
382         u8 otp_num_pages;
383         u8 otp_feat_addr;
384         u8 read_retry_options;
385         u8 reserved[72];
386         u8 param_revision;
387 } __packed;
388 
389 struct jedec_ecc_info {
390         u8 ecc_bits;
391         u8 codeword_size;
392         __le16 bb_per_lun;
393         __le16 block_endurance;
394         u8 reserved[2];
395 } __packed;
396 
397 /* JEDEC features */
398 #define JEDEC_FEATURE_16_BIT_BUS        (1 << 0)
399 
400 struct nand_jedec_params {
401         /* rev info and features block */
402         /* 'J' 'E' 'S' 'D'  */
403         u8 sig[4];
404         __le16 revision;
405         __le16 features;
406         u8 opt_cmd[3];
407         __le16 sec_cmd;
408         u8 num_of_param_pages;
409         u8 reserved0[18];
410 
411         /* manufacturer information block */
412         char manufacturer[12];
413         char model[20];
414         u8 jedec_id[6];
415         u8 reserved1[10];
416 
417         /* memory organization block */
418         __le32 byte_per_page;
419         __le16 spare_bytes_per_page;
420         u8 reserved2[6];
421         __le32 pages_per_block;
422         __le32 blocks_per_lun;
423         u8 lun_count;
424         u8 addr_cycles;
425         u8 bits_per_cell;
426         u8 programs_per_page;
427         u8 multi_plane_addr;
428         u8 multi_plane_op_attr;
429         u8 reserved3[38];
430 
431         /* electrical parameter block */
432         __le16 async_sdr_speed_grade;
433         __le16 toggle_ddr_speed_grade;
434         __le16 sync_ddr_speed_grade;
435         u8 async_sdr_features;
436         u8 toggle_ddr_features;
437         u8 sync_ddr_features;
438         __le16 t_prog;
439         __le16 t_bers;
440         __le16 t_r;
441         __le16 t_r_multi_plane;
442         __le16 t_ccs;
443         __le16 io_pin_capacitance_typ;
444         __le16 input_pin_capacitance_typ;
445         __le16 clk_pin_capacitance_typ;
446         u8 driver_strength_support;
447         __le16 t_adl;
448         u8 reserved4[36];
449 
450         /* ECC and endurance block */
451         u8 guaranteed_good_blocks;
452         __le16 guaranteed_block_endurance;
453         struct jedec_ecc_info ecc_info[4];
454         u8 reserved5[29];
455 
456         /* reserved */
457         u8 reserved6[148];
458 
459         /* vendor */
460         __le16 vendor_rev_num;
461         u8 reserved7[88];
462 
463         /* CRC for Parameter Page */
464         __le16 crc;
465 } __packed;
466 
467 /**
468  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
469  * @lock:               protection lock
470  * @active:             the mtd device which holds the controller currently
471  * @wq:                 wait queue to sleep on if a NAND operation is in
472  *                      progress used instead of the per chip wait queue
473  *                      when a hw controller is available.
474  */
475 struct nand_hw_control {
476         spinlock_t lock;
477         struct nand_chip *active;
478         wait_queue_head_t wq;
479 };
480 
481 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
482 {
483         nfc->active = NULL;
484         spin_lock_init(&nfc->lock);
485         init_waitqueue_head(&nfc->wq);
486 }
487 
488 /**
489  * struct nand_ecc_ctrl - Control structure for ECC
490  * @mode:       ECC mode
491  * @algo:       ECC algorithm
492  * @steps:      number of ECC steps per page
493  * @size:       data bytes per ECC step
494  * @bytes:      ECC bytes per step
495  * @strength:   max number of correctible bits per ECC step
496  * @total:      total number of ECC bytes per page
497  * @prepad:     padding information for syndrome based ECC generators
498  * @postpad:    padding information for syndrome based ECC generators
499  * @options:    ECC specific options (see NAND_ECC_XXX flags defined above)
500  * @priv:       pointer to private ECC control data
501  * @hwctl:      function to control hardware ECC generator. Must only
502  *              be provided if an hardware ECC is available
503  * @calculate:  function for ECC calculation or readback from ECC hardware
504  * @correct:    function for ECC correction, matching to ECC generator (sw/hw).
505  *              Should return a positive number representing the number of
506  *              corrected bitflips, -EBADMSG if the number of bitflips exceed
507  *              ECC strength, or any other error code if the error is not
508  *              directly related to correction.
509  *              If -EBADMSG is returned the input buffers should be left
510  *              untouched.
511  * @read_page_raw:      function to read a raw page without ECC. This function
512  *                      should hide the specific layout used by the ECC
513  *                      controller and always return contiguous in-band and
514  *                      out-of-band data even if they're not stored
515  *                      contiguously on the NAND chip (e.g.
516  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
517  *                      out-of-band data).
518  * @write_page_raw:     function to write a raw page without ECC. This function
519  *                      should hide the specific layout used by the ECC
520  *                      controller and consider the passed data as contiguous
521  *                      in-band and out-of-band data. ECC controller is
522  *                      responsible for doing the appropriate transformations
523  *                      to adapt to its specific layout (e.g.
524  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
525  *                      out-of-band data).
526  * @read_page:  function to read a page according to the ECC generator
527  *              requirements; returns maximum number of bitflips corrected in
528  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
529  * @read_subpage:       function to read parts of the page covered by ECC;
530  *                      returns same as read_page()
531  * @write_subpage:      function to write parts of the page covered by ECC.
532  * @write_page: function to write a page according to the ECC generator
533  *              requirements.
534  * @write_oob_raw:      function to write chip OOB data without ECC
535  * @read_oob_raw:       function to read chip OOB data without ECC
536  * @read_oob:   function to read chip OOB data
537  * @write_oob:  function to write chip OOB data
538  */
539 struct nand_ecc_ctrl {
540         nand_ecc_modes_t mode;
541         enum nand_ecc_algo algo;
542         int steps;
543         int size;
544         int bytes;
545         int total;
546         int strength;
547         int prepad;
548         int postpad;
549         unsigned int options;
550         void *priv;
551         void (*hwctl)(struct mtd_info *mtd, int mode);
552         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
553                         uint8_t *ecc_code);
554         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
555                         uint8_t *calc_ecc);
556         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
557                         uint8_t *buf, int oob_required, int page);
558         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
559                         const uint8_t *buf, int oob_required, int page);
560         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
561                         uint8_t *buf, int oob_required, int page);
562         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
563                         uint32_t offs, uint32_t len, uint8_t *buf, int page);
564         int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
565                         uint32_t offset, uint32_t data_len,
566                         const uint8_t *data_buf, int oob_required, int page);
567         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
568                         const uint8_t *buf, int oob_required, int page);
569         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
570                         int page);
571         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
572                         int page);
573         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
574         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
575                         int page);
576 };
577 
578 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
579 {
580         return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
581 }
582 
583 /**
584  * struct nand_buffers - buffer structure for read/write
585  * @ecccalc:    buffer pointer for calculated ECC, size is oobsize.
586  * @ecccode:    buffer pointer for ECC read from flash, size is oobsize.
587  * @databuf:    buffer pointer for data, size is (page size + oobsize).
588  *
589  * Do not change the order of buffers. databuf and oobrbuf must be in
590  * consecutive order.
591  */
592 struct nand_buffers {
593         uint8_t *ecccalc;
594         uint8_t *ecccode;
595         uint8_t *databuf;
596 };
597 
598 /**
599  * struct nand_sdr_timings - SDR NAND chip timings
600  *
601  * This struct defines the timing requirements of a SDR NAND chip.
602  * These information can be found in every NAND datasheets and the timings
603  * meaning are described in the ONFI specifications:
604  * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
605  * Parameters)
606  *
607  * All these timings are expressed in picoseconds.
608  *
609  * @tBERS_max: Block erase time
610  * @tCCS_min: Change column setup time
611  * @tPROG_max: Page program time
612  * @tR_max: Page read time
613  * @tALH_min: ALE hold time
614  * @tADL_min: ALE to data loading time
615  * @tALS_min: ALE setup time
616  * @tAR_min: ALE to RE# delay
617  * @tCEA_max: CE# access time
618  * @tCEH_min:
619  * @tCH_min:  CE# hold time
620  * @tCHZ_max: CE# high to output hi-Z
621  * @tCLH_min: CLE hold time
622  * @tCLR_min: CLE to RE# delay
623  * @tCLS_min: CLE setup time
624  * @tCOH_min: CE# high to output hold
625  * @tCS_min: CE# setup time
626  * @tDH_min: Data hold time
627  * @tDS_min: Data setup time
628  * @tFEAT_max: Busy time for Set Features and Get Features
629  * @tIR_min: Output hi-Z to RE# low
630  * @tITC_max: Interface and Timing Mode Change time
631  * @tRC_min: RE# cycle time
632  * @tREA_max: RE# access time
633  * @tREH_min: RE# high hold time
634  * @tRHOH_min: RE# high to output hold
635  * @tRHW_min: RE# high to WE# low
636  * @tRHZ_max: RE# high to output hi-Z
637  * @tRLOH_min: RE# low to output hold
638  * @tRP_min: RE# pulse width
639  * @tRR_min: Ready to RE# low (data only)
640  * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
641  *            rising edge of R/B#.
642  * @tWB_max: WE# high to SR[6] low
643  * @tWC_min: WE# cycle time
644  * @tWH_min: WE# high hold time
645  * @tWHR_min: WE# high to RE# low
646  * @tWP_min: WE# pulse width
647  * @tWW_min: WP# transition to WE# low
648  */
649 struct nand_sdr_timings {
650         u32 tBERS_max;
651         u32 tCCS_min;
652         u32 tPROG_max;
653         u32 tR_max;
654         u32 tALH_min;
655         u32 tADL_min;
656         u32 tALS_min;
657         u32 tAR_min;
658         u32 tCEA_max;
659         u32 tCEH_min;
660         u32 tCH_min;
661         u32 tCHZ_max;
662         u32 tCLH_min;
663         u32 tCLR_min;
664         u32 tCLS_min;
665         u32 tCOH_min;
666         u32 tCS_min;
667         u32 tDH_min;
668         u32 tDS_min;
669         u32 tFEAT_max;
670         u32 tIR_min;
671         u32 tITC_max;
672         u32 tRC_min;
673         u32 tREA_max;
674         u32 tREH_min;
675         u32 tRHOH_min;
676         u32 tRHW_min;
677         u32 tRHZ_max;
678         u32 tRLOH_min;
679         u32 tRP_min;
680         u32 tRR_min;
681         u64 tRST_max;
682         u32 tWB_max;
683         u32 tWC_min;
684         u32 tWH_min;
685         u32 tWHR_min;
686         u32 tWP_min;
687         u32 tWW_min;
688 };
689 
690 /**
691  * enum nand_data_interface_type - NAND interface timing type
692  * @NAND_SDR_IFACE:     Single Data Rate interface
693  */
694 enum nand_data_interface_type {
695         NAND_SDR_IFACE,
696 };
697 
698 /**
699  * struct nand_data_interface - NAND interface timing
700  * @type:       type of the timing
701  * @timings:    The timing, type according to @type
702  */
703 struct nand_data_interface {
704         enum nand_data_interface_type type;
705         union {
706                 struct nand_sdr_timings sdr;
707         } timings;
708 };
709 
710 /**
711  * nand_get_sdr_timings - get SDR timing from data interface
712  * @conf:       The data interface
713  */
714 static inline const struct nand_sdr_timings *
715 nand_get_sdr_timings(const struct nand_data_interface *conf)
716 {
717         if (conf->type != NAND_SDR_IFACE)
718                 return ERR_PTR(-EINVAL);
719 
720         return &conf->timings.sdr;
721 }
722 
723 /**
724  * struct nand_chip - NAND Private Flash Chip Data
725  * @mtd:                MTD device registered to the MTD framework
726  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
727  *                      flash device
728  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
729  *                      flash device.
730  * @read_byte:          [REPLACEABLE] read one byte from the chip
731  * @read_word:          [REPLACEABLE] read one word from the chip
732  * @write_byte:         [REPLACEABLE] write a single byte to the chip on the
733  *                      low 8 I/O lines
734  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
735  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
736  * @select_chip:        [REPLACEABLE] select chip nr
737  * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
738  * @block_markbad:      [REPLACEABLE] mark a block bad
739  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
740  *                      ALE/CLE/nCE. Also used to write command and address
741  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
742  *                      device ready/busy line. If set to NULL no access to
743  *                      ready/busy is available and the ready/busy information
744  *                      is read from the chip status register.
745  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
746  *                      commands to the chip.
747  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
748  *                      ready.
749  * @setup_read_retry:   [FLASHSPECIFIC] flash (vendor) specific function for
750  *                      setting the read-retry mode. Mostly needed for MLC NAND.
751  * @ecc:                [BOARDSPECIFIC] ECC control structure
752  * @buffers:            buffer structure for read/write
753  * @hwcontrol:          platform-specific hardware control structure
754  * @erase:              [REPLACEABLE] erase function
755  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
756  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
757  *                      data from array to read regs (tR).
758  * @state:              [INTERN] the current state of the NAND device
759  * @oob_poi:            "poison value buffer," used for laying out OOB data
760  *                      before writing
761  * @page_shift:         [INTERN] number of address bits in a page (column
762  *                      address bits).
763  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
764  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
765  * @chip_shift:         [INTERN] number of address bits in one chip
766  * @options:            [BOARDSPECIFIC] various chip options. They can partly
767  *                      be set to inform nand_scan about special functionality.
768  *                      See the defines for further explanation.
769  * @bbt_options:        [INTERN] bad block specific options. All options used
770  *                      here must come from bbm.h. By default, these options
771  *                      will be copied to the appropriate nand_bbt_descr's.
772  * @badblockpos:        [INTERN] position of the bad block marker in the oob
773  *                      area.
774  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
775  *                      bad block marker position; i.e., BBM == 11110111b is
776  *                      not bad when badblockbits == 7
777  * @bits_per_cell:      [INTERN] number of bits per cell. i.e., 1 means SLC.
778  * @ecc_strength_ds:    [INTERN] ECC correctability from the datasheet.
779  *                      Minimum amount of bit errors per @ecc_step_ds guaranteed
780  *                      to be correctable. If unknown, set to zero.
781  * @ecc_step_ds:        [INTERN] ECC step required by the @ecc_strength_ds,
782  *                      also from the datasheet. It is the recommended ECC step
783  *                      size, if known; if unknown, set to zero.
784  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
785  *                            set to the actually used ONFI mode if the chip is
786  *                            ONFI compliant or deduced from the datasheet if
787  *                            the NAND chip is not ONFI compliant.
788  * @numchips:           [INTERN] number of physical chips
789  * @chipsize:           [INTERN] the size of one chip for multichip arrays
790  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
791  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
792  *                      data_buf.
793  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
794  *                      currently in data_buf.
795  * @subpagesize:        [INTERN] holds the subpagesize
796  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
797  *                      non 0 if ONFI supported.
798  * @jedec_version:      [INTERN] holds the chip JEDEC version (BCD encoded),
799  *                      non 0 if JEDEC supported.
800  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
801  *                      supported, 0 otherwise.
802  * @jedec_params:       [INTERN] holds the JEDEC parameter page when JEDEC is
803  *                      supported, 0 otherwise.
804  * @read_retries:       [INTERN] the number of read retry modes supported
805  * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
806  * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
807  * @setup_data_interface: [OPTIONAL] setup the data interface and timing
808  * @bbt:                [INTERN] bad block table pointer
809  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
810  *                      lookup.
811  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
812  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
813  *                      bad block scan.
814  * @controller:         [REPLACEABLE] a pointer to a hardware controller
815  *                      structure which is shared among multiple independent
816  *                      devices.
817  * @priv:               [OPTIONAL] pointer to private chip data
818  * @errstat:            [OPTIONAL] hardware specific function to perform
819  *                      additional error status checks (determine if errors are
820  *                      correctable).
821  * @write_page:         [REPLACEABLE] High-level page write function
822  */
823 
824 struct nand_chip {
825         struct mtd_info mtd;
826         void __iomem *IO_ADDR_R;
827         void __iomem *IO_ADDR_W;
828 
829         uint8_t (*read_byte)(struct mtd_info *mtd);
830         u16 (*read_word)(struct mtd_info *mtd);
831         void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
832         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
833         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
834         void (*select_chip)(struct mtd_info *mtd, int chip);
835         int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
836         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
837         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
838         int (*dev_ready)(struct mtd_info *mtd);
839         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
840                         int page_addr);
841         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
842         int (*erase)(struct mtd_info *mtd, int page);
843         int (*scan_bbt)(struct mtd_info *mtd);
844         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
845                         int status, int page);
846         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
847                         uint32_t offset, int data_len, const uint8_t *buf,
848                         int oob_required, int page, int cached, int raw);
849         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
850                         int feature_addr, uint8_t *subfeature_para);
851         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
852                         int feature_addr, uint8_t *subfeature_para);
853         int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
854         int (*setup_data_interface)(struct mtd_info *mtd,
855                                     const struct nand_data_interface *conf,
856                                     bool check_only);
857 
858 
859         int chip_delay;
860         unsigned int options;
861         unsigned int bbt_options;
862 
863         int page_shift;
864         int phys_erase_shift;
865         int bbt_erase_shift;
866         int chip_shift;
867         int numchips;
868         uint64_t chipsize;
869         int pagemask;
870         int pagebuf;
871         unsigned int pagebuf_bitflips;
872         int subpagesize;
873         uint8_t bits_per_cell;
874         uint16_t ecc_strength_ds;
875         uint16_t ecc_step_ds;
876         int onfi_timing_mode_default;
877         int badblockpos;
878         int badblockbits;
879 
880         int onfi_version;
881         int jedec_version;
882         union {
883                 struct nand_onfi_params onfi_params;
884                 struct nand_jedec_params jedec_params;
885         };
886 
887         struct nand_data_interface *data_interface;
888 
889         int read_retries;
890 
891         flstate_t state;
892 
893         uint8_t *oob_poi;
894         struct nand_hw_control *controller;
895 
896         struct nand_ecc_ctrl ecc;
897         struct nand_buffers *buffers;
898         struct nand_hw_control hwcontrol;
899 
900         uint8_t *bbt;
901         struct nand_bbt_descr *bbt_td;
902         struct nand_bbt_descr *bbt_md;
903 
904         struct nand_bbt_descr *badblock_pattern;
905 
906         void *priv;
907 };
908 
909 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
910 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
911 
912 static inline void nand_set_flash_node(struct nand_chip *chip,
913                                        struct device_node *np)
914 {
915         mtd_set_of_node(&chip->mtd, np);
916 }
917 
918 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
919 {
920         return mtd_get_of_node(&chip->mtd);
921 }
922 
923 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
924 {
925         return container_of(mtd, struct nand_chip, mtd);
926 }
927 
928 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
929 {
930         return &chip->mtd;
931 }
932 
933 static inline void *nand_get_controller_data(struct nand_chip *chip)
934 {
935         return chip->priv;
936 }
937 
938 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
939 {
940         chip->priv = priv;
941 }
942 
943 /*
944  * NAND Flash Manufacturer ID Codes
945  */
946 #define NAND_MFR_TOSHIBA        0x98
947 #define NAND_MFR_ESMT           0xc8
948 #define NAND_MFR_SAMSUNG        0xec
949 #define NAND_MFR_FUJITSU        0x04
950 #define NAND_MFR_NATIONAL       0x8f
951 #define NAND_MFR_RENESAS        0x07
952 #define NAND_MFR_STMICRO        0x20
953 #define NAND_MFR_HYNIX          0xad
954 #define NAND_MFR_MICRON         0x2c
955 #define NAND_MFR_AMD            0x01
956 #define NAND_MFR_MACRONIX       0xc2
957 #define NAND_MFR_EON            0x92
958 #define NAND_MFR_SANDISK        0x45
959 #define NAND_MFR_INTEL          0x89
960 #define NAND_MFR_ATO            0x9b
961 
962 /* The maximum expected count of bytes in the NAND ID sequence */
963 #define NAND_MAX_ID_LEN 8
964 
965 /*
966  * A helper for defining older NAND chips where the second ID byte fully
967  * defined the chip, including the geometry (chip size, eraseblock size, page
968  * size). All these chips have 512 bytes NAND page size.
969  */
970 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
971         { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
972           .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
973 
974 /*
975  * A helper for defining newer chips which report their page size and
976  * eraseblock size via the extended ID bytes.
977  *
978  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
979  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
980  * device ID now only represented a particular total chip size (and voltage,
981  * buswidth), and the page size, eraseblock size, and OOB size could vary while
982  * using the same device ID.
983  */
984 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
985         { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
986           .options = (opts) }
987 
988 #define NAND_ECC_INFO(_strength, _step) \
989                         { .strength_ds = (_strength), .step_ds = (_step) }
990 #define NAND_ECC_STRENGTH(type)         ((type)->ecc.strength_ds)
991 #define NAND_ECC_STEP(type)             ((type)->ecc.step_ds)
992 
993 /**
994  * struct nand_flash_dev - NAND Flash Device ID Structure
995  * @name: a human-readable name of the NAND chip
996  * @dev_id: the device ID (the second byte of the full chip ID array)
997  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
998  *          memory address as @id[0])
999  * @dev_id: device ID part of the full chip ID array (refers the same memory
1000  *          address as @id[1])
1001  * @id: full device ID array
1002  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1003  *            well as the eraseblock size) is determined from the extended NAND
1004  *            chip ID array)
1005  * @chipsize: total chip size in MiB
1006  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1007  * @options: stores various chip bit options
1008  * @id_len: The valid length of the @id.
1009  * @oobsize: OOB size
1010  * @ecc: ECC correctability and step information from the datasheet.
1011  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1012  *                   @ecc_strength_ds in nand_chip{}.
1013  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1014  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
1015  *               For example, the "4bit ECC for each 512Byte" can be set with
1016  *               NAND_ECC_INFO(4, 512).
1017  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1018  *                            reset. Should be deduced from timings described
1019  *                            in the datasheet.
1020  *
1021  */
1022 struct nand_flash_dev {
1023         char *name;
1024         union {
1025                 struct {
1026                         uint8_t mfr_id;
1027                         uint8_t dev_id;
1028                 };
1029                 uint8_t id[NAND_MAX_ID_LEN];
1030         };
1031         unsigned int pagesize;
1032         unsigned int chipsize;
1033         unsigned int erasesize;
1034         unsigned int options;
1035         uint16_t id_len;
1036         uint16_t oobsize;
1037         struct {
1038                 uint16_t strength_ds;
1039                 uint16_t step_ds;
1040         } ecc;
1041         int onfi_timing_mode_default;
1042 };
1043 
1044 /**
1045  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1046  * @name:       Manufacturer name
1047  * @id:         manufacturer ID code of device.
1048 */
1049 struct nand_manufacturers {
1050         int id;
1051         char *name;
1052 };
1053 
1054 extern struct nand_flash_dev nand_flash_ids[];
1055 extern struct nand_manufacturers nand_manuf_ids[];
1056 
1057 int nand_default_bbt(struct mtd_info *mtd);
1058 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1059 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1060 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1061 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1062                     int allowbbt);
1063 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1064                  size_t *retlen, uint8_t *buf);
1065 
1066 /**
1067  * struct platform_nand_chip - chip level device structure
1068  * @nr_chips:           max. number of chips to scan for
1069  * @chip_offset:        chip number offset
1070  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
1071  * @partitions:         mtd partition list
1072  * @chip_delay:         R/B delay value in us
1073  * @options:            Option flags, e.g. 16bit buswidth
1074  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
1075  * @part_probe_types:   NULL-terminated array of probe types
1076  */
1077 struct platform_nand_chip {
1078         int nr_chips;
1079         int chip_offset;
1080         int nr_partitions;
1081         struct mtd_partition *partitions;
1082         int chip_delay;
1083         unsigned int options;
1084         unsigned int bbt_options;
1085         const char **part_probe_types;
1086 };
1087 
1088 /* Keep gcc happy */
1089 struct platform_device;
1090 
1091 /**
1092  * struct platform_nand_ctrl - controller level device structure
1093  * @probe:              platform specific function to probe/setup hardware
1094  * @remove:             platform specific function to remove/teardown hardware
1095  * @hwcontrol:          platform specific hardware control structure
1096  * @dev_ready:          platform specific function to read ready/busy pin
1097  * @select_chip:        platform specific chip select function
1098  * @cmd_ctrl:           platform specific function for controlling
1099  *                      ALE/CLE/nCE. Also used to write command and address
1100  * @write_buf:          platform specific function for write buffer
1101  * @read_buf:           platform specific function for read buffer
1102  * @read_byte:          platform specific function to read one byte from chip
1103  * @priv:               private data to transport driver specific settings
1104  *
1105  * All fields are optional and depend on the hardware driver requirements
1106  */
1107 struct platform_nand_ctrl {
1108         int (*probe)(struct platform_device *pdev);
1109         void (*remove)(struct platform_device *pdev);
1110         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1111         int (*dev_ready)(struct mtd_info *mtd);
1112         void (*select_chip)(struct mtd_info *mtd, int chip);
1113         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1114         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1115         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1116         unsigned char (*read_byte)(struct mtd_info *mtd);
1117         void *priv;
1118 };
1119 
1120 /**
1121  * struct platform_nand_data - container structure for platform-specific data
1122  * @chip:               chip level chip structure
1123  * @ctrl:               controller level device structure
1124  */
1125 struct platform_nand_data {
1126         struct platform_nand_chip chip;
1127         struct platform_nand_ctrl ctrl;
1128 };
1129 
1130 /* return the supported features. */
1131 static inline int onfi_feature(struct nand_chip *chip)
1132 {
1133         return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1134 }
1135 
1136 /* return the supported asynchronous timing mode. */
1137 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1138 {
1139         if (!chip->onfi_version)
1140                 return ONFI_TIMING_MODE_UNKNOWN;
1141         return le16_to_cpu(chip->onfi_params.async_timing_mode);
1142 }
1143 
1144 /* return the supported synchronous timing mode. */
1145 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1146 {
1147         if (!chip->onfi_version)
1148                 return ONFI_TIMING_MODE_UNKNOWN;
1149         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1150 }
1151 
1152 int onfi_init_data_interface(struct nand_chip *chip,
1153                              struct nand_data_interface *iface,
1154                              enum nand_data_interface_type type,
1155                              int timing_mode);
1156 
1157 /*
1158  * Check if it is a SLC nand.
1159  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1160  * We do not distinguish the MLC and TLC now.
1161  */
1162 static inline bool nand_is_slc(struct nand_chip *chip)
1163 {
1164         return chip->bits_per_cell == 1;
1165 }
1166 
1167 /**
1168  * Check if the opcode's address should be sent only on the lower 8 bits
1169  * @command: opcode to check
1170  */
1171 static inline int nand_opcode_8bits(unsigned int command)
1172 {
1173         switch (command) {
1174         case NAND_CMD_READID:
1175         case NAND_CMD_PARAM:
1176         case NAND_CMD_GET_FEATURES:
1177         case NAND_CMD_SET_FEATURES:
1178                 return 1;
1179         default:
1180                 break;
1181         }
1182         return 0;
1183 }
1184 
1185 /* return the supported JEDEC features. */
1186 static inline int jedec_feature(struct nand_chip *chip)
1187 {
1188         return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1189                 : 0;
1190 }
1191 
1192 /* get timing characteristics from ONFI timing mode. */
1193 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1194 /* get data interface from ONFI timing mode 0, used after reset. */
1195 const struct nand_data_interface *nand_get_default_data_interface(void);
1196 
1197 int nand_check_erased_ecc_chunk(void *data, int datalen,
1198                                 void *ecc, int ecclen,
1199                                 void *extraoob, int extraooblen,
1200                                 int threshold);
1201 
1202 /* Default write_oob implementation */
1203 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1204 
1205 /* Default write_oob syndrome implementation */
1206 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1207                             int page);
1208 
1209 /* Default read_oob implementation */
1210 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1211 
1212 /* Default read_oob syndrome implementation */
1213 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1214                            int page);
1215 
1216 /* Reset and initialize a NAND device */
1217 int nand_reset(struct nand_chip *chip, int chipnr);
1218 
1219 /* Free resources held by the NAND device */
1220 void nand_cleanup(struct nand_chip *chip);
1221 
1222 #endif /* __LINUX_MTD_NAND_H */
1223 

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